singlepulse registers that are more than 1 bit wide

[mkahane]

I am aware that the systemrdl specification says (on page 50):

g.) singlepulse fields shall be instantiated with a width of 1 and the reset value shall be specified as 0.

However, I believe that both the RDL specification and the compiler should support multibit registers with a singlepulse output from the register block.

For example, imagine a counter implemented outside of the register block. It is often useful to have a clear bit for this counter that is triggered by writing 1 to the register.

[amykyta3]

Regardless of the width of the field, using singlepulse in this context wouldn't really be an appropriate choice, since the singlepulse property acts on the internally implemented storage element of the field. That contradicts the ability to feed in an external counter value.

Any reason you need it to be write-1-to-clear? If its the only counter field in the register, any write-to-clear would be sufficient.
If your counter is implemented internally via RDL, you could do this:

field {
    sw=rw;
    counter;
    onwrite=wclr;
} my_counter[7:0];

If you truly want a write-1-to-clear action, you could hide a singlepulse trigger bit "behind" the counter. This is legal since the sw read and write actions do not conflict:

reg my_reg {
    
    field {
        sw=r;
        counter;
    } my_counter[7:0];

    field {
        sw=w;
        singlepulse;
    } counter_clear[0:0]; // hide this in bit 0 of the counter

    // Pulse from writing 1 to counter_clear will zero the counter value
    my_counter->hwclr = counter_clear;
};

I haven't explicitly tried it, but PeakRDL-regblock should be able to support this.

[mkahane]

the main reason is that I'm trying to rework legacy code into RDL with minimal changes to drivers :)

The suggestion above is clever. I did not know you could overload bits like that.