Confused about registerwidth, accesswidth and "Regmap Width"

[miguel9554]

I'm new to systemRDL and I'm confused about how to specify "the" width of an address map. Every time I worked with a register map, it consisted of a set of addresses which pointed to N amount of bits (this N being "the" width). I don't come from a CPU background but more from custom ASIC development, so I know I'm probably missing some "cultural" things here.

I'm not understanding how this "regmap width" is determined. For what I've read, I think it is related to registerwidth and acceswidth properties, but it is not 100% clear to me yet.

registerwidth

What really confuses me is that each register may have an independent register width. I always understood that a register map had a constant register width. I really do not understand the applications in which different register widths are useful, If I could be pointed to any references it would be great.

accesswidth

On page 66 table 23 of the 2.0 standard it says that accesswidth "Specifies the minimum software access width (power of two) operation that may be performed on the register."

So apparently, it is useful to determine for example that a 32-bit register is byte addressable. However, I don't see how this is relevant to the implementation, and again I have the same doubt as regarding registerwidth: why is this a property settable per-register? Shouldn't it be set at the addrmap/regfile level?

Then I found an interesting discussion at #98: particulary in comment #98 (comment), @amykyta3 interpreted from the spec that the accesswidth is actually the bus width, which I find much more reasonable, and I understand it coincides with what I called "the" width above. But, being this the case, the question remains: why can we define it multiple times for a single address map?

To aid in the confusion, I tested setting accesswidth at the addrmap level and peakrdl regblock resulted in the following errror:

Generating SystemVerilog RAL model (regblock)...
peakrdl regblock fir_filter.rdl -o output/rtl --cpuif passthrough
fir_filter.rdl:4:5: fatal: The property 'accesswidth' is not valid for 'addrmap' components
    accesswidth = 16;
    ^^^^^^^^^^^
make: *** [Makefile:31: output/rtl/fir_filter.sv] Error 1

I'm probably missing some things here or misunderstanding, so any comments or feedback is appreciated. Thanks!