8 and 16-bit alignement of CSR fields in HAL

[chili-chips-ba]

In order to maximize CPU performance when accessing CSR fields, the project is looking to define them aligned to the natural byte and word boundaries. The objective is to avoid Read-Modify-Write (RMW) sequences and maximize the use of RISC-V 8-bit and 16-bit addressing modes.

However, PeakRDL currently does not have a facility for declaring aligned fields.

For example, consider we want a 3-bit control field to be byte aligned. That can be done by teaming it up with 5 "reserved" bits. So far, so good. The problem arises in the HAL, where 'C' structs will include both 3-bit and 5-bit members. That will then force the GCC into using RMW sequence.

What we'd like to have is an align8 or align16 attribute that can be attached to a register field. PeakRDL would respond to it not only by padding the bits behind such fields with the proper number of reserved/unused slots (so not to consume the physical flops), but also adding aligned struct to the union of structs that models the register. Similarly, aligned option would be provided for the macros. That would then allow the user to chose either aligned or unaligned access for any field, at any time.

The proposed method is only an initial thought, to start the exploration process. We look at the PeakRDL folks to revise it, and ideally respond with proposals that blend more naturally into their existing flow and schemes of things.

This question was originally posed here and is an offshoot of Co-sim/co-design with peakrdl output discussion track.