{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"cvw-arch-verif","owner":"openhwgroup","isFork":false,"description":"The purpose of the repo is to support CORE-V Wally architectural verification","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":7,"starsCount":1,"forksCount":18,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-11T15:02:33.251Z"}},{"type":"Public","name":"cv-hpdcache-verif","owner":"openhwgroup","isFork":false,"description":"Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":1,"starsCount":3,"forksCount":1,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-09-06T16:25:34.556Z"}},{"type":"Public","name":"cv-hpdcache","owner":"openhwgroup","isFork":false,"description":"RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":2,"starsCount":47,"forksCount":16,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-20T09:57:05.827Z"}},{"type":"Public","name":"cv32e40s","owner":"openhwgroup","isFork":false,"description":"4 stage, in-order, secure RISC-V core based on the CV32E40P","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":1,"starsCount":126,"forksCount":21,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-16T08:00:13.044Z"}},{"type":"Public","name":"cv32e40x","owner":"openhwgroup","isFork":false,"description":"4 stage, in-order, compute RISC-V core based on the CV32E40P","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":4,"issueCount":28,"starsCount":208,"forksCount":48,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-08T12:04:11.070Z"}},{"type":"Public","name":"cvfpu","owner":"openhwgroup","isFork":false,"description":"Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":11,"issueCount":38,"starsCount":416,"forksCount":112,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-08-02T14:05:35.698Z"}},{"type":"Public","name":"cv32e40p","owner":"openhwgroup","isFork":false,"description":"CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform","allTopics":["riscv","riscv32imfc"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":11,"issueCount":49,"starsCount":923,"forksCount":410,"license":"Other","participation":[8,2,8,16,7,6,3,9,10,7,14,5,7,3,8,0,11,4,2,5,1,2,8,1,5,5,6,18,0,17,12,6,5,0,0,0,2,14,8,15,3,4,5,5,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-19T14:17:37.022Z"}},{"type":"Public","name":"core-v-mcu-uvm","owner":"openhwgroup","isFork":false,"description":"CORE-V MCU UVM Environment and Test Bench","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":16,"starsCount":16,"forksCount":7,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-07-19T12:53:53.936Z"}},{"type":"Public","name":"cve2","owner":"openhwgroup","isFork":true,"description":"The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":10,"issueCount":169,"starsCount":27,"forksCount":516,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-19T12:02:12.404Z"}},{"type":"Public","name":"core-v-xif","owner":"openhwgroup","isFork":false,"description":"RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":17,"starsCount":59,"forksCount":24,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-22T09:42:14.058Z"}},{"type":"Public","name":"cva5","owner":"openhwgroup","isFork":false,"description":"The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":10,"starsCount":56,"forksCount":14,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-04-03T02:37:02.525Z"}},{"type":"Public","name":"core-v-mcu","owner":"openhwgroup","isFork":false,"description":"This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.","allTopics":["microcontroller","riscv","systemverilog","openhwgroup"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":5,"issueCount":73,"starsCount":163,"forksCount":50,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-01-18T19:04:43.646Z"}},{"type":"Public archive","name":"cv32e41p","owner":"openhwgroup","isFork":false,"description":"4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":2,"issueCount":9,"starsCount":25,"forksCount":10,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-08-16T21:27:36.015Z"}},{"type":"Public","name":"cva5-accelerators","owner":"openhwgroup","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":0,"starsCount":0,"forksCount":4,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-05-02T20:55:13.065Z"}},{"type":"Public","name":"advanced-riscv-verification-methodologies","owner":"openhwgroup","isFork":false,"description":"Advanced Verification Methodologies for RISC-V and related IP","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":7,"forksCount":4,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-01-16T20:18:44.876Z"}},{"type":"Public","name":"timer_unit","owner":"openhwgroup","isFork":true,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":1,"starsCount":2,"forksCount":4,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-02-18T03:50:50.237Z"}},{"type":"Public","name":"apb_interrupt_cntrl","owner":"openhwgroup","isFork":true,"description":"Small and simple APB interrupt controller","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":4,"forksCount":7,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-11-09T17:25:12.174Z"}}],"repositoryCount":17,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"openhwgroup repositories"}