PolarFire-SoC
Can REFCLK_x_PLL_NW frequency be Decimal? #120
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I got following compilation errors from Softconsole if I use REFCLK_x_PLL_NW as the MSS PLL reference clock source and RTC clock source and set PLL_NW frequency to be a decimal, i.e. 122.88 MHz in MSS Configurator ...\src\boards\icicle-kit-es/fpga_design_config/clocks/hw_mss_clks.h:27: error: unterminated #ifndef The reason for causing this error is: There is no issue if I give an integer number, like 122 MHz. Thanks in advance! |
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Replies: 1 comment 2 replies
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The values you're using sound valid :) The issue here is in the XML generation from the looks of it - I recreated your set up below (value of 122.88MHz left and 125MHz right): The MHz value is converted to Hz in the XML and when you use a decimal value for the clock source in MHz the resulting XML has a ".0" appended to the Hz value. I was able to successfully generate the config files by removing the ".0" at the end of the |
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Yes, your solution resolves the problem. Thanks so much, Hugh! |
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Great 🙂 We'll get this fixed for a future release of the configurator |
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Hi @henryding-emcore
The values you're using sound valid :)
The issue here is in the XML generation from the looks of it - I recreated your set up below (value of 122.88MHz left and 125MHz right):
The MHz value is converted to Hz in the XML and when you use a decimal value for the clock source in MHz the resulting XML has a ".0" appended to the Hz value.
I was able to successfully generate the config files by removing the ".0" at the end of the
MSS_EXT_SGMII_REF_CLKfield. If you search your XML forMSS_EXT_SGMII_REF_CLKyou should see the ".0", can you confirm removing this resolves the build error for you?