Bugs in MSS Configurator(2021.2, .3) while using REFCLK_x_PLL_NW

[henryding-emcore]

In MSS, there is no option for me to choose MSS PLL reference clock source and RTC reference clock source to be the same source from NW PLL. Instead, seems REFCLK_0_PLL_NW is dedicated to MSS PLL and REFCLK_1_PLL_NW is dedicated to RTC.
With this, the auto generated file ICICLE_MSS.v only exposes REFCLK_0_PLL_NW to the top and connects REFCLK_1_PLL_NW to VCC.

I have to manually modify my top file (generated from SmartDesign) and ICICLE_MSS.v file to connect REFCLK_1_PLL_NW to either OUT2 or OUT3 of NW PLL .

[hughbreslin]

Hi @henryding-emcore

from the screenshot above, you aren't using DDR correct? I can reproduce this using the following MSS configuration:

If I enable DDR and use the REFCLK_1_PLL_NW for its reference clock I can see both reference clocks:

If I use the dedicated I/O from Bank5 as the reference clock the REFCLK_1_PLL_NW also doesn't show up

[henryding-emcore]

Hi Hugh, I'm glad you can reproduce the problem I saw. No, I'm not using DDR.

[hughbreslin]

Hi Henry, this is reported internally for a fix but it will be released in a future version of the configurator.

For now the best suggestions are:

1. Do as you've done already and manually connect the pin
2. You could enable DDR so the pin is exposed and not include DDR support in your project so the DDR is never enabled / brought up

Thank you for reporting this