How to configure Zephyr SMP Example to execute from internal memory (L2-LIM) on Icicle Kit ? #237
Unanswered
ChrRudel
asked this question in
RTOS for PolarFire SoC
Replies: 1 comment
-
Hi @ChrRudel we are looking into this and will prepare an example |
Beta Was this translation helpful? Give feedback.
0 replies
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
-
I would like to modify the SMP Zephyr application example to run from internal memory (L2-LIM@0x0800_0000).
Currently the Zephyr SMP example seems to run from external Memory.
"..../build/zephyr/.config" contains:
CONFIG_SRAM_BASE_ADDRESS=0x80000000 (start of external DDR cached access address range)
Below what I have tried.
Changed project configuration file for the SMP example as follows:
.../PfSoC_Zephyr/polarfire-soc-zephyr-applications/mpfs-applications/smp/pi/prj.conf
CONFIG_SRAM_SIZE=512
CONFIG_SRAM_BASE_ADDRESS=0x08000000
Example builds without errors:
...
[100%] Linking C executable zephyr.elf
Memory region Used Size Region Size %age Used
RAM: 212428 B 512 KB 40.52%
IDT_LIST: 0 GB 2 KB 0.00%
Entry point is 0x8000000 as expected:
readelf -l zephyr.elf
Elf file type is EXEC (Executable file)
Entry point 0x8000000
...
When I am starting the "smp_pi_debug" debug configuration and select "Resume" two times, I don't get any UART output on Interface0.
For comparison, Interface0 outputs the PI calculation values as expected when using the default example configuration (CONFIG_SRAM_BASE_ADDRESS=0x80000000).
Are there any further changes required besides CONFIG_SRAM_BASE_ADDRESS to run the SMP example inside L2-LIM ?
friendly regards,
Christian
Beta Was this translation helpful? Give feedback.
All reactions