How to allocate DDR cache and non-cache areas to the same physical address？

[Usutatsu]

I am currently using the Icicle kit reference design for various experiments.
So i would like to change the DDR settings of the Icicle kit.
Specifically, I mean to place the DDR cache space and non-cache space at the same physical address.

The operation I want to do is the following operation.

1. Write a value to the non-cache area (address of 0xC000_0000).
2. Read the cache area (address of 0x8000_0000) to read the value written to 0xC000_0000 in step 1.

To achieve this behavior, I used MSS configurator v2022.3 and set the physical DDR offset to all 0's from the memory partition settings tab.

However, the values readable for 0x8000_0000 and 0XC000_0000 were different, even when accessed using the procedure described above.

I see two possible causes for this problem.
The first is that the two DDR areas do not point to the same physical address.
However, in the 2022.10 release notes of the Icicle kit, it states that if the physical ddr offset is set manually, the cache and non-cache areas will be in the same physical memory.

The second is that after writing a value to the non-cache area, the cache area is accessed but hit in the L1 or L2 cache and the DDR is not read.
To resolve this concern, I need to explicitly clear or flush the L1 and L2 caches, but I don't know how to do that.

If anyone is familiar with these issues, I would love to know how to solve them.

[hughbreslin]

Hey @Usutatsu

My first question is did you add the newly generated XML to your bare metal / HSS project, and apply the changes using the debugger or by programming the eNVM? If you only imported an updated MSS component into Libero the SEG values won't be changed.

You can flush regions of the L2 cache using the cache flush registers, table 4-9 on page 22 of the TRM contains the address of the registers, there is a description of the registers in section 4.1.6.3.12. You're looking for Flush64 and Flush32.

[Usutatsu]

Thanks for your comment.
I had forgotten to add a new .cfg file to the bare metal/HSS project file.
So, instead of the default .cfg file, I added the .cfg file to boards/icicle-kit-es/fpga_design/ in the project.
As a result, I was able to verify that the memory partitions were accurately reflected and that the cache and non-cache areas pointed to the same physical DDR address.

[hughbreslin]

Brilliant :)