Flush L1/L2 on the U54-MC

[Usutatsu]

Hi everyone,

I'm currently working on a polarfire soc icicle-kit and I'm trying to verify cache flush operation.
I could check L2 cahce flush operation using L2 control register flush64.
However, I can't understand how to flush L1 d-cache explicitly.

Some references (i.e. U54-MC core complex manual) state that we can use CFLUSH.D.L1 custom instruction to flush L1 d-cache.
So, I tried using CFLUSH.D.L1 instruction, but could not flush the cache successfully.

Does anyone know how to flush the L1 d-cache with polarfire soc?
If there is no way to explicitly flush the L1 d-cache, could you please tell me the detailed process by which the L1 d-cache is flushed?

[hughbreslin]

Hi @Usutatsu :)

check out Ralph’s response on this forum - using the flush register should also flush any related data in the L1 cache. The CFLUSH.D.L1 isn’t available on PF SoC.