MSS DDR controller access and conflict

[Usutatsu]

Hi, I have two questions about MSS DDR controller embedded in PolarFire SoC.

The first question is about how the master access to DDR memory from the fabric.
I'm considering that fabric master DDR memory access throught FIC2.
However, "PolarFire SoC MSS Technical Reference Manual Tablle 3-49." state that the MSS DDR Controller Interface form AXI Switch via fabric interface controller (FIC0) for masters in the fabric.
From this description, I understood that memory access from the fabric should be via FIC0, but I am confused because the description of FIC2 states that it is used for master access to memory from the fabric.
In conclusion, is it not possible to use memory access from the fabric via FIC2?

Second question is about arbitration of MSS DDR controller.
If memory access from core complex and memory access from fabric conflict, how will arbitration be done on the MSS DDR controller?
For example, does the one accessed first get priority or is it arbitrated like a round-robin?
Are there any documents that describe them?

That's all. Thank you.

[hughbreslin]

Hi @Usutatsu

sorry for the delay in getting back!

You can use any FIC to access the DDR from the fabric, the main differences as I understand are due to the placement of the FICs in the fabric, for PCIe -> DDR access (which is through the fabric) using a FIC closer to the PCIe will allow better timing closure, but you should be ok to access via any of them.

In terms of arbitration, do you mean the harts and fabric accessing the same DDR memory location?

[Usutatsu]

Hi @hughbreslin

Thanks for the response.
I understood that I need to choose the FIC to use if I consider the timing, but if I don't consider it, then I am free to use it.

A related question, can you tell me?
Does AXI switch support exclusive access?
For example, can RISC-V core access the fabric via FIC0 while the fabric accesses DDR memory controller via FIC2?

[hughbreslin]

Yes you can use the FICs independently that’s no problem, for MSS -> fabric each FIC has its own address space and fabric -> MSS uses the mss memory map. You can also use the MPU and PMPs to restrict access from different initiators to a specific address range.

[Usutatsu]

Sorry for the delay in responding.

Maybe I didn't ask the right question.
The intent of my question is whether it is possible to go through the AXI Switch twice during one access.

For example, is it possible to access the DDR memory controller from the fabric via FIC2 while accessing the fabric via FIC1 from RISC-V?

In this example, do I need to complete the access to the fabric via FIC1 and then start accessing the DDR controller from FIC2?

[hughbreslin]

Ahh yes its ok to use both simultaneously. The switch will arbitrate the transactions.

[Usutatsu]

Is it correct that AXI Switch arbitrates, meaning that simultaneous accesses are processed in order?

For example, it is not possible to access DDR memory from FIC2 while accessing the fabric from RISC-V via FIC1 and waiting for the response phase, right?