PolarFire-SoC
How to test the ECC function of E51 and U54? #404
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May I ask if ECC for L1 cache, L2 cache, and DDR is enabled by default? Can ECC be turned off? How to test if the ECC function is effective? |
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Replies: 1 comment 2 replies
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Hi @Balle0500 have you seen this document on ECC? There are ECC error injection registers to test ECC and the HSS can print out ECC stats from the latest release. The addresses for the individual registers and documentation on how to use them can be found in the TRM or the register map. ECC is there for L1 and L2 by default, if you have DDR that supports ECC it is available and the implementation is explained in the first document I linked. I don't think you can turn off ECC but you can mask interrupts so theres notification of an error. |
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Thank you for your reply! May I ask how to use ECC error injection registers? I didn't see any relevant explanation about them in the document. Also, how can I test whether the ECC interrupt function of L2 cache works well? |
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There is a description in the TRM: You just need to set which bit(s) you would like to toggle and the error injection is enabled :) In terms of testing, you will need to enable and configure interrupts (the MSS GPIO bare metal example is useful for this), set the error injection register, write to the L2 and then readback from the L2. In terms of the cache you can set the error injection bits but you will need to wait for writes and readbacks on the cache which you can't directly control. Your best bet would be to write to DDR via the cache and then readback. |
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There is a description in the TRM:
You just need to set which bit(s) you would like to toggle and the error injection is enabled :)
In terms of testing, you will need to enable and configure interrupts (the MSS GPIO bare metal example is useful for this), set the error injection register, write to the L2 and then readback from the L2. In terms of the cache you can set the error injection bits but you will need to wait for writes and readbacks on the cache which you can't directly control. Your best bet would be to write to DDR via the cache and then readback.