DEVICE TREE - LPDDR4 question in: Accessing shared LPDDR4 Memory from Fabric and Linux User Application

[jladowsk]

As the example is pretty straightforward I would like to ask about the DDR handling in Polarfire Icicle.
According to the Table 10-3 [LINK](https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_T0x80000000 - 0xBFFFFFFF RWXC DDR Cached Access - 1 GB
0x1000000000 - 0x13FFFFFFFF RWXC DDR Cached Access - 16 GB
Also we have:
0xC0000000 - 0xCFFFFFFF RWX DDR Non-Cached Access - 256 MB

In the device-tree blob we can see:

memory@80000000 {
	device_type = "memory";
	reg = <0x00 0x80000000 0x00 0x40000000>;
	status = "okay";
};

memory@1040000000 {
	device_type = "memory";
	reg = <0x10 0x40000000 0x00 0x40000000>;
	status = "okay";
};

In the example we mapped: 0xc8000000 address.
My question is about mapping the addresses without taking back them from kernel. As far as I understand these addresses would be the same, but with other access type:
0x80000000
0xc0000000
0xd0000000
0x1000000000

• so that memory@1040000000 starts at 0x1040000000 not 0x1000000000 (Please correct me if I am wrong).
  So writing to the 0xc0000000 without modyfing the device tree to take the address (0x80000000) out from the kernel would be at least dangerous. Another issue is not respecting changes in those spaces (memory@80000000 and memory@1040000000) via simple editing dts blob and restarting the system (I would appreciate if anyone could guide me how to edit dts.)
  Kind Regards,
  Jakub