Injecting Faults on FPGA

[NickSchmidt64]

Currently working with the Icicle Kit trying to do fault analysis.

I have implemented matrix multiplication in VHDL and I want to do some fault analysis of the FPGA design to make it more resilient. I have been exploring options and I believe (from the tools that are available) there are two options. Please correct me if these statements are inaccurate.

Option 1: Hardware-based fault injection can be achieved using SmartDebug and assigning probes to pins.

Option 2: Instantiating the coreEDAC IP into the design to inject errors into the RAM.

Are there any other methods of injecting faults onto the FPGA that do not require extensive model development? Also, can the coreEDAC be used solely to inject errors without enabling the error detection and correction?