diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..f6c6aea --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +**/[Oo]ut_* \ No newline at end of file diff --git a/examples/.Xil/top_propImpl.xdc b/examples/.Xil/top_propImpl.xdc index 2bbec23..fda5837 100644 --- a/examples/.Xil/top_propImpl.xdc +++ b/examples/.Xil/top_propImpl.xdc @@ -1,145 +1,323 @@ -set_property SRC_FILE_INFO {cfile:/home/atom/Virtual-FPGA-Lab/fpga/constraints/fpga_lab_constr_basys3.xdc rfile:../../fpga/constraints/fpga_lab_constr_basys3.xdc id:1} [current_design] -set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W5 [get_ports clk] +set_property SRC_FILE_INFO {cfile:/mnt/d/Dale/Work/FPGA_Projects/Open_Source/Virtual-FPGA-Lab/fpga/constraints/fpga_lab_constr_nexys_A7_100T.xdc rfile:../../fpga/constraints/fpga_lab_constr_nexys_A7_100T.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V17 [get_ports {sw[0]}] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V16 [get_ports {sw[1]}] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W16 [get_ports {sw[2]}] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W17 [get_ports {sw[3]}] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W15 [get_ports {sw[4]}] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V15 [get_ports {sw[5]}] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W14 [get_ports {sw[6]}] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] -set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W13 [get_ports {sw[7]}] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V2 [get_ports {sw[8]}] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T3 [get_ports {sw[9]}] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T2 [get_ports {sw[10]}] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R3 [get_ports {sw[11]}] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W2 [get_ports {sw[12]}] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U1 [get_ports {sw[13]}] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T1 [get_ports {sw[14]}] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R2 [get_ports {reset}] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U16 [get_ports {led[0]}] +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_G }]; #IO_0_14 Sch=led17_g set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN E19 [get_ports {led[1]}] +set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U19 [get_ports {led[2]}] +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V19 [get_ports {led[3]}] +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W18 [get_ports {led[4]}] +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U15 [get_ports {led[5]}] +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U14 [get_ports {led[6]}] +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V14 [get_ports {led[7]}] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V13 [get_ports {led[8]}] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property src_info {type:XDC file:1 line:63 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V3 [get_ports {led[9]}] -set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W3 [get_ports {led[10]}] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] +set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn set_property src_info {type:XDC file:1 line:68 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U3 [get_ports {led[11]}] +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc +set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN P3 [get_ports {led[12]}] +set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl +set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN N3 [get_ports {led[13]}] -set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN P1 [get_ports {led[14]}] +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd +set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1] set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN L1 [get_ports {led[15]}] +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +set_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +set_property src_info {type:XDC file:1 line:79 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +set_property src_info {type:XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] set_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W7 [get_ports {sseg[6]}] +set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] set_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sseg[6]}] -set_property src_info {type:XDC file:1 line:83 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W6 [get_ports {sseg[5]}] +set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] set_property src_info {type:XDC file:1 line:84 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sseg[5]}] +set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] set_property src_info {type:XDC file:1 line:85 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U8 [get_ports {sseg[4]}] +set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] set_property src_info {type:XDC file:1 line:86 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sseg[4]}] +set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V8 [get_ports {sseg[3]}] +set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sseg[3]}] +set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] set_property src_info {type:XDC file:1 line:89 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U5 [get_ports {sseg[2]}] +set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] set_property src_info {type:XDC file:1 line:90 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sseg[2]}] +set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] set_property src_info {type:XDC file:1 line:91 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V5 [get_ports {sseg[1]}] -set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sseg[1]}] +set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U7 [get_ports {sseg[0]}] +set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {sseg[0]}] +set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V7 [get_ports dp] +set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] set_property src_info {type:XDC file:1 line:97 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports dp] +set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7] +set_property src_info {type:XDC file:1 line:98 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8] set_property src_info {type:XDC file:1 line:99 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U2 [get_ports {digit[0]}] +set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {digit[0]}] -set_property src_info {type:XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U4 [get_ports {digit[1]}] +set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {digit[1]}] +set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] set_property src_info {type:XDC file:1 line:103 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V4 [get_ports {digit[2]}] +set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] set_property src_info {type:XDC file:1 line:104 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {digit[2]}] +set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] set_property src_info {type:XDC file:1 line:105 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN W4 [get_ports {digit[3]}] +set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS33 [get_ports {digit[3]}] +set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +set_property src_info {type:XDC file:1 line:107 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] +set_property src_info {type:XDC file:1 line:108 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +set_property src_info {type:XDC file:1 line:109 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] +set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +set_property src_info {type:XDC file:1 line:112 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +set_property src_info {type:XDC file:1 line:116 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] +set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +set_property src_info {type:XDC file:1 line:121 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +set_property src_info {type:XDC file:1 line:122 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +set_property src_info {type:XDC file:1 line:123 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] +set_property src_info {type:XDC file:1 line:124 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +set_property src_info {type:XDC file:1 line:125 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +set_property src_info {type:XDC file:1 line:126 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +set_property src_info {type:XDC file:1 line:127 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] +set_property src_info {type:XDC file:1 line:128 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +set_property src_info {type:XDC file:1 line:129 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +set_property src_info {type:XDC file:1 line:130 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +set_property src_info {type:XDC file:1 line:131 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] +set_property src_info {type:XDC file:1 line:132 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs +set_property src_info {type:XDC file:1 line:133 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs +set_property src_info {type:XDC file:1 line:135 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +set_property src_info {type:XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +set_property src_info {type:XDC file:1 line:137 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +set_property src_info {type:XDC file:1 line:138 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd +set_property src_info {type:XDC file:1 line:139 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +set_property src_info {type:XDC file:1 line:140 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +set_property src_info {type:XDC file:1 line:141 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +set_property src_info {type:XDC file:1 line:142 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] +set_property src_info {type:XDC file:1 line:144 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +set_property src_info {type:XDC file:1 line:145 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +set_property src_info {type:XDC file:1 line:146 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +set_property src_info {type:XDC file:1 line:147 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +set_property src_info {type:XDC file:1 line:148 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +set_property src_info {type:XDC file:1 line:149 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] +set_property src_info {type:XDC file:1 line:151 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +set_property src_info {type:XDC file:1 line:152 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +set_property src_info {type:XDC file:1 line:153 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +set_property src_info {type:XDC file:1 line:154 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct +set_property src_info {type:XDC file:1 line:156 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk +set_property src_info {type:XDC file:1 line:157 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data +set_property src_info {type:XDC file:1 line:158 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel +set_property src_info {type:XDC file:1 line:160 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm +set_property src_info {type:XDC file:1 line:161 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd +set_property src_info {type:XDC file:1 line:163 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property src_info {type:XDC file:1 line:164 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +set_property src_info {type:XDC file:1 line:165 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +set_property src_info {type:XDC file:1 line:166 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts +set_property src_info {type:XDC file:1 line:168 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +set_property src_info {type:XDC file:1 line:169 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data +set_property src_info {type:XDC file:1 line:171 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +set_property src_info {type:XDC file:1 line:172 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +set_property src_info {type:XDC file:1 line:173 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +set_property src_info {type:XDC file:1 line:174 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +set_property src_info {type:XDC file:1 line:175 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +set_property src_info {type:XDC file:1 line:176 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +set_property src_info {type:XDC file:1 line:177 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +set_property src_info {type:XDC file:1 line:178 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +set_property src_info {type:XDC file:1 line:179 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +set_property src_info {type:XDC file:1 line:180 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +set_property src_info {type:XDC file:1 line:181 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +set_property src_info {type:XDC file:1 line:182 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn +set_property src_info {type:XDC file:1 line:184 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +set_property src_info {type:XDC file:1 line:185 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +set_property src_info {type:XDC file:1 line:186 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +set_property src_info {type:XDC file:1 line:187 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +set_property src_info {type:XDC file:1 line:188 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn diff --git a/fpga/constraints/fpga_lab_constr_nexys_A7_100T.xdc b/fpga/constraints/fpga_lab_constr_nexys_A7_100T.xdc new file mode 100644 index 0000000..e852a2c --- /dev/null +++ b/fpga/constraints/fpga_lab_constr_nexys_A7_100T.xdc @@ -0,0 +1,188 @@ +# This file is a general .xdc for the Nexys A7-100T +# To use it in a project: +# - uncomment the lines corresponding to used pins +# - rename the used ports (in each line, after get_ports) according to the top level signal names in the project +# Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}]; +#Switches +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] +# leds +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +# RGB leds +set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b +set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g +set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_G }]; #IO_0_14 Sch=led17_g +set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r +#7 segment display +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] +#Buttons +set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc +set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu +set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl +set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd +#Pmod Headers +#Pmod Header JA +set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] +#Pmod Header JB +set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] +set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] +#Pmod Header JC +set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] +set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] +set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] +set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7] +set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8] +set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] +#Pmod Header JD +set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] +set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] +set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] +set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] +set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] +#Pmod Header JXADC +set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] +#VGA Connector +set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] +set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] +set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] +set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs +set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs +#Micro SD Connector +set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd +set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] +#Accelerometer +set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] +#Temperature Sensor +set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct +#Omnidirectional Microphone +set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk +set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data +set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel +#PWM Audio Amplifier +set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm +set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd +#USB-RS232 Interface +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts +#USB HID (PS/2) +set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data +#SMSC Ethernet PHY +set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn +#Quad SPI Flash +set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn \ No newline at end of file diff --git a/fpga/run.tcl b/fpga/run.tcl index f396dd9..0cef516 100644 --- a/fpga/run.tcl +++ b/fpga/run.tcl @@ -8,34 +8,37 @@ set fp [open "tmp.txt" r] set content [read $fp] close $fp set lines [split $content \n] -set file_name [lindex $lines 0] -set part_name [lindex $lines 1] -set cons_name [lindex $lines 2] +set file_name [lindex $lines 0] +set part_name [lindex $lines 1] +set cons_name [lindex $lines 2] set shell_path [lindex $lines 3] +set board [lindex $lines 4] # -# STEP#1: define output directory area. +# STEP#1: define output and input directory area. # -set outputDir ./out_${file_name}_${part_name}/FPGA_${file_name} +# set outputDir ./out_${file_name}_${part_name}/FPGA_${file_name} +set outputDir ./../out/${board}/${file_name}/Output +set inputDir ./../out/${board}/${file_name}/Dependencies file mkdir $outputDir # # STEP#2: setup design sources and constraints # -read_verilog ./out_${file_name}_${part_name}/${file_name}.v -read_verilog ./out_${file_name}_${part_name}/includes/proj_verilog/clk_gate.v +read_verilog $inputDir/${file_name}.v +read_verilog $inputDir/includes/proj_verilog/clk_gate.v #read_verilog ${shell_path}/../../includes/clock_divider.v #set_property -include_dirs {./out_${file_name}_${part_name}/includes/* ./out_${file_name}_${part_name}/includes/proj_verilog/* ./out_${file_name}_${part_name}/includes/proj_default/*} [current_fileset] read_xdc $cons_name -read_xdc ./out_${file_name}_${part_name}/clock_constraints.xdc +read_xdc $inputDir/clock_constraints.xdc # # STEP#3: run synthesis, report utilization and timing estimates, write checkpoint design # set multi_include_dirs " \ -./out_${file_name}_${part_name}/includes \ -./out_${file_name}_${part_name}/includes/proj_verilog \ -./out_${file_name}_${part_name}/includes/proj_default \ +$inputDir/includes \ +$inputDir/includes/proj_verilog \ +$inputDir/includes/proj_default \ " synth_design -top top -part $part_name -retiming -include_dirs $multi_include_dirs file mkdir $outputDir/syn/reports @@ -122,7 +125,7 @@ write_bitstream -force $outputDir/$file_name.bit # # STEP#7: connect to your board # -open_hw +open_hw_manager connect_hw_server open_hw_target #current_hw_device [lindex [get_hw_devices] 0] diff --git a/out/basys3/led_counter/Dependencies/clock_constraints.xdc b/out/basys3/led_counter/Dependencies/clock_constraints.xdc new file mode 100644 index 0000000..414fe4b --- /dev/null +++ b/out/basys3/led_counter/Dependencies/clock_constraints.xdc @@ -0,0 +1,3 @@ +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] diff --git a/out/basys3/led_counter/Dependencies/includes/proj_default/clk_gate.sv b/out/basys3/led_counter/Dependencies/includes/proj_default/clk_gate.sv new file mode 100644 index 0000000..e028887 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/proj_default/clk_gate.sv @@ -0,0 +1,38 @@ +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Clock gate module used by SandPiper default project. + +// Note: No X injection for X on free_clk.) +module clk_gate (output logic gated_clk, input logic free_clk, func_en, pwr_en, gating_override); + logic clk_en; + logic latched_clk_en /*verilator clock_enable*/; + always_comb clk_en = func_en & (pwr_en | gating_override); + always_latch if (~free_clk) latched_clk_en <= clk_en; + // latched_clk_en <= (~free_clk) ? clk_en : latched_clk_en; + always_comb gated_clk = latched_clk_en & free_clk; +endmodule diff --git a/out/basys3/led_counter/Dependencies/includes/proj_default/sp_default.vh b/out/basys3/led_counter/Dependencies/includes/proj_default/sp_default.vh new file mode 100644 index 0000000..a733969 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/proj_default/sp_default.vh @@ -0,0 +1,8 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +`endif // SP_DEFAULT diff --git a/out/basys3/led_counter/Dependencies/includes/proj_verilog/clk_gate.v b/out/basys3/led_counter/Dependencies/includes/proj_verilog/clk_gate.v new file mode 100644 index 0000000..5afd28f --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/proj_verilog/clk_gate.v @@ -0,0 +1,39 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +`include "sp_verilog.vh" + + +// Clock gate module used by SandPiper default project. + +module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override); + wire clk_en; + reg latched_clk_en /*verilator clock_enable*/; + assign clk_en = func_en & (pwr_en | gating_override); + `TLV_BLATCH(latched_clk_en, clk_en, free_clk) + assign gated_clk = latched_clk_en & free_clk; +endmodule diff --git a/out/basys3/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh b/out/basys3/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh new file mode 100644 index 0000000..0c28412 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh @@ -0,0 +1,65 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +// Latch macros. Inject 'x in simulation for clk === 'x. + +// A-phase latch. +`ifdef SP_PHYS +`define TLV_LATCH(in, out, clk) \ +always @ (in, clk) begin \ + if (clk === 1'b1) \ + out <= in; \ + else if (clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_LATCH(in, out, clk) always @ (in, clk) if (clk == 1'b1) out <= in; +`endif // SP_PHYS + +// B-phase latch. +`ifdef SP_PHYS +`define TLV_BLATCH(out, in, clk) \ +always @ (in, clk) begin \ + if (!clk === 1'b1) \ + out <= in; \ + else if (!clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_BLATCH(out, in, clk) always @ (in, clk) if (!clk == 1'b1) out <= in; +`endif // SP_PHYS + + + +`endif // SP_DEFAULT diff --git a/out/basys3/led_counter/Dependencies/includes/pseudo_rand.tlv b/out/basys3/led_counter/Dependencies/includes/pseudo_rand.tlv new file mode 100644 index 0000000..cb0d614 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/pseudo_rand.tlv @@ -0,0 +1,69 @@ +\m4_TLV_version 1b: tl-x.org +\SV +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +module pseudo_rand + #(parameter WIDTH=257) // Random vector width, to a max of 257. + (input logic clk, + input logic reset, + output logic [WIDTH-1:0] rand_vect + ); + +// Currently, this implements a Galois LFSR. +// TODO: It should be XORed with something else so it doesn't just shift. +// Using polynomials with maximal number of taps would have less regular shifting behavior. + +// Bits are numbered in the reverse of the traditional order. This puts the taps in the lower bit positions. + +// Choose optimal parameters for given WIDTH. +localparam LFSR_WIDTH = + (WIDTH <= 64) ? 64 : + (WIDTH <= 128) ? 128 : + (WIDTH <= 257) ? 257 : 0; // 257 enables a large non-power of two for replication on an irregular boundary. +// Polynomial source: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf +localparam [LFSR_WIDTH-1:0] LFSR_POLY = {{(LFSR_WIDTH-8){1'b0}}, + (LFSR_WIDTH == 64) ? 8'b00011011 : + (LFSR_WIDTH == 128) ? 8'b10000111 : + (LFSR_WIDTH == 257) ? 8'b11000101 : 8'b0}; + +bit [256:0] SEED = 257'h0_7163e168_713d5431_6684e132_5cd84848_f3048b46_76874654_0c45f864_04e4684a; + + + +\TLV + |default + @0 + $reset = reset; + @1 + $lfsr[LFSR_WIDTH-1:0] = $reset ? *SEED : {$lfsr#+1[LFSR_WIDTH-2:0], 1'b0} ^ ({LFSR_WIDTH{$lfsr#+1[LFSR_WIDTH-1]}} & *LFSR_POLY); + @2 + *rand_vect = $lfsr[WIDTH-1:0]; + +\SV + +endmodule diff --git a/out/basys3/led_counter/Dependencies/includes/rw_lib.vh b/out/basys3/led_counter/Dependencies/includes/rw_lib.vh new file mode 100644 index 0000000..39d5cd5 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/rw_lib.vh @@ -0,0 +1 @@ +`define RW_ZX(in, width) {{width-$width(in){1'b0}}, in} diff --git a/out/basys3/led_counter/Dependencies/includes/sandhost/README.txt b/out/basys3/led_counter/Dependencies/includes/sandhost/README.txt new file mode 100644 index 0000000..1816fee --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/sandhost/README.txt @@ -0,0 +1 @@ +Veriog include files that are available only within Makerchip. diff --git a/out/basys3/led_counter/Dependencies/includes/sandhost/sqrt32.v b/out/basys3/led_counter/Dependencies/includes/sandhost/sqrt32.v new file mode 100644 index 0000000..23e5dbc --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/sandhost/sqrt32.v @@ -0,0 +1,13 @@ +// A non-synthesizable Verilog-2005 sqrt function for tutorials. +`ifndef RW_NON_SYNTH_SQRT +`define RW_NON_SYNTH_SQRT + +function [31:0] sqrt; + input [31:0] a; + + /* verilator lint_off REALCVT */ + sqrt = $sqrt(a); + /* verilator lint_on REALCVT */ +endfunction + +`endif diff --git a/out/basys3/led_counter/Dependencies/includes/sandhost/tb.sv b/out/basys3/led_counter/Dependencies/includes/sandhost/tb.sv new file mode 100644 index 0000000..187fa4f --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/sandhost/tb.sv @@ -0,0 +1,76 @@ +// Provides clk and reset to design.tlv. +// Instantiates design as design(.*) so additional inputs and outputs can be added. +// Ends simulation on max cycles argument below, or assertion of success signal. +// Additional testbench functionality can be added here, or within design using TLV. +// See: "top_module_tlv.m4" for definition. + +// ------------------------------------------------------------------- +// Expanded from instantiation: m4_top_module_inst(m4_name, m4_max_cycles) +// + +module tb(); + +logic clk, reset; // Generated in this module for DUT. +logic passed, failed; // Returned from DUT to this module. Passed must assert before + // max cycles, without failed having asserted. Failed can be undriven. +logic [15:0] cyc_cnt; + + +// Instantiate main module. +top top(.*); + + +// Clock +initial begin + clk = 1'b1; + forever #5 clk = ~clk; +end + + +// Run +initial begin + + //`ifdef DUMP_ON + $dumpfile("top.vcd"); + $dumpvars(0, clk, reset, passed, failed, cyc_cnt, top.DEBUG_SIGS); + $dumpon; + //`endif + + reset = 1'b1; + #55; + reset = 1'b0; + + // Run + + cyc_cnt = '0; + for (int cyc = 0; cyc < 100; cyc++) begin + // Failed + if (failed === 1'b1) begin + FAILED: assert(1'b1) begin + $display("Failed!!! Error condition asserted."); + $finish; + end + end + + // Success + if (passed) begin + SUCCESS: assert(1'b1) begin + $display("Success!!!"); + $finish; + end + end + + #10; + + cyc_cnt++; + end + + // Fail + DIE: assert (1'b1) begin + $error("Failed!!! Test did not complete within m4_max_cycles time."); + $finish; + end + +end + +endmodule // life_tb diff --git a/out/basys3/led_counter/Dependencies/includes/sandpiper.vh b/out/basys3/led_counter/Dependencies/includes/sandpiper.vh new file mode 100644 index 0000000..26d3f19 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/sandpiper.vh @@ -0,0 +1,71 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Project-independent SandPiper header file. + +`ifndef SANDPIPER_VH +`define SANDPIPER_VH + + +// Note, these have no SP prefix, so collisions are possible. + + +`ifdef WHEN + // Make sure user definition does not collide. + !!!ERROR: WHEN macro already defined +`else + `ifdef SP_PHYS + // Phys compilation disabled X-injection. + `define WHEN(valid_sig) + `else + // Inject X. + `define WHEN(valid_sig) !valid_sig ? 'x : + `endif +`endif + + +// SandPiper does not generate set/reset flops. Reset is implemented as combinational +// logic, and it is up to synthesis to infer set/reset flops when possible. +//`ifdef RESET +// // Make sure user definition does not collide. +// !!!ERROR: RESET macro already defined +//`else +// `define RESET(i, reset) ((reset) ? '0 : i) +//`endif +// +//`ifdef SET +// // Make sure user definition does not collide. +// !!!ERROR: SET macro already defined +//`else +// `define SET(i, set) ((set) ? '1 : i) +//`endif + +// Since SandPiper required use of all signals, this is useful to create a +// bogus use and keep SandPiper happy when a signal, by intent, has no uses. +`define BOGUS_USE(ignore) + +`endif // SANDPIPER_VH diff --git a/out/basys3/led_counter/Dependencies/includes/sandpiper_gen.vh b/out/basys3/led_counter/Dependencies/includes/sandpiper_gen.vh new file mode 100644 index 0000000..d063661 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/sandpiper_gen.vh @@ -0,0 +1,4 @@ +// This just verifies that sandpiper.vh has been included. +`ifndef SANDPIPER_VH + !!!ERROR: SandPiper project's sp_.vh file must include sandpiper.vh. +`endif diff --git a/out/basys3/led_counter/Dependencies/includes/simple_bypass_fifo.sv b/out/basys3/led_counter/Dependencies/includes/simple_bypass_fifo.sv new file mode 100644 index 0000000..601c655 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/includes/simple_bypass_fifo.sv @@ -0,0 +1,98 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +`include "rw_lib.vh" + +// A simple implementation of a FIFO with bypass. +// Head is stored outside of the FIFO array. +// When the FIFO is empty, input goes straight through mux to output. +module simple_bypass_fifo( + input logic clk, + input logic reset, + input logic push, + input logic [WIDTH-1:0] data_in, // Timed with push. + input logic pop, // May pop in same cycle as push to empty FIFO. + output logic [WIDTH-1:0] data_out, // Same cycle as pop. + output logic [$clog2(DEPTH+1)-1:0] cnt // Reflecting push/pop last cycle. 0..DEPTH. +); + parameter WIDTH = 8; + parameter DEPTH = 8; + + logic [$clog2(DEPTH)-1:0] next_head, tail; + logic [WIDTH-1:0] arr [DEPTH-1:0], arr_out, head_data; + logic cnt_zero_or_one, cnt_zero, cnt_one; + logic push_arr, push_head, pop_from_arr, popped_from_arr; + + always_ff @(posedge clk) begin + if (reset) begin + tail <= {$clog2(DEPTH){1'b0}}; + next_head <= {$clog2(DEPTH){1'b0}}; + cnt <= {$clog2(DEPTH+1){1'b0}}; + end else begin + if (push_arr + ) begin + arr[tail] <= data_in; + tail <= tail + {{$clog2(DEPTH)-1{1'b0}}, 1'b1}; + end + if (pop) begin + arr_out <= arr[next_head]; + next_head <= next_head + {{$clog2(DEPTH)-1{1'b0}}, 1'b1}; + end + if (push ^ pop) begin + cnt <= cnt + (push ? {{$clog2(DEPTH+1)-1{1'b0}}, 1'b1} /* 1 */ : {$clog2(DEPTH+1){1'b1}} /* -1 */); + end + end + end + always_comb begin + // Control signals + + // These are timed with cnt (cycle after push/pop) + cnt_zero_or_one = (cnt >> 1) == {$clog2(DEPTH+1){1'b0}}; + cnt_zero = cnt_zero_or_one && ~cnt[0]; + cnt_one = cnt_zero_or_one && cnt[0]; + + // These are timed with push/pop + // Cases in which a push would not got into array. + push_arr = push && !(cnt_zero || (cnt_zero_or_one && pop)); + push_head = push && (pop ? cnt_one : cnt_zero); + pop_from_arr = pop && !cnt_zero_or_one; + + // Output data + data_out = cnt_zero ? data_in : head_data; + end + + // Head + always_ff @(posedge clk) begin + popped_from_arr <= pop_from_arr; + if (push_head) begin + head_data <= data_in; + end else if (popped_from_arr) begin + head_data <= arr_out; + end + end +endmodule diff --git a/out/basys3/led_counter/Dependencies/led_counter.v b/out/basys3/led_counter/Dependencies/led_counter.v new file mode 100644 index 0000000..88607c6 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/led_counter.v @@ -0,0 +1,345 @@ +//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta +`include "sp_verilog.vh" //_\SV + // Included URL: "https://raw.githubusercontent.com/BalaDhinesh/Virtual-FPGA-Lab/main/tlv_lib/fpga_includes.tlv" +//_\SV + + + + + module top(input clk, input reset, output reg [15:0] led); + + +`include "led_counter_gen.v" +generate //_\TLV + //_|led_pipe + //_@0 + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 3 // Instantiated from led_counter.tlv, 15 as: m4+fpga_refresh($refresh, m4_ifelse(M4_MAKERCHIP, 1, 1, 50000000)) + /* verilator lint_off UNSIGNED */ + assign LED_PIPE_rst1_a0 = reset; + assign LED_PIPE_count1_a0[31:0] = (LED_PIPE_count1_a1[31:0] >= 50000000 - 1) | LED_PIPE_rst1_a1 ? 1'b0 : LED_PIPE_count1_a1[31:0] + 1 ; + assign LED_PIPE_refresh_a0 = (LED_PIPE_count1_a0 == 50000000 - 1) ? 1'b1 : 1'b0 ; + + //_\end_source + assign LED_PIPE_reset_a0 = reset; + //_?$refresh + assign LED_PIPE_Leds_n1[15:0] = LED_PIPE_reset_a0 ? 1 : LED_PIPE_Leds_a0+1; + /*SV_plus*/ + always@(posedge clk) begin + led = LED_PIPE_Leds_a0; + end + // M4_BOARD numbering + // 1 - Zedboard + // 2 - Artix-7 + // 3 - Basys3 + // 4 - Icebreaker + // 5 - Nexys + + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 32 // Instantiated from led_counter.tlv, 30 as: m4+fpga_init() + //m4+osfpga_logo() + //_|fpga_init_macro + //_@0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + //_\end_source + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 245 // Instantiated from led_counter.tlv, 31 as: m4+fpga_led(*led) + //_|led_pipe_macro + //_@0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + //_\end_source +endgenerate +//_\SV + endmodule diff --git a/out/basys3/led_counter/Dependencies/led_counter_gen.v b/out/basys3/led_counter/Dependencies/led_counter_gen.v new file mode 100644 index 0000000..fc366a2 --- /dev/null +++ b/out/basys3/led_counter/Dependencies/led_counter_gen.v @@ -0,0 +1,81 @@ +// Generated by SandPiper(TM) 1.11-2021/01/28-beta from Redwood EDA. +// Redwood EDA does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality. + + +`include "sandpiper_gen.vh" + + + + + +// +// Signals declared top-level. +// + +// For |led_pipe$Leds. +wire [15:0] LED_PIPE_Leds_n1; +reg [15:0] LED_PIPE_Leds_a0; + +// For |led_pipe$count1. +wire [31:0] LED_PIPE_count1_a0; +reg [31:0] LED_PIPE_count1_a1; + +// For |led_pipe$refresh. +wire LED_PIPE_refresh_a0; + +// For |led_pipe$reset. +wire LED_PIPE_reset_a0; + +// For |led_pipe$rst1. +wire LED_PIPE_rst1_a0; +reg LED_PIPE_rst1_a1; + + +// +// Scope: |led_pipe +// + +// Clock signals. +wire clkF_LED_PIPE_refresh_a1 ; + + +generate + + + // + // Scope: |led_pipe + // + + // For $Leds. + always @(posedge clkF_LED_PIPE_refresh_a1) LED_PIPE_Leds_a0[15:0] <= LED_PIPE_Leds_n1[15:0]; + + // For $count1. + always @(posedge clk) LED_PIPE_count1_a1[31:0] <= LED_PIPE_count1_a0[31:0]; + + // For $rst1. + always @(posedge clk) LED_PIPE_rst1_a1 <= LED_PIPE_rst1_a0; + + + + +endgenerate + + + +// +// Gated clocks. +// + +generate + + + + // + // Scope: |led_pipe + // + + clk_gate gen_clkF_LED_PIPE_refresh_a1(clkF_LED_PIPE_refresh_a1, clk, LED_PIPE_refresh_a0, 1'b1, 1'b0); + + + +endgenerate diff --git a/out/basys3/led_counter/Output/fpga_impl.xdc b/out/basys3/led_counter/Output/fpga_impl.xdc new file mode 100644 index 0000000..b3af9f9 --- /dev/null +++ b/out/basys3/led_counter/Output/fpga_impl.xdc @@ -0,0 +1,485 @@ + +#################################################################################### +# Generated by Vivado 2020.2 built on 'Wed Nov 18 09:12:47 MST 2020' by 'xbuild' +# Command Used: write_xdc -no_fixed_only -force ./../out/basys3/led_counter/Output/fpga_impl.xdc +#################################################################################### + + +#################################################################################### +# Constraints from file : 'fpga_lab_constr_basys3.xdc' +#################################################################################### + +## This file is a general .xdc for the Basys3 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +# Clock signal +set_property PACKAGE_PIN W5 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports clk] + +# Switches +set_property PACKAGE_PIN R2 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports reset] + + +# LEDs +set_property PACKAGE_PIN U16 [get_ports {led[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +set_property PACKAGE_PIN E19 [get_ports {led[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +set_property PACKAGE_PIN U19 [get_ports {led[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +set_property PACKAGE_PIN V19 [get_ports {led[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +set_property PACKAGE_PIN W18 [get_ports {led[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +set_property PACKAGE_PIN U15 [get_ports {led[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +set_property PACKAGE_PIN U14 [get_ports {led[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +set_property PACKAGE_PIN V14 [get_ports {led[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +set_property PACKAGE_PIN V13 [get_ports {led[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +set_property PACKAGE_PIN V3 [get_ports {led[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +set_property PACKAGE_PIN W3 [get_ports {led[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +set_property PACKAGE_PIN U3 [get_ports {led[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +set_property PACKAGE_PIN P3 [get_ports {led[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +set_property PACKAGE_PIN N3 [get_ports {led[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +set_property PACKAGE_PIN P1 [get_ports {led[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +set_property PACKAGE_PIN L1 [get_ports {led[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] + + +#7 segment display + + + + +##Buttons +#set_property PACKAGE_PIN U18 [get_ports btnC] +#set_property IOSTANDARD LVCMOS33 [get_ports btnC] +#set_property PACKAGE_PIN T18 [get_ports btnU] +#set_property IOSTANDARD LVCMOS33 [get_ports btnU] +#set_property PACKAGE_PIN W19 [get_ports btnL] +#set_property IOSTANDARD LVCMOS33 [get_ports btnL] +#set_property PACKAGE_PIN T17 [get_ports btnR] +#set_property IOSTANDARD LVCMOS33 [get_ports btnR] +#set_property PACKAGE_PIN U17 [get_ports btnD] +#set_property IOSTANDARD LVCMOS33 [get_ports btnD] + + + +##Pmod Header JA +##Sch name = JA1 +#set_property PACKAGE_PIN J1 [get_ports {JA[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +##Sch name = JA2 +#set_property PACKAGE_PIN L2 [get_ports {JA[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +##Sch name = JA3 +#set_property PACKAGE_PIN J2 [get_ports {JA[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +##Sch name = JA4 +#set_property PACKAGE_PIN G2 [get_ports {JA[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +##Sch name = JA7 +#set_property PACKAGE_PIN H1 [get_ports {JA[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +##Sch name = JA8 +#set_property PACKAGE_PIN K2 [get_ports {JA[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +##Sch name = JA9 +#set_property PACKAGE_PIN H2 [get_ports {JA[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +##Sch name = JA10 +#set_property PACKAGE_PIN G3 [get_ports {JA[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +##Sch name = JB1 +#set_property PACKAGE_PIN A14 [get_ports {JB[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +##Sch name = JB2 +#set_property PACKAGE_PIN A16 [get_ports {JB[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +##Sch name = JB3 +#set_property PACKAGE_PIN B15 [get_ports {JB[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +##Sch name = JB4 +#set_property PACKAGE_PIN B16 [get_ports {JB[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +##Sch name = JB7 +#set_property PACKAGE_PIN A15 [get_ports {JB[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +##Sch name = JB8 +#set_property PACKAGE_PIN A17 [get_ports {JB[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +##Sch name = JB9 +#set_property PACKAGE_PIN C15 [get_ports {JB[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +##Sch name = JB10 +#set_property PACKAGE_PIN C16 [get_ports {JB[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +##Sch name = JC1 +#set_property PACKAGE_PIN K17 [get_ports {JC[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +##Sch name = JC2 +#set_property PACKAGE_PIN M18 [get_ports {JC[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +##Sch name = JC3 +#set_property PACKAGE_PIN N17 [get_ports {JC[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +##Sch name = JC4 +#set_property PACKAGE_PIN P18 [get_ports {JC[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +##Sch name = JC7 +#set_property PACKAGE_PIN L17 [get_ports {JC[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +##Sch name = JC8 +#set_property PACKAGE_PIN M19 [get_ports {JC[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +##Sch name = JC9 +#set_property PACKAGE_PIN P17 [get_ports {JC[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +##Sch name = JC10 +#set_property PACKAGE_PIN R18 [get_ports {JC[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + +#Pmod Header JXADC +#Sch name = XA1_P +#set_property PACKAGE_PIN J3 [get_ports {vauxp6}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vauxp6}] +#Sch name = XA2_P +#set_property PACKAGE_PIN L3 [get_ports {vauxp14}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vauxp14}] +#Sch name = XA3_P +#set_property PACKAGE_PIN M2 [get_ports {vauxp7}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vauxp7}] +#Sch name = XA4_P +#set_property PACKAGE_PIN N2 [get_ports {vauxp15}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vauxp15}] +#Sch name = XA1_N +#set_property PACKAGE_PIN K3 [get_ports {vauxn6}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vauxn6}] +#Sch name = XA2_N +#set_property PACKAGE_PIN M3 [get_ports {vauxn14}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vauxn14}] +#Sch name = XA3_N +#set_property PACKAGE_PIN M1 [get_ports {vauxn7}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vauxn7}] +#Sch name = XA4_N +#set_property PACKAGE_PIN N1 [get_ports {vauxn15}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vauxn15}] + + + +##VGA Connector +#set_property PACKAGE_PIN G19 [get_ports {vga_r[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[0]}] +#set_property PACKAGE_PIN H19 [get_ports {vga_r[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[1]}] +#set_property PACKAGE_PIN J19 [get_ports {vga_r[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[2]}] +#set_property PACKAGE_PIN N19 [get_ports {vga_r[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[3]}] +#set_property PACKAGE_PIN N18 [get_ports {vga_b[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[0]}] +#set_property PACKAGE_PIN L18 [get_ports {vga_b[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[1]}] +#set_property PACKAGE_PIN K18 [get_ports {vga_b[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[2]}] +#set_property PACKAGE_PIN J18 [get_ports {vga_b[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[3]}] +#set_property PACKAGE_PIN J17 [get_ports {vga_g[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[0]}] +#set_property PACKAGE_PIN H17 [get_ports {vga_g[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[1]}] +#set_property PACKAGE_PIN G17 [get_ports {vga_g[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[2]}] +#set_property PACKAGE_PIN D17 [get_ports {vga_g[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[3]}] +#set_property PACKAGE_PIN P19 [get_ports vga_hsync] +#set_property IOSTANDARD LVCMOS33 [get_ports vga_hsync] +#set_property PACKAGE_PIN R19 [get_ports vga_vsync] +#set_property IOSTANDARD LVCMOS33 [get_ports vga_vsync] + + +##USB-RS232 Interface +#set_property PACKAGE_PIN B18 [get_ports RsRx] +#set_property IOSTANDARD LVCMOS33 [get_ports RsRx] +#set_property PACKAGE_PIN A18 [get_ports RsTx] +#set_property IOSTANDARD LVCMOS33 [get_ports RsTx] + + +##USB HID (PS/2) +#set_property PACKAGE_PIN C17 [get_ports PS2Clk] +#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] +#set_property PULLUP true [get_ports PS2Clk] +#set_property PACKAGE_PIN B17 [get_ports PS2Data] +#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] +#set_property PULLUP true [get_ports PS2Data] + + +##Quad SPI Flash +##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the +##STARTUPE2 primitive. +#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +#set_property PACKAGE_PIN K19 [get_ports QspiCSn] +#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + + + +#################################################################################### +# Constraints from file : 'clock_constraints.xdc' +#################################################################################### + +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] + + +# Vivado Generated physical constraints + +set_property BEL A6LUT [get_cells {LED_PIPE_Leds_a0[0]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[0]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[10]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[11]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[12]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[12]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[13]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[14]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[15]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[15]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[1]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[2]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[3]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[4]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[4]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[5]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[6]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[7]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[8]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[8]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[9]}] +set_property BEL A5LUT [get_cells {LED_PIPE_count1_a1[0]_i_1}] +set_property BEL C6LUT [get_cells {LED_PIPE_count1_a1[31]_i_1}] +set_property BEL A6LUT [get_cells {LED_PIPE_count1_a1[31]_i_4}] +set_property BEL A6LUT [get_cells {LED_PIPE_count1_a1[31]_i_5}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[0]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[10]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[11]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[12]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[12]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[13]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[14]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[15]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[16]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[16]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[17]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[18]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[19]}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[1]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[20]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[20]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[21]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[22]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[23]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[24]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[24]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[25]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[26]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[27]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[28]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[28]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[29]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[2]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[30]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[31]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[31]_i_2}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[3]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[4]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[4]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[5]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[6]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[7]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[8]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[8]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[9]}] +set_property BEL AFF [get_cells LED_PIPE_rst1_a1_reg] +set_property BEL BUFG [get_cells clk_IBUF_BUFG_inst] +set_property BEL INBUF_EN [get_cells clk_IBUF_inst] +set_property BEL C6LUT [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2}] +set_property BEL A6LUT [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_count1_a1[31]_i_3}] +set_property BEL AFF [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1] +set_property BEL D6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_10] +set_property BEL D6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_11] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_12] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_13] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_14] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_4] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_5] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_6] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8] +set_property BEL D6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_9] +set_property BEL OUTBUF [get_cells {led_OBUF[0]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[10]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[11]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[12]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[13]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[14]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[15]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[1]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[2]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[3]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[4]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[5]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[6]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[7]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[8]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[9]_inst}] +set_property BEL AFF [get_cells {led_reg[0]}] +set_property BEL AFF [get_cells {led_reg[10]}] +set_property BEL BFF [get_cells {led_reg[11]}] +set_property BEL AFF [get_cells {led_reg[12]}] +set_property BEL AFF [get_cells {led_reg[13]}] +set_property BEL BFF [get_cells {led_reg[14]}] +set_property BEL CFF [get_cells {led_reg[15]}] +set_property BEL BFF [get_cells {led_reg[1]}] +set_property BEL AFF [get_cells {led_reg[2]}] +set_property BEL AFF [get_cells {led_reg[3]}] +set_property BEL BFF [get_cells {led_reg[4]}] +set_property BEL CFF [get_cells {led_reg[5]}] +set_property BEL AFF [get_cells {led_reg[6]}] +set_property BEL BFF [get_cells {led_reg[7]}] +set_property BEL CFF [get_cells {led_reg[8]}] +set_property BEL CFF [get_cells {led_reg[9]}] +set_property BEL INBUF_EN [get_cells reset_IBUF_inst] +set_property LOC SLICE_X64Y46 [get_cells {LED_PIPE_Leds_a0[0]_i_1}] +set_property LOC SLICE_X64Y46 [get_cells {LED_PIPE_Leds_a0_reg[0]}] +set_property LOC SLICE_X63Y48 [get_cells {LED_PIPE_Leds_a0_reg[10]}] +set_property LOC SLICE_X63Y48 [get_cells {LED_PIPE_Leds_a0_reg[11]}] +set_property LOC SLICE_X63Y48 [get_cells {LED_PIPE_Leds_a0_reg[12]}] +set_property LOC SLICE_X63Y48 [get_cells {LED_PIPE_Leds_a0_reg[12]_i_1}] +set_property LOC SLICE_X63Y49 [get_cells {LED_PIPE_Leds_a0_reg[13]}] +set_property LOC SLICE_X63Y49 [get_cells {LED_PIPE_Leds_a0_reg[14]}] +set_property LOC SLICE_X63Y49 [get_cells {LED_PIPE_Leds_a0_reg[15]}] +set_property LOC SLICE_X63Y49 [get_cells {LED_PIPE_Leds_a0_reg[15]_i_1}] +set_property LOC SLICE_X63Y46 [get_cells {LED_PIPE_Leds_a0_reg[1]}] +set_property LOC SLICE_X63Y46 [get_cells {LED_PIPE_Leds_a0_reg[2]}] +set_property LOC SLICE_X63Y46 [get_cells {LED_PIPE_Leds_a0_reg[3]}] +set_property LOC SLICE_X63Y46 [get_cells {LED_PIPE_Leds_a0_reg[4]}] +set_property LOC SLICE_X63Y46 [get_cells {LED_PIPE_Leds_a0_reg[4]_i_1}] +set_property LOC SLICE_X63Y47 [get_cells {LED_PIPE_Leds_a0_reg[5]}] +set_property LOC SLICE_X63Y47 [get_cells {LED_PIPE_Leds_a0_reg[6]}] +set_property LOC SLICE_X63Y47 [get_cells {LED_PIPE_Leds_a0_reg[7]}] +set_property LOC SLICE_X63Y47 [get_cells {LED_PIPE_Leds_a0_reg[8]}] +set_property LOC SLICE_X63Y47 [get_cells {LED_PIPE_Leds_a0_reg[8]_i_1}] +set_property LOC SLICE_X63Y48 [get_cells {LED_PIPE_Leds_a0_reg[9]}] +set_property LOC SLICE_X63Y45 [get_cells {LED_PIPE_count1_a1[0]_i_1}] +set_property LOC SLICE_X64Y48 [get_cells {LED_PIPE_count1_a1[31]_i_1}] +set_property LOC SLICE_X63Y45 [get_cells {LED_PIPE_count1_a1[31]_i_4}] +set_property LOC SLICE_X63Y44 [get_cells {LED_PIPE_count1_a1[31]_i_5}] +set_property LOC SLICE_X63Y44 [get_cells {LED_PIPE_count1_a1_reg[0]}] +set_property LOC SLICE_X62Y46 [get_cells {LED_PIPE_count1_a1_reg[10]}] +set_property LOC SLICE_X62Y46 [get_cells {LED_PIPE_count1_a1_reg[11]}] +set_property LOC SLICE_X62Y46 [get_cells {LED_PIPE_count1_a1_reg[12]}] +set_property LOC SLICE_X62Y46 [get_cells {LED_PIPE_count1_a1_reg[12]_i_1}] +set_property LOC SLICE_X62Y47 [get_cells {LED_PIPE_count1_a1_reg[13]}] +set_property LOC SLICE_X62Y47 [get_cells {LED_PIPE_count1_a1_reg[14]}] +set_property LOC SLICE_X62Y47 [get_cells {LED_PIPE_count1_a1_reg[15]}] +set_property LOC SLICE_X62Y47 [get_cells {LED_PIPE_count1_a1_reg[16]}] +set_property LOC SLICE_X62Y47 [get_cells {LED_PIPE_count1_a1_reg[16]_i_1}] +set_property LOC SLICE_X62Y48 [get_cells {LED_PIPE_count1_a1_reg[17]}] +set_property LOC SLICE_X62Y48 [get_cells {LED_PIPE_count1_a1_reg[18]}] +set_property LOC SLICE_X62Y48 [get_cells {LED_PIPE_count1_a1_reg[19]}] +set_property LOC SLICE_X62Y44 [get_cells {LED_PIPE_count1_a1_reg[1]}] +set_property LOC SLICE_X62Y48 [get_cells {LED_PIPE_count1_a1_reg[20]}] +set_property LOC SLICE_X62Y48 [get_cells {LED_PIPE_count1_a1_reg[20]_i_1}] +set_property LOC SLICE_X62Y49 [get_cells {LED_PIPE_count1_a1_reg[21]}] +set_property LOC SLICE_X62Y49 [get_cells {LED_PIPE_count1_a1_reg[22]}] +set_property LOC SLICE_X62Y49 [get_cells {LED_PIPE_count1_a1_reg[23]}] +set_property LOC SLICE_X62Y49 [get_cells {LED_PIPE_count1_a1_reg[24]}] +set_property LOC SLICE_X62Y49 [get_cells {LED_PIPE_count1_a1_reg[24]_i_1}] +set_property LOC SLICE_X62Y50 [get_cells {LED_PIPE_count1_a1_reg[25]}] +set_property LOC SLICE_X62Y50 [get_cells {LED_PIPE_count1_a1_reg[26]}] +set_property LOC SLICE_X62Y50 [get_cells {LED_PIPE_count1_a1_reg[27]}] +set_property LOC SLICE_X62Y50 [get_cells {LED_PIPE_count1_a1_reg[28]}] +set_property LOC SLICE_X62Y50 [get_cells {LED_PIPE_count1_a1_reg[28]_i_1}] +set_property LOC SLICE_X62Y51 [get_cells {LED_PIPE_count1_a1_reg[29]}] +set_property LOC SLICE_X62Y44 [get_cells {LED_PIPE_count1_a1_reg[2]}] +set_property LOC SLICE_X62Y51 [get_cells {LED_PIPE_count1_a1_reg[30]}] +set_property LOC SLICE_X62Y51 [get_cells {LED_PIPE_count1_a1_reg[31]}] +set_property LOC SLICE_X62Y51 [get_cells {LED_PIPE_count1_a1_reg[31]_i_2}] +set_property LOC SLICE_X62Y44 [get_cells {LED_PIPE_count1_a1_reg[3]}] +set_property LOC SLICE_X62Y44 [get_cells {LED_PIPE_count1_a1_reg[4]}] +set_property LOC SLICE_X62Y44 [get_cells {LED_PIPE_count1_a1_reg[4]_i_1}] +set_property LOC SLICE_X62Y45 [get_cells {LED_PIPE_count1_a1_reg[5]}] +set_property LOC SLICE_X62Y45 [get_cells {LED_PIPE_count1_a1_reg[6]}] +set_property LOC SLICE_X62Y45 [get_cells {LED_PIPE_count1_a1_reg[7]}] +set_property LOC SLICE_X62Y45 [get_cells {LED_PIPE_count1_a1_reg[8]}] +set_property LOC SLICE_X62Y45 [get_cells {LED_PIPE_count1_a1_reg[8]_i_1}] +set_property LOC SLICE_X62Y46 [get_cells {LED_PIPE_count1_a1_reg[9]}] +set_property LOC SLICE_X64Y48 [get_cells LED_PIPE_rst1_a1_reg] +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] +set_property LOC SLICE_X64Y46 [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2}] +set_property LOC SLICE_X63Y50 [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_count1_a1[31]_i_3}] +set_property LOC SLICE_X65Y48 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg] +set_property LOC SLICE_X65Y48 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1] +set_property LOC SLICE_X63Y45 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_10] +set_property LOC SLICE_X64Y48 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_11] +set_property LOC SLICE_X64Y47 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_12] +set_property LOC SLICE_X63Y45 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_13] +set_property LOC SLICE_X60Y46 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_14] +set_property LOC SLICE_X65Y48 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3] +set_property LOC SLICE_X64Y47 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_4] +set_property LOC SLICE_X64Y48 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_5] +set_property LOC SLICE_X65Y46 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_6] +set_property LOC SLICE_X65Y48 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7] +set_property LOC SLICE_X64Y47 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8] +set_property LOC SLICE_X65Y48 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_9] +set_property LOC SLICE_X62Y43 [get_cells {led_reg[0]}] +set_property LOC SLICE_X65Y47 [get_cells {led_reg[10]}] +set_property LOC SLICE_X65Y47 [get_cells {led_reg[11]}] +set_property LOC SLICE_X64Y52 [get_cells {led_reg[12]}] +set_property LOC SLICE_X64Y54 [get_cells {led_reg[13]}] +set_property LOC SLICE_X64Y52 [get_cells {led_reg[14]}] +set_property LOC SLICE_X64Y52 [get_cells {led_reg[15]}] +set_property LOC SLICE_X62Y43 [get_cells {led_reg[1]}] +set_property LOC SLICE_X62Y40 [get_cells {led_reg[2]}] +set_property LOC SLICE_X60Y46 [get_cells {led_reg[3]}] +set_property LOC SLICE_X60Y46 [get_cells {led_reg[4]}] +set_property LOC SLICE_X62Y43 [get_cells {led_reg[5]}] +set_property LOC SLICE_X63Y45 [get_cells {led_reg[6]}] +set_property LOC SLICE_X63Y45 [get_cells {led_reg[7]}] +set_property LOC SLICE_X63Y45 [get_cells {led_reg[8]}] +set_property LOC SLICE_X65Y47 [get_cells {led_reg[9]}] + +# Vivado Generated miscellaneous constraints + +#revert back to original instance +current_instance -quiet diff --git a/out/basys3/led_counter/Output/fpga_impl_netlist.v b/out/basys3/led_counter/Output/fpga_impl_netlist.v new file mode 100644 index 0000000..54ace19 --- /dev/null +++ b/out/basys3/led_counter/Output/fpga_impl_netlist.v @@ -0,0 +1,928 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Sat Oct 30 02:46:35 2021 +// Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +// Command : write_verilog -force ./../out/basys3/led_counter/Output/fpga_impl_netlist.v +// Design : top +// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an +// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input +// design files. +// Device : xc7a35tcpg236-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module clk_gate + (\LED_PIPE_count1_a1_reg[11] , + \LED_PIPE_count1_a1_reg[24] , + \LED_PIPE_count1_a1_reg[28] , + CLK, + LED_PIPE_count1_a1, + O, + latched_clk_en_reg_i_6_0, + latched_clk_en_reg_i_3_0, + latched_clk_en_reg_i_6_1, + latched_clk_en_reg_i_3_1, + latched_clk_en_reg_i_3_2, + latched_clk_en_reg_i_3_3, + latched_clk_en_reg_i_3_4, + LED_PIPE_rst1_a1, + clk_IBUF, + clk_IBUF_BUFG); + output \LED_PIPE_count1_a1_reg[11] ; + output \LED_PIPE_count1_a1_reg[24] ; + output \LED_PIPE_count1_a1_reg[28] ; + output CLK; + input [25:0]LED_PIPE_count1_a1; + input [3:0]O; + input [3:0]latched_clk_en_reg_i_6_0; + input [3:0]latched_clk_en_reg_i_3_0; + input [3:0]latched_clk_en_reg_i_6_1; + input [3:0]latched_clk_en_reg_i_3_1; + input [3:0]latched_clk_en_reg_i_3_2; + input [3:0]latched_clk_en_reg_i_3_3; + input [2:0]latched_clk_en_reg_i_3_4; + input LED_PIPE_rst1_a1; + input clk_IBUF; + input clk_IBUF_BUFG; + + wire CLK; + wire GND_1; + wire [25:0]LED_PIPE_count1_a1; + wire \LED_PIPE_count1_a1_reg[11] ; + wire \LED_PIPE_count1_a1_reg[24] ; + wire \LED_PIPE_count1_a1_reg[28] ; + wire LED_PIPE_refresh_a0; + wire LED_PIPE_rst1_a1; + wire [3:0]O; + wire VCC_1; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire latched_clk_en; + wire latched_clk_en_reg_i_10_n_0; + wire latched_clk_en_reg_i_11_n_0; + wire latched_clk_en_reg_i_12_n_0; + wire latched_clk_en_reg_i_13_n_0; + wire latched_clk_en_reg_i_14_n_0; + wire [3:0]latched_clk_en_reg_i_3_0; + wire [3:0]latched_clk_en_reg_i_3_1; + wire [3:0]latched_clk_en_reg_i_3_2; + wire [3:0]latched_clk_en_reg_i_3_3; + wire [2:0]latched_clk_en_reg_i_3_4; + wire latched_clk_en_reg_i_3_n_0; + wire [3:0]latched_clk_en_reg_i_6_0; + wire [3:0]latched_clk_en_reg_i_6_1; + wire latched_clk_en_reg_i_6_n_0; + wire latched_clk_en_reg_i_7_n_0; + wire latched_clk_en_reg_i_8_n_0; + wire latched_clk_en_reg_i_9_n_0; + + GND GND + (.G(GND_1)); + LUT2 #( + .INIT(4'h8)) + \LED_PIPE_Leds_a0[15]_i_2 + (.I0(latched_clk_en), + .I1(clk_IBUF), + .O(CLK)); + LUT6 #( + .INIT(64'h0000000000000001)) + \LED_PIPE_count1_a1[31]_i_3 + (.I0(LED_PIPE_count1_a1[22]), + .I1(LED_PIPE_count1_a1[23]), + .I2(LED_PIPE_count1_a1[20]), + .I3(LED_PIPE_count1_a1[21]), + .I4(LED_PIPE_count1_a1[25]), + .I5(LED_PIPE_count1_a1[24]), + .O(\LED_PIPE_count1_a1_reg[28] )); + VCC VCC + (.P(VCC_1)); + (* OPT_MODIFIED = "MLO" *) + (* XILINX_LEGACY_PRIM = "LD" *) + LDCE #( + .INIT(1'b0), + .IS_G_INVERTED(1'b1)) + latched_clk_en_reg + (.CLR(GND_1), + .D(LED_PIPE_refresh_a0), + .G(clk_IBUF_BUFG), + .GE(VCC_1), + .Q(latched_clk_en)); + LUT4 #( + .INIT(16'hA800)) + latched_clk_en_reg_i_1 + (.I0(latched_clk_en_reg_i_3_n_0), + .I1(\LED_PIPE_count1_a1_reg[11] ), + .I2(\LED_PIPE_count1_a1_reg[24] ), + .I3(latched_clk_en_reg_i_6_n_0), + .O(LED_PIPE_refresh_a0)); + LUT4 #( + .INIT(16'h0001)) + latched_clk_en_reg_i_10 + (.I0(LED_PIPE_count1_a1[2]), + .I1(LED_PIPE_count1_a1[1]), + .I2(LED_PIPE_count1_a1[4]), + .I3(LED_PIPE_count1_a1[3]), + .O(latched_clk_en_reg_i_10_n_0)); + LUT4 #( + .INIT(16'h7FFF)) + latched_clk_en_reg_i_11 + (.I0(LED_PIPE_count1_a1[14]), + .I1(LED_PIPE_count1_a1[13]), + .I2(LED_PIPE_count1_a1[16]), + .I3(LED_PIPE_count1_a1[15]), + .O(latched_clk_en_reg_i_11_n_0)); + LUT6 #( + .INIT(64'h15555555FFFFFFFF)) + latched_clk_en_reg_i_12 + (.I0(LED_PIPE_count1_a1[10]), + .I1(LED_PIPE_count1_a1[7]), + .I2(LED_PIPE_count1_a1[6]), + .I3(LED_PIPE_count1_a1[9]), + .I4(LED_PIPE_count1_a1[8]), + .I5(LED_PIPE_count1_a1[11]), + .O(latched_clk_en_reg_i_12_n_0)); + LUT6 #( + .INIT(64'h0000000000002000)) + latched_clk_en_reg_i_13 + (.I0(latched_clk_en_reg_i_6_1[1]), + .I1(latched_clk_en_reg_i_6_1[2]), + .I2(O[3]), + .I3(latched_clk_en_reg_i_6_1[0]), + .I4(latched_clk_en_reg_i_6_0[0]), + .I5(latched_clk_en_reg_i_6_1[3]), + .O(latched_clk_en_reg_i_13_n_0)); + LUT6 #( + .INIT(64'h0008000000000000)) + latched_clk_en_reg_i_14 + (.I0(latched_clk_en_reg_i_6_0[3]), + .I1(latched_clk_en_reg_i_3_0[0]), + .I2(latched_clk_en_reg_i_6_0[1]), + .I3(latched_clk_en_reg_i_6_0[2]), + .I4(latched_clk_en_reg_i_3_0[2]), + .I5(latched_clk_en_reg_i_3_0[1]), + .O(latched_clk_en_reg_i_14_n_0)); + LUT4 #( + .INIT(16'h8000)) + latched_clk_en_reg_i_3 + (.I0(latched_clk_en_reg_i_7_n_0), + .I1(\LED_PIPE_count1_a1_reg[28] ), + .I2(latched_clk_en_reg_i_8_n_0), + .I3(latched_clk_en_reg_i_9_n_0), + .O(latched_clk_en_reg_i_3_n_0)); + LUT5 #( + .INIT(32'h00010000)) + latched_clk_en_reg_i_4 + (.I0(LED_PIPE_count1_a1[5]), + .I1(LED_PIPE_count1_a1[10]), + .I2(LED_PIPE_count1_a1[12]), + .I3(LED_PIPE_count1_a1[18]), + .I4(latched_clk_en_reg_i_10_n_0), + .O(\LED_PIPE_count1_a1_reg[11] )); + LUT6 #( + .INIT(64'h45455545FFFFFFFF)) + latched_clk_en_reg_i_5 + (.I0(LED_PIPE_count1_a1[18]), + .I1(latched_clk_en_reg_i_11_n_0), + .I2(LED_PIPE_count1_a1[17]), + .I3(latched_clk_en_reg_i_12_n_0), + .I4(LED_PIPE_count1_a1[12]), + .I5(LED_PIPE_count1_a1[19]), + .O(\LED_PIPE_count1_a1_reg[24] )); + LUT5 #( + .INIT(32'h80000000)) + latched_clk_en_reg_i_6 + (.I0(latched_clk_en_reg_i_13_n_0), + .I1(O[2]), + .I2(O[1]), + .I3(O[0]), + .I4(latched_clk_en_reg_i_14_n_0), + .O(latched_clk_en_reg_i_6_n_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + latched_clk_en_reg_i_7 + (.I0(latched_clk_en_reg_i_3_4[1]), + .I1(latched_clk_en_reg_i_3_4[2]), + .I2(latched_clk_en_reg_i_3_3[3]), + .I3(latched_clk_en_reg_i_3_4[0]), + .I4(LED_PIPE_count1_a1[0]), + .I5(LED_PIPE_rst1_a1), + .O(latched_clk_en_reg_i_7_n_0)); + LUT6 #( + .INIT(64'h0020000000000000)) + latched_clk_en_reg_i_8 + (.I0(latched_clk_en_reg_i_3_1[2]), + .I1(latched_clk_en_reg_i_3_1[1]), + .I2(latched_clk_en_reg_i_3_1[0]), + .I3(latched_clk_en_reg_i_3_0[3]), + .I4(latched_clk_en_reg_i_3_2[0]), + .I5(latched_clk_en_reg_i_3_1[3]), + .O(latched_clk_en_reg_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000000002000)) + latched_clk_en_reg_i_9 + (.I0(latched_clk_en_reg_i_3_3[0]), + .I1(latched_clk_en_reg_i_3_2[3]), + .I2(latched_clk_en_reg_i_3_2[1]), + .I3(latched_clk_en_reg_i_3_2[2]), + .I4(latched_clk_en_reg_i_3_3[2]), + .I5(latched_clk_en_reg_i_3_3[1]), + .O(latched_clk_en_reg_i_9_n_0)); +endmodule + +(* ECO_CHECKSUM = "96723c4c" *) +(* STRUCTURAL_NETLIST = "yes" *) +module top + (clk, + reset, + led); + input clk; + input reset; + output [15:0]led; + + wire \ ; + wire \ ; + wire [15:0]LED_PIPE_Leds_a0; + wire \LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ; + wire \LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ; + wire \LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ; + wire [15:0]LED_PIPE_Leds_n10_in; + wire [31:0]LED_PIPE_count1_a1; + wire \LED_PIPE_count1_a1[0]_i_1_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_1_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_4_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_5_n_0 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_5 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_6 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_7 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_7 ; + wire LED_PIPE_rst1_a1; + wire clk; + wire clkF_LED_PIPE_refresh_a1; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire gen_clkF_LED_PIPE_refresh_a1_n_0; + wire gen_clkF_LED_PIPE_refresh_a1_n_1; + wire gen_clkF_LED_PIPE_refresh_a1_n_2; + wire [15:0]led; + wire [15:0]led_OBUF; + wire reset; + wire reset_IBUF; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[4]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[8]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[16]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[20]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[24]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[4]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[8]_i_1_CO_UNCONNECTED ; + + GND GND + (.G(\ )); + LUT1 #( + .INIT(2'h1)) + \LED_PIPE_Leds_a0[0]_i_1 + (.I0(LED_PIPE_Leds_a0[0]), + .O(LED_PIPE_Leds_n10_in[0])); + FDSE \LED_PIPE_Leds_a0_reg[0] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[0]), + .Q(LED_PIPE_Leds_a0[0]), + .S(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[10] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[10]), + .Q(LED_PIPE_Leds_a0[10]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[11] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[11]), + .Q(LED_PIPE_Leds_a0[11]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[12] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[12]), + .Q(LED_PIPE_Leds_a0[12]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[12]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ), + .CO({\LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[12]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[12:9]), + .S(LED_PIPE_Leds_a0[12:9])); + FDRE \LED_PIPE_Leds_a0_reg[13] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[13]), + .Q(LED_PIPE_Leds_a0[13]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[14] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[14]), + .Q(LED_PIPE_Leds_a0[14]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[15] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[15]), + .Q(LED_PIPE_Leds_a0[15]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[15]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[15:13]), + .S({\ ,LED_PIPE_Leds_a0[15:13]})); + FDRE \LED_PIPE_Leds_a0_reg[1] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[1]), + .Q(LED_PIPE_Leds_a0[1]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[2] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[2]), + .Q(LED_PIPE_Leds_a0[2]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[3] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[3]), + .Q(LED_PIPE_Leds_a0[3]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[4] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[4]), + .Q(LED_PIPE_Leds_a0[4]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[4]_i_1 + (.CI(\ ), + .CO({\LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[4]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(LED_PIPE_Leds_a0[0]), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[4:1]), + .S(LED_PIPE_Leds_a0[4:1])); + FDRE \LED_PIPE_Leds_a0_reg[5] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[5]), + .Q(LED_PIPE_Leds_a0[5]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[6] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[6]), + .Q(LED_PIPE_Leds_a0[6]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[7] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[7]), + .Q(LED_PIPE_Leds_a0[7]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[8] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[8]), + .Q(LED_PIPE_Leds_a0[8]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[8]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ), + .CO({\LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[8]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[8:5]), + .S(LED_PIPE_Leds_a0[8:5])); + FDRE \LED_PIPE_Leds_a0_reg[9] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[9]), + .Q(LED_PIPE_Leds_a0[9]), + .R(reset_IBUF)); + LUT1 #( + .INIT(2'h1)) + \LED_PIPE_count1_a1[0]_i_1 + (.I0(LED_PIPE_count1_a1[0]), + .O(\LED_PIPE_count1_a1[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hBBBFBFBF)) + \LED_PIPE_count1_a1[31]_i_1 + (.I0(LED_PIPE_rst1_a1), + .I1(gen_clkF_LED_PIPE_refresh_a1_n_2), + .I2(gen_clkF_LED_PIPE_refresh_a1_n_1), + .I3(gen_clkF_LED_PIPE_refresh_a1_n_0), + .I4(\LED_PIPE_count1_a1[31]_i_4_n_0 ), + .O(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + LUT4 #( + .INIT(16'hBFFF)) + \LED_PIPE_count1_a1[31]_i_4 + (.I0(\LED_PIPE_count1_a1[31]_i_5_n_0 ), + .I1(LED_PIPE_count1_a1[0]), + .I2(LED_PIPE_count1_a1[5]), + .I3(LED_PIPE_count1_a1[6]), + .O(\LED_PIPE_count1_a1[31]_i_4_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \LED_PIPE_count1_a1[31]_i_5 + (.I0(LED_PIPE_count1_a1[2]), + .I1(LED_PIPE_count1_a1[1]), + .I2(LED_PIPE_count1_a1[4]), + .I3(LED_PIPE_count1_a1[3]), + .O(\LED_PIPE_count1_a1[31]_i_5_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[0] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1[0]_i_1_n_0 ), + .Q(LED_PIPE_count1_a1[0]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[10] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[10]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[11] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[11]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[12] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[12]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[12]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[8]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[12]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[12]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[12:9])); + FDRE \LED_PIPE_count1_a1_reg[13] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[13]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[14] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[14]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[15] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[15]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[16] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[16]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[16]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[12]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[16]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[16]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[16:13])); + FDRE \LED_PIPE_count1_a1_reg[17] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[17]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[18] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[18]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[19] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[19]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[1] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[1]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[20] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[20]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[20]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[16]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[20]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[20]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[20:17])); + FDRE \LED_PIPE_count1_a1_reg[21] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[21]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[22] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[22]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[23] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[23]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[24] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[24]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[24]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[20]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[24]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[24]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[24:21])); + FDRE \LED_PIPE_count1_a1_reg[25] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[25]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[26] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[26]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[27] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[27]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[28] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[28]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[28]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[24]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[28]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[28]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[28:25])); + FDRE \LED_PIPE_count1_a1_reg[29] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_7 ), + .Q(LED_PIPE_count1_a1[29]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[2] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[2]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[30] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ), + .Q(LED_PIPE_count1_a1[30]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[31] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ), + .Q(LED_PIPE_count1_a1[31]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[31]_i_2 + (.CI(\LED_PIPE_count1_a1_reg[28]_i_1_n_0 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_7 }), + .S({\ ,LED_PIPE_count1_a1[31:29]})); + FDRE \LED_PIPE_count1_a1_reg[3] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[3]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[4] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[4]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[4]_i_1 + (.CI(\ ), + .CO({\LED_PIPE_count1_a1_reg[4]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[4]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(LED_PIPE_count1_a1[0]), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[4:1])); + FDRE \LED_PIPE_count1_a1_reg[5] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[5]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[6] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[6]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[7] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[7]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[8] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[8]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[8]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[4]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[8]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[8]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[8:5])); + FDRE \LED_PIPE_count1_a1_reg[9] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[9]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE LED_PIPE_rst1_a1_reg + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(reset_IBUF), + .Q(LED_PIPE_rst1_a1), + .R(\ )); + VCC VCC + (.P(\ )); + BUFG clk_IBUF_BUFG_inst + (.I(clk_IBUF), + .O(clk_IBUF_BUFG)); + IBUF clk_IBUF_inst + (.I(clk), + .O(clk_IBUF)); + clk_gate gen_clkF_LED_PIPE_refresh_a1 + (.CLK(clkF_LED_PIPE_refresh_a1), + .LED_PIPE_count1_a1({LED_PIPE_count1_a1[31:7],LED_PIPE_count1_a1[0]}), + .\LED_PIPE_count1_a1_reg[11] (gen_clkF_LED_PIPE_refresh_a1_n_0), + .\LED_PIPE_count1_a1_reg[24] (gen_clkF_LED_PIPE_refresh_a1_n_1), + .\LED_PIPE_count1_a1_reg[28] (gen_clkF_LED_PIPE_refresh_a1_n_2), + .LED_PIPE_rst1_a1(LED_PIPE_rst1_a1), + .O({\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_7 }), + .clk_IBUF(clk_IBUF), + .clk_IBUF_BUFG(clk_IBUF_BUFG), + .latched_clk_en_reg_i_3_0({\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_7 }), + .latched_clk_en_reg_i_3_1({\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_7 }), + .latched_clk_en_reg_i_3_2({\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_7 }), + .latched_clk_en_reg_i_3_3({\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_7 }), + .latched_clk_en_reg_i_3_4({\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_7 }), + .latched_clk_en_reg_i_6_0({\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_7 }), + .latched_clk_en_reg_i_6_1({\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_7 })); + OBUF \led_OBUF[0]_inst + (.I(led_OBUF[0]), + .O(led[0])); + OBUF \led_OBUF[10]_inst + (.I(led_OBUF[10]), + .O(led[10])); + OBUF \led_OBUF[11]_inst + (.I(led_OBUF[11]), + .O(led[11])); + OBUF \led_OBUF[12]_inst + (.I(led_OBUF[12]), + .O(led[12])); + OBUF \led_OBUF[13]_inst + (.I(led_OBUF[13]), + .O(led[13])); + OBUF \led_OBUF[14]_inst + (.I(led_OBUF[14]), + .O(led[14])); + OBUF \led_OBUF[15]_inst + (.I(led_OBUF[15]), + .O(led[15])); + OBUF \led_OBUF[1]_inst + (.I(led_OBUF[1]), + .O(led[1])); + OBUF \led_OBUF[2]_inst + (.I(led_OBUF[2]), + .O(led[2])); + OBUF \led_OBUF[3]_inst + (.I(led_OBUF[3]), + .O(led[3])); + OBUF \led_OBUF[4]_inst + (.I(led_OBUF[4]), + .O(led[4])); + OBUF \led_OBUF[5]_inst + (.I(led_OBUF[5]), + .O(led[5])); + OBUF \led_OBUF[6]_inst + (.I(led_OBUF[6]), + .O(led[6])); + OBUF \led_OBUF[7]_inst + (.I(led_OBUF[7]), + .O(led[7])); + OBUF \led_OBUF[8]_inst + (.I(led_OBUF[8]), + .O(led[8])); + OBUF \led_OBUF[9]_inst + (.I(led_OBUF[9]), + .O(led[9])); + FDRE \led_reg[0] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[0]), + .Q(led_OBUF[0]), + .R(\ )); + FDRE \led_reg[10] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[10]), + .Q(led_OBUF[10]), + .R(\ )); + FDRE \led_reg[11] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[11]), + .Q(led_OBUF[11]), + .R(\ )); + FDRE \led_reg[12] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[12]), + .Q(led_OBUF[12]), + .R(\ )); + FDRE \led_reg[13] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[13]), + .Q(led_OBUF[13]), + .R(\ )); + FDRE \led_reg[14] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[14]), + .Q(led_OBUF[14]), + .R(\ )); + FDRE \led_reg[15] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[15]), + .Q(led_OBUF[15]), + .R(\ )); + FDRE \led_reg[1] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[1]), + .Q(led_OBUF[1]), + .R(\ )); + FDRE \led_reg[2] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[2]), + .Q(led_OBUF[2]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "1247" *) + FDRE \led_reg[3] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[3]), + .Q(led_OBUF[3]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "1187" *) + FDRE \led_reg[4] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[4]), + .Q(led_OBUF[4]), + .R(\ )); + FDRE \led_reg[5] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[5]), + .Q(led_OBUF[5]), + .R(\ )); + FDRE \led_reg[6] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[6]), + .Q(led_OBUF[6]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "965" *) + FDRE \led_reg[7] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[7]), + .Q(led_OBUF[7]), + .R(\ )); + FDRE \led_reg[8] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[8]), + .Q(led_OBUF[8]), + .R(\ )); + FDRE \led_reg[9] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[9]), + .Q(led_OBUF[9]), + .R(\ )); + IBUF reset_IBUF_inst + (.I(reset), + .O(reset_IBUF)); +endmodule diff --git a/out/basys3/led_counter/Output/led_counter.bit b/out/basys3/led_counter/Output/led_counter.bit new file mode 100644 index 0000000..daae850 Binary files /dev/null and b/out/basys3/led_counter/Output/led_counter.bit differ diff --git a/out/basys3/led_counter/Output/place/post_place.dcp b/out/basys3/led_counter/Output/place/post_place.dcp new file mode 100644 index 0000000..99523dd Binary files /dev/null and b/out/basys3/led_counter/Output/place/post_place.dcp differ diff --git a/out/basys3/led_counter/Output/place/reports/post_place_timing_summary.rpt b/out/basys3/led_counter/Output/place/reports/post_place_timing_summary.rpt new file mode 100644 index 0000000..9787f32 --- /dev/null +++ b/out/basys3/led_counter/Output/place/reports/post_place_timing_summary.rpt @@ -0,0 +1,347 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:46:08 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/basys3/led_counter/Output/place/reports/post_place_timing_summary.rpt +| Design : top +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +---------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.432 0.000 0 114 -3.283 -38.766 33 114 4.500 0.000 0 67 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.432 0.000 0 114 -3.283 -38.766 33 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.432ns, Total Violation 0.000ns +Hold : 33 Failing Endpoints, Worst Slack -3.283ns, Total Violation -38.766ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.432ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 4.509ns (logic 2.695ns (59.769%) route 1.814ns (40.231%)) + Logic Levels: 11 (CARRY4=8 LUT4=2 LUT6=1) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.871ns = ( 9.871 - 5.000 ) + Source Clock Delay (SCD): 5.161ns + Clock Pessimism Removal (CPR): 0.267ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=2, estimated) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.640 5.161 clk_IBUF_BUFG + SLICE_X62Y44 FDRE r LED_PIPE_count1_a1_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y44 FDRE (Prop_fdre_C_Q) 0.456 5.617 r LED_PIPE_count1_a1_reg[1]/Q + net (fo=2, estimated) 0.623 6.240 LED_PIPE_count1_a1[1] + SLICE_X62Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.656 6.896 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, estimated) 0.000 6.896 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + SLICE_X62Y45 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.010 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.010 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + SLICE_X62Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.124 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.124 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + SLICE_X62Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.238 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.238 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + SLICE_X62Y48 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.352 r LED_PIPE_count1_a1_reg[20]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.352 LED_PIPE_count1_a1_reg[20]_i_1_n_0 + SLICE_X62Y49 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.466 r LED_PIPE_count1_a1_reg[24]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.466 LED_PIPE_count1_a1_reg[24]_i_1_n_0 + SLICE_X62Y50 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.580 r LED_PIPE_count1_a1_reg[28]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.580 LED_PIPE_count1_a1_reg[28]_i_1_n_0 + SLICE_X62Y51 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.928 f LED_PIPE_count1_a1_reg[31]_i_2/O[1] + net (fo=2, estimated) 0.883 8.811 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_4[1] + SLICE_X65Y48 LUT6 (Prop_lut6_I0_O) 0.303 9.114 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7/O + net (fo=1, estimated) 0.151 9.265 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7_n_0 + SLICE_X65Y48 LUT4 (Prop_lut4_I0_O) 0.124 9.389 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, estimated) 0.157 9.546 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + SLICE_X65Y48 LUT4 (Prop_lut4_I0_O) 0.124 9.670 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, routed) 0.000 9.670 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + SLICE_X65Y48 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + W5 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 6.388 f clk_IBUF_inst/O + net (fo=2, estimated) 1.869 8.257 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 8.348 f clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.523 9.871 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + SLICE_X65Y48 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.267 10.137 + clock uncertainty -0.035 10.102 + ------------------------------------------------------------------- + required time 10.102 + arrival time -9.670 + ------------------------------------------------------------------- + slack 0.432 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -3.283ns (arrival time - required time) + Source: reset + (input port clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: LED_PIPE_rst1_a1_reg/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.158ns (logic 1.386ns (64.213%) route 0.772ns (35.787%)) + Logic Levels: 1 (IBUF=1) + Input Delay: 0.000ns + Clock Path Skew: 5.162ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.162ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + input delay 0.000 0.000 + R2 0.000 0.000 r reset (IN) + net (fo=0) 0.000 0.000 reset + R2 IBUF (Prop_ibuf_I_O) 1.386 1.386 r reset_IBUF_inst/O + net (fo=17, estimated) 0.772 2.158 reset_IBUF + SLICE_X64Y48 FDRE r LED_PIPE_rst1_a1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=2, estimated) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.641 5.162 clk_IBUF_BUFG + SLICE_X64Y48 FDRE r LED_PIPE_rst1_a1_reg/C + clock pessimism 0.000 5.162 + clock uncertainty 0.035 5.198 + SLICE_X64Y48 FDRE (Hold_fdre_C_D) 0.243 5.441 LED_PIPE_rst1_a1_reg + ------------------------------------------------------------------- + required time -5.441 + arrival time 2.158 + ------------------------------------------------------------------- + slack -3.283 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 clk_IBUF_BUFG_inst/I +Low Pulse Width Slow FDSE/C n/a 0.500 5.000 4.500 SLICE_X64Y46 LED_PIPE_Leds_a0_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X62Y50 LED_PIPE_count1_a1_reg[25]/C + + + diff --git a/out/basys3/led_counter/Output/route/post_route.dcp b/out/basys3/led_counter/Output/route/post_route.dcp new file mode 100644 index 0000000..4c66c7c Binary files /dev/null and b/out/basys3/led_counter/Output/route/post_route.dcp differ diff --git a/out/basys3/led_counter/Output/route/reports/clock_util.rpt b/out/basys3/led_counter/Output/route/reports/clock_util.rpt new file mode 100644 index 0000000..3b9bb84 --- /dev/null +++ b/out/basys3/led_counter/Output/route/reports/clock_util.rpt @@ -0,0 +1,160 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:46:24 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_clock_utilization -file ./../out/basys3/led_counter/Output/route/reports/clock_util.rpt +| Design : top +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +---------------------------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +8. Clock Region Cell Placement per Global Clock: Region X1Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 50 | 0 | 10.000 | clk | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 1 | 10.000 | clk | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 38 | 1500 | 3 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 11 | 1500 | 4 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 1 | +| Y0 | 0 | 1 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | clk | 10.000 | {0.000 5.000} | 50 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+-----------------------+ +| | X0 | X1 | HORIZONTAL PROG DELAY | ++----+----+-----+-----------------------+ +| Y2 | 0 | 0 | 0 | +| Y1 | 0 | 11 | 0 | +| Y0 | 0 | 39 | 0 | ++----+----+-----+-----------------------+ + + +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 39 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +8. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 11 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y26 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} +#endgroup diff --git a/out/basys3/led_counter/Output/route/reports/post_imp_drc.rpt b/out/basys3/led_counter/Output/route/reports/post_imp_drc.rpt new file mode 100644 index 0000000..6adefd3 --- /dev/null +++ b/out/basys3/led_counter/Output/route/reports/post_imp_drc.rpt @@ -0,0 +1,68 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:46:35 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_drc -file ./../out/basys3/led_counter/Output/route/reports/post_imp_drc.rpt +| Design : top +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Fully Routed +---------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++-------------+----------+-------------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-------------+----------+-------------------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PDRC-153 | Warning | Gated clock check | 1 | +| PLHOLDVIO-2 | Warning | Non-Optimal connections which could lead to hold violations | 1 | ++-------------+----------+-------------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PDRC-153#1 Warning +Gated clock check +Net gen_clkF_LED_PIPE_refresh_a1/CLK is a gated clock net sourced by a combinational pin gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2/O, cell gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PLHOLDVIO-2#1 Warning +Non-Optimal connections which could lead to hold violations +A LUT gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2 is driving clock pin of 16 cells. This could lead to large hold time violations. Involved cells are: +LED_PIPE_Leds_a0_reg[0], LED_PIPE_Leds_a0_reg[10], +LED_PIPE_Leds_a0_reg[11], LED_PIPE_Leds_a0_reg[12], +LED_PIPE_Leds_a0_reg[13], LED_PIPE_Leds_a0_reg[14], +LED_PIPE_Leds_a0_reg[15], LED_PIPE_Leds_a0_reg[1], LED_PIPE_Leds_a0_reg[2], +LED_PIPE_Leds_a0_reg[3], LED_PIPE_Leds_a0_reg[4], LED_PIPE_Leds_a0_reg[5], +LED_PIPE_Leds_a0_reg[6], LED_PIPE_Leds_a0_reg[7], LED_PIPE_Leds_a0_reg[8] + (the first 15 of 16 listed) +Related violations: + + diff --git a/out/basys3/led_counter/Output/route/reports/post_route_power.rpt b/out/basys3/led_counter/Output/route/reports/post_route_power.rpt new file mode 100644 index 0000000..1a7d1e0 --- /dev/null +++ b/out/basys3/led_counter/Output/route/reports/post_route_power.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:46:25 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_power -file ./../out/basys3/led_counter/Output/route/reports/post_route_power.rpt +| Design : top +| Device : xc7a35tcpg236-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.096 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.025 | +| Device Static (W) | 0.072 | +| Effective TJA (C/W) | 5.0 | +| Max Ambient (C) | 84.5 | +| Junction Temperature (C) | 25.5 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.001 | 3 | --- | --- | +| Slice Logic | <0.001 | 102 | --- | --- | +| LUT as Logic | <0.001 | 19 | 20800 | 0.09 | +| CARRY4 | <0.001 | 12 | 8150 | 0.15 | +| Register | <0.001 | 66 | 41600 | 0.16 | +| Others | 0.000 | 4 | --- | --- | +| Signals | <0.001 | 125 | --- | --- | +| I/O | 0.023 | 18 | 106 | 16.98 | +| Static Power | 0.072 | | | | +| Total | 0.096 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.012 | 0.002 | 0.010 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.013 | 0.001 | 0.013 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.007 | 0.006 | 0.001 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 5.0 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ +| clk | clk | 10.0 | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------+-----------+ +| Name | Power (W) | ++------+-----------+ +| top | 0.025 | ++------+-----------+ + + diff --git a/out/basys3/led_counter/Output/route/reports/post_route_timing.rpt b/out/basys3/led_counter/Output/route/reports/post_route_timing.rpt new file mode 100644 index 0000000..ad20f4a --- /dev/null +++ b/out/basys3/led_counter/Output/route/reports/post_route_timing.rpt @@ -0,0 +1,119 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:46:24 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing -sort_by group -max_paths 100 -path_type summary -file ./../out/basys3/led_counter/Output/route/reports/post_route_timing.rpt +| Design : top +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Startpoint Endpoint Slack(ns) +---------------------------------------------------------------------------- +LED_PIPE_count1_a1_reg[2]/C gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + 0.362 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[10]/R 4.461 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[11]/R 4.461 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[12]/R 4.461 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[9]/R 4.461 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[5]/R 4.751 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[6]/R 4.751 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[7]/R 4.751 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[8]/R 4.751 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[0]/R 4.907 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[1]/R 4.925 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[2]/R 4.925 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[3]/R 4.925 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[4]/R 4.925 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[25]/R 5.019 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[26]/R 5.019 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[27]/R 5.019 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[28]/R 5.019 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[29]/R 5.334 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[30]/R 5.334 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[31]/R 5.334 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[21]/R 5.402 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[22]/R 5.402 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[23]/R 5.402 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[24]/R 5.402 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[13]/R 5.529 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[14]/R 5.529 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[15]/R 5.529 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[16]/R 5.529 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[17]/R 5.565 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[18]/R 5.565 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[19]/R 5.565 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[20]/R 5.565 +reset LED_PIPE_Leds_a0_reg[5]/R 5.650 +reset LED_PIPE_Leds_a0_reg[6]/R 5.650 +reset LED_PIPE_Leds_a0_reg[7]/R 5.650 +reset LED_PIPE_Leds_a0_reg[8]/R 5.650 +reset LED_PIPE_Leds_a0_reg[0]/S 5.663 +reset LED_PIPE_Leds_a0_reg[13]/R 5.679 +reset LED_PIPE_Leds_a0_reg[14]/R 5.679 +reset LED_PIPE_Leds_a0_reg[15]/R 5.679 +reset LED_PIPE_Leds_a0_reg[1]/R 5.770 +reset LED_PIPE_Leds_a0_reg[2]/R 5.770 +reset LED_PIPE_Leds_a0_reg[3]/R 5.770 +reset LED_PIPE_Leds_a0_reg[4]/R 5.770 +reset LED_PIPE_Leds_a0_reg[10]/R 5.796 +reset LED_PIPE_Leds_a0_reg[11]/R 5.796 +reset LED_PIPE_Leds_a0_reg[12]/R 5.796 +reset LED_PIPE_Leds_a0_reg[9]/R 5.796 +LED_PIPE_Leds_a0_reg[3]/C led_reg[3]/D 6.665 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[30]/D 7.130 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[31]/D 7.222 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[29]/D 7.243 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[26]/D 7.244 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[28]/D 7.263 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[27]/D 7.336 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[25]/D 7.357 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[22]/D 7.463 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[24]/D 7.482 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[23]/D 7.555 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[21]/D 7.576 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[18]/D 7.577 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[20]/D 7.596 +LED_PIPE_Leds_a0_reg[4]/C led_reg[4]/D 7.603 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[19]/D 7.669 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[17]/D 7.690 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[14]/D 7.691 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[16]/D 7.710 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[10]/D 7.756 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[14]/D 7.761 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[12]/D 7.777 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[15]/D 7.783 +LED_PIPE_Leds_a0_reg[7]/C led_reg[7]/D 7.791 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[10]/D 7.804 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[13]/D 7.804 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[12]/D 7.823 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[11]/D 7.851 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[15]/D 7.856 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[9]/D 7.867 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[13]/D 7.872 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[6]/D 7.872 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[8]/D 7.893 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[11]/D 7.896 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[9]/D 7.917 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[6]/D 7.918 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[8]/D 7.937 +reset LED_PIPE_rst1_a1_reg/D 7.942 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[7]/D 7.967 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[5]/D 7.983 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[7]/D 8.010 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[5]/D 8.031 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[4]/D 8.070 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[2]/D 8.114 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[3]/D 8.128 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[0]/D 8.172 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[4]/D 8.201 +LED_PIPE_Leds_a0_reg[14]/C led_reg[14]/D 8.229 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[1]/D 8.230 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[3]/D 8.261 +LED_PIPE_Leds_a0_reg[9]/C led_reg[9]/D 8.273 + + + diff --git a/out/basys3/led_counter/Output/route/reports/post_route_timing_summary.rpt b/out/basys3/led_counter/Output/route/reports/post_route_timing_summary.rpt new file mode 100644 index 0000000..51c60a6 --- /dev/null +++ b/out/basys3/led_counter/Output/route/reports/post_route_timing_summary.rpt @@ -0,0 +1,345 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:46:24 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/basys3/led_counter/Output/route/reports/post_route_timing_summary.rpt +| Design : top +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +---------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.362 0.000 0 114 0.061 0.000 0 114 4.500 0.000 0 67 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.362 0.000 0 114 0.061 0.000 0 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.362ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.061ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.362ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 4.579ns (logic 2.713ns (59.253%) route 1.866ns (40.747%)) + Logic Levels: 11 (CARRY4=8 LUT4=2 LUT6=1) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.861ns = ( 9.861 - 5.000 ) + Source Clock Delay (SCD): 5.159ns + Clock Pessimism Removal (CPR): 0.274ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=2, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.638 5.159 clk_IBUF_BUFG + SLICE_X62Y44 FDRE r LED_PIPE_count1_a1_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y44 FDRE (Prop_fdre_C_Q) 0.456 5.615 r LED_PIPE_count1_a1_reg[2]/Q + net (fo=2, routed) 0.594 6.210 LED_PIPE_count1_a1[2] + SLICE_X62Y44 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.674 6.884 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 6.884 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + SLICE_X62Y45 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.998 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.000 6.998 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + SLICE_X62Y46 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.112 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 7.112 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + SLICE_X62Y47 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.226 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 7.226 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + SLICE_X62Y48 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.340 r LED_PIPE_count1_a1_reg[20]_i_1/CO[3] + net (fo=1, routed) 0.000 7.340 LED_PIPE_count1_a1_reg[20]_i_1_n_0 + SLICE_X62Y49 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.454 r LED_PIPE_count1_a1_reg[24]_i_1/CO[3] + net (fo=1, routed) 0.001 7.454 LED_PIPE_count1_a1_reg[24]_i_1_n_0 + SLICE_X62Y50 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.568 r LED_PIPE_count1_a1_reg[28]_i_1/CO[3] + net (fo=1, routed) 0.000 7.568 LED_PIPE_count1_a1_reg[28]_i_1_n_0 + SLICE_X62Y51 CARRY4 (Prop_carry4_CI_O[1]) + 0.348 7.916 f LED_PIPE_count1_a1_reg[31]_i_2/O[1] + net (fo=2, routed) 0.967 8.884 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_4[1] + SLICE_X65Y48 LUT6 (Prop_lut6_I0_O) 0.303 9.187 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7/O + net (fo=1, routed) 0.149 9.336 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7_n_0 + SLICE_X65Y48 LUT4 (Prop_lut4_I0_O) 0.124 9.460 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, routed) 0.154 9.614 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + SLICE_X65Y48 LUT4 (Prop_lut4_I0_O) 0.124 9.738 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, routed) 0.000 9.738 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + SLICE_X65Y48 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + W5 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 6.388 f clk_IBUF_inst/O + net (fo=2, routed) 1.862 8.250 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 8.341 f clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.520 9.861 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + SLICE_X65Y48 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.274 10.135 + clock uncertainty -0.035 10.100 + ------------------------------------------------------------------- + required time 10.100 + arrival time -9.738 + ------------------------------------------------------------------- + slack 0.362 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.061ns (arrival time - required time) + Source: LED_PIPE_Leds_a0_reg[8]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: led_reg[8]/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.080ns (logic 0.367ns (17.644%) route 1.713ns (82.356%)) + Logic Levels: 0 + Clock Path Skew: 1.823ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.159ns + Source Clock Delay (SCD): 3.266ns + Clock Pessimism Removal (CPR): 0.070ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 1.388 r clk_IBUF_inst/O + net (fo=2, routed) 1.226 2.614 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF + SLICE_X64Y46 LUT2 (Prop_lut2_I1_O) 0.100 2.714 r gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2/O + net (fo=16, routed) 0.552 3.266 clkF_LED_PIPE_refresh_a1 + SLICE_X63Y47 FDRE r LED_PIPE_Leds_a0_reg[8]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y47 FDRE (Prop_fdre_C_Q) 0.367 3.633 r LED_PIPE_Leds_a0_reg[8]/Q + net (fo=2, routed) 1.713 5.346 LED_PIPE_Leds_a0[8] + SLICE_X63Y45 FDRE r led_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=2, routed) 1.967 3.425 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.521 r clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.638 5.159 clk_IBUF_BUFG + SLICE_X63Y45 FDRE r led_reg[8]/C + clock pessimism -0.070 5.089 + SLICE_X63Y45 FDRE (Hold_fdre_C_D) 0.196 5.285 led_reg[8] + ------------------------------------------------------------------- + required time -5.285 + arrival time 5.346 + ------------------------------------------------------------------- + slack 0.061 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 clk_IBUF_BUFG_inst/I +Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X63Y48 LED_PIPE_Leds_a0_reg[10]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X63Y44 LED_PIPE_count1_a1_reg[0]/C + + + diff --git a/out/basys3/led_counter/Output/route/reports/post_route_util.rpt b/out/basys3/led_counter/Output/route/reports/post_route_util.rpt new file mode 100644 index 0000000..8426cd3 --- /dev/null +++ b/out/basys3/led_counter/Output/route/reports/post_route_util.rpt @@ -0,0 +1,210 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:46:25 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_utilization -file ./../out/basys3/led_counter/Output/route/reports/post_route_util.rpt +| Design : top +| Device : 7a35tcpg236-1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 19 | 0 | 20800 | 0.09 | +| LUT as Logic | 19 | 0 | 20800 | 0.09 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 66 | 0 | 41600 | 0.16 | +| Register as Flip Flop | 65 | 0 | 41600 | 0.16 | +| Register as Latch | 1 | 0 | 41600 | <0.01 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 1 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 64 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------------------------+------+-------+-----------+-------+ +| Slice | 26 | 0 | 8150 | 0.32 | +| SLICEL | 20 | 0 | | | +| SLICEM | 6 | 0 | | | +| LUT as Logic | 19 | 0 | 20800 | 0.09 | +| using O5 output only | 0 | | | | +| using O6 output only | 18 | | | | +| using O5 and O6 | 1 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 66 | 0 | 41600 | 0.16 | +| Register driven from within the Slice | 48 | | | | +| Register driven from outside the Slice | 18 | | | | +| LUT in front of the register is unused | 14 | | | | +| LUT in front of the register is used | 4 | | | | +| Unique Control Sets | 4 | | 8150 | 0.05 | ++--------------------------------------------+------+-------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 18 | 18 | 106 | 16.98 | +| IOB Master Pads | 9 | | | | +| IOB Slave Pads | 8 | | | | +| Bonded IPADs | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 64 | Flop & Latch | +| OBUF | 16 | IO | +| CARRY4 | 12 | CarryLogic | +| LUT6 | 8 | LUT | +| LUT4 | 6 | LUT | +| LUT5 | 3 | LUT | +| LUT1 | 2 | LUT | +| IBUF | 2 | IO | +| LUT2 | 1 | LUT | +| LDCE | 1 | Flop & Latch | +| FDSE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/out/basys3/led_counter/Output/syn/post_synth.dcp b/out/basys3/led_counter/Output/syn/post_synth.dcp new file mode 100644 index 0000000..ee42da3 Binary files /dev/null and b/out/basys3/led_counter/Output/syn/post_synth.dcp differ diff --git a/out/basys3/led_counter/Output/syn/reports/post_synth_power.rpt b/out/basys3/led_counter/Output/syn/reports/post_synth_power.rpt new file mode 100644 index 0000000..df0ff20 --- /dev/null +++ b/out/basys3/led_counter/Output/syn/reports/post_synth_power.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:45:44 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_power -file ./../out/basys3/led_counter/Output/syn/reports/post_synth_power.rpt +| Design : top +| Device : xc7a35tcpg236-1 +| Design State : synthesized +| Grade : commercial +| Process : typical +| Characterization : Production +-------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.101 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.029 | +| Device Static (W) | 0.072 | +| Effective TJA (C/W) | 5.0 | +| Max Ambient (C) | 84.5 | +| Junction Temperature (C) | 25.5 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.002 | 3 | --- | --- | +| Slice Logic | <0.001 | 102 | --- | --- | +| LUT as Logic | <0.001 | 19 | 20800 | 0.09 | +| CARRY4 | <0.001 | 12 | 8150 | 0.15 | +| Register | <0.001 | 66 | 41600 | 0.16 | +| Others | 0.000 | 4 | --- | --- | +| Signals | <0.001 | 127 | --- | --- | +| I/O | 0.027 | 18 | 106 | 16.98 | +| Static Power | 0.072 | | | | +| Total | 0.101 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.012 | 0.002 | 0.010 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.014 | 0.001 | 0.013 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.009 | 0.008 | 0.001 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | Low | Design is synthesized | Accuracy of the tool is not optimal until design is fully placed and routed | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 5.0 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ +| clk | clk | 10.0 | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------+-----------+ +| Name | Power (W) | ++------+-----------+ +| top | 0.029 | ++------+-----------+ + + diff --git a/out/basys3/led_counter/Output/syn/reports/post_synth_timing_summary.rpt b/out/basys3/led_counter/Output/syn/reports/post_synth_timing_summary.rpt new file mode 100644 index 0000000..b329533 --- /dev/null +++ b/out/basys3/led_counter/Output/syn/reports/post_synth_timing_summary.rpt @@ -0,0 +1,346 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:45:43 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/basys3/led_counter/Output/syn/reports/post_synth_timing_summary.rpt +| Design : top +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.000 0.000 0 114 -1.035 -15.003 17 114 4.500 0.000 0 67 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.000 0.000 0 114 -1.035 -15.003 17 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.000ns, Total Violation 0.000ns +Hold : 17 Failing Endpoints, Worst Slack -1.035ns, Total Violation -15.003ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.000ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 5.612ns (logic 2.277ns (40.574%) route 3.335ns (59.426%)) + Logic Levels: 8 (CARRY4=5 LUT4=2 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.678ns = ( 7.678 - 5.000 ) + Source Clock Delay (SCD): 2.938ns + Clock Pessimism Removal (CPR): 0.115ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + Time Borrowing: + Nominal pulse width: 5.000ns + Library setup time: 0.043ns + Computed max time borrow: 5.043ns + Time borrowed from endpoint: 0.792ns + Open edge uncertainty: -0.035ns + Time given to startpoint: 0.757ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=2, unplaced) 0.800 2.258 clk_IBUF + BUFG (Prop_bufg_I_O) 0.096 2.354 r clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.584 2.938 clk_IBUF_BUFG + FDRE r LED_PIPE_count1_a1_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.456 3.394 r LED_PIPE_count1_a1_reg[2]/Q + net (fo=2, unplaced) 0.850 4.244 LED_PIPE_count1_a1[2] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.674 4.918 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, unplaced) 0.009 4.927 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 5.041 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.041 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 5.155 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.155 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 5.269 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.269 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.256 5.525 r LED_PIPE_count1_a1_reg[20]_i_1/O[2] + net (fo=2, unplaced) 1.125 6.650 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_1[2] + LUT6 (Prop_lut6_I0_O) 0.301 6.951 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, unplaced) 0.902 7.853 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + LUT4 (Prop_lut4_I2_O) 0.124 7.977 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, unplaced) 0.449 8.426 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + LUT4 (Prop_lut4_I0_O) 0.124 8.550 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, unplaced) 0.000 8.550 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + W5 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.388 6.388 f clk_IBUF_inst/O + net (fo=2, unplaced) 0.760 7.148 clk_IBUF + BUFG (Prop_bufg_I_O) 0.091 7.239 f clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.439 7.678 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.115 7.793 + clock uncertainty -0.035 7.758 + time borrowed 0.792 8.550 + ------------------------------------------------------------------- + required time 8.550 + arrival time -8.550 + ------------------------------------------------------------------- + slack 0.000 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -1.035ns (arrival time - required time) + Source: reset + (input port clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: LED_PIPE_rst1_a1_reg/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.146ns (logic 1.386ns (64.591%) route 0.760ns (35.409%)) + Logic Levels: 1 (IBUF=1) + Input Delay: 0.000ns + Clock Path Skew: 2.938ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.938ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + input delay 0.000 0.000 + R2 0.000 0.000 r reset (IN) + net (fo=0) 0.000 0.000 reset + R2 IBUF (Prop_ibuf_I_O) 1.386 1.386 r reset_IBUF_inst/O + net (fo=17, unplaced) 0.760 2.146 reset_IBUF + FDRE r LED_PIPE_rst1_a1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + W5 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + W5 IBUF (Prop_ibuf_I_O) 1.458 1.458 r clk_IBUF_inst/O + net (fo=2, unplaced) 0.800 2.258 clk_IBUF + BUFG (Prop_bufg_I_O) 0.096 2.354 r clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.584 2.938 clk_IBUF_BUFG + FDRE r LED_PIPE_rst1_a1_reg/C + clock pessimism 0.000 2.938 + clock uncertainty 0.035 2.973 + FDRE (Hold_fdre_C_D) 0.207 3.180 LED_PIPE_rst1_a1_reg + ------------------------------------------------------------------- + required time -3.180 + arrival time 2.146 + ------------------------------------------------------------------- + slack -1.035 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 clk_IBUF_BUFG_inst/I +Low Pulse Width Fast FDSE/C n/a 0.500 5.000 4.500 LED_PIPE_Leds_a0_reg[0]/C +High Pulse Width Slow FDSE/C n/a 0.500 5.000 4.500 LED_PIPE_Leds_a0_reg[0]/C + + + diff --git a/out/edge_artix-7/led_counter/Dependencies/clock_constraints.xdc b/out/edge_artix-7/led_counter/Dependencies/clock_constraints.xdc new file mode 100644 index 0000000..55c2eb4 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/clock_constraints.xdc @@ -0,0 +1,18 @@ +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/proj_default/clk_gate.sv b/out/edge_artix-7/led_counter/Dependencies/includes/proj_default/clk_gate.sv new file mode 100644 index 0000000..e028887 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/proj_default/clk_gate.sv @@ -0,0 +1,38 @@ +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Clock gate module used by SandPiper default project. + +// Note: No X injection for X on free_clk.) +module clk_gate (output logic gated_clk, input logic free_clk, func_en, pwr_en, gating_override); + logic clk_en; + logic latched_clk_en /*verilator clock_enable*/; + always_comb clk_en = func_en & (pwr_en | gating_override); + always_latch if (~free_clk) latched_clk_en <= clk_en; + // latched_clk_en <= (~free_clk) ? clk_en : latched_clk_en; + always_comb gated_clk = latched_clk_en & free_clk; +endmodule diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/proj_default/sp_default.vh b/out/edge_artix-7/led_counter/Dependencies/includes/proj_default/sp_default.vh new file mode 100644 index 0000000..a733969 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/proj_default/sp_default.vh @@ -0,0 +1,8 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +`endif // SP_DEFAULT diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/proj_verilog/clk_gate.v b/out/edge_artix-7/led_counter/Dependencies/includes/proj_verilog/clk_gate.v new file mode 100644 index 0000000..5afd28f --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/proj_verilog/clk_gate.v @@ -0,0 +1,39 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +`include "sp_verilog.vh" + + +// Clock gate module used by SandPiper default project. + +module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override); + wire clk_en; + reg latched_clk_en /*verilator clock_enable*/; + assign clk_en = func_en & (pwr_en | gating_override); + `TLV_BLATCH(latched_clk_en, clk_en, free_clk) + assign gated_clk = latched_clk_en & free_clk; +endmodule diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh b/out/edge_artix-7/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh new file mode 100644 index 0000000..0c28412 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh @@ -0,0 +1,65 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +// Latch macros. Inject 'x in simulation for clk === 'x. + +// A-phase latch. +`ifdef SP_PHYS +`define TLV_LATCH(in, out, clk) \ +always @ (in, clk) begin \ + if (clk === 1'b1) \ + out <= in; \ + else if (clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_LATCH(in, out, clk) always @ (in, clk) if (clk == 1'b1) out <= in; +`endif // SP_PHYS + +// B-phase latch. +`ifdef SP_PHYS +`define TLV_BLATCH(out, in, clk) \ +always @ (in, clk) begin \ + if (!clk === 1'b1) \ + out <= in; \ + else if (!clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_BLATCH(out, in, clk) always @ (in, clk) if (!clk == 1'b1) out <= in; +`endif // SP_PHYS + + + +`endif // SP_DEFAULT diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/pseudo_rand.tlv b/out/edge_artix-7/led_counter/Dependencies/includes/pseudo_rand.tlv new file mode 100644 index 0000000..cb0d614 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/pseudo_rand.tlv @@ -0,0 +1,69 @@ +\m4_TLV_version 1b: tl-x.org +\SV +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +module pseudo_rand + #(parameter WIDTH=257) // Random vector width, to a max of 257. + (input logic clk, + input logic reset, + output logic [WIDTH-1:0] rand_vect + ); + +// Currently, this implements a Galois LFSR. +// TODO: It should be XORed with something else so it doesn't just shift. +// Using polynomials with maximal number of taps would have less regular shifting behavior. + +// Bits are numbered in the reverse of the traditional order. This puts the taps in the lower bit positions. + +// Choose optimal parameters for given WIDTH. +localparam LFSR_WIDTH = + (WIDTH <= 64) ? 64 : + (WIDTH <= 128) ? 128 : + (WIDTH <= 257) ? 257 : 0; // 257 enables a large non-power of two for replication on an irregular boundary. +// Polynomial source: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf +localparam [LFSR_WIDTH-1:0] LFSR_POLY = {{(LFSR_WIDTH-8){1'b0}}, + (LFSR_WIDTH == 64) ? 8'b00011011 : + (LFSR_WIDTH == 128) ? 8'b10000111 : + (LFSR_WIDTH == 257) ? 8'b11000101 : 8'b0}; + +bit [256:0] SEED = 257'h0_7163e168_713d5431_6684e132_5cd84848_f3048b46_76874654_0c45f864_04e4684a; + + + +\TLV + |default + @0 + $reset = reset; + @1 + $lfsr[LFSR_WIDTH-1:0] = $reset ? *SEED : {$lfsr#+1[LFSR_WIDTH-2:0], 1'b0} ^ ({LFSR_WIDTH{$lfsr#+1[LFSR_WIDTH-1]}} & *LFSR_POLY); + @2 + *rand_vect = $lfsr[WIDTH-1:0]; + +\SV + +endmodule diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/rw_lib.vh b/out/edge_artix-7/led_counter/Dependencies/includes/rw_lib.vh new file mode 100644 index 0000000..39d5cd5 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/rw_lib.vh @@ -0,0 +1 @@ +`define RW_ZX(in, width) {{width-$width(in){1'b0}}, in} diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/sandhost/README.txt b/out/edge_artix-7/led_counter/Dependencies/includes/sandhost/README.txt new file mode 100644 index 0000000..1816fee --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/sandhost/README.txt @@ -0,0 +1 @@ +Veriog include files that are available only within Makerchip. diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/sandhost/sqrt32.v b/out/edge_artix-7/led_counter/Dependencies/includes/sandhost/sqrt32.v new file mode 100644 index 0000000..23e5dbc --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/sandhost/sqrt32.v @@ -0,0 +1,13 @@ +// A non-synthesizable Verilog-2005 sqrt function for tutorials. +`ifndef RW_NON_SYNTH_SQRT +`define RW_NON_SYNTH_SQRT + +function [31:0] sqrt; + input [31:0] a; + + /* verilator lint_off REALCVT */ + sqrt = $sqrt(a); + /* verilator lint_on REALCVT */ +endfunction + +`endif diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/sandhost/tb.sv b/out/edge_artix-7/led_counter/Dependencies/includes/sandhost/tb.sv new file mode 100644 index 0000000..187fa4f --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/sandhost/tb.sv @@ -0,0 +1,76 @@ +// Provides clk and reset to design.tlv. +// Instantiates design as design(.*) so additional inputs and outputs can be added. +// Ends simulation on max cycles argument below, or assertion of success signal. +// Additional testbench functionality can be added here, or within design using TLV. +// See: "top_module_tlv.m4" for definition. + +// ------------------------------------------------------------------- +// Expanded from instantiation: m4_top_module_inst(m4_name, m4_max_cycles) +// + +module tb(); + +logic clk, reset; // Generated in this module for DUT. +logic passed, failed; // Returned from DUT to this module. Passed must assert before + // max cycles, without failed having asserted. Failed can be undriven. +logic [15:0] cyc_cnt; + + +// Instantiate main module. +top top(.*); + + +// Clock +initial begin + clk = 1'b1; + forever #5 clk = ~clk; +end + + +// Run +initial begin + + //`ifdef DUMP_ON + $dumpfile("top.vcd"); + $dumpvars(0, clk, reset, passed, failed, cyc_cnt, top.DEBUG_SIGS); + $dumpon; + //`endif + + reset = 1'b1; + #55; + reset = 1'b0; + + // Run + + cyc_cnt = '0; + for (int cyc = 0; cyc < 100; cyc++) begin + // Failed + if (failed === 1'b1) begin + FAILED: assert(1'b1) begin + $display("Failed!!! Error condition asserted."); + $finish; + end + end + + // Success + if (passed) begin + SUCCESS: assert(1'b1) begin + $display("Success!!!"); + $finish; + end + end + + #10; + + cyc_cnt++; + end + + // Fail + DIE: assert (1'b1) begin + $error("Failed!!! Test did not complete within m4_max_cycles time."); + $finish; + end + +end + +endmodule // life_tb diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/sandpiper.vh b/out/edge_artix-7/led_counter/Dependencies/includes/sandpiper.vh new file mode 100644 index 0000000..26d3f19 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/sandpiper.vh @@ -0,0 +1,71 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Project-independent SandPiper header file. + +`ifndef SANDPIPER_VH +`define SANDPIPER_VH + + +// Note, these have no SP prefix, so collisions are possible. + + +`ifdef WHEN + // Make sure user definition does not collide. + !!!ERROR: WHEN macro already defined +`else + `ifdef SP_PHYS + // Phys compilation disabled X-injection. + `define WHEN(valid_sig) + `else + // Inject X. + `define WHEN(valid_sig) !valid_sig ? 'x : + `endif +`endif + + +// SandPiper does not generate set/reset flops. Reset is implemented as combinational +// logic, and it is up to synthesis to infer set/reset flops when possible. +//`ifdef RESET +// // Make sure user definition does not collide. +// !!!ERROR: RESET macro already defined +//`else +// `define RESET(i, reset) ((reset) ? '0 : i) +//`endif +// +//`ifdef SET +// // Make sure user definition does not collide. +// !!!ERROR: SET macro already defined +//`else +// `define SET(i, set) ((set) ? '1 : i) +//`endif + +// Since SandPiper required use of all signals, this is useful to create a +// bogus use and keep SandPiper happy when a signal, by intent, has no uses. +`define BOGUS_USE(ignore) + +`endif // SANDPIPER_VH diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/sandpiper_gen.vh b/out/edge_artix-7/led_counter/Dependencies/includes/sandpiper_gen.vh new file mode 100644 index 0000000..d063661 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/sandpiper_gen.vh @@ -0,0 +1,4 @@ +// This just verifies that sandpiper.vh has been included. +`ifndef SANDPIPER_VH + !!!ERROR: SandPiper project's sp_.vh file must include sandpiper.vh. +`endif diff --git a/out/edge_artix-7/led_counter/Dependencies/includes/simple_bypass_fifo.sv b/out/edge_artix-7/led_counter/Dependencies/includes/simple_bypass_fifo.sv new file mode 100644 index 0000000..601c655 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/includes/simple_bypass_fifo.sv @@ -0,0 +1,98 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +`include "rw_lib.vh" + +// A simple implementation of a FIFO with bypass. +// Head is stored outside of the FIFO array. +// When the FIFO is empty, input goes straight through mux to output. +module simple_bypass_fifo( + input logic clk, + input logic reset, + input logic push, + input logic [WIDTH-1:0] data_in, // Timed with push. + input logic pop, // May pop in same cycle as push to empty FIFO. + output logic [WIDTH-1:0] data_out, // Same cycle as pop. + output logic [$clog2(DEPTH+1)-1:0] cnt // Reflecting push/pop last cycle. 0..DEPTH. +); + parameter WIDTH = 8; + parameter DEPTH = 8; + + logic [$clog2(DEPTH)-1:0] next_head, tail; + logic [WIDTH-1:0] arr [DEPTH-1:0], arr_out, head_data; + logic cnt_zero_or_one, cnt_zero, cnt_one; + logic push_arr, push_head, pop_from_arr, popped_from_arr; + + always_ff @(posedge clk) begin + if (reset) begin + tail <= {$clog2(DEPTH){1'b0}}; + next_head <= {$clog2(DEPTH){1'b0}}; + cnt <= {$clog2(DEPTH+1){1'b0}}; + end else begin + if (push_arr + ) begin + arr[tail] <= data_in; + tail <= tail + {{$clog2(DEPTH)-1{1'b0}}, 1'b1}; + end + if (pop) begin + arr_out <= arr[next_head]; + next_head <= next_head + {{$clog2(DEPTH)-1{1'b0}}, 1'b1}; + end + if (push ^ pop) begin + cnt <= cnt + (push ? {{$clog2(DEPTH+1)-1{1'b0}}, 1'b1} /* 1 */ : {$clog2(DEPTH+1){1'b1}} /* -1 */); + end + end + end + always_comb begin + // Control signals + + // These are timed with cnt (cycle after push/pop) + cnt_zero_or_one = (cnt >> 1) == {$clog2(DEPTH+1){1'b0}}; + cnt_zero = cnt_zero_or_one && ~cnt[0]; + cnt_one = cnt_zero_or_one && cnt[0]; + + // These are timed with push/pop + // Cases in which a push would not got into array. + push_arr = push && !(cnt_zero || (cnt_zero_or_one && pop)); + push_head = push && (pop ? cnt_one : cnt_zero); + pop_from_arr = pop && !cnt_zero_or_one; + + // Output data + data_out = cnt_zero ? data_in : head_data; + end + + // Head + always_ff @(posedge clk) begin + popped_from_arr <= pop_from_arr; + if (push_head) begin + head_data <= data_in; + end else if (popped_from_arr) begin + head_data <= arr_out; + end + end +endmodule diff --git a/out/edge_artix-7/led_counter/Dependencies/led_counter.v b/out/edge_artix-7/led_counter/Dependencies/led_counter.v new file mode 100644 index 0000000..88607c6 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/led_counter.v @@ -0,0 +1,345 @@ +//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta +`include "sp_verilog.vh" //_\SV + // Included URL: "https://raw.githubusercontent.com/BalaDhinesh/Virtual-FPGA-Lab/main/tlv_lib/fpga_includes.tlv" +//_\SV + + + + + module top(input clk, input reset, output reg [15:0] led); + + +`include "led_counter_gen.v" +generate //_\TLV + //_|led_pipe + //_@0 + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 3 // Instantiated from led_counter.tlv, 15 as: m4+fpga_refresh($refresh, m4_ifelse(M4_MAKERCHIP, 1, 1, 50000000)) + /* verilator lint_off UNSIGNED */ + assign LED_PIPE_rst1_a0 = reset; + assign LED_PIPE_count1_a0[31:0] = (LED_PIPE_count1_a1[31:0] >= 50000000 - 1) | LED_PIPE_rst1_a1 ? 1'b0 : LED_PIPE_count1_a1[31:0] + 1 ; + assign LED_PIPE_refresh_a0 = (LED_PIPE_count1_a0 == 50000000 - 1) ? 1'b1 : 1'b0 ; + + //_\end_source + assign LED_PIPE_reset_a0 = reset; + //_?$refresh + assign LED_PIPE_Leds_n1[15:0] = LED_PIPE_reset_a0 ? 1 : LED_PIPE_Leds_a0+1; + /*SV_plus*/ + always@(posedge clk) begin + led = LED_PIPE_Leds_a0; + end + // M4_BOARD numbering + // 1 - Zedboard + // 2 - Artix-7 + // 3 - Basys3 + // 4 - Icebreaker + // 5 - Nexys + + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 32 // Instantiated from led_counter.tlv, 30 as: m4+fpga_init() + //m4+osfpga_logo() + //_|fpga_init_macro + //_@0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + //_\end_source + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 245 // Instantiated from led_counter.tlv, 31 as: m4+fpga_led(*led) + //_|led_pipe_macro + //_@0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + //_\end_source +endgenerate +//_\SV + endmodule diff --git a/out/edge_artix-7/led_counter/Dependencies/led_counter_gen.v b/out/edge_artix-7/led_counter/Dependencies/led_counter_gen.v new file mode 100644 index 0000000..fc366a2 --- /dev/null +++ b/out/edge_artix-7/led_counter/Dependencies/led_counter_gen.v @@ -0,0 +1,81 @@ +// Generated by SandPiper(TM) 1.11-2021/01/28-beta from Redwood EDA. +// Redwood EDA does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality. + + +`include "sandpiper_gen.vh" + + + + + +// +// Signals declared top-level. +// + +// For |led_pipe$Leds. +wire [15:0] LED_PIPE_Leds_n1; +reg [15:0] LED_PIPE_Leds_a0; + +// For |led_pipe$count1. +wire [31:0] LED_PIPE_count1_a0; +reg [31:0] LED_PIPE_count1_a1; + +// For |led_pipe$refresh. +wire LED_PIPE_refresh_a0; + +// For |led_pipe$reset. +wire LED_PIPE_reset_a0; + +// For |led_pipe$rst1. +wire LED_PIPE_rst1_a0; +reg LED_PIPE_rst1_a1; + + +// +// Scope: |led_pipe +// + +// Clock signals. +wire clkF_LED_PIPE_refresh_a1 ; + + +generate + + + // + // Scope: |led_pipe + // + + // For $Leds. + always @(posedge clkF_LED_PIPE_refresh_a1) LED_PIPE_Leds_a0[15:0] <= LED_PIPE_Leds_n1[15:0]; + + // For $count1. + always @(posedge clk) LED_PIPE_count1_a1[31:0] <= LED_PIPE_count1_a0[31:0]; + + // For $rst1. + always @(posedge clk) LED_PIPE_rst1_a1 <= LED_PIPE_rst1_a0; + + + + +endgenerate + + + +// +// Gated clocks. +// + +generate + + + + // + // Scope: |led_pipe + // + + clk_gate gen_clkF_LED_PIPE_refresh_a1(clkF_LED_PIPE_refresh_a1, clk, LED_PIPE_refresh_a0, 1'b1, 1'b0); + + + +endgenerate diff --git a/out/edge_artix-7/led_counter/Output/fpga_impl.xdc b/out/edge_artix-7/led_counter/Output/fpga_impl.xdc new file mode 100644 index 0000000..35809a2 --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/fpga_impl.xdc @@ -0,0 +1,371 @@ + +#################################################################################### +# Generated by Vivado 2020.2 built on 'Wed Nov 18 09:12:47 MST 2020' by 'xbuild' +# Command Used: write_xdc -no_fixed_only -force ./../out/edge_artix-7/led_counter/Output/fpga_impl.xdc +#################################################################################### + + +#################################################################################### +# Constraints from file : 'fpga_lab_constr_edge_artix-7.xdc' +#################################################################################### + +## This file is a general .xdc for the EDGE Artix 7 board +## To use it in a project: +## - comment the lines corresponding to unused pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +# Clock signal +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS33} [get_ports clk] + +# Switches +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports reset] + +# LEDs +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports {led[4]}] +set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS33} [get_ports {led[5]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led[7]}] +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports {led[8]}] +set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS33} [get_ports {led[9]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {led[10]}] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports {led[11]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {led[12]}] +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports {led[13]}] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[14]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[15]}] + +# Push Button + +#7 segment display + + +# Bluetooth + +# Buzzer + +# SPI DAC (MCP4921) + +# HDMI + +# 2x16 LCD +#LCD R/W pin is connected to ground by default.No need to assign LCD R/W Pin. + +#256Mb SDRAM (Only available with latest version of board) + + + + + + +# SPI TFT 1.8 inch + +# USB UART + +# WiFi + +# CMOS Camera + +#20 pin expansion connector +#pin1 5V +#pin2 NC +#pin3 3V3 +#pin4 GND + +# VGA 12 bit + +# SD Card + +# XADC Single Ended Input available at J13 Connector + +# Audio Jack + +# SRAM 512 KB (SRAM replaced with SDRAM in the latest version of board) only required for older boards +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[0]}]; +#set_property -dict { PACKAGE_PIN C8 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[1]}]; +#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[2]}]; +#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[3]}]; +#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[4]}]; +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[5]}]; +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[6]}]; +#set_property -dict { PACKAGE_PIN B10 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[7]}]; +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[8]}]; +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[9]}]; +#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[10]}]; +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[11]}]; +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[12]}]; +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[13]}]; +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[14]}]; +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[15]}]; +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[16]}]; +#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[17]}]; +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {sram_addr[18]}]; + +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {sram_data[0]}]; +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {sram_data[1]}]; +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports {sram_data[2]}]; +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports {sram_data[3]}]; +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports {sram_data[4]}]; +#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports {sram_data[5]}]; +#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS33 } [get_ports {sram_data[6]}]; +#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports {sram_data[7]}]; + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports {sram_we_n}]; +#set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS33 } [get_ports {sram_oe_n}]; +#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS33 } [get_ports {sram_ce_a_n}]; + + + + + + +#################################################################################### +# Constraints from file : 'clock_constraints.xdc' +#################################################################################### + +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] + + +# Vivado Generated physical constraints + +set_property BEL A6LUT [get_cells {LED_PIPE_Leds_a0[0]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[0]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[10]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[11]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[12]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[12]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[13]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[14]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[15]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[15]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[1]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[2]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[3]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[4]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[4]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[5]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[6]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[7]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[8]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[8]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[9]}] +set_property BEL A5LUT [get_cells {LED_PIPE_count1_a1[0]_i_1}] +set_property BEL B6LUT [get_cells {LED_PIPE_count1_a1[31]_i_1}] +set_property BEL A6LUT [get_cells {LED_PIPE_count1_a1[31]_i_4}] +set_property BEL A6LUT [get_cells {LED_PIPE_count1_a1[31]_i_5}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[0]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[10]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[11]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[12]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[12]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[13]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[14]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[15]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[16]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[16]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[17]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[18]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[19]}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[1]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[20]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[20]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[21]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[22]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[23]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[24]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[24]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[25]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[26]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[27]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[28]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[28]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[29]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[2]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[30]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[31]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[31]_i_2}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[3]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[4]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[4]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[5]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[6]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[7]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[8]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[8]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[9]}] +set_property BEL AFF [get_cells LED_PIPE_rst1_a1_reg] +set_property BEL BUFG [get_cells clk_IBUF_BUFG_inst] +set_property BEL INBUF_EN [get_cells clk_IBUF_inst] +set_property BEL A6LUT [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2}] +set_property BEL A6LUT [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_count1_a1[31]_i_3}] +set_property BEL CFF [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_10] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_11] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_12] +set_property BEL D6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_13] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_14] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_4] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_5] +set_property BEL D6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_6] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_9] +set_property BEL OUTBUF [get_cells {led_OBUF[0]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[10]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[11]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[12]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[13]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[14]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[15]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[1]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[2]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[3]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[4]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[5]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[6]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[7]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[8]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[9]_inst}] +set_property BEL AFF [get_cells {led_reg[0]}] +set_property BEL AFF [get_cells {led_reg[10]}] +set_property BEL BFF [get_cells {led_reg[11]}] +set_property BEL CFF [get_cells {led_reg[12]}] +set_property BEL AFF [get_cells {led_reg[13]}] +set_property BEL BFF [get_cells {led_reg[14]}] +set_property BEL CFF [get_cells {led_reg[15]}] +set_property BEL AFF [get_cells {led_reg[1]}] +set_property BEL BFF [get_cells {led_reg[2]}] +set_property BEL CFF [get_cells {led_reg[3]}] +set_property BEL DFF [get_cells {led_reg[4]}] +set_property BEL AFF [get_cells {led_reg[5]}] +set_property BEL BFF [get_cells {led_reg[6]}] +set_property BEL BFF [get_cells {led_reg[7]}] +set_property BEL CFF [get_cells {led_reg[8]}] +set_property BEL BFF [get_cells {led_reg[9]}] +set_property BEL INBUF_EN [get_cells reset_IBUF_inst] +set_property LOC SLICE_X3Y12 [get_cells {LED_PIPE_Leds_a0[0]_i_1}] +set_property LOC SLICE_X3Y12 [get_cells {LED_PIPE_Leds_a0_reg[0]}] +set_property LOC SLICE_X2Y13 [get_cells {LED_PIPE_Leds_a0_reg[10]}] +set_property LOC SLICE_X2Y13 [get_cells {LED_PIPE_Leds_a0_reg[11]}] +set_property LOC SLICE_X2Y13 [get_cells {LED_PIPE_Leds_a0_reg[12]}] +set_property LOC SLICE_X2Y13 [get_cells {LED_PIPE_Leds_a0_reg[12]_i_1}] +set_property LOC SLICE_X2Y14 [get_cells {LED_PIPE_Leds_a0_reg[13]}] +set_property LOC SLICE_X2Y14 [get_cells {LED_PIPE_Leds_a0_reg[14]}] +set_property LOC SLICE_X2Y14 [get_cells {LED_PIPE_Leds_a0_reg[15]}] +set_property LOC SLICE_X2Y14 [get_cells {LED_PIPE_Leds_a0_reg[15]_i_1}] +set_property LOC SLICE_X2Y11 [get_cells {LED_PIPE_Leds_a0_reg[1]}] +set_property LOC SLICE_X2Y11 [get_cells {LED_PIPE_Leds_a0_reg[2]}] +set_property LOC SLICE_X2Y11 [get_cells {LED_PIPE_Leds_a0_reg[3]}] +set_property LOC SLICE_X2Y11 [get_cells {LED_PIPE_Leds_a0_reg[4]}] +set_property LOC SLICE_X2Y11 [get_cells {LED_PIPE_Leds_a0_reg[4]_i_1}] +set_property LOC SLICE_X2Y12 [get_cells {LED_PIPE_Leds_a0_reg[5]}] +set_property LOC SLICE_X2Y12 [get_cells {LED_PIPE_Leds_a0_reg[6]}] +set_property LOC SLICE_X2Y12 [get_cells {LED_PIPE_Leds_a0_reg[7]}] +set_property LOC SLICE_X2Y12 [get_cells {LED_PIPE_Leds_a0_reg[8]}] +set_property LOC SLICE_X2Y12 [get_cells {LED_PIPE_Leds_a0_reg[8]_i_1}] +set_property LOC SLICE_X2Y13 [get_cells {LED_PIPE_Leds_a0_reg[9]}] +set_property LOC SLICE_X0Y9 [get_cells {LED_PIPE_count1_a1[0]_i_1}] +set_property LOC SLICE_X0Y12 [get_cells {LED_PIPE_count1_a1[31]_i_1}] +set_property LOC SLICE_X0Y9 [get_cells {LED_PIPE_count1_a1[31]_i_4}] +set_property LOC SLICE_X0Y8 [get_cells {LED_PIPE_count1_a1[31]_i_5}] +set_property LOC SLICE_X0Y9 [get_cells {LED_PIPE_count1_a1_reg[0]}] +set_property LOC SLICE_X1Y10 [get_cells {LED_PIPE_count1_a1_reg[10]}] +set_property LOC SLICE_X1Y10 [get_cells {LED_PIPE_count1_a1_reg[11]}] +set_property LOC SLICE_X1Y10 [get_cells {LED_PIPE_count1_a1_reg[12]}] +set_property LOC SLICE_X1Y10 [get_cells {LED_PIPE_count1_a1_reg[12]_i_1}] +set_property LOC SLICE_X1Y11 [get_cells {LED_PIPE_count1_a1_reg[13]}] +set_property LOC SLICE_X1Y11 [get_cells {LED_PIPE_count1_a1_reg[14]}] +set_property LOC SLICE_X1Y11 [get_cells {LED_PIPE_count1_a1_reg[15]}] +set_property LOC SLICE_X1Y11 [get_cells {LED_PIPE_count1_a1_reg[16]}] +set_property LOC SLICE_X1Y11 [get_cells {LED_PIPE_count1_a1_reg[16]_i_1}] +set_property LOC SLICE_X1Y12 [get_cells {LED_PIPE_count1_a1_reg[17]}] +set_property LOC SLICE_X1Y12 [get_cells {LED_PIPE_count1_a1_reg[18]}] +set_property LOC SLICE_X1Y12 [get_cells {LED_PIPE_count1_a1_reg[19]}] +set_property LOC SLICE_X1Y8 [get_cells {LED_PIPE_count1_a1_reg[1]}] +set_property LOC SLICE_X1Y12 [get_cells {LED_PIPE_count1_a1_reg[20]}] +set_property LOC SLICE_X1Y12 [get_cells {LED_PIPE_count1_a1_reg[20]_i_1}] +set_property LOC SLICE_X1Y13 [get_cells {LED_PIPE_count1_a1_reg[21]}] +set_property LOC SLICE_X1Y13 [get_cells {LED_PIPE_count1_a1_reg[22]}] +set_property LOC SLICE_X1Y13 [get_cells {LED_PIPE_count1_a1_reg[23]}] +set_property LOC SLICE_X1Y13 [get_cells {LED_PIPE_count1_a1_reg[24]}] +set_property LOC SLICE_X1Y13 [get_cells {LED_PIPE_count1_a1_reg[24]_i_1}] +set_property LOC SLICE_X1Y14 [get_cells {LED_PIPE_count1_a1_reg[25]}] +set_property LOC SLICE_X1Y14 [get_cells {LED_PIPE_count1_a1_reg[26]}] +set_property LOC SLICE_X1Y14 [get_cells {LED_PIPE_count1_a1_reg[27]}] +set_property LOC SLICE_X1Y14 [get_cells {LED_PIPE_count1_a1_reg[28]}] +set_property LOC SLICE_X1Y14 [get_cells {LED_PIPE_count1_a1_reg[28]_i_1}] +set_property LOC SLICE_X1Y15 [get_cells {LED_PIPE_count1_a1_reg[29]}] +set_property LOC SLICE_X1Y8 [get_cells {LED_PIPE_count1_a1_reg[2]}] +set_property LOC SLICE_X1Y15 [get_cells {LED_PIPE_count1_a1_reg[30]}] +set_property LOC SLICE_X1Y15 [get_cells {LED_PIPE_count1_a1_reg[31]}] +set_property LOC SLICE_X1Y15 [get_cells {LED_PIPE_count1_a1_reg[31]_i_2}] +set_property LOC SLICE_X1Y8 [get_cells {LED_PIPE_count1_a1_reg[3]}] +set_property LOC SLICE_X1Y8 [get_cells {LED_PIPE_count1_a1_reg[4]}] +set_property LOC SLICE_X1Y8 [get_cells {LED_PIPE_count1_a1_reg[4]_i_1}] +set_property LOC SLICE_X1Y9 [get_cells {LED_PIPE_count1_a1_reg[5]}] +set_property LOC SLICE_X1Y9 [get_cells {LED_PIPE_count1_a1_reg[6]}] +set_property LOC SLICE_X1Y9 [get_cells {LED_PIPE_count1_a1_reg[7]}] +set_property LOC SLICE_X1Y9 [get_cells {LED_PIPE_count1_a1_reg[8]}] +set_property LOC SLICE_X1Y9 [get_cells {LED_PIPE_count1_a1_reg[8]_i_1}] +set_property LOC SLICE_X1Y10 [get_cells {LED_PIPE_count1_a1_reg[9]}] +set_property LOC SLICE_X0Y13 [get_cells LED_PIPE_rst1_a1_reg] +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] +set_property LOC SLICE_X0Y15 [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2}] +set_property LOC SLICE_X0Y14 [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_count1_a1[31]_i_3}] +set_property LOC SLICE_X0Y12 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg] +set_property LOC SLICE_X0Y12 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1] +set_property LOC SLICE_X0Y10 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_10] +set_property LOC SLICE_X0Y13 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_11] +set_property LOC SLICE_X0Y11 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_12] +set_property LOC SLICE_X3Y9 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_13] +set_property LOC SLICE_X0Y10 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_14] +set_property LOC SLICE_X3Y12 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3] +set_property LOC SLICE_X0Y11 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_4] +set_property LOC SLICE_X0Y13 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_5] +set_property LOC SLICE_X3Y10 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_6] +set_property LOC SLICE_X3Y14 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7] +set_property LOC SLICE_X3Y11 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8] +set_property LOC SLICE_X0Y13 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_9] +set_property LOC SLICE_X6Y14 [get_cells {led_reg[0]}] +set_property LOC SLICE_X0Y11 [get_cells {led_reg[10]}] +set_property LOC SLICE_X0Y11 [get_cells {led_reg[11]}] +set_property LOC SLICE_X0Y11 [get_cells {led_reg[12]}] +set_property LOC SLICE_X0Y14 [get_cells {led_reg[13]}] +set_property LOC SLICE_X0Y14 [get_cells {led_reg[14]}] +set_property LOC SLICE_X0Y14 [get_cells {led_reg[15]}] +set_property LOC SLICE_X6Y11 [get_cells {led_reg[1]}] +set_property LOC SLICE_X6Y11 [get_cells {led_reg[2]}] +set_property LOC SLICE_X6Y11 [get_cells {led_reg[3]}] +set_property LOC SLICE_X6Y11 [get_cells {led_reg[4]}] +set_property LOC SLICE_X6Y12 [get_cells {led_reg[5]}] +set_property LOC SLICE_X6Y14 [get_cells {led_reg[6]}] +set_property LOC SLICE_X6Y12 [get_cells {led_reg[7]}] +set_property LOC SLICE_X6Y12 [get_cells {led_reg[8]}] +set_property LOC SLICE_X0Y13 [get_cells {led_reg[9]}] + +# Vivado Generated miscellaneous constraints + +#revert back to original instance +current_instance -quiet diff --git a/out/edge_artix-7/led_counter/Output/fpga_impl_netlist.v b/out/edge_artix-7/led_counter/Output/fpga_impl_netlist.v new file mode 100644 index 0000000..7fcd7e8 --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/fpga_impl_netlist.v @@ -0,0 +1,931 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Sat Oct 30 02:37:19 2021 +// Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +// Command : write_verilog -force ./../out/edge_artix-7/led_counter/Output/fpga_impl_netlist.v +// Design : top +// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an +// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input +// design files. +// Device : xc7a35tftg256-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module clk_gate + (\LED_PIPE_count1_a1_reg[11] , + \LED_PIPE_count1_a1_reg[24] , + \LED_PIPE_count1_a1_reg[28] , + CLK, + LED_PIPE_count1_a1, + O, + latched_clk_en_reg_i_6_0, + latched_clk_en_reg_i_3_0, + latched_clk_en_reg_i_6_1, + latched_clk_en_reg_i_3_1, + latched_clk_en_reg_i_3_2, + latched_clk_en_reg_i_3_3, + latched_clk_en_reg_i_3_4, + LED_PIPE_rst1_a1, + clk_IBUF, + clk_IBUF_BUFG); + output \LED_PIPE_count1_a1_reg[11] ; + output \LED_PIPE_count1_a1_reg[24] ; + output \LED_PIPE_count1_a1_reg[28] ; + output CLK; + input [25:0]LED_PIPE_count1_a1; + input [3:0]O; + input [3:0]latched_clk_en_reg_i_6_0; + input [3:0]latched_clk_en_reg_i_3_0; + input [3:0]latched_clk_en_reg_i_6_1; + input [3:0]latched_clk_en_reg_i_3_1; + input [3:0]latched_clk_en_reg_i_3_2; + input [3:0]latched_clk_en_reg_i_3_3; + input [2:0]latched_clk_en_reg_i_3_4; + input LED_PIPE_rst1_a1; + input clk_IBUF; + input clk_IBUF_BUFG; + + wire CLK; + wire GND_1; + wire [25:0]LED_PIPE_count1_a1; + wire \LED_PIPE_count1_a1_reg[11] ; + wire \LED_PIPE_count1_a1_reg[24] ; + wire \LED_PIPE_count1_a1_reg[28] ; + wire LED_PIPE_refresh_a0; + wire LED_PIPE_rst1_a1; + wire [3:0]O; + wire VCC_1; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire latched_clk_en; + wire latched_clk_en_reg_i_10_n_0; + wire latched_clk_en_reg_i_11_n_0; + wire latched_clk_en_reg_i_12_n_0; + wire latched_clk_en_reg_i_13_n_0; + wire latched_clk_en_reg_i_14_n_0; + wire [3:0]latched_clk_en_reg_i_3_0; + wire [3:0]latched_clk_en_reg_i_3_1; + wire [3:0]latched_clk_en_reg_i_3_2; + wire [3:0]latched_clk_en_reg_i_3_3; + wire [2:0]latched_clk_en_reg_i_3_4; + wire latched_clk_en_reg_i_3_n_0; + wire [3:0]latched_clk_en_reg_i_6_0; + wire [3:0]latched_clk_en_reg_i_6_1; + wire latched_clk_en_reg_i_6_n_0; + wire latched_clk_en_reg_i_7_n_0; + wire latched_clk_en_reg_i_8_n_0; + wire latched_clk_en_reg_i_9_n_0; + + GND GND + (.G(GND_1)); + LUT2 #( + .INIT(4'h8)) + \LED_PIPE_Leds_a0[15]_i_2 + (.I0(latched_clk_en), + .I1(clk_IBUF), + .O(CLK)); + LUT6 #( + .INIT(64'h0000000000000001)) + \LED_PIPE_count1_a1[31]_i_3 + (.I0(LED_PIPE_count1_a1[22]), + .I1(LED_PIPE_count1_a1[23]), + .I2(LED_PIPE_count1_a1[20]), + .I3(LED_PIPE_count1_a1[21]), + .I4(LED_PIPE_count1_a1[25]), + .I5(LED_PIPE_count1_a1[24]), + .O(\LED_PIPE_count1_a1_reg[28] )); + VCC VCC + (.P(VCC_1)); + (* OPT_MODIFIED = "MLO" *) + (* XILINX_LEGACY_PRIM = "LD" *) + LDCE #( + .INIT(1'b0), + .IS_G_INVERTED(1'b1)) + latched_clk_en_reg + (.CLR(GND_1), + .D(LED_PIPE_refresh_a0), + .G(clk_IBUF_BUFG), + .GE(VCC_1), + .Q(latched_clk_en)); + LUT4 #( + .INIT(16'hA800)) + latched_clk_en_reg_i_1 + (.I0(latched_clk_en_reg_i_3_n_0), + .I1(\LED_PIPE_count1_a1_reg[11] ), + .I2(\LED_PIPE_count1_a1_reg[24] ), + .I3(latched_clk_en_reg_i_6_n_0), + .O(LED_PIPE_refresh_a0)); + LUT4 #( + .INIT(16'h0001)) + latched_clk_en_reg_i_10 + (.I0(LED_PIPE_count1_a1[2]), + .I1(LED_PIPE_count1_a1[1]), + .I2(LED_PIPE_count1_a1[4]), + .I3(LED_PIPE_count1_a1[3]), + .O(latched_clk_en_reg_i_10_n_0)); + LUT4 #( + .INIT(16'h7FFF)) + latched_clk_en_reg_i_11 + (.I0(LED_PIPE_count1_a1[14]), + .I1(LED_PIPE_count1_a1[13]), + .I2(LED_PIPE_count1_a1[16]), + .I3(LED_PIPE_count1_a1[15]), + .O(latched_clk_en_reg_i_11_n_0)); + LUT6 #( + .INIT(64'h15555555FFFFFFFF)) + latched_clk_en_reg_i_12 + (.I0(LED_PIPE_count1_a1[10]), + .I1(LED_PIPE_count1_a1[7]), + .I2(LED_PIPE_count1_a1[6]), + .I3(LED_PIPE_count1_a1[9]), + .I4(LED_PIPE_count1_a1[8]), + .I5(LED_PIPE_count1_a1[11]), + .O(latched_clk_en_reg_i_12_n_0)); + LUT6 #( + .INIT(64'h0000000000002000)) + latched_clk_en_reg_i_13 + (.I0(latched_clk_en_reg_i_6_1[1]), + .I1(latched_clk_en_reg_i_6_1[2]), + .I2(O[3]), + .I3(latched_clk_en_reg_i_6_1[0]), + .I4(latched_clk_en_reg_i_6_0[0]), + .I5(latched_clk_en_reg_i_6_1[3]), + .O(latched_clk_en_reg_i_13_n_0)); + LUT6 #( + .INIT(64'h0008000000000000)) + latched_clk_en_reg_i_14 + (.I0(latched_clk_en_reg_i_6_0[3]), + .I1(latched_clk_en_reg_i_3_0[0]), + .I2(latched_clk_en_reg_i_6_0[1]), + .I3(latched_clk_en_reg_i_6_0[2]), + .I4(latched_clk_en_reg_i_3_0[2]), + .I5(latched_clk_en_reg_i_3_0[1]), + .O(latched_clk_en_reg_i_14_n_0)); + LUT4 #( + .INIT(16'h8000)) + latched_clk_en_reg_i_3 + (.I0(latched_clk_en_reg_i_7_n_0), + .I1(\LED_PIPE_count1_a1_reg[28] ), + .I2(latched_clk_en_reg_i_8_n_0), + .I3(latched_clk_en_reg_i_9_n_0), + .O(latched_clk_en_reg_i_3_n_0)); + LUT5 #( + .INIT(32'h00010000)) + latched_clk_en_reg_i_4 + (.I0(LED_PIPE_count1_a1[5]), + .I1(LED_PIPE_count1_a1[10]), + .I2(LED_PIPE_count1_a1[12]), + .I3(LED_PIPE_count1_a1[18]), + .I4(latched_clk_en_reg_i_10_n_0), + .O(\LED_PIPE_count1_a1_reg[11] )); + LUT6 #( + .INIT(64'h45455545FFFFFFFF)) + latched_clk_en_reg_i_5 + (.I0(LED_PIPE_count1_a1[18]), + .I1(latched_clk_en_reg_i_11_n_0), + .I2(LED_PIPE_count1_a1[17]), + .I3(latched_clk_en_reg_i_12_n_0), + .I4(LED_PIPE_count1_a1[12]), + .I5(LED_PIPE_count1_a1[19]), + .O(\LED_PIPE_count1_a1_reg[24] )); + LUT5 #( + .INIT(32'h80000000)) + latched_clk_en_reg_i_6 + (.I0(latched_clk_en_reg_i_13_n_0), + .I1(O[2]), + .I2(O[1]), + .I3(O[0]), + .I4(latched_clk_en_reg_i_14_n_0), + .O(latched_clk_en_reg_i_6_n_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + latched_clk_en_reg_i_7 + (.I0(latched_clk_en_reg_i_3_4[1]), + .I1(latched_clk_en_reg_i_3_4[2]), + .I2(latched_clk_en_reg_i_3_3[3]), + .I3(latched_clk_en_reg_i_3_4[0]), + .I4(LED_PIPE_count1_a1[0]), + .I5(LED_PIPE_rst1_a1), + .O(latched_clk_en_reg_i_7_n_0)); + LUT6 #( + .INIT(64'h0020000000000000)) + latched_clk_en_reg_i_8 + (.I0(latched_clk_en_reg_i_3_1[2]), + .I1(latched_clk_en_reg_i_3_1[1]), + .I2(latched_clk_en_reg_i_3_1[0]), + .I3(latched_clk_en_reg_i_3_0[3]), + .I4(latched_clk_en_reg_i_3_2[0]), + .I5(latched_clk_en_reg_i_3_1[3]), + .O(latched_clk_en_reg_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000000002000)) + latched_clk_en_reg_i_9 + (.I0(latched_clk_en_reg_i_3_3[0]), + .I1(latched_clk_en_reg_i_3_2[3]), + .I2(latched_clk_en_reg_i_3_2[1]), + .I3(latched_clk_en_reg_i_3_2[2]), + .I4(latched_clk_en_reg_i_3_3[2]), + .I5(latched_clk_en_reg_i_3_3[1]), + .O(latched_clk_en_reg_i_9_n_0)); +endmodule + +(* ECO_CHECKSUM = "96723c4c" *) +(* STRUCTURAL_NETLIST = "yes" *) +module top + (clk, + reset, + led); + input clk; + input reset; + output [15:0]led; + + wire \ ; + wire \ ; + wire [15:0]LED_PIPE_Leds_a0; + wire \LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ; + wire \LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ; + wire \LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ; + wire [15:0]LED_PIPE_Leds_n10_in; + wire [31:0]LED_PIPE_count1_a1; + wire \LED_PIPE_count1_a1[0]_i_1_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_1_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_4_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_5_n_0 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_5 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_6 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_7 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_7 ; + wire LED_PIPE_rst1_a1; + wire clk; + wire clkF_LED_PIPE_refresh_a1; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire gen_clkF_LED_PIPE_refresh_a1_n_0; + wire gen_clkF_LED_PIPE_refresh_a1_n_1; + wire gen_clkF_LED_PIPE_refresh_a1_n_2; + wire [15:0]led; + wire [15:0]led_OBUF; + wire reset; + wire reset_IBUF; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[4]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[8]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[16]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[20]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[24]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[4]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[8]_i_1_CO_UNCONNECTED ; + + GND GND + (.G(\ )); + LUT1 #( + .INIT(2'h1)) + \LED_PIPE_Leds_a0[0]_i_1 + (.I0(LED_PIPE_Leds_a0[0]), + .O(LED_PIPE_Leds_n10_in[0])); + FDSE \LED_PIPE_Leds_a0_reg[0] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[0]), + .Q(LED_PIPE_Leds_a0[0]), + .S(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[10] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[10]), + .Q(LED_PIPE_Leds_a0[10]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[11] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[11]), + .Q(LED_PIPE_Leds_a0[11]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[12] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[12]), + .Q(LED_PIPE_Leds_a0[12]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[12]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ), + .CO({\LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[12]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[12:9]), + .S(LED_PIPE_Leds_a0[12:9])); + FDRE \LED_PIPE_Leds_a0_reg[13] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[13]), + .Q(LED_PIPE_Leds_a0[13]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[14] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[14]), + .Q(LED_PIPE_Leds_a0[14]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[15] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[15]), + .Q(LED_PIPE_Leds_a0[15]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[15]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[15:13]), + .S({\ ,LED_PIPE_Leds_a0[15:13]})); + FDRE \LED_PIPE_Leds_a0_reg[1] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[1]), + .Q(LED_PIPE_Leds_a0[1]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[2] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[2]), + .Q(LED_PIPE_Leds_a0[2]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[3] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[3]), + .Q(LED_PIPE_Leds_a0[3]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[4] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[4]), + .Q(LED_PIPE_Leds_a0[4]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[4]_i_1 + (.CI(\ ), + .CO({\LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[4]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(LED_PIPE_Leds_a0[0]), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[4:1]), + .S(LED_PIPE_Leds_a0[4:1])); + FDRE \LED_PIPE_Leds_a0_reg[5] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[5]), + .Q(LED_PIPE_Leds_a0[5]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[6] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[6]), + .Q(LED_PIPE_Leds_a0[6]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[7] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[7]), + .Q(LED_PIPE_Leds_a0[7]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[8] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[8]), + .Q(LED_PIPE_Leds_a0[8]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[8]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ), + .CO({\LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[8]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[8:5]), + .S(LED_PIPE_Leds_a0[8:5])); + FDRE \LED_PIPE_Leds_a0_reg[9] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[9]), + .Q(LED_PIPE_Leds_a0[9]), + .R(reset_IBUF)); + (* \PinAttr:I0:HOLD_DETOUR = "195" *) + LUT1 #( + .INIT(2'h1)) + \LED_PIPE_count1_a1[0]_i_1 + (.I0(LED_PIPE_count1_a1[0]), + .O(\LED_PIPE_count1_a1[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hBBBFBFBF)) + \LED_PIPE_count1_a1[31]_i_1 + (.I0(LED_PIPE_rst1_a1), + .I1(gen_clkF_LED_PIPE_refresh_a1_n_2), + .I2(gen_clkF_LED_PIPE_refresh_a1_n_1), + .I3(gen_clkF_LED_PIPE_refresh_a1_n_0), + .I4(\LED_PIPE_count1_a1[31]_i_4_n_0 ), + .O(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* \PinAttr:I1:HOLD_DETOUR = "195" *) + LUT4 #( + .INIT(16'hBFFF)) + \LED_PIPE_count1_a1[31]_i_4 + (.I0(\LED_PIPE_count1_a1[31]_i_5_n_0 ), + .I1(LED_PIPE_count1_a1[0]), + .I2(LED_PIPE_count1_a1[5]), + .I3(LED_PIPE_count1_a1[6]), + .O(\LED_PIPE_count1_a1[31]_i_4_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \LED_PIPE_count1_a1[31]_i_5 + (.I0(LED_PIPE_count1_a1[2]), + .I1(LED_PIPE_count1_a1[1]), + .I2(LED_PIPE_count1_a1[4]), + .I3(LED_PIPE_count1_a1[3]), + .O(\LED_PIPE_count1_a1[31]_i_5_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[0] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1[0]_i_1_n_0 ), + .Q(LED_PIPE_count1_a1[0]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[10] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[10]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[11] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[11]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[12] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[12]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[12]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[8]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[12]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[12]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[12:9])); + FDRE \LED_PIPE_count1_a1_reg[13] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[13]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[14] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[14]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[15] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[15]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[16] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[16]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[16]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[12]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[16]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[16]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[16:13])); + FDRE \LED_PIPE_count1_a1_reg[17] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[17]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[18] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[18]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[19] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[19]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[1] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[1]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[20] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[20]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[20]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[16]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[20]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[20]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[20:17])); + FDRE \LED_PIPE_count1_a1_reg[21] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[21]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[22] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[22]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[23] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[23]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[24] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[24]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[24]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[20]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[24]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[24]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[24:21])); + FDRE \LED_PIPE_count1_a1_reg[25] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[25]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[26] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[26]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[27] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[27]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[28] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[28]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[28]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[24]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[28]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[28]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[28:25])); + FDRE \LED_PIPE_count1_a1_reg[29] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_7 ), + .Q(LED_PIPE_count1_a1[29]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[2] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[2]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[30] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ), + .Q(LED_PIPE_count1_a1[30]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[31] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ), + .Q(LED_PIPE_count1_a1[31]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[31]_i_2 + (.CI(\LED_PIPE_count1_a1_reg[28]_i_1_n_0 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_7 }), + .S({\ ,LED_PIPE_count1_a1[31:29]})); + FDRE \LED_PIPE_count1_a1_reg[3] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[3]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[4] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[4]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[4]_i_1 + (.CI(\ ), + .CO({\LED_PIPE_count1_a1_reg[4]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[4]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(LED_PIPE_count1_a1[0]), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[4:1])); + FDRE \LED_PIPE_count1_a1_reg[5] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[5]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[6] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[6]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[7] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[7]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[8] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[8]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[8]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[4]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[8]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[8]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[8:5])); + FDRE \LED_PIPE_count1_a1_reg[9] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[9]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE LED_PIPE_rst1_a1_reg + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(reset_IBUF), + .Q(LED_PIPE_rst1_a1), + .R(\ )); + VCC VCC + (.P(\ )); + BUFG clk_IBUF_BUFG_inst + (.I(clk_IBUF), + .O(clk_IBUF_BUFG)); + IBUF clk_IBUF_inst + (.I(clk), + .O(clk_IBUF)); + clk_gate gen_clkF_LED_PIPE_refresh_a1 + (.CLK(clkF_LED_PIPE_refresh_a1), + .LED_PIPE_count1_a1({LED_PIPE_count1_a1[31:7],LED_PIPE_count1_a1[0]}), + .\LED_PIPE_count1_a1_reg[11] (gen_clkF_LED_PIPE_refresh_a1_n_0), + .\LED_PIPE_count1_a1_reg[24] (gen_clkF_LED_PIPE_refresh_a1_n_1), + .\LED_PIPE_count1_a1_reg[28] (gen_clkF_LED_PIPE_refresh_a1_n_2), + .LED_PIPE_rst1_a1(LED_PIPE_rst1_a1), + .O({\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_7 }), + .clk_IBUF(clk_IBUF), + .clk_IBUF_BUFG(clk_IBUF_BUFG), + .latched_clk_en_reg_i_3_0({\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_7 }), + .latched_clk_en_reg_i_3_1({\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_7 }), + .latched_clk_en_reg_i_3_2({\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_7 }), + .latched_clk_en_reg_i_3_3({\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_7 }), + .latched_clk_en_reg_i_3_4({\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_7 }), + .latched_clk_en_reg_i_6_0({\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_7 }), + .latched_clk_en_reg_i_6_1({\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_7 })); + OBUF \led_OBUF[0]_inst + (.I(led_OBUF[0]), + .O(led[0])); + OBUF \led_OBUF[10]_inst + (.I(led_OBUF[10]), + .O(led[10])); + OBUF \led_OBUF[11]_inst + (.I(led_OBUF[11]), + .O(led[11])); + OBUF \led_OBUF[12]_inst + (.I(led_OBUF[12]), + .O(led[12])); + OBUF \led_OBUF[13]_inst + (.I(led_OBUF[13]), + .O(led[13])); + OBUF \led_OBUF[14]_inst + (.I(led_OBUF[14]), + .O(led[14])); + OBUF \led_OBUF[15]_inst + (.I(led_OBUF[15]), + .O(led[15])); + OBUF \led_OBUF[1]_inst + (.I(led_OBUF[1]), + .O(led[1])); + OBUF \led_OBUF[2]_inst + (.I(led_OBUF[2]), + .O(led[2])); + OBUF \led_OBUF[3]_inst + (.I(led_OBUF[3]), + .O(led[3])); + OBUF \led_OBUF[4]_inst + (.I(led_OBUF[4]), + .O(led[4])); + OBUF \led_OBUF[5]_inst + (.I(led_OBUF[5]), + .O(led[5])); + OBUF \led_OBUF[6]_inst + (.I(led_OBUF[6]), + .O(led[6])); + OBUF \led_OBUF[7]_inst + (.I(led_OBUF[7]), + .O(led[7])); + OBUF \led_OBUF[8]_inst + (.I(led_OBUF[8]), + .O(led[8])); + OBUF \led_OBUF[9]_inst + (.I(led_OBUF[9]), + .O(led[9])); + FDRE \led_reg[0] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[0]), + .Q(led_OBUF[0]), + .R(\ )); + FDRE \led_reg[10] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[10]), + .Q(led_OBUF[10]), + .R(\ )); + FDRE \led_reg[11] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[11]), + .Q(led_OBUF[11]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "1103" *) + FDRE \led_reg[12] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[12]), + .Q(led_OBUF[12]), + .R(\ )); + FDRE \led_reg[13] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[13]), + .Q(led_OBUF[13]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "1215" *) + FDRE \led_reg[14] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[14]), + .Q(led_OBUF[14]), + .R(\ )); + FDRE \led_reg[15] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[15]), + .Q(led_OBUF[15]), + .R(\ )); + FDRE \led_reg[1] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[1]), + .Q(led_OBUF[1]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "1178" *) + FDRE \led_reg[2] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[2]), + .Q(led_OBUF[2]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "1307" *) + FDRE \led_reg[3] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[3]), + .Q(led_OBUF[3]), + .R(\ )); + FDRE \led_reg[4] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[4]), + .Q(led_OBUF[4]), + .R(\ )); + FDRE \led_reg[5] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[5]), + .Q(led_OBUF[5]), + .R(\ )); + FDRE \led_reg[6] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[6]), + .Q(led_OBUF[6]), + .R(\ )); + FDRE \led_reg[7] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[7]), + .Q(led_OBUF[7]), + .R(\ )); + FDRE \led_reg[8] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[8]), + .Q(led_OBUF[8]), + .R(\ )); + FDRE \led_reg[9] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[9]), + .Q(led_OBUF[9]), + .R(\ )); + IBUF reset_IBUF_inst + (.I(reset), + .O(reset_IBUF)); +endmodule diff --git a/out/edge_artix-7/led_counter/Output/led_counter.bit b/out/edge_artix-7/led_counter/Output/led_counter.bit new file mode 100644 index 0000000..694c09c Binary files /dev/null and b/out/edge_artix-7/led_counter/Output/led_counter.bit differ diff --git a/out/edge_artix-7/led_counter/Output/place/post_place.dcp b/out/edge_artix-7/led_counter/Output/place/post_place.dcp new file mode 100644 index 0000000..814e6e3 Binary files /dev/null and b/out/edge_artix-7/led_counter/Output/place/post_place.dcp differ diff --git a/out/edge_artix-7/led_counter/Output/place/reports/post_place_timing_summary.rpt b/out/edge_artix-7/led_counter/Output/place/reports/post_place_timing_summary.rpt new file mode 100644 index 0000000..252e1df --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/place/reports/post_place_timing_summary.rpt @@ -0,0 +1,338 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:36:52 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/edge_artix-7/led_counter/Output/place/reports/post_place_timing_summary.rpt +| Design : top +| Device : 7a35t-ftg256 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +---------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.261 0.000 0 114 -3.111 -39.391 33 114 4.500 0.000 0 67 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.261 0.000 0 114 -3.111 -39.391 33 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.261ns, Total Violation 0.000ns +Hold : 33 Failing Endpoints, Worst Slack -3.111ns, Total Violation -39.391ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.261ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 4.676ns (logic 2.260ns (48.332%) route 2.416ns (51.668%)) + Logic Levels: 8 (CARRY4=5 LUT4=2 LUT6=1) + Clock Path Skew: -0.028ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.930ns = ( 9.930 - 5.000 ) + Source Clock Delay (SCD): 5.226ns + Clock Pessimism Removal (CPR): 0.268ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + N11 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.519 1.519 r clk_IBUF_inst/O + net (fo=2, estimated) 1.972 3.491 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.587 r clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.639 5.226 clk_IBUF_BUFG + SLICE_X1Y8 FDRE r LED_PIPE_count1_a1_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y8 FDRE (Prop_fdre_C_Q) 0.456 5.682 r LED_PIPE_count1_a1_reg[1]/Q + net (fo=2, estimated) 0.604 6.286 LED_PIPE_count1_a1[1] + SLICE_X1Y8 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.656 6.942 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, estimated) 0.000 6.942 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + SLICE_X1Y9 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.056 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.056 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + SLICE_X1Y10 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.170 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.170 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + SLICE_X1Y11 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.284 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.284 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + SLICE_X1Y12 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.540 r LED_PIPE_count1_a1_reg[20]_i_1/O[2] + net (fo=2, estimated) 0.946 8.486 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_1[2] + SLICE_X3Y11 LUT6 (Prop_lut6_I0_O) 0.302 8.788 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, estimated) 0.574 9.362 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + SLICE_X3Y12 LUT4 (Prop_lut4_I2_O) 0.124 9.486 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, estimated) 0.292 9.778 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + SLICE_X0Y12 LUT4 (Prop_lut4_I0_O) 0.124 9.902 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, routed) 0.000 9.902 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + SLICE_X0Y12 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + N11 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.448 6.448 f clk_IBUF_inst/O + net (fo=2, estimated) 1.873 8.321 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 8.412 f clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.518 9.930 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + SLICE_X0Y12 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.268 10.198 + clock uncertainty -0.035 10.163 + ------------------------------------------------------------------- + required time 10.163 + arrival time -9.902 + ------------------------------------------------------------------- + slack 0.261 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -3.111ns (arrival time - required time) + Source: reset + (input port clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: LED_PIPE_rst1_a1_reg/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.338ns (logic 1.465ns (62.657%) route 0.873ns (37.343%)) + Logic Levels: 1 (IBUF=1) + Input Delay: 0.000ns + Clock Path Skew: 5.222ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.222ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + input delay 0.000 0.000 + M6 0.000 0.000 r reset (IN) + net (fo=0) 0.000 0.000 reset + M6 IBUF (Prop_ibuf_I_O) 1.465 1.465 r reset_IBUF_inst/O + net (fo=17, estimated) 0.873 2.338 reset_IBUF + SLICE_X0Y13 FDRE r LED_PIPE_rst1_a1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + N11 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.519 1.519 r clk_IBUF_inst/O + net (fo=2, estimated) 1.972 3.491 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.587 r clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.635 5.222 clk_IBUF_BUFG + SLICE_X0Y13 FDRE r LED_PIPE_rst1_a1_reg/C + clock pessimism 0.000 5.222 + clock uncertainty 0.035 5.257 + SLICE_X0Y13 FDRE (Hold_fdre_C_D) 0.192 5.449 LED_PIPE_rst1_a1_reg + ------------------------------------------------------------------- + required time -5.449 + arrival time 2.338 + ------------------------------------------------------------------- + slack -3.111 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 clk_IBUF_BUFG_inst/I +Low Pulse Width Slow FDSE/C n/a 0.500 5.000 4.500 SLICE_X3Y12 LED_PIPE_Leds_a0_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y12 LED_PIPE_count1_a1_reg[17]/C + + + diff --git a/out/edge_artix-7/led_counter/Output/route/post_route.dcp b/out/edge_artix-7/led_counter/Output/route/post_route.dcp new file mode 100644 index 0000000..5d442e3 Binary files /dev/null and b/out/edge_artix-7/led_counter/Output/route/post_route.dcp differ diff --git a/out/edge_artix-7/led_counter/Output/route/reports/clock_util.rpt b/out/edge_artix-7/led_counter/Output/route/reports/clock_util.rpt new file mode 100644 index 0000000..649d13d --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/route/reports/clock_util.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:37:08 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_clock_utilization -file ./../out/edge_artix-7/led_counter/Output/route/reports/clock_util.rpt +| Design : top +| Device : 7a35t-ftg256 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +---------------------------------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 50 | 0 | 10.000 | clk | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y24 | IOB_X0Y24 | X0Y0 | 1 | 1 | 10.000 | clk | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 49 | 1200 | 9 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 1 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | clk | 10.000 | {0.000 5.000} | 50 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+-----+----+-----------------------+ +| | X0 | X1 | HORIZONTAL PROG DELAY | ++----+-----+----+-----------------------+ +| Y2 | 0 | 0 | 0 | +| Y1 | 0 | 0 | 0 | +| Y0 | 50 | 0 | 0 | ++----+-----+----+-----------------------+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 50 | 0 | 49 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y24 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} +#endgroup diff --git a/out/edge_artix-7/led_counter/Output/route/reports/post_imp_drc.rpt b/out/edge_artix-7/led_counter/Output/route/reports/post_imp_drc.rpt new file mode 100644 index 0000000..47fef65 --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/route/reports/post_imp_drc.rpt @@ -0,0 +1,68 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:37:18 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_drc -file ./../out/edge_artix-7/led_counter/Output/route/reports/post_imp_drc.rpt +| Design : top +| Device : xc7a35tftg256-1 +| Speed File : -1 +| Design State : Fully Routed +---------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++-------------+----------+-------------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-------------+----------+-------------------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PDRC-153 | Warning | Gated clock check | 1 | +| PLHOLDVIO-2 | Warning | Non-Optimal connections which could lead to hold violations | 1 | ++-------------+----------+-------------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PDRC-153#1 Warning +Gated clock check +Net gen_clkF_LED_PIPE_refresh_a1/CLK is a gated clock net sourced by a combinational pin gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2/O, cell gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PLHOLDVIO-2#1 Warning +Non-Optimal connections which could lead to hold violations +A LUT gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2 is driving clock pin of 16 cells. This could lead to large hold time violations. Involved cells are: +LED_PIPE_Leds_a0_reg[0], LED_PIPE_Leds_a0_reg[10], +LED_PIPE_Leds_a0_reg[11], LED_PIPE_Leds_a0_reg[12], +LED_PIPE_Leds_a0_reg[13], LED_PIPE_Leds_a0_reg[14], +LED_PIPE_Leds_a0_reg[15], LED_PIPE_Leds_a0_reg[1], LED_PIPE_Leds_a0_reg[2], +LED_PIPE_Leds_a0_reg[3], LED_PIPE_Leds_a0_reg[4], LED_PIPE_Leds_a0_reg[5], +LED_PIPE_Leds_a0_reg[6], LED_PIPE_Leds_a0_reg[7], LED_PIPE_Leds_a0_reg[8] + (the first 15 of 16 listed) +Related violations: + + diff --git a/out/edge_artix-7/led_counter/Output/route/reports/post_route_power.rpt b/out/edge_artix-7/led_counter/Output/route/reports/post_route_power.rpt new file mode 100644 index 0000000..8a0ff2d --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/route/reports/post_route_power.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:37:09 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_power -file ./../out/edge_artix-7/led_counter/Output/route/reports/post_route_power.rpt +| Design : top +| Device : xc7a35tftg256-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.096 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.024 | +| Device Static (W) | 0.072 | +| Effective TJA (C/W) | 4.9 | +| Max Ambient (C) | 84.5 | +| Junction Temperature (C) | 25.5 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | <0.001 | 3 | --- | --- | +| Slice Logic | <0.001 | 102 | --- | --- | +| LUT as Logic | <0.001 | 19 | 20800 | 0.09 | +| CARRY4 | <0.001 | 12 | 8150 | 0.15 | +| Register | <0.001 | 66 | 41600 | 0.16 | +| Others | 0.000 | 4 | --- | --- | +| Signals | <0.001 | 124 | --- | --- | +| I/O | 0.023 | 18 | 170 | 10.59 | +| Static Power | 0.072 | | | | +| Total | 0.096 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.011 | 0.002 | 0.010 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.013 | 0.001 | 0.013 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.007 | 0.006 | 0.001 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.9 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ +| clk | clk | 10.0 | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------+-----------+ +| Name | Power (W) | ++------+-----------+ +| top | 0.024 | ++------+-----------+ + + diff --git a/out/edge_artix-7/led_counter/Output/route/reports/post_route_timing.rpt b/out/edge_artix-7/led_counter/Output/route/reports/post_route_timing.rpt new file mode 100644 index 0000000..293573c --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/route/reports/post_route_timing.rpt @@ -0,0 +1,119 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:37:08 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing -sort_by group -max_paths 100 -path_type summary -file ./../out/edge_artix-7/led_counter/Output/route/reports/post_route_timing.rpt +| Design : top +| Device : 7a35t-ftg256 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Startpoint Endpoint Slack(ns) +---------------------------------------------------------------------------- +LED_PIPE_count1_a1_reg[2]/C gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + 0.419 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[1]/R 5.276 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[2]/R 5.276 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[3]/R 5.276 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[4]/R 5.276 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[5]/R 5.408 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[6]/R 5.408 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[7]/R 5.408 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[8]/R 5.408 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[0]/R 5.426 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[10]/R 5.567 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[11]/R 5.567 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[12]/R 5.567 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[9]/R 5.567 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[25]/R 5.612 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[26]/R 5.612 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[27]/R 5.612 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[28]/R 5.612 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[14]/D 5.711 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[17]/R 5.719 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[18]/R 5.719 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[19]/R 5.719 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[20]/R 5.719 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[29]/R 5.759 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[30]/R 5.759 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[31]/R 5.759 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[15]/D 5.795 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[13]/D 5.815 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[10]/D 5.864 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[12]/D 5.872 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[21]/R 5.912 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[22]/R 5.912 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[23]/R 5.912 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[24]/R 5.912 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[11]/D 5.948 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[9]/D 5.968 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[13]/R 6.051 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[14]/R 6.051 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[15]/R 6.051 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[16]/R 6.051 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[6]/D 6.093 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[8]/D 6.101 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[7]/D 6.177 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[5]/D 6.197 +LED_PIPE_Leds_a0_reg[4]/C LED_PIPE_Leds_a0_reg[4]/D 6.612 +reset LED_PIPE_Leds_a0_reg[10]/R 7.328 +reset LED_PIPE_Leds_a0_reg[11]/R 7.328 +reset LED_PIPE_Leds_a0_reg[12]/R 7.328 +reset LED_PIPE_Leds_a0_reg[9]/R 7.328 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[30]/D 7.332 +reset LED_PIPE_Leds_a0_reg[13]/R 7.406 +reset LED_PIPE_Leds_a0_reg[14]/R 7.406 +reset LED_PIPE_Leds_a0_reg[15]/R 7.406 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[31]/D 7.424 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[29]/D 7.445 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[26]/D 7.447 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[28]/D 7.466 +reset LED_PIPE_Leds_a0_reg[1]/R 7.538 +reset LED_PIPE_Leds_a0_reg[2]/R 7.538 +reset LED_PIPE_Leds_a0_reg[3]/R 7.538 +reset LED_PIPE_Leds_a0_reg[4]/R 7.538 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[27]/D 7.539 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[25]/D 7.560 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[22]/D 7.561 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[24]/D 7.580 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[23]/D 7.653 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[21]/D 7.674 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[18]/D 7.676 +reset LED_PIPE_Leds_a0_reg[5]/R 7.685 +reset LED_PIPE_Leds_a0_reg[6]/R 7.685 +reset LED_PIPE_Leds_a0_reg[7]/R 7.685 +reset LED_PIPE_Leds_a0_reg[8]/R 7.685 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[20]/D 7.695 +LED_PIPE_Leds_a0_reg[3]/C led_reg[3]/D 7.702 +LED_PIPE_Leds_a0_reg[14]/C led_reg[14]/D 7.717 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[19]/D 7.768 +reset LED_PIPE_Leds_a0_reg[0]/S 7.780 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[17]/D 7.789 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[14]/D 7.791 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[0]/D 7.804 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[16]/D 7.810 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[15]/D 7.883 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[13]/D 7.904 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[10]/D 7.906 +LED_PIPE_Leds_a0_reg[2]/C led_reg[2]/D 7.910 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[12]/D 7.925 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[11]/D 7.998 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[9]/D 8.019 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[6]/D 8.020 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[8]/D 8.039 +reset LED_PIPE_rst1_a1_reg/D 8.040 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[7]/D 8.112 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[5]/D 8.133 +LED_PIPE_Leds_a0_reg[2]/C LED_PIPE_Leds_a0_reg[3]/D 8.299 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[4]/D 8.304 +LED_PIPE_Leds_a0_reg[13]/C led_reg[13]/D 8.307 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[3]/D 8.364 +LED_PIPE_Leds_a0_reg[1]/C LED_PIPE_Leds_a0_reg[2]/D 8.471 +LED_PIPE_Leds_a0_reg[7]/C led_reg[7]/D 8.478 +LED_PIPE_Leds_a0_reg[5]/C led_reg[5]/D 8.481 + + + diff --git a/out/edge_artix-7/led_counter/Output/route/reports/post_route_timing_summary.rpt b/out/edge_artix-7/led_counter/Output/route/reports/post_route_timing_summary.rpt new file mode 100644 index 0000000..5899947 --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/route/reports/post_route_timing_summary.rpt @@ -0,0 +1,336 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:37:07 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/edge_artix-7/led_counter/Output/route/reports/post_route_timing_summary.rpt +| Design : top +| Device : 7a35t-ftg256 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +---------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.419 0.000 0 114 0.111 0.000 0 114 4.500 0.000 0 67 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.419 0.000 0 114 0.111 0.000 0 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.419ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.111ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.419ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 4.518ns (logic 2.355ns (52.130%) route 2.163ns (47.870%)) + Logic Levels: 8 (CARRY4=5 LUT4=2 LUT6=1) + Clock Path Skew: -0.028ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 4.922ns = ( 9.922 - 5.000 ) + Source Clock Delay (SCD): 5.224ns + Clock Pessimism Removal (CPR): 0.273ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + N11 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.519 1.519 r clk_IBUF_inst/O + net (fo=2, routed) 1.972 3.490 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.586 r clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.637 5.224 clk_IBUF_BUFG + SLICE_X1Y8 FDRE r LED_PIPE_count1_a1_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y8 FDRE (Prop_fdre_C_Q) 0.456 5.680 r LED_PIPE_count1_a1_reg[2]/Q + net (fo=2, routed) 0.492 6.171 LED_PIPE_count1_a1[2] + SLICE_X1Y8 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.674 6.845 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 6.845 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + SLICE_X1Y9 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 6.959 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.000 6.959 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + SLICE_X1Y10 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.073 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 7.073 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + SLICE_X1Y11 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.187 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.000 7.187 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + SLICE_X1Y12 CARRY4 (Prop_carry4_CI_O[3]) + 0.329 7.516 r LED_PIPE_count1_a1_reg[20]_i_1/O[3] + net (fo=2, routed) 0.807 8.323 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_1[3] + SLICE_X3Y11 LUT6 (Prop_lut6_I5_O) 0.306 8.629 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, routed) 0.573 9.202 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + SLICE_X3Y12 LUT4 (Prop_lut4_I2_O) 0.124 9.326 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, routed) 0.291 9.617 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + SLICE_X0Y12 LUT4 (Prop_lut4_I0_O) 0.124 9.741 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, routed) 0.000 9.741 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + SLICE_X0Y12 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + N11 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.448 6.448 f clk_IBUF_inst/O + net (fo=2, routed) 1.868 8.316 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 8.407 f clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.515 9.922 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + SLICE_X0Y12 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.273 10.196 + clock uncertainty -0.035 10.160 + ------------------------------------------------------------------- + required time 10.160 + arrival time -9.741 + ------------------------------------------------------------------- + slack 0.419 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.111ns (arrival time - required time) + Source: LED_PIPE_Leds_a0_reg[9]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: led_reg[9]/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.403ns (logic 0.418ns (17.395%) route 1.985ns (82.605%)) + Logic Levels: 0 + Clock Path Skew: 2.112ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.220ns + Source Clock Delay (SCD): 3.036ns + Clock Pessimism Removal (CPR): 0.071ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + N11 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.448 1.448 r clk_IBUF_inst/O + net (fo=2, routed) 1.050 2.498 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF + SLICE_X0Y15 LUT2 (Prop_lut2_I1_O) 0.100 2.598 r gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2/O + net (fo=16, routed) 0.439 3.036 clkF_LED_PIPE_refresh_a1 + SLICE_X2Y13 FDRE r LED_PIPE_Leds_a0_reg[9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X2Y13 FDRE (Prop_fdre_C_Q) 0.418 3.454 r LED_PIPE_Leds_a0_reg[9]/Q + net (fo=2, routed) 1.985 5.439 LED_PIPE_Leds_a0[9] + SLICE_X0Y13 FDRE r led_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + N11 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.519 1.519 r clk_IBUF_inst/O + net (fo=2, routed) 1.972 3.490 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.586 r clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.633 5.220 clk_IBUF_BUFG + SLICE_X0Y13 FDRE r led_reg[9]/C + clock pessimism -0.071 5.149 + SLICE_X0Y13 FDRE (Hold_fdre_C_D) 0.180 5.329 led_reg[9] + ------------------------------------------------------------------- + required time -5.329 + arrival time 5.439 + ------------------------------------------------------------------- + slack 0.111 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 clk_IBUF_BUFG_inst/I +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X2Y13 LED_PIPE_Leds_a0_reg[10]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y9 LED_PIPE_count1_a1_reg[0]/C + + + diff --git a/out/edge_artix-7/led_counter/Output/route/reports/post_route_util.rpt b/out/edge_artix-7/led_counter/Output/route/reports/post_route_util.rpt new file mode 100644 index 0000000..29c9dbe --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/route/reports/post_route_util.rpt @@ -0,0 +1,207 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:37:09 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_utilization -file ./../out/edge_artix-7/led_counter/Output/route/reports/post_route_util.rpt +| Design : top +| Device : 7a35tftg256-1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 19 | 0 | 20800 | 0.09 | +| LUT as Logic | 19 | 0 | 20800 | 0.09 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 66 | 0 | 41600 | 0.16 | +| Register as Flip Flop | 65 | 0 | 41600 | 0.16 | +| Register as Latch | 1 | 0 | 41600 | <0.01 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 1 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 64 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------------------------+------+-------+-----------+-------+ +| Slice | 28 | 0 | 8150 | 0.34 | +| SLICEL | 21 | 0 | | | +| SLICEM | 7 | 0 | | | +| LUT as Logic | 19 | 0 | 20800 | 0.09 | +| using O5 output only | 0 | | | | +| using O6 output only | 18 | | | | +| using O5 and O6 | 1 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 66 | 0 | 41600 | 0.16 | +| Register driven from within the Slice | 49 | | | | +| Register driven from outside the Slice | 17 | | | | +| LUT in front of the register is unused | 12 | | | | +| LUT in front of the register is used | 5 | | | | +| Unique Control Sets | 4 | | 8150 | 0.05 | ++--------------------------------------------+------+-------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 18 | 18 | 170 | 10.59 | +| IOB Master Pads | 9 | | | | +| IOB Slave Pads | 7 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 163 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 170 | 0.00 | +| OLOGIC | 0 | 0 | 170 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 64 | Flop & Latch | +| OBUF | 16 | IO | +| CARRY4 | 12 | CarryLogic | +| LUT6 | 8 | LUT | +| LUT4 | 6 | LUT | +| LUT5 | 3 | LUT | +| LUT1 | 2 | LUT | +| IBUF | 2 | IO | +| LUT2 | 1 | LUT | +| LDCE | 1 | Flop & Latch | +| FDSE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/out/edge_artix-7/led_counter/Output/syn/post_synth.dcp b/out/edge_artix-7/led_counter/Output/syn/post_synth.dcp new file mode 100644 index 0000000..d6050f1 Binary files /dev/null and b/out/edge_artix-7/led_counter/Output/syn/post_synth.dcp differ diff --git a/out/edge_artix-7/led_counter/Output/syn/reports/post_synth_power.rpt b/out/edge_artix-7/led_counter/Output/syn/reports/post_synth_power.rpt new file mode 100644 index 0000000..f62422e --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/syn/reports/post_synth_power.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:36:27 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_power -file ./../out/edge_artix-7/led_counter/Output/syn/reports/post_synth_power.rpt +| Design : top +| Device : xc7a35tftg256-1 +| Design State : synthesized +| Grade : commercial +| Process : typical +| Characterization : Production +-------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.101 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.029 | +| Device Static (W) | 0.072 | +| Effective TJA (C/W) | 4.9 | +| Max Ambient (C) | 84.5 | +| Junction Temperature (C) | 25.5 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.002 | 3 | --- | --- | +| Slice Logic | <0.001 | 102 | --- | --- | +| LUT as Logic | <0.001 | 19 | 20800 | 0.09 | +| CARRY4 | <0.001 | 12 | 8150 | 0.15 | +| Register | <0.001 | 66 | 41600 | 0.16 | +| Others | 0.000 | 4 | --- | --- | +| Signals | <0.001 | 127 | --- | --- | +| I/O | 0.027 | 18 | 170 | 10.59 | +| Static Power | 0.072 | | | | +| Total | 0.101 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.012 | 0.002 | 0.010 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.014 | 0.001 | 0.013 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.009 | 0.008 | 0.001 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | Low | Design is synthesized | Accuracy of the tool is not optimal until design is fully placed and routed | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.9 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ +| clk | clk | 10.0 | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------+-----------+ +| Name | Power (W) | ++------+-----------+ +| top | 0.029 | ++------+-----------+ + + diff --git a/out/edge_artix-7/led_counter/Output/syn/reports/post_synth_timing_summary.rpt b/out/edge_artix-7/led_counter/Output/syn/reports/post_synth_timing_summary.rpt new file mode 100644 index 0000000..aa5e36e --- /dev/null +++ b/out/edge_artix-7/led_counter/Output/syn/reports/post_synth_timing_summary.rpt @@ -0,0 +1,346 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:36:26 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/edge_artix-7/led_counter/Output/syn/reports/post_synth_timing_summary.rpt +| Design : top +| Device : 7a35t-ftg256 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.000 0.000 0 114 -1.016 -14.689 17 114 4.500 0.000 0 67 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.000 0.000 0 114 -1.016 -14.689 17 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.000ns, Total Violation 0.000ns +Hold : 17 Failing Endpoints, Worst Slack -1.016ns, Total Violation -14.689ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.000ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 5.612ns (logic 2.277ns (40.574%) route 3.335ns (59.426%)) + Logic Levels: 8 (CARRY4=5 LUT4=2 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.738ns = ( 7.738 - 5.000 ) + Source Clock Delay (SCD): 2.999ns + Clock Pessimism Removal (CPR): 0.116ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + Time Borrowing: + Nominal pulse width: 5.000ns + Library setup time: 0.043ns + Computed max time borrow: 5.043ns + Time borrowed from endpoint: 0.792ns + Open edge uncertainty: -0.035ns + Time given to startpoint: 0.757ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + N11 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.519 1.519 r clk_IBUF_inst/O + net (fo=2, unplaced) 0.800 2.319 clk_IBUF + BUFG (Prop_bufg_I_O) 0.096 2.415 r clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.584 2.999 clk_IBUF_BUFG + FDRE r LED_PIPE_count1_a1_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.456 3.455 r LED_PIPE_count1_a1_reg[2]/Q + net (fo=2, unplaced) 0.850 4.305 LED_PIPE_count1_a1[2] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.674 4.979 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, unplaced) 0.009 4.988 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 5.102 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.102 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 5.216 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.216 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 5.330 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.330 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.256 5.586 r LED_PIPE_count1_a1_reg[20]_i_1/O[2] + net (fo=2, unplaced) 1.125 6.711 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_1[2] + LUT6 (Prop_lut6_I0_O) 0.301 7.012 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, unplaced) 0.902 7.914 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + LUT4 (Prop_lut4_I2_O) 0.124 8.038 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, unplaced) 0.449 8.487 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + LUT4 (Prop_lut4_I0_O) 0.124 8.611 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, unplaced) 0.000 8.611 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + N11 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.448 6.448 f clk_IBUF_inst/O + net (fo=2, unplaced) 0.760 7.208 clk_IBUF + BUFG (Prop_bufg_I_O) 0.091 7.299 f clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.439 7.738 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.116 7.854 + clock uncertainty -0.035 7.818 + time borrowed 0.792 8.611 + ------------------------------------------------------------------- + required time 8.611 + arrival time -8.611 + ------------------------------------------------------------------- + slack 0.000 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -1.016ns (arrival time - required time) + Source: reset + (input port clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: LED_PIPE_rst1_a1_reg/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.225ns (logic 1.465ns (65.849%) route 0.760ns (34.151%)) + Logic Levels: 1 (IBUF=1) + Input Delay: 0.000ns + Clock Path Skew: 2.999ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.999ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + input delay 0.000 0.000 + M6 0.000 0.000 r reset (IN) + net (fo=0) 0.000 0.000 reset + M6 IBUF (Prop_ibuf_I_O) 1.465 1.465 r reset_IBUF_inst/O + net (fo=17, unplaced) 0.760 2.225 reset_IBUF + FDRE r LED_PIPE_rst1_a1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + N11 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + N11 IBUF (Prop_ibuf_I_O) 1.519 1.519 r clk_IBUF_inst/O + net (fo=2, unplaced) 0.800 2.319 clk_IBUF + BUFG (Prop_bufg_I_O) 0.096 2.415 r clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.584 2.999 clk_IBUF_BUFG + FDRE r LED_PIPE_rst1_a1_reg/C + clock pessimism 0.000 2.999 + clock uncertainty 0.035 3.034 + FDRE (Hold_fdre_C_D) 0.207 3.241 LED_PIPE_rst1_a1_reg + ------------------------------------------------------------------- + required time -3.241 + arrival time 2.225 + ------------------------------------------------------------------- + slack -1.016 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 clk_IBUF_BUFG_inst/I +Low Pulse Width Fast FDSE/C n/a 0.500 5.000 4.500 LED_PIPE_Leds_a0_reg[0]/C +High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 LED_PIPE_count1_a1_reg[0]/C + + + diff --git a/out/nexys_A7_100T/led_counter/Dependencies/clock_constraints.xdc b/out/nexys_A7_100T/led_counter/Dependencies/clock_constraints.xdc new file mode 100644 index 0000000..414fe4b --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/clock_constraints.xdc @@ -0,0 +1,3 @@ +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_default/clk_gate.sv b/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_default/clk_gate.sv new file mode 100644 index 0000000..e028887 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_default/clk_gate.sv @@ -0,0 +1,38 @@ +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Clock gate module used by SandPiper default project. + +// Note: No X injection for X on free_clk.) +module clk_gate (output logic gated_clk, input logic free_clk, func_en, pwr_en, gating_override); + logic clk_en; + logic latched_clk_en /*verilator clock_enable*/; + always_comb clk_en = func_en & (pwr_en | gating_override); + always_latch if (~free_clk) latched_clk_en <= clk_en; + // latched_clk_en <= (~free_clk) ? clk_en : latched_clk_en; + always_comb gated_clk = latched_clk_en & free_clk; +endmodule diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_default/sp_default.vh b/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_default/sp_default.vh new file mode 100644 index 0000000..a733969 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_default/sp_default.vh @@ -0,0 +1,8 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +`endif // SP_DEFAULT diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_verilog/clk_gate.v b/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_verilog/clk_gate.v new file mode 100644 index 0000000..5afd28f --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_verilog/clk_gate.v @@ -0,0 +1,39 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +`include "sp_verilog.vh" + + +// Clock gate module used by SandPiper default project. + +module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override); + wire clk_en; + reg latched_clk_en /*verilator clock_enable*/; + assign clk_en = func_en & (pwr_en | gating_override); + `TLV_BLATCH(latched_clk_en, clk_en, free_clk) + assign gated_clk = latched_clk_en & free_clk; +endmodule diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh b/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh new file mode 100644 index 0000000..0c28412 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh @@ -0,0 +1,65 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +// Latch macros. Inject 'x in simulation for clk === 'x. + +// A-phase latch. +`ifdef SP_PHYS +`define TLV_LATCH(in, out, clk) \ +always @ (in, clk) begin \ + if (clk === 1'b1) \ + out <= in; \ + else if (clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_LATCH(in, out, clk) always @ (in, clk) if (clk == 1'b1) out <= in; +`endif // SP_PHYS + +// B-phase latch. +`ifdef SP_PHYS +`define TLV_BLATCH(out, in, clk) \ +always @ (in, clk) begin \ + if (!clk === 1'b1) \ + out <= in; \ + else if (!clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_BLATCH(out, in, clk) always @ (in, clk) if (!clk == 1'b1) out <= in; +`endif // SP_PHYS + + + +`endif // SP_DEFAULT diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/pseudo_rand.tlv b/out/nexys_A7_100T/led_counter/Dependencies/includes/pseudo_rand.tlv new file mode 100644 index 0000000..cb0d614 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/pseudo_rand.tlv @@ -0,0 +1,69 @@ +\m4_TLV_version 1b: tl-x.org +\SV +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +module pseudo_rand + #(parameter WIDTH=257) // Random vector width, to a max of 257. + (input logic clk, + input logic reset, + output logic [WIDTH-1:0] rand_vect + ); + +// Currently, this implements a Galois LFSR. +// TODO: It should be XORed with something else so it doesn't just shift. +// Using polynomials with maximal number of taps would have less regular shifting behavior. + +// Bits are numbered in the reverse of the traditional order. This puts the taps in the lower bit positions. + +// Choose optimal parameters for given WIDTH. +localparam LFSR_WIDTH = + (WIDTH <= 64) ? 64 : + (WIDTH <= 128) ? 128 : + (WIDTH <= 257) ? 257 : 0; // 257 enables a large non-power of two for replication on an irregular boundary. +// Polynomial source: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf +localparam [LFSR_WIDTH-1:0] LFSR_POLY = {{(LFSR_WIDTH-8){1'b0}}, + (LFSR_WIDTH == 64) ? 8'b00011011 : + (LFSR_WIDTH == 128) ? 8'b10000111 : + (LFSR_WIDTH == 257) ? 8'b11000101 : 8'b0}; + +bit [256:0] SEED = 257'h0_7163e168_713d5431_6684e132_5cd84848_f3048b46_76874654_0c45f864_04e4684a; + + + +\TLV + |default + @0 + $reset = reset; + @1 + $lfsr[LFSR_WIDTH-1:0] = $reset ? *SEED : {$lfsr#+1[LFSR_WIDTH-2:0], 1'b0} ^ ({LFSR_WIDTH{$lfsr#+1[LFSR_WIDTH-1]}} & *LFSR_POLY); + @2 + *rand_vect = $lfsr[WIDTH-1:0]; + +\SV + +endmodule diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/rw_lib.vh b/out/nexys_A7_100T/led_counter/Dependencies/includes/rw_lib.vh new file mode 100644 index 0000000..39d5cd5 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/rw_lib.vh @@ -0,0 +1 @@ +`define RW_ZX(in, width) {{width-$width(in){1'b0}}, in} diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/sandhost/README.txt b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandhost/README.txt new file mode 100644 index 0000000..1816fee --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandhost/README.txt @@ -0,0 +1 @@ +Veriog include files that are available only within Makerchip. diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/sandhost/sqrt32.v b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandhost/sqrt32.v new file mode 100644 index 0000000..23e5dbc --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandhost/sqrt32.v @@ -0,0 +1,13 @@ +// A non-synthesizable Verilog-2005 sqrt function for tutorials. +`ifndef RW_NON_SYNTH_SQRT +`define RW_NON_SYNTH_SQRT + +function [31:0] sqrt; + input [31:0] a; + + /* verilator lint_off REALCVT */ + sqrt = $sqrt(a); + /* verilator lint_on REALCVT */ +endfunction + +`endif diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/sandhost/tb.sv b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandhost/tb.sv new file mode 100644 index 0000000..187fa4f --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandhost/tb.sv @@ -0,0 +1,76 @@ +// Provides clk and reset to design.tlv. +// Instantiates design as design(.*) so additional inputs and outputs can be added. +// Ends simulation on max cycles argument below, or assertion of success signal. +// Additional testbench functionality can be added here, or within design using TLV. +// See: "top_module_tlv.m4" for definition. + +// ------------------------------------------------------------------- +// Expanded from instantiation: m4_top_module_inst(m4_name, m4_max_cycles) +// + +module tb(); + +logic clk, reset; // Generated in this module for DUT. +logic passed, failed; // Returned from DUT to this module. Passed must assert before + // max cycles, without failed having asserted. Failed can be undriven. +logic [15:0] cyc_cnt; + + +// Instantiate main module. +top top(.*); + + +// Clock +initial begin + clk = 1'b1; + forever #5 clk = ~clk; +end + + +// Run +initial begin + + //`ifdef DUMP_ON + $dumpfile("top.vcd"); + $dumpvars(0, clk, reset, passed, failed, cyc_cnt, top.DEBUG_SIGS); + $dumpon; + //`endif + + reset = 1'b1; + #55; + reset = 1'b0; + + // Run + + cyc_cnt = '0; + for (int cyc = 0; cyc < 100; cyc++) begin + // Failed + if (failed === 1'b1) begin + FAILED: assert(1'b1) begin + $display("Failed!!! Error condition asserted."); + $finish; + end + end + + // Success + if (passed) begin + SUCCESS: assert(1'b1) begin + $display("Success!!!"); + $finish; + end + end + + #10; + + cyc_cnt++; + end + + // Fail + DIE: assert (1'b1) begin + $error("Failed!!! Test did not complete within m4_max_cycles time."); + $finish; + end + +end + +endmodule // life_tb diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/sandpiper.vh b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandpiper.vh new file mode 100644 index 0000000..26d3f19 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandpiper.vh @@ -0,0 +1,71 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Project-independent SandPiper header file. + +`ifndef SANDPIPER_VH +`define SANDPIPER_VH + + +// Note, these have no SP prefix, so collisions are possible. + + +`ifdef WHEN + // Make sure user definition does not collide. + !!!ERROR: WHEN macro already defined +`else + `ifdef SP_PHYS + // Phys compilation disabled X-injection. + `define WHEN(valid_sig) + `else + // Inject X. + `define WHEN(valid_sig) !valid_sig ? 'x : + `endif +`endif + + +// SandPiper does not generate set/reset flops. Reset is implemented as combinational +// logic, and it is up to synthesis to infer set/reset flops when possible. +//`ifdef RESET +// // Make sure user definition does not collide. +// !!!ERROR: RESET macro already defined +//`else +// `define RESET(i, reset) ((reset) ? '0 : i) +//`endif +// +//`ifdef SET +// // Make sure user definition does not collide. +// !!!ERROR: SET macro already defined +//`else +// `define SET(i, set) ((set) ? '1 : i) +//`endif + +// Since SandPiper required use of all signals, this is useful to create a +// bogus use and keep SandPiper happy when a signal, by intent, has no uses. +`define BOGUS_USE(ignore) + +`endif // SANDPIPER_VH diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/sandpiper_gen.vh b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandpiper_gen.vh new file mode 100644 index 0000000..d063661 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/sandpiper_gen.vh @@ -0,0 +1,4 @@ +// This just verifies that sandpiper.vh has been included. +`ifndef SANDPIPER_VH + !!!ERROR: SandPiper project's sp_.vh file must include sandpiper.vh. +`endif diff --git a/out/nexys_A7_100T/led_counter/Dependencies/includes/simple_bypass_fifo.sv b/out/nexys_A7_100T/led_counter/Dependencies/includes/simple_bypass_fifo.sv new file mode 100644 index 0000000..601c655 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/includes/simple_bypass_fifo.sv @@ -0,0 +1,98 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +`include "rw_lib.vh" + +// A simple implementation of a FIFO with bypass. +// Head is stored outside of the FIFO array. +// When the FIFO is empty, input goes straight through mux to output. +module simple_bypass_fifo( + input logic clk, + input logic reset, + input logic push, + input logic [WIDTH-1:0] data_in, // Timed with push. + input logic pop, // May pop in same cycle as push to empty FIFO. + output logic [WIDTH-1:0] data_out, // Same cycle as pop. + output logic [$clog2(DEPTH+1)-1:0] cnt // Reflecting push/pop last cycle. 0..DEPTH. +); + parameter WIDTH = 8; + parameter DEPTH = 8; + + logic [$clog2(DEPTH)-1:0] next_head, tail; + logic [WIDTH-1:0] arr [DEPTH-1:0], arr_out, head_data; + logic cnt_zero_or_one, cnt_zero, cnt_one; + logic push_arr, push_head, pop_from_arr, popped_from_arr; + + always_ff @(posedge clk) begin + if (reset) begin + tail <= {$clog2(DEPTH){1'b0}}; + next_head <= {$clog2(DEPTH){1'b0}}; + cnt <= {$clog2(DEPTH+1){1'b0}}; + end else begin + if (push_arr + ) begin + arr[tail] <= data_in; + tail <= tail + {{$clog2(DEPTH)-1{1'b0}}, 1'b1}; + end + if (pop) begin + arr_out <= arr[next_head]; + next_head <= next_head + {{$clog2(DEPTH)-1{1'b0}}, 1'b1}; + end + if (push ^ pop) begin + cnt <= cnt + (push ? {{$clog2(DEPTH+1)-1{1'b0}}, 1'b1} /* 1 */ : {$clog2(DEPTH+1){1'b1}} /* -1 */); + end + end + end + always_comb begin + // Control signals + + // These are timed with cnt (cycle after push/pop) + cnt_zero_or_one = (cnt >> 1) == {$clog2(DEPTH+1){1'b0}}; + cnt_zero = cnt_zero_or_one && ~cnt[0]; + cnt_one = cnt_zero_or_one && cnt[0]; + + // These are timed with push/pop + // Cases in which a push would not got into array. + push_arr = push && !(cnt_zero || (cnt_zero_or_one && pop)); + push_head = push && (pop ? cnt_one : cnt_zero); + pop_from_arr = pop && !cnt_zero_or_one; + + // Output data + data_out = cnt_zero ? data_in : head_data; + end + + // Head + always_ff @(posedge clk) begin + popped_from_arr <= pop_from_arr; + if (push_head) begin + head_data <= data_in; + end else if (popped_from_arr) begin + head_data <= arr_out; + end + end +endmodule diff --git a/out/nexys_A7_100T/led_counter/Dependencies/led_counter.v b/out/nexys_A7_100T/led_counter/Dependencies/led_counter.v new file mode 100644 index 0000000..88607c6 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/led_counter.v @@ -0,0 +1,345 @@ +//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta +`include "sp_verilog.vh" //_\SV + // Included URL: "https://raw.githubusercontent.com/BalaDhinesh/Virtual-FPGA-Lab/main/tlv_lib/fpga_includes.tlv" +//_\SV + + + + + module top(input clk, input reset, output reg [15:0] led); + + +`include "led_counter_gen.v" +generate //_\TLV + //_|led_pipe + //_@0 + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 3 // Instantiated from led_counter.tlv, 15 as: m4+fpga_refresh($refresh, m4_ifelse(M4_MAKERCHIP, 1, 1, 50000000)) + /* verilator lint_off UNSIGNED */ + assign LED_PIPE_rst1_a0 = reset; + assign LED_PIPE_count1_a0[31:0] = (LED_PIPE_count1_a1[31:0] >= 50000000 - 1) | LED_PIPE_rst1_a1 ? 1'b0 : LED_PIPE_count1_a1[31:0] + 1 ; + assign LED_PIPE_refresh_a0 = (LED_PIPE_count1_a0 == 50000000 - 1) ? 1'b1 : 1'b0 ; + + //_\end_source + assign LED_PIPE_reset_a0 = reset; + //_?$refresh + assign LED_PIPE_Leds_n1[15:0] = LED_PIPE_reset_a0 ? 1 : LED_PIPE_Leds_a0+1; + /*SV_plus*/ + always@(posedge clk) begin + led = LED_PIPE_Leds_a0; + end + // M4_BOARD numbering + // 1 - Zedboard + // 2 - Artix-7 + // 3 - Basys3 + // 4 - Icebreaker + // 5 - Nexys + + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 32 // Instantiated from led_counter.tlv, 30 as: m4+fpga_init() + //m4+osfpga_logo() + //_|fpga_init_macro + //_@0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + //_\end_source + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 245 // Instantiated from led_counter.tlv, 31 as: m4+fpga_led(*led) + //_|led_pipe_macro + //_@0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + //_\end_source +endgenerate +//_\SV + endmodule diff --git a/out/nexys_A7_100T/led_counter/Dependencies/led_counter_gen.v b/out/nexys_A7_100T/led_counter/Dependencies/led_counter_gen.v new file mode 100644 index 0000000..fc366a2 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Dependencies/led_counter_gen.v @@ -0,0 +1,81 @@ +// Generated by SandPiper(TM) 1.11-2021/01/28-beta from Redwood EDA. +// Redwood EDA does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality. + + +`include "sandpiper_gen.vh" + + + + + +// +// Signals declared top-level. +// + +// For |led_pipe$Leds. +wire [15:0] LED_PIPE_Leds_n1; +reg [15:0] LED_PIPE_Leds_a0; + +// For |led_pipe$count1. +wire [31:0] LED_PIPE_count1_a0; +reg [31:0] LED_PIPE_count1_a1; + +// For |led_pipe$refresh. +wire LED_PIPE_refresh_a0; + +// For |led_pipe$reset. +wire LED_PIPE_reset_a0; + +// For |led_pipe$rst1. +wire LED_PIPE_rst1_a0; +reg LED_PIPE_rst1_a1; + + +// +// Scope: |led_pipe +// + +// Clock signals. +wire clkF_LED_PIPE_refresh_a1 ; + + +generate + + + // + // Scope: |led_pipe + // + + // For $Leds. + always @(posedge clkF_LED_PIPE_refresh_a1) LED_PIPE_Leds_a0[15:0] <= LED_PIPE_Leds_n1[15:0]; + + // For $count1. + always @(posedge clk) LED_PIPE_count1_a1[31:0] <= LED_PIPE_count1_a0[31:0]; + + // For $rst1. + always @(posedge clk) LED_PIPE_rst1_a1 <= LED_PIPE_rst1_a0; + + + + +endgenerate + + + +// +// Gated clocks. +// + +generate + + + + // + // Scope: |led_pipe + // + + clk_gate gen_clkF_LED_PIPE_refresh_a1(clkF_LED_PIPE_refresh_a1, clk, LED_PIPE_refresh_a0, 1'b1, 1'b0); + + + +endgenerate diff --git a/out/nexys_A7_100T/led_counter/Output/fpga_impl.xdc b/out/nexys_A7_100T/led_counter/Output/fpga_impl.xdc new file mode 100644 index 0000000..d9feed7 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/fpga_impl.xdc @@ -0,0 +1,290 @@ + +#################################################################################### +# Generated by Vivado 2020.2 built on 'Wed Nov 18 09:12:47 MST 2020' by 'xbuild' +# Command Used: write_xdc -no_fixed_only -force ./../out/nexys_A7_100T/led_counter/Output/fpga_impl.xdc +#################################################################################### + + +#################################################################################### +# Constraints from file : 'fpga_lab_constr_nexys_A7_100T.xdc' +#################################################################################### + +# This file is a general .xdc for the Nexys A7-100T +# To use it in a project: +# - uncomment the lines corresponding to used pins +# - rename the used ports (in each line, after get_ports) according to the top level signal names in the project +# Clock signal +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk] +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk] +#Switches +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports reset] +# leds +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {led[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {led[5]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {led[6]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {led[7]}] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {led[8]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {led[9]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {led[10]}] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {led[11]}] +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {led[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {led[13]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {led[14]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {led[15]}] +# RGB leds +#7 segment display +#Buttons +#Pmod Headers +#Pmod Header JA +#Pmod Header JB +#Pmod Header JC +#Pmod Header JD +#Pmod Header JXADC +#VGA Connector +#Micro SD Connector +#Accelerometer +#Temperature Sensor +#Omnidirectional Microphone +#PWM Audio Amplifier +#USB-RS232 Interface +#USB HID (PS/2) +#SMSC Ethernet PHY +#Quad SPI Flash + + +#################################################################################### +# Constraints from file : 'clock_constraints.xdc' +#################################################################################### + +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] + + +# Vivado Generated physical constraints + +set_property BEL A6LUT [get_cells {LED_PIPE_Leds_a0[0]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[0]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[10]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[11]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[12]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[12]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[13]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[14]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[15]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[15]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[1]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[2]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[3]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[4]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[4]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[5]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[6]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[7]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[8]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[8]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[9]}] +set_property BEL A5LUT [get_cells {LED_PIPE_count1_a1[0]_i_1}] +set_property BEL D6LUT [get_cells {LED_PIPE_count1_a1[31]_i_1}] +set_property BEL A6LUT [get_cells {LED_PIPE_count1_a1[31]_i_4}] +set_property BEL B6LUT [get_cells {LED_PIPE_count1_a1[31]_i_5}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[0]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[10]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[11]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[12]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[12]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[13]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[14]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[15]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[16]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[16]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[17]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[18]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[19]}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[1]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[20]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[20]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[21]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[22]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[23]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[24]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[24]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[25]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[26]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[27]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[28]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[28]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[29]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[2]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[30]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[31]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[31]_i_2}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[3]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[4]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[4]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[5]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[6]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[7]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[8]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[8]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[9]}] +set_property BEL AFF [get_cells LED_PIPE_rst1_a1_reg] +set_property BEL BUFG [get_cells clk_IBUF_BUFG_inst] +set_property BEL INBUF_EN [get_cells clk_IBUF_inst] +set_property BEL A6LUT [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2}] +set_property BEL A6LUT [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_count1_a1[31]_i_3}] +set_property BEL CFF [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_10] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_11] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_12] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_13] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_14] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_4] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_5] +set_property BEL D6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_6] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7] +set_property BEL D6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_9] +set_property BEL OUTBUF [get_cells {led_OBUF[0]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[10]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[11]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[12]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[13]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[14]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[15]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[1]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[2]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[3]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[4]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[5]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[6]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[7]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[8]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[9]_inst}] +set_property BEL AFF [get_cells {led_reg[0]}] +set_property BEL BFF [get_cells {led_reg[10]}] +set_property BEL CFF [get_cells {led_reg[11]}] +set_property BEL AFF [get_cells {led_reg[12]}] +set_property BEL BFF [get_cells {led_reg[13]}] +set_property BEL CFF [get_cells {led_reg[14]}] +set_property BEL DFF [get_cells {led_reg[15]}] +set_property BEL AFF [get_cells {led_reg[1]}] +set_property BEL BFF [get_cells {led_reg[2]}] +set_property BEL AFF [get_cells {led_reg[3]}] +set_property BEL BFF [get_cells {led_reg[4]}] +set_property BEL CFF [get_cells {led_reg[5]}] +set_property BEL DFF [get_cells {led_reg[6]}] +set_property BEL A5FF [get_cells {led_reg[7]}] +set_property BEL B5FF [get_cells {led_reg[8]}] +set_property BEL BFF [get_cells {led_reg[9]}] +set_property BEL INBUF_EN [get_cells reset_IBUF_inst] +set_property LOC SLICE_X2Y99 [get_cells {LED_PIPE_Leds_a0[0]_i_1}] +set_property LOC SLICE_X2Y99 [get_cells {LED_PIPE_Leds_a0_reg[0]}] +set_property LOC SLICE_X5Y101 [get_cells {LED_PIPE_Leds_a0_reg[10]}] +set_property LOC SLICE_X5Y101 [get_cells {LED_PIPE_Leds_a0_reg[11]}] +set_property LOC SLICE_X5Y101 [get_cells {LED_PIPE_Leds_a0_reg[12]}] +set_property LOC SLICE_X5Y101 [get_cells {LED_PIPE_Leds_a0_reg[12]_i_1}] +set_property LOC SLICE_X5Y102 [get_cells {LED_PIPE_Leds_a0_reg[13]}] +set_property LOC SLICE_X5Y102 [get_cells {LED_PIPE_Leds_a0_reg[14]}] +set_property LOC SLICE_X5Y102 [get_cells {LED_PIPE_Leds_a0_reg[15]}] +set_property LOC SLICE_X5Y102 [get_cells {LED_PIPE_Leds_a0_reg[15]_i_1}] +set_property LOC SLICE_X5Y99 [get_cells {LED_PIPE_Leds_a0_reg[1]}] +set_property LOC SLICE_X5Y99 [get_cells {LED_PIPE_Leds_a0_reg[2]}] +set_property LOC SLICE_X5Y99 [get_cells {LED_PIPE_Leds_a0_reg[3]}] +set_property LOC SLICE_X5Y99 [get_cells {LED_PIPE_Leds_a0_reg[4]}] +set_property LOC SLICE_X5Y99 [get_cells {LED_PIPE_Leds_a0_reg[4]_i_1}] +set_property LOC SLICE_X5Y100 [get_cells {LED_PIPE_Leds_a0_reg[5]}] +set_property LOC SLICE_X5Y100 [get_cells {LED_PIPE_Leds_a0_reg[6]}] +set_property LOC SLICE_X5Y100 [get_cells {LED_PIPE_Leds_a0_reg[7]}] +set_property LOC SLICE_X5Y100 [get_cells {LED_PIPE_Leds_a0_reg[8]}] +set_property LOC SLICE_X5Y100 [get_cells {LED_PIPE_Leds_a0_reg[8]_i_1}] +set_property LOC SLICE_X5Y101 [get_cells {LED_PIPE_Leds_a0_reg[9]}] +set_property LOC SLICE_X0Y97 [get_cells {LED_PIPE_count1_a1[0]_i_1}] +set_property LOC SLICE_X0Y100 [get_cells {LED_PIPE_count1_a1[31]_i_1}] +set_property LOC SLICE_X0Y97 [get_cells {LED_PIPE_count1_a1[31]_i_4}] +set_property LOC SLICE_X0Y96 [get_cells {LED_PIPE_count1_a1[31]_i_5}] +set_property LOC SLICE_X0Y97 [get_cells {LED_PIPE_count1_a1_reg[0]}] +set_property LOC SLICE_X1Y98 [get_cells {LED_PIPE_count1_a1_reg[10]}] +set_property LOC SLICE_X1Y98 [get_cells {LED_PIPE_count1_a1_reg[11]}] +set_property LOC SLICE_X1Y98 [get_cells {LED_PIPE_count1_a1_reg[12]}] +set_property LOC SLICE_X1Y98 [get_cells {LED_PIPE_count1_a1_reg[12]_i_1}] +set_property LOC SLICE_X1Y99 [get_cells {LED_PIPE_count1_a1_reg[13]}] +set_property LOC SLICE_X1Y99 [get_cells {LED_PIPE_count1_a1_reg[14]}] +set_property LOC SLICE_X1Y99 [get_cells {LED_PIPE_count1_a1_reg[15]}] +set_property LOC SLICE_X1Y99 [get_cells {LED_PIPE_count1_a1_reg[16]}] +set_property LOC SLICE_X1Y99 [get_cells {LED_PIPE_count1_a1_reg[16]_i_1}] +set_property LOC SLICE_X1Y100 [get_cells {LED_PIPE_count1_a1_reg[17]}] +set_property LOC SLICE_X1Y100 [get_cells {LED_PIPE_count1_a1_reg[18]}] +set_property LOC SLICE_X1Y100 [get_cells {LED_PIPE_count1_a1_reg[19]}] +set_property LOC SLICE_X1Y96 [get_cells {LED_PIPE_count1_a1_reg[1]}] +set_property LOC SLICE_X1Y100 [get_cells {LED_PIPE_count1_a1_reg[20]}] +set_property LOC SLICE_X1Y100 [get_cells {LED_PIPE_count1_a1_reg[20]_i_1}] +set_property LOC SLICE_X1Y101 [get_cells {LED_PIPE_count1_a1_reg[21]}] +set_property LOC SLICE_X1Y101 [get_cells {LED_PIPE_count1_a1_reg[22]}] +set_property LOC SLICE_X1Y101 [get_cells {LED_PIPE_count1_a1_reg[23]}] +set_property LOC SLICE_X1Y101 [get_cells {LED_PIPE_count1_a1_reg[24]}] +set_property LOC SLICE_X1Y101 [get_cells {LED_PIPE_count1_a1_reg[24]_i_1}] +set_property LOC SLICE_X1Y102 [get_cells {LED_PIPE_count1_a1_reg[25]}] +set_property LOC SLICE_X1Y102 [get_cells {LED_PIPE_count1_a1_reg[26]}] +set_property LOC SLICE_X1Y102 [get_cells {LED_PIPE_count1_a1_reg[27]}] +set_property LOC SLICE_X1Y102 [get_cells {LED_PIPE_count1_a1_reg[28]}] +set_property LOC SLICE_X1Y102 [get_cells {LED_PIPE_count1_a1_reg[28]_i_1}] +set_property LOC SLICE_X1Y103 [get_cells {LED_PIPE_count1_a1_reg[29]}] +set_property LOC SLICE_X1Y96 [get_cells {LED_PIPE_count1_a1_reg[2]}] +set_property LOC SLICE_X1Y103 [get_cells {LED_PIPE_count1_a1_reg[30]}] +set_property LOC SLICE_X1Y103 [get_cells {LED_PIPE_count1_a1_reg[31]}] +set_property LOC SLICE_X1Y103 [get_cells {LED_PIPE_count1_a1_reg[31]_i_2}] +set_property LOC SLICE_X1Y96 [get_cells {LED_PIPE_count1_a1_reg[3]}] +set_property LOC SLICE_X1Y96 [get_cells {LED_PIPE_count1_a1_reg[4]}] +set_property LOC SLICE_X1Y96 [get_cells {LED_PIPE_count1_a1_reg[4]_i_1}] +set_property LOC SLICE_X1Y97 [get_cells {LED_PIPE_count1_a1_reg[5]}] +set_property LOC SLICE_X1Y97 [get_cells {LED_PIPE_count1_a1_reg[6]}] +set_property LOC SLICE_X1Y97 [get_cells {LED_PIPE_count1_a1_reg[7]}] +set_property LOC SLICE_X1Y97 [get_cells {LED_PIPE_count1_a1_reg[8]}] +set_property LOC SLICE_X1Y97 [get_cells {LED_PIPE_count1_a1_reg[8]_i_1}] +set_property LOC SLICE_X1Y98 [get_cells {LED_PIPE_count1_a1_reg[9]}] +set_property LOC SLICE_X0Y100 [get_cells LED_PIPE_rst1_a1_reg] +set_property LOC BUFGCTRL_X0Y16 [get_cells clk_IBUF_BUFG_inst] +set_property LOC SLICE_X4Y100 [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2}] +set_property LOC SLICE_X0Y102 [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_count1_a1[31]_i_3}] +set_property LOC SLICE_X3Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg] +set_property LOC SLICE_X3Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1] +set_property LOC SLICE_X0Y96 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_10] +set_property LOC SLICE_X0Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_11] +set_property LOC SLICE_X0Y99 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_12] +set_property LOC SLICE_X0Y98 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_13] +set_property LOC SLICE_X0Y98 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_14] +set_property LOC SLICE_X3Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3] +set_property LOC SLICE_X0Y99 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_4] +set_property LOC SLICE_X0Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_5] +set_property LOC SLICE_X0Y99 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_6] +set_property LOC SLICE_X3Y102 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7] +set_property LOC SLICE_X3Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8] +set_property LOC SLICE_X0Y101 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_9] +set_property LOC SLICE_X2Y102 [get_cells {led_reg[0]}] +set_property LOC SLICE_X0Y100 [get_cells {led_reg[10]}] +set_property LOC SLICE_X0Y100 [get_cells {led_reg[11]}] +set_property LOC SLICE_X0Y101 [get_cells {led_reg[12]}] +set_property LOC SLICE_X2Y102 [get_cells {led_reg[13]}] +set_property LOC SLICE_X2Y102 [get_cells {led_reg[14]}] +set_property LOC SLICE_X2Y102 [get_cells {led_reg[15]}] +set_property LOC SLICE_X0Y99 [get_cells {led_reg[1]}] +set_property LOC SLICE_X0Y99 [get_cells {led_reg[2]}] +set_property LOC SLICE_X0Y96 [get_cells {led_reg[3]}] +set_property LOC SLICE_X0Y96 [get_cells {led_reg[4]}] +set_property LOC SLICE_X0Y96 [get_cells {led_reg[5]}] +set_property LOC SLICE_X0Y100 [get_cells {led_reg[6]}] +set_property LOC SLICE_X0Y100 [get_cells {led_reg[7]}] +set_property LOC SLICE_X0Y100 [get_cells {led_reg[8]}] +set_property LOC SLICE_X0Y101 [get_cells {led_reg[9]}] + +# Vivado Generated miscellaneous constraints + +#revert back to original instance +current_instance -quiet diff --git a/out/nexys_A7_100T/led_counter/Output/fpga_impl_netlist.v b/out/nexys_A7_100T/led_counter/Output/fpga_impl_netlist.v new file mode 100644 index 0000000..ac9cf01 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/fpga_impl_netlist.v @@ -0,0 +1,938 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Sat Oct 30 02:59:15 2021 +// Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +// Command : write_verilog -force ./../out/nexys_A7_100T/led_counter/Output/fpga_impl_netlist.v +// Design : top +// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an +// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input +// design files. +// Device : xc7a100tcsg324-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module clk_gate + (\LED_PIPE_count1_a1_reg[11] , + \LED_PIPE_count1_a1_reg[24] , + \LED_PIPE_count1_a1_reg[28] , + CLK, + LED_PIPE_count1_a1, + O, + latched_clk_en_reg_i_6_0, + latched_clk_en_reg_i_3_0, + latched_clk_en_reg_i_6_1, + latched_clk_en_reg_i_3_1, + latched_clk_en_reg_i_3_2, + latched_clk_en_reg_i_3_3, + latched_clk_en_reg_i_3_4, + LED_PIPE_rst1_a1, + clk_IBUF, + clk_IBUF_BUFG); + output \LED_PIPE_count1_a1_reg[11] ; + output \LED_PIPE_count1_a1_reg[24] ; + output \LED_PIPE_count1_a1_reg[28] ; + output CLK; + input [25:0]LED_PIPE_count1_a1; + input [3:0]O; + input [3:0]latched_clk_en_reg_i_6_0; + input [3:0]latched_clk_en_reg_i_3_0; + input [3:0]latched_clk_en_reg_i_6_1; + input [3:0]latched_clk_en_reg_i_3_1; + input [3:0]latched_clk_en_reg_i_3_2; + input [3:0]latched_clk_en_reg_i_3_3; + input [2:0]latched_clk_en_reg_i_3_4; + input LED_PIPE_rst1_a1; + input clk_IBUF; + input clk_IBUF_BUFG; + + wire CLK; + wire GND_1; + wire [25:0]LED_PIPE_count1_a1; + wire \LED_PIPE_count1_a1_reg[11] ; + wire \LED_PIPE_count1_a1_reg[24] ; + wire \LED_PIPE_count1_a1_reg[28] ; + wire LED_PIPE_refresh_a0; + wire LED_PIPE_rst1_a1; + wire [3:0]O; + wire VCC_1; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire latched_clk_en; + wire latched_clk_en_reg_i_10_n_0; + wire latched_clk_en_reg_i_11_n_0; + wire latched_clk_en_reg_i_12_n_0; + wire latched_clk_en_reg_i_13_n_0; + wire latched_clk_en_reg_i_14_n_0; + wire [3:0]latched_clk_en_reg_i_3_0; + wire [3:0]latched_clk_en_reg_i_3_1; + wire [3:0]latched_clk_en_reg_i_3_2; + wire [3:0]latched_clk_en_reg_i_3_3; + wire [2:0]latched_clk_en_reg_i_3_4; + wire latched_clk_en_reg_i_3_n_0; + wire [3:0]latched_clk_en_reg_i_6_0; + wire [3:0]latched_clk_en_reg_i_6_1; + wire latched_clk_en_reg_i_6_n_0; + wire latched_clk_en_reg_i_7_n_0; + wire latched_clk_en_reg_i_8_n_0; + wire latched_clk_en_reg_i_9_n_0; + + GND GND + (.G(GND_1)); + LUT2 #( + .INIT(4'h8)) + \LED_PIPE_Leds_a0[15]_i_2 + (.I0(latched_clk_en), + .I1(clk_IBUF), + .O(CLK)); + LUT6 #( + .INIT(64'h0000000000000001)) + \LED_PIPE_count1_a1[31]_i_3 + (.I0(LED_PIPE_count1_a1[22]), + .I1(LED_PIPE_count1_a1[23]), + .I2(LED_PIPE_count1_a1[20]), + .I3(LED_PIPE_count1_a1[21]), + .I4(LED_PIPE_count1_a1[25]), + .I5(LED_PIPE_count1_a1[24]), + .O(\LED_PIPE_count1_a1_reg[28] )); + VCC VCC + (.P(VCC_1)); + (* OPT_MODIFIED = "MLO" *) + (* XILINX_LEGACY_PRIM = "LD" *) + LDCE #( + .INIT(1'b0), + .IS_G_INVERTED(1'b1)) + latched_clk_en_reg + (.CLR(GND_1), + .D(LED_PIPE_refresh_a0), + .G(clk_IBUF_BUFG), + .GE(VCC_1), + .Q(latched_clk_en)); + LUT4 #( + .INIT(16'hA800)) + latched_clk_en_reg_i_1 + (.I0(latched_clk_en_reg_i_3_n_0), + .I1(\LED_PIPE_count1_a1_reg[11] ), + .I2(\LED_PIPE_count1_a1_reg[24] ), + .I3(latched_clk_en_reg_i_6_n_0), + .O(LED_PIPE_refresh_a0)); + LUT4 #( + .INIT(16'h0001)) + latched_clk_en_reg_i_10 + (.I0(LED_PIPE_count1_a1[2]), + .I1(LED_PIPE_count1_a1[1]), + .I2(LED_PIPE_count1_a1[4]), + .I3(LED_PIPE_count1_a1[3]), + .O(latched_clk_en_reg_i_10_n_0)); + LUT4 #( + .INIT(16'h7FFF)) + latched_clk_en_reg_i_11 + (.I0(LED_PIPE_count1_a1[14]), + .I1(LED_PIPE_count1_a1[13]), + .I2(LED_PIPE_count1_a1[16]), + .I3(LED_PIPE_count1_a1[15]), + .O(latched_clk_en_reg_i_11_n_0)); + LUT6 #( + .INIT(64'h15555555FFFFFFFF)) + latched_clk_en_reg_i_12 + (.I0(LED_PIPE_count1_a1[10]), + .I1(LED_PIPE_count1_a1[7]), + .I2(LED_PIPE_count1_a1[6]), + .I3(LED_PIPE_count1_a1[9]), + .I4(LED_PIPE_count1_a1[8]), + .I5(LED_PIPE_count1_a1[11]), + .O(latched_clk_en_reg_i_12_n_0)); + LUT6 #( + .INIT(64'h0000000000002000)) + latched_clk_en_reg_i_13 + (.I0(latched_clk_en_reg_i_6_1[1]), + .I1(latched_clk_en_reg_i_6_1[2]), + .I2(O[3]), + .I3(latched_clk_en_reg_i_6_1[0]), + .I4(latched_clk_en_reg_i_6_0[0]), + .I5(latched_clk_en_reg_i_6_1[3]), + .O(latched_clk_en_reg_i_13_n_0)); + LUT6 #( + .INIT(64'h0008000000000000)) + latched_clk_en_reg_i_14 + (.I0(latched_clk_en_reg_i_6_0[3]), + .I1(latched_clk_en_reg_i_3_0[0]), + .I2(latched_clk_en_reg_i_6_0[1]), + .I3(latched_clk_en_reg_i_6_0[2]), + .I4(latched_clk_en_reg_i_3_0[2]), + .I5(latched_clk_en_reg_i_3_0[1]), + .O(latched_clk_en_reg_i_14_n_0)); + LUT4 #( + .INIT(16'h8000)) + latched_clk_en_reg_i_3 + (.I0(latched_clk_en_reg_i_7_n_0), + .I1(\LED_PIPE_count1_a1_reg[28] ), + .I2(latched_clk_en_reg_i_8_n_0), + .I3(latched_clk_en_reg_i_9_n_0), + .O(latched_clk_en_reg_i_3_n_0)); + LUT5 #( + .INIT(32'h00010000)) + latched_clk_en_reg_i_4 + (.I0(LED_PIPE_count1_a1[5]), + .I1(LED_PIPE_count1_a1[10]), + .I2(LED_PIPE_count1_a1[12]), + .I3(LED_PIPE_count1_a1[18]), + .I4(latched_clk_en_reg_i_10_n_0), + .O(\LED_PIPE_count1_a1_reg[11] )); + LUT6 #( + .INIT(64'h45455545FFFFFFFF)) + latched_clk_en_reg_i_5 + (.I0(LED_PIPE_count1_a1[18]), + .I1(latched_clk_en_reg_i_11_n_0), + .I2(LED_PIPE_count1_a1[17]), + .I3(latched_clk_en_reg_i_12_n_0), + .I4(LED_PIPE_count1_a1[12]), + .I5(LED_PIPE_count1_a1[19]), + .O(\LED_PIPE_count1_a1_reg[24] )); + LUT5 #( + .INIT(32'h80000000)) + latched_clk_en_reg_i_6 + (.I0(latched_clk_en_reg_i_13_n_0), + .I1(O[2]), + .I2(O[1]), + .I3(O[0]), + .I4(latched_clk_en_reg_i_14_n_0), + .O(latched_clk_en_reg_i_6_n_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + latched_clk_en_reg_i_7 + (.I0(latched_clk_en_reg_i_3_4[1]), + .I1(latched_clk_en_reg_i_3_4[2]), + .I2(latched_clk_en_reg_i_3_3[3]), + .I3(latched_clk_en_reg_i_3_4[0]), + .I4(LED_PIPE_count1_a1[0]), + .I5(LED_PIPE_rst1_a1), + .O(latched_clk_en_reg_i_7_n_0)); + LUT6 #( + .INIT(64'h0020000000000000)) + latched_clk_en_reg_i_8 + (.I0(latched_clk_en_reg_i_3_1[2]), + .I1(latched_clk_en_reg_i_3_1[1]), + .I2(latched_clk_en_reg_i_3_1[0]), + .I3(latched_clk_en_reg_i_3_0[3]), + .I4(latched_clk_en_reg_i_3_2[0]), + .I5(latched_clk_en_reg_i_3_1[3]), + .O(latched_clk_en_reg_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000000002000)) + latched_clk_en_reg_i_9 + (.I0(latched_clk_en_reg_i_3_3[0]), + .I1(latched_clk_en_reg_i_3_2[3]), + .I2(latched_clk_en_reg_i_3_2[1]), + .I3(latched_clk_en_reg_i_3_2[2]), + .I4(latched_clk_en_reg_i_3_3[2]), + .I5(latched_clk_en_reg_i_3_3[1]), + .O(latched_clk_en_reg_i_9_n_0)); +endmodule + +(* ECO_CHECKSUM = "96723c4c" *) +(* STRUCTURAL_NETLIST = "yes" *) +module top + (clk, + reset, + led); + input clk; + input reset; + output [15:0]led; + + wire \ ; + wire \ ; + wire [15:0]LED_PIPE_Leds_a0; + wire \LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ; + wire \LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ; + wire \LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ; + wire [15:0]LED_PIPE_Leds_n10_in; + wire [31:0]LED_PIPE_count1_a1; + wire \LED_PIPE_count1_a1[0]_i_1_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_1_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_4_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_5_n_0 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_5 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_6 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_7 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_7 ; + wire LED_PIPE_rst1_a1; + wire clk; + wire clkF_LED_PIPE_refresh_a1; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire gen_clkF_LED_PIPE_refresh_a1_n_0; + wire gen_clkF_LED_PIPE_refresh_a1_n_1; + wire gen_clkF_LED_PIPE_refresh_a1_n_2; + wire [15:0]led; + wire [15:0]led_OBUF; + wire reset; + wire reset_IBUF; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[4]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[8]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[16]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[20]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[24]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[4]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[8]_i_1_CO_UNCONNECTED ; + + GND GND + (.G(\ )); + LUT1 #( + .INIT(2'h1)) + \LED_PIPE_Leds_a0[0]_i_1 + (.I0(LED_PIPE_Leds_a0[0]), + .O(LED_PIPE_Leds_n10_in[0])); + FDSE \LED_PIPE_Leds_a0_reg[0] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[0]), + .Q(LED_PIPE_Leds_a0[0]), + .S(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[10] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[10]), + .Q(LED_PIPE_Leds_a0[10]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[11] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[11]), + .Q(LED_PIPE_Leds_a0[11]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[12] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[12]), + .Q(LED_PIPE_Leds_a0[12]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[12]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ), + .CO({\LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[12]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[12:9]), + .S(LED_PIPE_Leds_a0[12:9])); + FDRE \LED_PIPE_Leds_a0_reg[13] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[13]), + .Q(LED_PIPE_Leds_a0[13]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[14] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[14]), + .Q(LED_PIPE_Leds_a0[14]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[15] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[15]), + .Q(LED_PIPE_Leds_a0[15]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[15]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[15:13]), + .S({\ ,LED_PIPE_Leds_a0[15:13]})); + FDRE \LED_PIPE_Leds_a0_reg[1] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[1]), + .Q(LED_PIPE_Leds_a0[1]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[2] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[2]), + .Q(LED_PIPE_Leds_a0[2]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[3] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[3]), + .Q(LED_PIPE_Leds_a0[3]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[4] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[4]), + .Q(LED_PIPE_Leds_a0[4]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[4]_i_1 + (.CI(\ ), + .CO({\LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[4]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(LED_PIPE_Leds_a0[0]), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[4:1]), + .S(LED_PIPE_Leds_a0[4:1])); + FDRE \LED_PIPE_Leds_a0_reg[5] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[5]), + .Q(LED_PIPE_Leds_a0[5]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[6] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[6]), + .Q(LED_PIPE_Leds_a0[6]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[7] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[7]), + .Q(LED_PIPE_Leds_a0[7]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[8] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[8]), + .Q(LED_PIPE_Leds_a0[8]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[8]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ), + .CO({\LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[8]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[8:5]), + .S(LED_PIPE_Leds_a0[8:5])); + FDRE \LED_PIPE_Leds_a0_reg[9] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[9]), + .Q(LED_PIPE_Leds_a0[9]), + .R(reset_IBUF)); + (* \PinAttr:I0:HOLD_DETOUR = "197" *) + LUT1 #( + .INIT(2'h1)) + \LED_PIPE_count1_a1[0]_i_1 + (.I0(LED_PIPE_count1_a1[0]), + .O(\LED_PIPE_count1_a1[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hBBBFBFBF)) + \LED_PIPE_count1_a1[31]_i_1 + (.I0(LED_PIPE_rst1_a1), + .I1(gen_clkF_LED_PIPE_refresh_a1_n_2), + .I2(gen_clkF_LED_PIPE_refresh_a1_n_1), + .I3(gen_clkF_LED_PIPE_refresh_a1_n_0), + .I4(\LED_PIPE_count1_a1[31]_i_4_n_0 ), + .O(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* \PinAttr:I1:HOLD_DETOUR = "197" *) + LUT4 #( + .INIT(16'hBFFF)) + \LED_PIPE_count1_a1[31]_i_4 + (.I0(\LED_PIPE_count1_a1[31]_i_5_n_0 ), + .I1(LED_PIPE_count1_a1[0]), + .I2(LED_PIPE_count1_a1[5]), + .I3(LED_PIPE_count1_a1[6]), + .O(\LED_PIPE_count1_a1[31]_i_4_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \LED_PIPE_count1_a1[31]_i_5 + (.I0(LED_PIPE_count1_a1[2]), + .I1(LED_PIPE_count1_a1[1]), + .I2(LED_PIPE_count1_a1[4]), + .I3(LED_PIPE_count1_a1[3]), + .O(\LED_PIPE_count1_a1[31]_i_5_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[0] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1[0]_i_1_n_0 ), + .Q(LED_PIPE_count1_a1[0]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[10] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[10]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[11] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[11]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[12] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[12]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[12]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[8]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[12]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[12]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[12:9])); + FDRE \LED_PIPE_count1_a1_reg[13] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[13]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[14] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[14]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[15] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[15]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[16] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[16]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[16]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[12]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[16]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[16]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[16:13])); + FDRE \LED_PIPE_count1_a1_reg[17] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[17]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[18] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[18]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[19] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[19]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[1] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[1]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[20] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[20]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[20]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[16]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[20]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[20]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[20:17])); + FDRE \LED_PIPE_count1_a1_reg[21] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[21]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[22] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[22]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[23] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[23]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[24] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[24]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[24]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[20]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[24]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[24]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[24:21])); + FDRE \LED_PIPE_count1_a1_reg[25] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[25]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[26] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[26]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[27] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[27]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[28] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[28]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[28]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[24]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[28]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[28]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[28:25])); + FDRE \LED_PIPE_count1_a1_reg[29] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_7 ), + .Q(LED_PIPE_count1_a1[29]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[2] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[2]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[30] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ), + .Q(LED_PIPE_count1_a1[30]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[31] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ), + .Q(LED_PIPE_count1_a1[31]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[31]_i_2 + (.CI(\LED_PIPE_count1_a1_reg[28]_i_1_n_0 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_7 }), + .S({\ ,LED_PIPE_count1_a1[31:29]})); + FDRE \LED_PIPE_count1_a1_reg[3] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[3]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[4] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[4]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[4]_i_1 + (.CI(\ ), + .CO({\LED_PIPE_count1_a1_reg[4]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[4]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(LED_PIPE_count1_a1[0]), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[4:1])); + FDRE \LED_PIPE_count1_a1_reg[5] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[5]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[6] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[6]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[7] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[7]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[8] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[8]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[8]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[4]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[8]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[8]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[8:5])); + FDRE \LED_PIPE_count1_a1_reg[9] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[9]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE LED_PIPE_rst1_a1_reg + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(reset_IBUF), + .Q(LED_PIPE_rst1_a1), + .R(\ )); + VCC VCC + (.P(\ )); + BUFG clk_IBUF_BUFG_inst + (.I(clk_IBUF), + .O(clk_IBUF_BUFG)); + IBUF clk_IBUF_inst + (.I(clk), + .O(clk_IBUF)); + clk_gate gen_clkF_LED_PIPE_refresh_a1 + (.CLK(clkF_LED_PIPE_refresh_a1), + .LED_PIPE_count1_a1({LED_PIPE_count1_a1[31:7],LED_PIPE_count1_a1[0]}), + .\LED_PIPE_count1_a1_reg[11] (gen_clkF_LED_PIPE_refresh_a1_n_0), + .\LED_PIPE_count1_a1_reg[24] (gen_clkF_LED_PIPE_refresh_a1_n_1), + .\LED_PIPE_count1_a1_reg[28] (gen_clkF_LED_PIPE_refresh_a1_n_2), + .LED_PIPE_rst1_a1(LED_PIPE_rst1_a1), + .O({\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_7 }), + .clk_IBUF(clk_IBUF), + .clk_IBUF_BUFG(clk_IBUF_BUFG), + .latched_clk_en_reg_i_3_0({\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_7 }), + .latched_clk_en_reg_i_3_1({\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_7 }), + .latched_clk_en_reg_i_3_2({\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_7 }), + .latched_clk_en_reg_i_3_3({\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_7 }), + .latched_clk_en_reg_i_3_4({\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_7 }), + .latched_clk_en_reg_i_6_0({\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_7 }), + .latched_clk_en_reg_i_6_1({\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_7 })); + OBUF \led_OBUF[0]_inst + (.I(led_OBUF[0]), + .O(led[0])); + OBUF \led_OBUF[10]_inst + (.I(led_OBUF[10]), + .O(led[10])); + OBUF \led_OBUF[11]_inst + (.I(led_OBUF[11]), + .O(led[11])); + OBUF \led_OBUF[12]_inst + (.I(led_OBUF[12]), + .O(led[12])); + OBUF \led_OBUF[13]_inst + (.I(led_OBUF[13]), + .O(led[13])); + OBUF \led_OBUF[14]_inst + (.I(led_OBUF[14]), + .O(led[14])); + OBUF \led_OBUF[15]_inst + (.I(led_OBUF[15]), + .O(led[15])); + OBUF \led_OBUF[1]_inst + (.I(led_OBUF[1]), + .O(led[1])); + OBUF \led_OBUF[2]_inst + (.I(led_OBUF[2]), + .O(led[2])); + OBUF \led_OBUF[3]_inst + (.I(led_OBUF[3]), + .O(led[3])); + OBUF \led_OBUF[4]_inst + (.I(led_OBUF[4]), + .O(led[4])); + OBUF \led_OBUF[5]_inst + (.I(led_OBUF[5]), + .O(led[5])); + OBUF \led_OBUF[6]_inst + (.I(led_OBUF[6]), + .O(led[6])); + OBUF \led_OBUF[7]_inst + (.I(led_OBUF[7]), + .O(led[7])); + OBUF \led_OBUF[8]_inst + (.I(led_OBUF[8]), + .O(led[8])); + OBUF \led_OBUF[9]_inst + (.I(led_OBUF[9]), + .O(led[9])); + (* \PinAttr:D:HOLD_DETOUR = "383" *) + FDRE \led_reg[0] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[0]), + .Q(led_OBUF[0]), + .R(\ )); + FDRE \led_reg[10] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[10]), + .Q(led_OBUF[10]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "439" *) + FDRE \led_reg[11] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[11]), + .Q(led_OBUF[11]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "423" *) + FDRE \led_reg[12] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[12]), + .Q(led_OBUF[12]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "422" *) + FDRE \led_reg[13] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[13]), + .Q(led_OBUF[13]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "389" *) + FDRE \led_reg[14] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[14]), + .Q(led_OBUF[14]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "431" *) + FDRE \led_reg[15] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[15]), + .Q(led_OBUF[15]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "471" *) + FDRE \led_reg[1] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[1]), + .Q(led_OBUF[1]), + .R(\ )); + FDRE \led_reg[2] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[2]), + .Q(led_OBUF[2]), + .R(\ )); + FDRE \led_reg[3] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[3]), + .Q(led_OBUF[3]), + .R(\ )); + FDRE \led_reg[4] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[4]), + .Q(led_OBUF[4]), + .R(\ )); + FDRE \led_reg[5] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[5]), + .Q(led_OBUF[5]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "429" *) + FDRE \led_reg[6] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[6]), + .Q(led_OBUF[6]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "422" *) + FDRE \led_reg[7] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[7]), + .Q(led_OBUF[7]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "421" *) + FDRE \led_reg[8] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[8]), + .Q(led_OBUF[8]), + .R(\ )); + (* \PinAttr:D:HOLD_DETOUR = "467" *) + FDRE \led_reg[9] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[9]), + .Q(led_OBUF[9]), + .R(\ )); + IBUF reset_IBUF_inst + (.I(reset), + .O(reset_IBUF)); +endmodule diff --git a/out/nexys_A7_100T/led_counter/Output/led_counter.bit b/out/nexys_A7_100T/led_counter/Output/led_counter.bit new file mode 100644 index 0000000..8baf2a1 Binary files /dev/null and b/out/nexys_A7_100T/led_counter/Output/led_counter.bit differ diff --git a/out/nexys_A7_100T/led_counter/Output/place/post_place.dcp b/out/nexys_A7_100T/led_counter/Output/place/post_place.dcp new file mode 100644 index 0000000..7368d19 Binary files /dev/null and b/out/nexys_A7_100T/led_counter/Output/place/post_place.dcp differ diff --git a/out/nexys_A7_100T/led_counter/Output/place/reports/post_place_timing_summary.rpt b/out/nexys_A7_100T/led_counter/Output/place/reports/post_place_timing_summary.rpt new file mode 100644 index 0000000..5534c48 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/place/reports/post_place_timing_summary.rpt @@ -0,0 +1,338 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:58:43 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/nexys_A7_100T/led_counter/Output/place/reports/post_place_timing_summary.rpt +| Design : top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +----------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.292 0.000 0 114 -3.059 -50.725 17 114 4.500 0.000 0 67 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.292 0.000 0 114 -3.059 -50.725 17 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.292ns, Total Violation 0.000ns +Hold : 17 Failing Endpoints, Worst Slack -3.059ns, Total Violation -50.725ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.292ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 4.537ns (logic 2.260ns (49.813%) route 2.277ns (50.187%)) + Logic Levels: 8 (CARRY4=5 LUT4=2 LUT6=1) + Clock Path Skew: -0.136ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 5.015ns = ( 10.015 - 5.000 ) + Source Clock Delay (SCD): 5.328ns + Clock Pessimism Removal (CPR): 0.177ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=2, estimated) 2.025 3.507 clk_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.603 r clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.725 5.328 clk_IBUF_BUFG + SLICE_X1Y96 FDRE r LED_PIPE_count1_a1_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y96 FDRE (Prop_fdre_C_Q) 0.456 5.784 r LED_PIPE_count1_a1_reg[1]/Q + net (fo=2, estimated) 0.604 6.388 LED_PIPE_count1_a1[1] + SLICE_X1Y96 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.656 7.044 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.044 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + SLICE_X1Y97 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.158 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.158 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + SLICE_X1Y98 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.272 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.272 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + SLICE_X1Y99 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.386 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.386 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + SLICE_X1Y100 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 7.642 r LED_PIPE_count1_a1_reg[20]_i_1/O[2] + net (fo=2, estimated) 0.948 8.590 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_1[2] + SLICE_X3Y100 LUT6 (Prop_lut6_I0_O) 0.302 8.892 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, estimated) 0.574 9.466 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + SLICE_X3Y100 LUT4 (Prop_lut4_I2_O) 0.124 9.590 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, estimated) 0.151 9.741 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + SLICE_X3Y100 LUT4 (Prop_lut4_I0_O) 0.124 9.865 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, routed) 0.000 9.865 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + SLICE_X3Y100 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + E3 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 f clk_IBUF_inst/O + net (fo=2, estimated) 1.924 8.335 clk_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 8.426 f clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.589 10.015 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + SLICE_X3Y100 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.177 10.192 + clock uncertainty -0.035 10.156 + ------------------------------------------------------------------- + required time 10.156 + arrival time -9.865 + ------------------------------------------------------------------- + slack 0.292 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -3.059ns (arrival time - required time) + Source: reset + (input port clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: LED_PIPE_Leds_a0_reg[13]/R + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.580ns (logic 1.407ns (54.530%) route 1.173ns (45.470%)) + Logic Levels: 1 (IBUF=1) + Input Delay: 0.000ns + Clock Path Skew: 5.624ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.624ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + input delay 0.000 0.000 + J15 0.000 0.000 r reset (IN) + net (fo=0) 0.000 0.000 reset + J15 IBUF (Prop_ibuf_I_O) 1.407 1.407 r reset_IBUF_inst/O + net (fo=17, estimated) 1.173 2.580 reset_IBUF + SLICE_X5Y102 FDRE r LED_PIPE_Leds_a0_reg[13]/R + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=2, estimated) 3.348 4.830 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF + SLICE_X4Y100 LUT2 (Prop_lut2_I1_O) 0.124 4.954 r gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2/O + net (fo=16, estimated) 0.670 5.624 clkF_LED_PIPE_refresh_a1 + SLICE_X5Y102 FDRE r LED_PIPE_Leds_a0_reg[13]/C + clock pessimism 0.000 5.624 + clock uncertainty 0.035 5.659 + SLICE_X5Y102 FDRE (Hold_fdre_C_R) -0.020 5.639 LED_PIPE_Leds_a0_reg[13] + ------------------------------------------------------------------- + required time -5.639 + arrival time 2.580 + ------------------------------------------------------------------- + slack -3.059 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y16 clk_IBUF_BUFG_inst/I +Low Pulse Width Fast FDSE/C n/a 0.500 5.000 4.500 SLICE_X2Y99 LED_PIPE_Leds_a0_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y97 LED_PIPE_count1_a1_reg[0]/C + + + diff --git a/out/nexys_A7_100T/led_counter/Output/route/post_route.dcp b/out/nexys_A7_100T/led_counter/Output/route/post_route.dcp new file mode 100644 index 0000000..38fe32c Binary files /dev/null and b/out/nexys_A7_100T/led_counter/Output/route/post_route.dcp differ diff --git a/out/nexys_A7_100T/led_counter/Output/route/reports/clock_util.rpt b/out/nexys_A7_100T/led_counter/Output/route/reports/clock_util.rpt new file mode 100644 index 0000000..7745bc1 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/route/reports/clock_util.rpt @@ -0,0 +1,164 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:59:05 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_clock_utilization -file ./../out/nexys_A7_100T/led_counter/Output/route/reports/clock_util.rpt +| Design : top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y1 +8. Clock Region Cell Placement per Global Clock: Region X0Y2 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 96 | 0 | 0 | 0 | +| BUFIO | 0 | 24 | 0 | 0 | 0 | +| BUFMR | 0 | 12 | 0 | 0 | 0 | +| BUFR | 0 | 24 | 0 | 0 | 0 | +| MMCM | 0 | 6 | 0 | 0 | 0 | +| PLL | 0 | 6 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 50 | 0 | 10.000 | clk | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X1Y126 | IOB_X1Y126 | X1Y2 | 1 | 1 | 10.000 | clk | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 22 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 27 | 2000 | 4 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 1 | 0 | +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | clk | 10.000 | {0.000 5.000} | 50 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+-----+----+-----------------------+ +| | X0 | X1 | HORIZONTAL PROG DELAY | ++----+-----+----+-----------------------+ +| Y3 | 0 | 0 | 0 | +| Y2 | 28 | 0 | 0 | +| Y1 | 22 | 0 | 0 | +| Y0 | 0 | 0 | 0 | ++----+-----+----+-----------------------+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 22 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +8. Clock Region Cell Placement per Global Clock: Region X0Y2 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 28 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y16 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y126 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2} +#endgroup diff --git a/out/nexys_A7_100T/led_counter/Output/route/reports/post_imp_drc.rpt b/out/nexys_A7_100T/led_counter/Output/route/reports/post_imp_drc.rpt new file mode 100644 index 0000000..e2cc33b --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/route/reports/post_imp_drc.rpt @@ -0,0 +1,68 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:59:15 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_drc -file ./../out/nexys_A7_100T/led_counter/Output/route/reports/post_imp_drc.rpt +| Design : top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +----------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++-------------+----------+-------------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-------------+----------+-------------------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PDRC-153 | Warning | Gated clock check | 1 | +| PLHOLDVIO-2 | Warning | Non-Optimal connections which could lead to hold violations | 1 | ++-------------+----------+-------------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PDRC-153#1 Warning +Gated clock check +Net gen_clkF_LED_PIPE_refresh_a1/CLK is a gated clock net sourced by a combinational pin gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2/O, cell gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PLHOLDVIO-2#1 Warning +Non-Optimal connections which could lead to hold violations +A LUT gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2 is driving clock pin of 16 cells. This could lead to large hold time violations. Involved cells are: +LED_PIPE_Leds_a0_reg[0], LED_PIPE_Leds_a0_reg[10], +LED_PIPE_Leds_a0_reg[11], LED_PIPE_Leds_a0_reg[12], +LED_PIPE_Leds_a0_reg[13], LED_PIPE_Leds_a0_reg[14], +LED_PIPE_Leds_a0_reg[15], LED_PIPE_Leds_a0_reg[1], LED_PIPE_Leds_a0_reg[2], +LED_PIPE_Leds_a0_reg[3], LED_PIPE_Leds_a0_reg[4], LED_PIPE_Leds_a0_reg[5], +LED_PIPE_Leds_a0_reg[6], LED_PIPE_Leds_a0_reg[7], LED_PIPE_Leds_a0_reg[8] + (the first 15 of 16 listed) +Related violations: + + diff --git a/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_power.rpt b/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_power.rpt new file mode 100644 index 0000000..e935240 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_power.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:59:06 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_power -file ./../out/nexys_A7_100T/led_counter/Output/route/reports/post_route_power.rpt +| Design : top +| Device : xc7a100tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +----------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.122 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.024 | +| Device Static (W) | 0.097 | +| Effective TJA (C/W) | 4.6 | +| Max Ambient (C) | 84.4 | +| Junction Temperature (C) | 25.6 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.001 | 3 | --- | --- | +| Slice Logic | <0.001 | 102 | --- | --- | +| LUT as Logic | <0.001 | 19 | 63400 | 0.03 | +| CARRY4 | <0.001 | 12 | 15850 | 0.08 | +| Register | <0.001 | 66 | 126800 | 0.05 | +| Others | 0.000 | 4 | --- | --- | +| Signals | <0.001 | 124 | --- | --- | +| I/O | 0.023 | 18 | 210 | 8.57 | +| Static Power | 0.097 | | | | +| Total | 0.122 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.017 | 0.002 | 0.015 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.019 | 0.001 | 0.018 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.010 | 0.006 | 0.004 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.6 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ +| clk | clk | 10.0 | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------+-----------+ +| Name | Power (W) | ++------+-----------+ +| top | 0.024 | ++------+-----------+ + + diff --git a/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_timing.rpt b/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_timing.rpt new file mode 100644 index 0000000..5549225 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_timing.rpt @@ -0,0 +1,119 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:59:04 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing -sort_by group -max_paths 100 -path_type summary -file ./../out/nexys_A7_100T/led_counter/Output/route/reports/post_route_timing.rpt +| Design : top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Startpoint Endpoint Slack(ns) +---------------------------------------------------------------------------- +LED_PIPE_count1_a1_reg[2]/C gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + 0.409 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[1]/R 4.956 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[2]/R 4.956 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[3]/R 4.956 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[4]/R 4.956 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[0]/R 5.058 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[5]/R 5.062 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[6]/R 5.062 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[7]/R 5.062 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[8]/R 5.062 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[10]/R 5.223 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[11]/R 5.223 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[12]/R 5.223 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[9]/R 5.223 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[17]/R 5.286 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[18]/R 5.286 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[19]/R 5.286 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[20]/R 5.286 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[13]/R 5.374 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[14]/R 5.374 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[15]/R 5.374 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[16]/R 5.374 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[21]/R 5.434 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[22]/R 5.434 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[23]/R 5.434 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[24]/R 5.434 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[29]/R 5.534 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[30]/R 5.534 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[31]/R 5.534 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[25]/R 5.673 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[26]/R 5.673 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[27]/R 5.673 +LED_PIPE_count1_a1_reg[4]/C LED_PIPE_count1_a1_reg[28]/R 5.673 +reset LED_PIPE_Leds_a0_reg[0]/S 6.586 +reset LED_PIPE_Leds_a0_reg[1]/R 6.627 +reset LED_PIPE_Leds_a0_reg[2]/R 6.627 +reset LED_PIPE_Leds_a0_reg[3]/R 6.627 +reset LED_PIPE_Leds_a0_reg[4]/R 6.627 +reset LED_PIPE_Leds_a0_reg[10]/R 6.636 +reset LED_PIPE_Leds_a0_reg[11]/R 6.636 +reset LED_PIPE_Leds_a0_reg[12]/R 6.636 +reset LED_PIPE_Leds_a0_reg[9]/R 6.636 +reset LED_PIPE_Leds_a0_reg[13]/R 6.924 +reset LED_PIPE_Leds_a0_reg[14]/R 6.924 +reset LED_PIPE_Leds_a0_reg[15]/R 6.924 +reset LED_PIPE_Leds_a0_reg[5]/R 6.961 +reset LED_PIPE_Leds_a0_reg[6]/R 6.961 +reset LED_PIPE_Leds_a0_reg[7]/R 6.961 +reset LED_PIPE_Leds_a0_reg[8]/R 6.961 +reset LED_PIPE_rst1_a1_reg/D 7.176 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[30]/D 7.225 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[31]/D 7.317 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[29]/D 7.338 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[26]/D 7.340 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[28]/D 7.359 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[27]/D 7.432 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[25]/D 7.453 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[22]/D 7.454 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[24]/D 7.473 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[23]/D 7.546 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[21]/D 7.567 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[18]/D 7.568 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[20]/D 7.587 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[19]/D 7.660 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[17]/D 7.681 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[10]/D 7.752 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[14]/D 7.757 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[12]/D 7.773 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[14]/D 7.794 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[16]/D 7.813 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[11]/D 7.847 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[15]/D 7.852 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[9]/D 7.863 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[13]/D 7.868 +LED_PIPE_count1_a1_reg[0]/C LED_PIPE_count1_a1_reg[0]/D 7.883 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[15]/D 7.886 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[6]/D 7.901 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[13]/D 7.907 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[10]/D 7.908 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[8]/D 7.922 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[12]/D 7.927 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[7]/D 7.996 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[11]/D 8.000 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[5]/D 8.012 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[9]/D 8.021 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[6]/D 8.022 +LED_PIPE_Leds_a0_reg[8]/C led_reg[8]/D 8.033 +LED_PIPE_Leds_a0_reg[12]/C led_reg[12]/D 8.036 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[8]/D 8.041 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[7]/D 8.114 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[5]/D 8.135 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[4]/D 8.164 +LED_PIPE_Leds_a0_reg[0]/C led_reg[0]/D 8.168 +LED_PIPE_Leds_a0_reg[7]/C led_reg[7]/D 8.179 +LED_PIPE_Leds_a0_reg[13]/C led_reg[13]/D 8.188 +LED_PIPE_Leds_a0_reg[14]/C led_reg[14]/D 8.201 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[2]/D 8.208 +LED_PIPE_Leds_a0_reg[1]/C led_reg[1]/D 8.217 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[3]/D 8.222 +LED_PIPE_Leds_a0_reg[6]/C led_reg[6]/D 8.261 + + + diff --git a/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_timing_summary.rpt b/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_timing_summary.rpt new file mode 100644 index 0000000..a3f8dc1 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_timing_summary.rpt @@ -0,0 +1,336 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:59:04 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/nexys_A7_100T/led_counter/Output/route/reports/post_route_timing_summary.rpt +| Design : top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +----------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.409 0.000 0 114 0.081 0.000 0 114 4.500 0.000 0 67 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.409 0.000 0 114 0.081 0.000 0 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.409ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.081ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.409ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 4.420ns (logic 2.254ns (50.994%) route 2.166ns (49.006%)) + Logic Levels: 8 (CARRY4=5 LUT4=2 LUT6=1) + Clock Path Skew: -0.136ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 5.012ns = ( 10.012 - 5.000 ) + Source Clock Delay (SCD): 5.328ns + Clock Pessimism Removal (CPR): 0.180ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=2, routed) 2.025 3.506 clk_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.725 5.328 clk_IBUF_BUFG + SLICE_X1Y96 FDRE r LED_PIPE_count1_a1_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y96 FDRE (Prop_fdre_C_Q) 0.456 5.784 r LED_PIPE_count1_a1_reg[2]/Q + net (fo=2, routed) 0.492 6.275 LED_PIPE_count1_a1[2] + SLICE_X1Y96 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.674 6.949 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 6.949 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + SLICE_X1Y97 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.063 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.000 7.063 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + SLICE_X1Y98 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.177 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 7.177 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + SLICE_X1Y99 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 7.291 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, routed) 0.001 7.292 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + SLICE_X1Y100 CARRY4 (Prop_carry4_CI_O[0]) + 0.235 7.527 r LED_PIPE_count1_a1_reg[20]_i_1/O[0] + net (fo=2, routed) 0.952 8.479 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_1[0] + SLICE_X3Y100 LUT6 (Prop_lut6_I2_O) 0.299 8.778 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, routed) 0.573 9.351 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + SLICE_X3Y100 LUT4 (Prop_lut4_I2_O) 0.124 9.475 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, routed) 0.149 9.624 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + SLICE_X3Y100 LUT4 (Prop_lut4_I0_O) 0.124 9.748 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, routed) 0.000 9.748 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + SLICE_X3Y100 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + E3 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 f clk_IBUF_inst/O + net (fo=2, routed) 1.920 8.331 clk_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 8.422 f clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.590 10.012 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + SLICE_X3Y100 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.180 10.192 + clock uncertainty -0.035 10.157 + ------------------------------------------------------------------- + required time 10.157 + arrival time -9.748 + ------------------------------------------------------------------- + slack 0.409 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.081ns (arrival time - required time) + Source: LED_PIPE_Leds_a0_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: led_reg[3]/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 0.984ns (logic 0.367ns (37.307%) route 0.617ns (62.693%)) + Logic Levels: 0 + Clock Path Skew: 0.711ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 5.328ns + Source Clock Delay (SCD): 4.547ns + Clock Pessimism Removal (CPR): 0.071ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r clk_IBUF_inst/O + net (fo=2, routed) 2.561 3.972 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF + SLICE_X4Y100 LUT2 (Prop_lut2_I1_O) 0.100 4.072 r gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2/O + net (fo=16, routed) 0.475 4.547 clkF_LED_PIPE_refresh_a1 + SLICE_X5Y99 FDRE r LED_PIPE_Leds_a0_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y99 FDRE (Prop_fdre_C_Q) 0.367 4.914 r LED_PIPE_Leds_a0_reg[3]/Q + net (fo=2, routed) 0.617 5.530 LED_PIPE_Leds_a0[3] + SLICE_X0Y96 FDRE r led_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=2, routed) 2.025 3.506 clk_IBUF + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.602 r clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.725 5.328 clk_IBUF_BUFG + SLICE_X0Y96 FDRE r led_reg[3]/C + clock pessimism -0.071 5.257 + SLICE_X0Y96 FDRE (Hold_fdre_C_D) 0.192 5.449 led_reg[3] + ------------------------------------------------------------------- + required time -5.449 + arrival time 5.530 + ------------------------------------------------------------------- + slack 0.081 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y16 clk_IBUF_BUFG_inst/I +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y102 LED_PIPE_Leds_a0_reg[13]/C +High Pulse Width Fast FDSE/C n/a 0.500 5.000 4.500 SLICE_X2Y99 LED_PIPE_Leds_a0_reg[0]/C + + + diff --git a/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_util.rpt b/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_util.rpt new file mode 100644 index 0000000..6a3f66b --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/route/reports/post_route_util.rpt @@ -0,0 +1,207 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:59:05 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_utilization -file ./../out/nexys_A7_100T/led_counter/Output/route/reports/post_route_util.rpt +| Design : top +| Device : 7a100tcsg324-1 +| Design State : Routed +---------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 19 | 0 | 63400 | 0.03 | +| LUT as Logic | 19 | 0 | 63400 | 0.03 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 66 | 0 | 126800 | 0.05 | +| Register as Flip Flop | 65 | 0 | 126800 | 0.05 | +| Register as Latch | 1 | 0 | 126800 | <0.01 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 1 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 64 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------------------------+------+-------+-----------+-------+ +| Slice | 24 | 0 | 15850 | 0.15 | +| SLICEL | 22 | 0 | | | +| SLICEM | 2 | 0 | | | +| LUT as Logic | 19 | 0 | 63400 | 0.03 | +| using O5 output only | 0 | | | | +| using O6 output only | 18 | | | | +| using O5 and O6 | 1 | | | | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 66 | 0 | 126800 | 0.05 | +| Register driven from within the Slice | 49 | | | | +| Register driven from outside the Slice | 17 | | | | +| LUT in front of the register is unused | 8 | | | | +| LUT in front of the register is used | 9 | | | | +| Unique Control Sets | 4 | | 15850 | 0.03 | ++--------------------------------------------+------+-------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 135 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 135 | 0.00 | +| RAMB18 | 0 | 0 | 270 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 240 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 18 | 18 | 210 | 8.57 | +| IOB Master Pads | 9 | | | | +| IOB Slave Pads | 9 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 64 | Flop & Latch | +| OBUF | 16 | IO | +| CARRY4 | 12 | CarryLogic | +| LUT6 | 8 | LUT | +| LUT4 | 6 | LUT | +| LUT5 | 3 | LUT | +| LUT1 | 2 | LUT | +| IBUF | 2 | IO | +| LUT2 | 1 | LUT | +| LDCE | 1 | Flop & Latch | +| FDSE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/out/nexys_A7_100T/led_counter/Output/syn/post_synth.dcp b/out/nexys_A7_100T/led_counter/Output/syn/post_synth.dcp new file mode 100644 index 0000000..f18766c Binary files /dev/null and b/out/nexys_A7_100T/led_counter/Output/syn/post_synth.dcp differ diff --git a/out/nexys_A7_100T/led_counter/Output/syn/reports/post_synth_power.rpt b/out/nexys_A7_100T/led_counter/Output/syn/reports/post_synth_power.rpt new file mode 100644 index 0000000..1a7339b --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/syn/reports/post_synth_power.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:58:19 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_power -file ./../out/nexys_A7_100T/led_counter/Output/syn/reports/post_synth_power.rpt +| Design : top +| Device : xc7a100tcsg324-1 +| Design State : synthesized +| Grade : commercial +| Process : typical +| Characterization : Production +--------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.127 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.029 | +| Device Static (W) | 0.097 | +| Effective TJA (C/W) | 4.6 | +| Max Ambient (C) | 84.4 | +| Junction Temperature (C) | 25.6 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.002 | 3 | --- | --- | +| Slice Logic | <0.001 | 102 | --- | --- | +| LUT as Logic | <0.001 | 19 | 63400 | 0.03 | +| CARRY4 | <0.001 | 12 | 15850 | 0.08 | +| Register | <0.001 | 66 | 126800 | 0.05 | +| Others | 0.000 | 4 | --- | --- | +| Signals | <0.001 | 127 | --- | --- | +| I/O | 0.027 | 18 | 210 | 8.57 | +| Static Power | 0.097 | | | | +| Total | 0.127 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.017 | 0.002 | 0.015 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.019 | 0.001 | 0.018 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.012 | 0.008 | 0.004 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | Low | Design is synthesized | Accuracy of the tool is not optimal until design is fully placed and routed | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.6 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ +| clk | clk | 10.0 | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------+-----------+ +| Name | Power (W) | ++------+-----------+ +| top | 0.029 | ++------+-----------+ + + diff --git a/out/nexys_A7_100T/led_counter/Output/syn/reports/post_synth_timing_summary.rpt b/out/nexys_A7_100T/led_counter/Output/syn/reports/post_synth_timing_summary.rpt new file mode 100644 index 0000000..f440085 --- /dev/null +++ b/out/nexys_A7_100T/led_counter/Output/syn/reports/post_synth_timing_summary.rpt @@ -0,0 +1,346 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:58:18 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/nexys_A7_100T/led_counter/Output/syn/reports/post_synth_timing_summary.rpt +| Design : top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +--------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.000 0.000 0 114 -1.058 -15.369 17 114 4.500 0.000 0 67 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.000 0.000 0 114 -1.058 -15.369 17 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.000ns, Total Violation 0.000ns +Hold : 17 Failing Endpoints, Worst Slack -1.058ns, Total Violation -15.369ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.000ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 5.298ns (logic 2.291ns (43.243%) route 3.007ns (56.757%)) + Logic Levels: 8 (CARRY4=5 LUT4=2 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.704ns = ( 7.704 - 5.000 ) + Source Clock Delay (SCD): 2.965ns + Clock Pessimism Removal (CPR): 0.116ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + Time Borrowing: + Nominal pulse width: 5.000ns + Library setup time: 0.051ns + Computed max time borrow: 5.051ns + Time borrowed from endpoint: 0.478ns + Open edge uncertainty: -0.035ns + Time given to startpoint: 0.443ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=2, unplaced) 0.803 2.285 clk_IBUF + BUFG (Prop_bufg_I_O) 0.096 2.381 r clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.584 2.965 clk_IBUF_BUFG + FDRE r LED_PIPE_count1_a1_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 3.443 r LED_PIPE_count1_a1_reg[2]/Q + net (fo=2, unplaced) 0.871 4.314 LED_PIPE_count1_a1[2] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.657 4.971 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, unplaced) 0.000 4.971 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 5.088 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.088 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 5.205 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.205 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 5.322 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.322 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.256 5.578 r LED_PIPE_count1_a1_reg[20]_i_1/O[2] + net (fo=2, unplaced) 0.955 6.533 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_1[2] + LUT6 (Prop_lut6_I0_O) 0.301 6.834 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, unplaced) 0.732 7.566 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + LUT4 (Prop_lut4_I2_O) 0.124 7.690 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, unplaced) 0.449 8.139 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + LUT4 (Prop_lut4_I0_O) 0.124 8.263 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, unplaced) 0.000 8.263 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + E3 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 f clk_IBUF_inst/O + net (fo=2, unplaced) 0.763 7.174 clk_IBUF + BUFG (Prop_bufg_I_O) 0.091 7.265 f clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.439 7.704 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.116 7.820 + clock uncertainty -0.035 7.784 + time borrowed 0.478 8.263 + ------------------------------------------------------------------- + required time 8.263 + arrival time -8.263 + ------------------------------------------------------------------- + slack 0.000 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -1.058ns (arrival time - required time) + Source: reset + (input port clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: LED_PIPE_rst1_a1_reg/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.170ns (logic 1.407ns (64.848%) route 0.763ns (35.152%)) + Logic Levels: 1 (IBUF=1) + Input Delay: 0.000ns + Clock Path Skew: 2.965ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.965ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + input delay 0.000 0.000 + J15 0.000 0.000 r reset (IN) + net (fo=0) 0.000 0.000 reset + J15 IBUF (Prop_ibuf_I_O) 1.407 1.407 r reset_IBUF_inst/O + net (fo=17, unplaced) 0.763 2.170 reset_IBUF + FDRE r LED_PIPE_rst1_a1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=2, unplaced) 0.803 2.285 clk_IBUF + BUFG (Prop_bufg_I_O) 0.096 2.381 r clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.584 2.965 clk_IBUF_BUFG + FDRE r LED_PIPE_rst1_a1_reg/C + clock pessimism 0.000 2.965 + clock uncertainty 0.035 3.000 + FDRE (Hold_fdre_C_D) 0.228 3.228 LED_PIPE_rst1_a1_reg + ------------------------------------------------------------------- + required time -3.228 + arrival time 2.170 + ------------------------------------------------------------------- + slack -1.058 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 clk_IBUF_BUFG_inst/I +Low Pulse Width Slow FDSE/C n/a 0.500 5.000 4.500 LED_PIPE_Leds_a0_reg[0]/C +High Pulse Width Slow FDSE/C n/a 0.500 5.000 4.500 LED_PIPE_Leds_a0_reg[0]/C + + + diff --git a/out/zedboard/led_counter/Dependencies/clock_constraints.xdc b/out/zedboard/led_counter/Dependencies/clock_constraints.xdc new file mode 100644 index 0000000..414fe4b --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/clock_constraints.xdc @@ -0,0 +1,3 @@ +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] diff --git a/out/zedboard/led_counter/Dependencies/includes/proj_default/clk_gate.sv b/out/zedboard/led_counter/Dependencies/includes/proj_default/clk_gate.sv new file mode 100644 index 0000000..e028887 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/proj_default/clk_gate.sv @@ -0,0 +1,38 @@ +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Clock gate module used by SandPiper default project. + +// Note: No X injection for X on free_clk.) +module clk_gate (output logic gated_clk, input logic free_clk, func_en, pwr_en, gating_override); + logic clk_en; + logic latched_clk_en /*verilator clock_enable*/; + always_comb clk_en = func_en & (pwr_en | gating_override); + always_latch if (~free_clk) latched_clk_en <= clk_en; + // latched_clk_en <= (~free_clk) ? clk_en : latched_clk_en; + always_comb gated_clk = latched_clk_en & free_clk; +endmodule diff --git a/out/zedboard/led_counter/Dependencies/includes/proj_default/sp_default.vh b/out/zedboard/led_counter/Dependencies/includes/proj_default/sp_default.vh new file mode 100644 index 0000000..a733969 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/proj_default/sp_default.vh @@ -0,0 +1,8 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +`endif // SP_DEFAULT diff --git a/out/zedboard/led_counter/Dependencies/includes/proj_verilog/clk_gate.v b/out/zedboard/led_counter/Dependencies/includes/proj_verilog/clk_gate.v new file mode 100644 index 0000000..5afd28f --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/proj_verilog/clk_gate.v @@ -0,0 +1,39 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +`include "sp_verilog.vh" + + +// Clock gate module used by SandPiper default project. + +module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override); + wire clk_en; + reg latched_clk_en /*verilator clock_enable*/; + assign clk_en = func_en & (pwr_en | gating_override); + `TLV_BLATCH(latched_clk_en, clk_en, free_clk) + assign gated_clk = latched_clk_en & free_clk; +endmodule diff --git a/out/zedboard/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh b/out/zedboard/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh new file mode 100644 index 0000000..0c28412 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh @@ -0,0 +1,65 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +// Latch macros. Inject 'x in simulation for clk === 'x. + +// A-phase latch. +`ifdef SP_PHYS +`define TLV_LATCH(in, out, clk) \ +always @ (in, clk) begin \ + if (clk === 1'b1) \ + out <= in; \ + else if (clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_LATCH(in, out, clk) always @ (in, clk) if (clk == 1'b1) out <= in; +`endif // SP_PHYS + +// B-phase latch. +`ifdef SP_PHYS +`define TLV_BLATCH(out, in, clk) \ +always @ (in, clk) begin \ + if (!clk === 1'b1) \ + out <= in; \ + else if (!clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_BLATCH(out, in, clk) always @ (in, clk) if (!clk == 1'b1) out <= in; +`endif // SP_PHYS + + + +`endif // SP_DEFAULT diff --git a/out/zedboard/led_counter/Dependencies/includes/pseudo_rand.tlv b/out/zedboard/led_counter/Dependencies/includes/pseudo_rand.tlv new file mode 100644 index 0000000..cb0d614 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/pseudo_rand.tlv @@ -0,0 +1,69 @@ +\m4_TLV_version 1b: tl-x.org +\SV +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +module pseudo_rand + #(parameter WIDTH=257) // Random vector width, to a max of 257. + (input logic clk, + input logic reset, + output logic [WIDTH-1:0] rand_vect + ); + +// Currently, this implements a Galois LFSR. +// TODO: It should be XORed with something else so it doesn't just shift. +// Using polynomials with maximal number of taps would have less regular shifting behavior. + +// Bits are numbered in the reverse of the traditional order. This puts the taps in the lower bit positions. + +// Choose optimal parameters for given WIDTH. +localparam LFSR_WIDTH = + (WIDTH <= 64) ? 64 : + (WIDTH <= 128) ? 128 : + (WIDTH <= 257) ? 257 : 0; // 257 enables a large non-power of two for replication on an irregular boundary. +// Polynomial source: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf +localparam [LFSR_WIDTH-1:0] LFSR_POLY = {{(LFSR_WIDTH-8){1'b0}}, + (LFSR_WIDTH == 64) ? 8'b00011011 : + (LFSR_WIDTH == 128) ? 8'b10000111 : + (LFSR_WIDTH == 257) ? 8'b11000101 : 8'b0}; + +bit [256:0] SEED = 257'h0_7163e168_713d5431_6684e132_5cd84848_f3048b46_76874654_0c45f864_04e4684a; + + + +\TLV + |default + @0 + $reset = reset; + @1 + $lfsr[LFSR_WIDTH-1:0] = $reset ? *SEED : {$lfsr#+1[LFSR_WIDTH-2:0], 1'b0} ^ ({LFSR_WIDTH{$lfsr#+1[LFSR_WIDTH-1]}} & *LFSR_POLY); + @2 + *rand_vect = $lfsr[WIDTH-1:0]; + +\SV + +endmodule diff --git a/out/zedboard/led_counter/Dependencies/includes/rw_lib.vh b/out/zedboard/led_counter/Dependencies/includes/rw_lib.vh new file mode 100644 index 0000000..39d5cd5 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/rw_lib.vh @@ -0,0 +1 @@ +`define RW_ZX(in, width) {{width-$width(in){1'b0}}, in} diff --git a/out/zedboard/led_counter/Dependencies/includes/sandhost/README.txt b/out/zedboard/led_counter/Dependencies/includes/sandhost/README.txt new file mode 100644 index 0000000..1816fee --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/sandhost/README.txt @@ -0,0 +1 @@ +Veriog include files that are available only within Makerchip. diff --git a/out/zedboard/led_counter/Dependencies/includes/sandhost/sqrt32.v b/out/zedboard/led_counter/Dependencies/includes/sandhost/sqrt32.v new file mode 100644 index 0000000..23e5dbc --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/sandhost/sqrt32.v @@ -0,0 +1,13 @@ +// A non-synthesizable Verilog-2005 sqrt function for tutorials. +`ifndef RW_NON_SYNTH_SQRT +`define RW_NON_SYNTH_SQRT + +function [31:0] sqrt; + input [31:0] a; + + /* verilator lint_off REALCVT */ + sqrt = $sqrt(a); + /* verilator lint_on REALCVT */ +endfunction + +`endif diff --git a/out/zedboard/led_counter/Dependencies/includes/sandhost/tb.sv b/out/zedboard/led_counter/Dependencies/includes/sandhost/tb.sv new file mode 100644 index 0000000..187fa4f --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/sandhost/tb.sv @@ -0,0 +1,76 @@ +// Provides clk and reset to design.tlv. +// Instantiates design as design(.*) so additional inputs and outputs can be added. +// Ends simulation on max cycles argument below, or assertion of success signal. +// Additional testbench functionality can be added here, or within design using TLV. +// See: "top_module_tlv.m4" for definition. + +// ------------------------------------------------------------------- +// Expanded from instantiation: m4_top_module_inst(m4_name, m4_max_cycles) +// + +module tb(); + +logic clk, reset; // Generated in this module for DUT. +logic passed, failed; // Returned from DUT to this module. Passed must assert before + // max cycles, without failed having asserted. Failed can be undriven. +logic [15:0] cyc_cnt; + + +// Instantiate main module. +top top(.*); + + +// Clock +initial begin + clk = 1'b1; + forever #5 clk = ~clk; +end + + +// Run +initial begin + + //`ifdef DUMP_ON + $dumpfile("top.vcd"); + $dumpvars(0, clk, reset, passed, failed, cyc_cnt, top.DEBUG_SIGS); + $dumpon; + //`endif + + reset = 1'b1; + #55; + reset = 1'b0; + + // Run + + cyc_cnt = '0; + for (int cyc = 0; cyc < 100; cyc++) begin + // Failed + if (failed === 1'b1) begin + FAILED: assert(1'b1) begin + $display("Failed!!! Error condition asserted."); + $finish; + end + end + + // Success + if (passed) begin + SUCCESS: assert(1'b1) begin + $display("Success!!!"); + $finish; + end + end + + #10; + + cyc_cnt++; + end + + // Fail + DIE: assert (1'b1) begin + $error("Failed!!! Test did not complete within m4_max_cycles time."); + $finish; + end + +end + +endmodule // life_tb diff --git a/out/zedboard/led_counter/Dependencies/includes/sandpiper.vh b/out/zedboard/led_counter/Dependencies/includes/sandpiper.vh new file mode 100644 index 0000000..26d3f19 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/sandpiper.vh @@ -0,0 +1,71 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Project-independent SandPiper header file. + +`ifndef SANDPIPER_VH +`define SANDPIPER_VH + + +// Note, these have no SP prefix, so collisions are possible. + + +`ifdef WHEN + // Make sure user definition does not collide. + !!!ERROR: WHEN macro already defined +`else + `ifdef SP_PHYS + // Phys compilation disabled X-injection. + `define WHEN(valid_sig) + `else + // Inject X. + `define WHEN(valid_sig) !valid_sig ? 'x : + `endif +`endif + + +// SandPiper does not generate set/reset flops. Reset is implemented as combinational +// logic, and it is up to synthesis to infer set/reset flops when possible. +//`ifdef RESET +// // Make sure user definition does not collide. +// !!!ERROR: RESET macro already defined +//`else +// `define RESET(i, reset) ((reset) ? '0 : i) +//`endif +// +//`ifdef SET +// // Make sure user definition does not collide. +// !!!ERROR: SET macro already defined +//`else +// `define SET(i, set) ((set) ? '1 : i) +//`endif + +// Since SandPiper required use of all signals, this is useful to create a +// bogus use and keep SandPiper happy when a signal, by intent, has no uses. +`define BOGUS_USE(ignore) + +`endif // SANDPIPER_VH diff --git a/out/zedboard/led_counter/Dependencies/includes/sandpiper_gen.vh b/out/zedboard/led_counter/Dependencies/includes/sandpiper_gen.vh new file mode 100644 index 0000000..d063661 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/sandpiper_gen.vh @@ -0,0 +1,4 @@ +// This just verifies that sandpiper.vh has been included. +`ifndef SANDPIPER_VH + !!!ERROR: SandPiper project's sp_.vh file must include sandpiper.vh. +`endif diff --git a/out/zedboard/led_counter/Dependencies/includes/simple_bypass_fifo.sv b/out/zedboard/led_counter/Dependencies/includes/simple_bypass_fifo.sv new file mode 100644 index 0000000..601c655 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/includes/simple_bypass_fifo.sv @@ -0,0 +1,98 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +`include "rw_lib.vh" + +// A simple implementation of a FIFO with bypass. +// Head is stored outside of the FIFO array. +// When the FIFO is empty, input goes straight through mux to output. +module simple_bypass_fifo( + input logic clk, + input logic reset, + input logic push, + input logic [WIDTH-1:0] data_in, // Timed with push. + input logic pop, // May pop in same cycle as push to empty FIFO. + output logic [WIDTH-1:0] data_out, // Same cycle as pop. + output logic [$clog2(DEPTH+1)-1:0] cnt // Reflecting push/pop last cycle. 0..DEPTH. +); + parameter WIDTH = 8; + parameter DEPTH = 8; + + logic [$clog2(DEPTH)-1:0] next_head, tail; + logic [WIDTH-1:0] arr [DEPTH-1:0], arr_out, head_data; + logic cnt_zero_or_one, cnt_zero, cnt_one; + logic push_arr, push_head, pop_from_arr, popped_from_arr; + + always_ff @(posedge clk) begin + if (reset) begin + tail <= {$clog2(DEPTH){1'b0}}; + next_head <= {$clog2(DEPTH){1'b0}}; + cnt <= {$clog2(DEPTH+1){1'b0}}; + end else begin + if (push_arr + ) begin + arr[tail] <= data_in; + tail <= tail + {{$clog2(DEPTH)-1{1'b0}}, 1'b1}; + end + if (pop) begin + arr_out <= arr[next_head]; + next_head <= next_head + {{$clog2(DEPTH)-1{1'b0}}, 1'b1}; + end + if (push ^ pop) begin + cnt <= cnt + (push ? {{$clog2(DEPTH+1)-1{1'b0}}, 1'b1} /* 1 */ : {$clog2(DEPTH+1){1'b1}} /* -1 */); + end + end + end + always_comb begin + // Control signals + + // These are timed with cnt (cycle after push/pop) + cnt_zero_or_one = (cnt >> 1) == {$clog2(DEPTH+1){1'b0}}; + cnt_zero = cnt_zero_or_one && ~cnt[0]; + cnt_one = cnt_zero_or_one && cnt[0]; + + // These are timed with push/pop + // Cases in which a push would not got into array. + push_arr = push && !(cnt_zero || (cnt_zero_or_one && pop)); + push_head = push && (pop ? cnt_one : cnt_zero); + pop_from_arr = pop && !cnt_zero_or_one; + + // Output data + data_out = cnt_zero ? data_in : head_data; + end + + // Head + always_ff @(posedge clk) begin + popped_from_arr <= pop_from_arr; + if (push_head) begin + head_data <= data_in; + end else if (popped_from_arr) begin + head_data <= arr_out; + end + end +endmodule diff --git a/out/zedboard/led_counter/Dependencies/led_counter.v b/out/zedboard/led_counter/Dependencies/led_counter.v new file mode 100644 index 0000000..88607c6 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/led_counter.v @@ -0,0 +1,345 @@ +//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta +`include "sp_verilog.vh" //_\SV + // Included URL: "https://raw.githubusercontent.com/BalaDhinesh/Virtual-FPGA-Lab/main/tlv_lib/fpga_includes.tlv" +//_\SV + + + + + module top(input clk, input reset, output reg [15:0] led); + + +`include "led_counter_gen.v" +generate //_\TLV + //_|led_pipe + //_@0 + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 3 // Instantiated from led_counter.tlv, 15 as: m4+fpga_refresh($refresh, m4_ifelse(M4_MAKERCHIP, 1, 1, 50000000)) + /* verilator lint_off UNSIGNED */ + assign LED_PIPE_rst1_a0 = reset; + assign LED_PIPE_count1_a0[31:0] = (LED_PIPE_count1_a1[31:0] >= 50000000 - 1) | LED_PIPE_rst1_a1 ? 1'b0 : LED_PIPE_count1_a1[31:0] + 1 ; + assign LED_PIPE_refresh_a0 = (LED_PIPE_count1_a0 == 50000000 - 1) ? 1'b1 : 1'b0 ; + + //_\end_source + assign LED_PIPE_reset_a0 = reset; + //_?$refresh + assign LED_PIPE_Leds_n1[15:0] = LED_PIPE_reset_a0 ? 1 : LED_PIPE_Leds_a0+1; + /*SV_plus*/ + always@(posedge clk) begin + led = LED_PIPE_Leds_a0; + end + // M4_BOARD numbering + // 1 - Zedboard + // 2 - Artix-7 + // 3 - Basys3 + // 4 - Icebreaker + // 5 - Nexys + + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 32 // Instantiated from led_counter.tlv, 30 as: m4+fpga_init() + //m4+osfpga_logo() + //_|fpga_init_macro + //_@0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + //_\end_source + //_\source /raw.githubusercontent.com/BalaDhinesh/VirtualFPGALab/main/tlvlib/fpgaincludes.tlv 245 // Instantiated from led_counter.tlv, 31 as: m4+fpga_led(*led) + //_|led_pipe_macro + //_@0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + //_\end_source +endgenerate +//_\SV + endmodule diff --git a/out/zedboard/led_counter/Dependencies/led_counter_gen.v b/out/zedboard/led_counter/Dependencies/led_counter_gen.v new file mode 100644 index 0000000..fc366a2 --- /dev/null +++ b/out/zedboard/led_counter/Dependencies/led_counter_gen.v @@ -0,0 +1,81 @@ +// Generated by SandPiper(TM) 1.11-2021/01/28-beta from Redwood EDA. +// Redwood EDA does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality. + + +`include "sandpiper_gen.vh" + + + + + +// +// Signals declared top-level. +// + +// For |led_pipe$Leds. +wire [15:0] LED_PIPE_Leds_n1; +reg [15:0] LED_PIPE_Leds_a0; + +// For |led_pipe$count1. +wire [31:0] LED_PIPE_count1_a0; +reg [31:0] LED_PIPE_count1_a1; + +// For |led_pipe$refresh. +wire LED_PIPE_refresh_a0; + +// For |led_pipe$reset. +wire LED_PIPE_reset_a0; + +// For |led_pipe$rst1. +wire LED_PIPE_rst1_a0; +reg LED_PIPE_rst1_a1; + + +// +// Scope: |led_pipe +// + +// Clock signals. +wire clkF_LED_PIPE_refresh_a1 ; + + +generate + + + // + // Scope: |led_pipe + // + + // For $Leds. + always @(posedge clkF_LED_PIPE_refresh_a1) LED_PIPE_Leds_a0[15:0] <= LED_PIPE_Leds_n1[15:0]; + + // For $count1. + always @(posedge clk) LED_PIPE_count1_a1[31:0] <= LED_PIPE_count1_a0[31:0]; + + // For $rst1. + always @(posedge clk) LED_PIPE_rst1_a1 <= LED_PIPE_rst1_a0; + + + + +endgenerate + + + +// +// Gated clocks. +// + +generate + + + + // + // Scope: |led_pipe + // + + clk_gate gen_clkF_LED_PIPE_refresh_a1(clkF_LED_PIPE_refresh_a1, clk, LED_PIPE_refresh_a0, 1'b1, 1'b0); + + + +endgenerate diff --git a/out/zedboard/led_counter/Output/fpga_impl.xdc b/out/zedboard/led_counter/Output/fpga_impl.xdc new file mode 100644 index 0000000..6a1c2a8 --- /dev/null +++ b/out/zedboard/led_counter/Output/fpga_impl.xdc @@ -0,0 +1,630 @@ + +#################################################################################### +# Generated by Vivado 2020.2 built on 'Wed Nov 18 09:12:47 MST 2020' by 'xbuild' +# Command Used: write_xdc -no_fixed_only -force ./../out/zedboard/led_counter/Output/fpga_impl.xdc +#################################################################################### + + +#################################################################################### +# Constraints from file : 'fpga_lab_constr_zedboard.xdc' +#################################################################################### + +# ---------------------------------------------------------------------------- +# _____ +# / # /____ \____ +# / \===\ \==/ +# /___\===\___\/ AVNET Design Resource Center +# \======/ www.em.avnet.com/drc +# \====/ +# ---------------------------------------------------------------------------- +# +# Created With Avnet UCF Generator V0.4.0 +# Date: Saturday, June 30, 2012 +# Time: 12:18:55 AM +# +# This design is the property of Avnet. Publication of this +# design is not authorized without written consent from Avnet. +# +# Please direct any questions to: +# ZedBoard.org Community Forums +# http://www.zedboard.org +# +# Disclaimer: +# Avnet, Inc. makes no warranty for the use of this code or design. +# This code is provided "As Is". Avnet, Inc assumes no responsibility for +# any errors, which may appear in this code, nor does it make a commitment +# to update the information contained herein. Avnet, Inc specifically +# disclaims any implied warranties of fitness for a particular purpose. +# Copyright(c) 2012 Avnet, Inc. +# All rights reserved. +# +# ---------------------------------------------------------------------------- +# +# Notes: +# +# 10 August 2012 +# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V, +# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings. +# By default, Vadj is expected to be set to 1.8V but if a different +# voltage is used for a particular design, then the corresponding IO +# standard within this UCF should also be updated to reflect the actual +# Vadj jumper selection. +# +# 09 September 2012 +# Net names are not allowed to contain hyphen characters '-' since this +# is not a legal VHDL87 or Verilog character within an identifier. +# HDL net names are adjusted to contain no hyphen characters '-' but +# rather use underscore '_' characters. Comment net name with the hyphen +# characters will remain in place since these are intended to match the +# schematic net names in order to better enable schematic search. +# +# 17 April 2014 +# Pin constraint for toggle switch SW7 was corrected to M15 location. +# +# 16 April 2015 +# Corrected the way that entire banks are assigned to a particular IO +# standard so that it works with more recent versions of Vivado Design +# Suite and moved the IO standard constraints to the end of the file +# along with some better organization and notes like we do with our SOMs. +# +# 6 June 2016 +# Corrected error in signal name for package pin N19 (FMC Expansion Connector) +# +# +# ---------------------------------------------------------------------------- + +# ---------------------------------------------------------------------------- +# Audio Codec - Bank 13 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}]; # "AC-ADR0" +#set_property PACKAGE_PIN Y5 [get_ports {AC_ADR1}]; # "AC-ADR1" +#set_property PACKAGE_PIN Y8 [get_ports {SDATA_O}]; # "AC-GPIO0" +#set_property PACKAGE_PIN AA7 [get_ports {SDATA_I}]; # "AC-GPIO1" +#set_property PACKAGE_PIN AA6 [get_ports {BCLK_O}]; # "AC-GPIO2" +#set_property PACKAGE_PIN Y6 [get_ports {LRCLK_O}]; # "AC-GPIO3" +#set_property PACKAGE_PIN AB2 [get_ports {MCLK_O}]; # "AC-MCLK" +#set_property PACKAGE_PIN AB4 [get_ports {iic_rtl_scl_io}]; # "AC-SCK" +#set_property PACKAGE_PIN AB5 [get_ports {iic_rtl_sda_io}]; # "AC-SDA" + +# ---------------------------------------------------------------------------- +# Clock Source - Bank 13 +# ---------------------------------------------------------------------------- +set_property PACKAGE_PIN Y9 [get_ports clk] + +# ---------------------------------------------------------------------------- +# JA Pmod - Bank 13 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN Y11 [get_ports {JA1}]; # "JA1" +#set_property PACKAGE_PIN AA8 [get_ports {JA10}]; # "JA10" +#set_property PACKAGE_PIN AA11 [get_ports {JA2}]; # "JA2" +#set_property PACKAGE_PIN Y10 [get_ports {JA3}]; # "JA3" +#set_property PACKAGE_PIN AA9 [get_ports {JA4}]; # "JA4" +#set_property PACKAGE_PIN AB11 [get_ports {JA7}]; # "JA7" +#set_property PACKAGE_PIN AB10 [get_ports {JA8}]; # "JA8" +#set_property PACKAGE_PIN AB9 [get_ports {JA9}]; # "JA9" + + +# ---------------------------------------------------------------------------- +# JB Pmod - Bank 13 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN W12 [get_ports {JB1}]; # "JB1" +#set_property PACKAGE_PIN W11 [get_ports {JB2}]; # "JB2" +#set_property PACKAGE_PIN V10 [get_ports {JB3}]; # "JB3" +#set_property PACKAGE_PIN W8 [get_ports {JB4}]; # "JB4" +#set_property PACKAGE_PIN V12 [get_ports {JB7}]; # "JB7" +#set_property PACKAGE_PIN W10 [get_ports {JB8}]; # "JB8" +#set_property PACKAGE_PIN V9 [get_ports {JB9}]; # "JB9" +#set_property PACKAGE_PIN V8 [get_ports {JB10}]; # "JB10" + +# ---------------------------------------------------------------------------- +# JC Pmod - Bank 13 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN AB6 [get_ports {JC1_N}]; # "JC1_N" +#set_property PACKAGE_PIN AB7 [get_ports {JC1_P}]; # "JC1_P" +#set_property PACKAGE_PIN AA4 [get_ports {JC2_N}]; # "JC2_N" +#set_property PACKAGE_PIN Y4 [get_ports {JC2_P}]; # "JC2_P" +#set_property PACKAGE_PIN T6 [get_ports {JC3_N}]; # "JC3_N" +#set_property PACKAGE_PIN R6 [get_ports {JC3_P}]; # "JC3_P" +#set_property PACKAGE_PIN U4 [get_ports {JC4_N}]; # "JC4_N" +#set_property PACKAGE_PIN T4 [get_ports {JC4_P}]; # "JC4_P" + +# ---------------------------------------------------------------------------- +# JD Pmod - Bank 13 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN W7 [get_ports {JD1_N}]; # "JD1_N" +#set_property PACKAGE_PIN V7 [get_ports {JD1_P}]; # "JD1_P" +#set_property PACKAGE_PIN V4 [get_ports {JD2_N}]; # "JD2_N" +#set_property PACKAGE_PIN V5 [get_ports {JD2_P}]; # "JD2_P" +#set_property PACKAGE_PIN W5 [get_ports {JD3_N}]; # "JD3_N" +#set_property PACKAGE_PIN W6 [get_ports {JD3_P}]; # "JD3_P" +#set_property PACKAGE_PIN U5 [get_ports {JD4_N}]; # "JD4_N" +#set_property PACKAGE_PIN U6 [get_ports {JD4_P}]; # "JD4_P" + +# ---------------------------------------------------------------------------- +# OLED Display - Bank 13 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN U10 [get_ports {OLED_DC}]; # "OLED-DC" +#set_property PACKAGE_PIN U9 [get_ports {OLED_RES}]; # "OLED-RES" +#set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}]; # "OLED-SCLK" +#set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}]; # "OLED-SDIN" +#set_property PACKAGE_PIN U11 [get_ports {OLED_VBAT}]; # "OLED-VBAT" +#set_property PACKAGE_PIN U12 [get_ports {OLED_VDD}]; # "OLED-VDD" + +# ---------------------------------------------------------------------------- +# HDMI Output - Bank 33 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN W18 [get_ports {HD_CLK}]; # "HD-CLK" +#set_property PACKAGE_PIN Y13 [get_ports {HD_D0}]; # "HD-D0" +#set_property PACKAGE_PIN AA13 [get_ports {HD_D1}]; # "HD-D1" +#set_property PACKAGE_PIN W13 [get_ports {HD_D10}]; # "HD-D10" +#set_property PACKAGE_PIN W15 [get_ports {HD_D11}]; # "HD-D11" +#set_property PACKAGE_PIN V15 [get_ports {HD_D12}]; # "HD-D12" +#set_property PACKAGE_PIN U17 [get_ports {HD_D13}]; # "HD-D13" +#set_property PACKAGE_PIN V14 [get_ports {HD_D14}]; # "HD-D14" +#set_property PACKAGE_PIN V13 [get_ports {HS_D15}]; # "HD-D15" +#set_property PACKAGE_PIN AA14 [get_ports {HD_D2}]; # "HD-D2" +#set_property PACKAGE_PIN Y14 [get_ports {HD_D3}]; # "HD-D3" +#set_property PACKAGE_PIN AB15 [get_ports {HD_D4}]; # "HD-D4" +#set_property PACKAGE_PIN AB16 [get_ports {HD_D5}]; # "HD-D5" +#set_property PACKAGE_PIN AA16 [get_ports {HD_D6}]; # "HD-D6" +#set_property PACKAGE_PIN AB17 [get_ports {HD_D7}]; # "HD-D7" +#set_property PACKAGE_PIN AA17 [get_ports {HD_D8}]; # "HD-D8" +#set_property PACKAGE_PIN Y15 [get_ports {HD_D9}]; # "HD-D9" +#set_property PACKAGE_PIN U16 [get_ports {HD_DE}]; # "HD-DE" +#set_property PACKAGE_PIN V17 [get_ports {HD_HSYNC}]; # "HD-HSYNC" +#set_property PACKAGE_PIN W16 [get_ports {HD_INT}]; # "HD-INT" +#set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}]; # "HD-SCL" +#set_property PACKAGE_PIN Y16 [get_ports {HD_SDA}]; # "HD-SDA" +#set_property PACKAGE_PIN U15 [get_ports {HD_SPDIF}]; # "HD-SPDIF" +#set_property PACKAGE_PIN Y18 [get_ports {HD_SPDIFO}]; # "HD-SPDIFO" +#set_property PACKAGE_PIN W17 [get_ports {HD_VSYNC}]; # "HD-VSYNC" + +# ---------------------------------------------------------------------------- +# User LEDs - Bank 33 +# ---------------------------------------------------------------------------- +set_property PACKAGE_PIN T22 [get_ports {led[0]}] +set_property PACKAGE_PIN T21 [get_ports {led[1]}] +set_property PACKAGE_PIN U22 [get_ports {led[2]}] +set_property PACKAGE_PIN U21 [get_ports {led[3]}] +set_property PACKAGE_PIN V22 [get_ports {led[4]}] +set_property PACKAGE_PIN W22 [get_ports {led[5]}] +set_property PACKAGE_PIN U19 [get_ports {led[6]}] +set_property PACKAGE_PIN U14 [get_ports {led[7]}] + +# ---------------------------------------------------------------------------- +# VGA Output - Bank 33 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN Y21 [get_ports {vga_b1}]; # "VGA-B1" +#set_property PACKAGE_PIN Y20 [get_ports {vga_b2}]; # "VGA-B2" +#set_property PACKAGE_PIN AB20 [get_ports {vga_b3}]; # "VGA-B3" +#set_property PACKAGE_PIN AB19 [get_ports {vga_b4}]; # "VGA-B4" +#set_property PACKAGE_PIN AB22 [get_ports {vga_g1}]; # "VGA-G1" +#set_property PACKAGE_PIN AA22 [get_ports {vga_g2}]; # "VGA-G2" +#set_property PACKAGE_PIN AB21 [get_ports {vga_g3}]; # "VGA-G3" +#set_property PACKAGE_PIN AA21 [get_ports {vga_g4}]; # "VGA-G4" +#set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}]; # "VGA-HS" +#set_property PACKAGE_PIN V20 [get_ports {vga_r1}]; # "VGA-R1" +#set_property PACKAGE_PIN U20 [get_ports {vga_r2}]; # "VGA-R2" +#set_property PACKAGE_PIN V19 [get_ports {vga_r3}]; # "VGA-R3" +#set_property PACKAGE_PIN V18 [get_ports {vga_r4}]; # "VGA-R4" +#set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}]; # "VGA-VS" + +# ---------------------------------------------------------------------------- +# User Push Buttons - Bank 34 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN P16 [get_ports {BTNC}]; # "BTNC" +#set_property PACKAGE_PIN R16 [get_ports {BTND}]; # "BTND" +#set_property PACKAGE_PIN N15 [get_ports {BTNL}]; # "BTNL" +#set_property PACKAGE_PIN R18 [get_ports {BTNR}]; # "BTNR" +#set_property PACKAGE_PIN T18 [get_ports {BTNU}]; # "BTNU" + +# ---------------------------------------------------------------------------- +# USB OTG Reset - Bank 34 +# ---------------------------------------------------------------------------- + +# ---------------------------------------------------------------------------- +# XADC GIO - Bank 34 +# ---------------------------------------------------------------------------- + +# ---------------------------------------------------------------------------- +# Miscellaneous - Bank 34 +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN K16 [get_ports {PUDC_B}]; # "PUDC_B" + +## ---------------------------------------------------------------------------- +## USB OTG Reset - Bank 35 +## ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}]; # "OTG-RESETN" + +## ---------------------------------------------------------------------------- +## User DIP Switches - Bank 35 +## ---------------------------------------------------------------------------- +set_property PACKAGE_PIN F22 [get_ports reset] +#set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1" +#set_property PACKAGE_PIN H22 [get_ports {SW2}]; # "SW2" +#set_property PACKAGE_PIN F21 [get_ports {SW3}]; # "SW3" +#set_property PACKAGE_PIN H19 [get_ports {SW4}]; # "SW4" +#set_property PACKAGE_PIN H18 [get_ports {SW5}]; # "SW5" +#set_property PACKAGE_PIN H17 [get_ports {SW6}]; # "SW6" +#set_property PACKAGE_PIN M15 [get_ports {SW7}]; # "SW7" + +## ---------------------------------------------------------------------------- +## XADC AD Channels - Bank 35 +## ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN E16 [get_ports {AD0N_R}]; # "XADC-AD0N-R" +#set_property PACKAGE_PIN F16 [get_ports {AD0P_R}]; # "XADC-AD0P-R" +#set_property PACKAGE_PIN D17 [get_ports {AD8N_N}]; # "XADC-AD8N-R" +#set_property PACKAGE_PIN D16 [get_ports {AD8P_R}]; # "XADC-AD8P-R" + +## ---------------------------------------------------------------------------- +## FMC Expansion Connector - Bank 13 +## ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}]; # "FMC-SCL" +#set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}]; # "FMC-SDA" + +## ---------------------------------------------------------------------------- +## FMC Expansion Connector - Bank 33 +## ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}]; # "FMC-PRSNT" + +## ---------------------------------------------------------------------------- +## FMC Expansion Connector - Bank 34 +## ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}]; # "FMC-CLK0_N" +#set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}]; # "FMC-CLK0_P" +#set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}]; # "FMC-LA00_CC_N" +#set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}]; # "FMC-LA00_CC_P" +#set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}]; # "FMC-LA01_CC_N" +#set_property PACKAGE_PIN N19 [get_ports {FMC_LA01_CC_P}]; # "FMC-LA01_CC_P" - corrected 6/6/16 GE +#set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}]; # "FMC-LA02_N" +#set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}]; # "FMC-LA02_P" +#set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}]; # "FMC-LA03_N" +#set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}]; # "FMC-LA03_P" +#set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}]; # "FMC-LA04_N" +#set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}]; # "FMC-LA04_P" +#set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}]; # "FMC-LA05_N" +#set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}]; # "FMC-LA05_P" +#set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}]; # "FMC-LA06_N" +#set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}]; # "FMC-LA06_P" +#set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}]; # "FMC-LA07_N" +#set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}]; # "FMC-LA07_P" +#set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}]; # "FMC-LA08_N" +#set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}]; # "FMC-LA08_P" +#set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}]; # "FMC-LA09_N" +#set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}]; # "FMC-LA09_P" +#set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}]; # "FMC-LA10_N" +#set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}]; # "FMC-LA10_P" +#set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}]; # "FMC-LA11_N" +#set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}]; # "FMC-LA11_P" +#set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}]; # "FMC-LA12_N" +#set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}]; # "FMC-LA12_P" +#set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}]; # "FMC-LA13_N" +#set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}]; # "FMC-LA13_P" +#set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}]; # "FMC-LA14_N" +#set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}]; # "FMC-LA14_P" +#set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}]; # "FMC-LA15_N" +#set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}]; # "FMC-LA15_P" +#set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}]; # "FMC-LA16_N" +#set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}]; # "FMC-LA16_P" + +## ---------------------------------------------------------------------------- +## FMC Expansion Connector - Bank 35 +## ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}]; # "FMC-CLK1_N" +#set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}]; # "FMC-CLK1_P" +#set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}]; # "FMC-LA17_CC_N" +#set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}]; # "FMC-LA17_CC_P" +#set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}]; # "FMC-LA18_CC_N" +#set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}]; # "FMC-LA18_CC_P" +#set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}]; # "FMC-LA19_N" +#set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}]; # "FMC-LA19_P" +#set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}]; # "FMC-LA20_N" +#set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}]; # "FMC-LA20_P" +#set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}]; # "FMC-LA21_N" +#set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}]; # "FMC-LA21_P" +#set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}]; # "FMC-LA22_N" +#set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}]; # "FMC-LA22_P" +#set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}]; # "FMC-LA23_N" +#set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}]; # "FMC-LA23_P" +#set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}]; # "FMC-LA24_N" +#set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}]; # "FMC-LA24_P" +#set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}]; # "FMC-LA25_N" +#set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}]; # "FMC-LA25_P" +#set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}]; # "FMC-LA26_N" +#set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}]; # "FMC-LA26_P" +#set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}]; # "FMC-LA27_N" +#set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}]; # "FMC-LA27_P" +#set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}]; # "FMC-LA28_N" +#set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}]; # "FMC-LA28_P" +#set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}]; # "FMC-LA29_N" +#set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}]; # "FMC-LA29_P" +#set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}]; # "FMC-LA30_N" +#set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}]; # "FMC-LA30_P" +#set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}]; # "FMC-LA31_N" +#set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}]; # "FMC-LA31_P" +#set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}]; # "FMC-LA32_N" +#set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}]; # "FMC-LA32_P" +#set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}]; # "FMC-LA33_N" +#set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}]; # "FMC-LA33_P" + + +# ---------------------------------------------------------------------------- +# IOSTANDARD Constraints +# +# Note that these IOSTANDARD constraints are applied to all IOs currently +# assigned within an I/O bank. If these IOSTANDARD constraints are +# evaluated prior to other PACKAGE_PIN constraints being applied, then +# the IOSTANDARD specified will likely not be applied properly to those +# pins. Therefore, bank wide IOSTANDARD constraints should be placed +# within the XDC file in a location that is evaluated AFTER all +# PACKAGE_PIN constraints within the target bank have been evaluated. +# +# Un-comment one or more of the following IOSTANDARD constraints according to +# the bank pin assignments that are required within a design. +# ---------------------------------------------------------------------------- + +# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. +set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]] + +# Set the bank voltage for IO Bank 34 to 1.8V by default. +# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]]; +# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]]; +# set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]]; + +# Set the bank voltage for IO Bank 35 to 1.8V by default. +set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]] +# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]]; +# set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]]; + +# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. +set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]] + + +#################################################################################### +# Constraints from file : 'clock_constraints.xdc' +#################################################################################### + +create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] +set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset] +set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset] + + +# Vivado Generated physical constraints + +set_property BEL D6LUT [get_cells {LED_PIPE_Leds_a0[0]_i_1}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[0]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[10]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[11]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[12]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[12]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[13]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[14]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[15]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[15]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[1]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[2]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[3]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[4]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[4]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[5]}] +set_property BEL BFF [get_cells {LED_PIPE_Leds_a0_reg[6]}] +set_property BEL CFF [get_cells {LED_PIPE_Leds_a0_reg[7]}] +set_property BEL DFF [get_cells {LED_PIPE_Leds_a0_reg[8]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_Leds_a0_reg[8]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_Leds_a0_reg[9]}] +set_property BEL A5LUT [get_cells {LED_PIPE_count1_a1[0]_i_1}] +set_property BEL C6LUT [get_cells {LED_PIPE_count1_a1[31]_i_1}] +set_property BEL A6LUT [get_cells {LED_PIPE_count1_a1[31]_i_4}] +set_property BEL A6LUT [get_cells {LED_PIPE_count1_a1[31]_i_5}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[0]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[10]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[11]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[12]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[12]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[13]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[14]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[15]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[16]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[16]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[17]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[18]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[19]}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[1]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[20]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[20]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[21]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[22]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[23]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[24]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[24]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[25]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[26]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[27]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[28]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[28]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[29]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[2]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[30]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[31]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[31]_i_2}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[3]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[4]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[4]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[5]}] +set_property BEL BFF [get_cells {LED_PIPE_count1_a1_reg[6]}] +set_property BEL CFF [get_cells {LED_PIPE_count1_a1_reg[7]}] +set_property BEL DFF [get_cells {LED_PIPE_count1_a1_reg[8]}] +set_property BEL CARRY4 [get_cells {LED_PIPE_count1_a1_reg[8]_i_1}] +set_property BEL AFF [get_cells {LED_PIPE_count1_a1_reg[9]}] +set_property BEL AFF [get_cells LED_PIPE_rst1_a1_reg] +set_property BEL BUFG [get_cells clk_IBUF_BUFG_inst] +set_property BEL INBUF_EN [get_cells clk_IBUF_inst] +set_property BEL A6LUT [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2}] +set_property BEL A6LUT [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_count1_a1[31]_i_3}] +set_property BEL BFF [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_10] +set_property BEL D6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_11] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_12] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_13] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_14] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_4] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_5] +set_property BEL B6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_6] +set_property BEL C6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7] +set_property BEL D6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8] +set_property BEL A6LUT [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_9] +set_property BEL OUTBUF [get_cells {led_OBUF[0]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[10]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[11]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[12]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[13]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[14]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[15]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[1]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[2]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[3]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[4]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[5]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[6]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[7]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[8]_inst}] +set_property BEL OUTBUF [get_cells {led_OBUF[9]_inst}] +set_property BEL AFF [get_cells {led_reg[0]}] +set_property BEL AFF [get_cells {led_reg[10]}] +set_property BEL BFF [get_cells {led_reg[11]}] +set_property BEL AFF [get_cells {led_reg[12]}] +set_property BEL BFF [get_cells {led_reg[13]}] +set_property BEL CFF [get_cells {led_reg[14]}] +set_property BEL DFF [get_cells {led_reg[15]}] +set_property BEL AFF [get_cells {led_reg[1]}] +set_property BEL BFF [get_cells {led_reg[2]}] +set_property BEL CFF [get_cells {led_reg[3]}] +set_property BEL DFF [get_cells {led_reg[4]}] +set_property BEL AFF [get_cells {led_reg[5]}] +set_property BEL BFF [get_cells {led_reg[6]}] +set_property BEL CFF [get_cells {led_reg[7]}] +set_property BEL CFF [get_cells {led_reg[8]}] +set_property BEL A5FF [get_cells {led_reg[9]}] +set_property BEL INBUF_EN [get_cells reset_IBUF_inst] +set_property LOC SLICE_X111Y100 [get_cells {LED_PIPE_Leds_a0[0]_i_1}] +set_property LOC SLICE_X111Y100 [get_cells {LED_PIPE_Leds_a0_reg[0]}] +set_property LOC SLICE_X110Y102 [get_cells {LED_PIPE_Leds_a0_reg[10]}] +set_property LOC SLICE_X110Y102 [get_cells {LED_PIPE_Leds_a0_reg[11]}] +set_property LOC SLICE_X110Y102 [get_cells {LED_PIPE_Leds_a0_reg[12]}] +set_property LOC SLICE_X110Y102 [get_cells {LED_PIPE_Leds_a0_reg[12]_i_1}] +set_property LOC SLICE_X110Y103 [get_cells {LED_PIPE_Leds_a0_reg[13]}] +set_property LOC SLICE_X110Y103 [get_cells {LED_PIPE_Leds_a0_reg[14]}] +set_property LOC SLICE_X110Y103 [get_cells {LED_PIPE_Leds_a0_reg[15]}] +set_property LOC SLICE_X110Y103 [get_cells {LED_PIPE_Leds_a0_reg[15]_i_1}] +set_property LOC SLICE_X110Y100 [get_cells {LED_PIPE_Leds_a0_reg[1]}] +set_property LOC SLICE_X110Y100 [get_cells {LED_PIPE_Leds_a0_reg[2]}] +set_property LOC SLICE_X110Y100 [get_cells {LED_PIPE_Leds_a0_reg[3]}] +set_property LOC SLICE_X110Y100 [get_cells {LED_PIPE_Leds_a0_reg[4]}] +set_property LOC SLICE_X110Y100 [get_cells {LED_PIPE_Leds_a0_reg[4]_i_1}] +set_property LOC SLICE_X110Y101 [get_cells {LED_PIPE_Leds_a0_reg[5]}] +set_property LOC SLICE_X110Y101 [get_cells {LED_PIPE_Leds_a0_reg[6]}] +set_property LOC SLICE_X110Y101 [get_cells {LED_PIPE_Leds_a0_reg[7]}] +set_property LOC SLICE_X110Y101 [get_cells {LED_PIPE_Leds_a0_reg[8]}] +set_property LOC SLICE_X110Y101 [get_cells {LED_PIPE_Leds_a0_reg[8]_i_1}] +set_property LOC SLICE_X110Y102 [get_cells {LED_PIPE_Leds_a0_reg[9]}] +set_property LOC SLICE_X113Y99 [get_cells {LED_PIPE_count1_a1[0]_i_1}] +set_property LOC SLICE_X113Y102 [get_cells {LED_PIPE_count1_a1[31]_i_1}] +set_property LOC SLICE_X113Y99 [get_cells {LED_PIPE_count1_a1[31]_i_4}] +set_property LOC SLICE_X113Y98 [get_cells {LED_PIPE_count1_a1[31]_i_5}] +set_property LOC SLICE_X113Y99 [get_cells {LED_PIPE_count1_a1_reg[0]}] +set_property LOC SLICE_X112Y100 [get_cells {LED_PIPE_count1_a1_reg[10]}] +set_property LOC SLICE_X112Y100 [get_cells {LED_PIPE_count1_a1_reg[11]}] +set_property LOC SLICE_X112Y100 [get_cells {LED_PIPE_count1_a1_reg[12]}] +set_property LOC SLICE_X112Y100 [get_cells {LED_PIPE_count1_a1_reg[12]_i_1}] +set_property LOC SLICE_X112Y101 [get_cells {LED_PIPE_count1_a1_reg[13]}] +set_property LOC SLICE_X112Y101 [get_cells {LED_PIPE_count1_a1_reg[14]}] +set_property LOC SLICE_X112Y101 [get_cells {LED_PIPE_count1_a1_reg[15]}] +set_property LOC SLICE_X112Y101 [get_cells {LED_PIPE_count1_a1_reg[16]}] +set_property LOC SLICE_X112Y101 [get_cells {LED_PIPE_count1_a1_reg[16]_i_1}] +set_property LOC SLICE_X112Y102 [get_cells {LED_PIPE_count1_a1_reg[17]}] +set_property LOC SLICE_X112Y102 [get_cells {LED_PIPE_count1_a1_reg[18]}] +set_property LOC SLICE_X112Y102 [get_cells {LED_PIPE_count1_a1_reg[19]}] +set_property LOC SLICE_X112Y98 [get_cells {LED_PIPE_count1_a1_reg[1]}] +set_property LOC SLICE_X112Y102 [get_cells {LED_PIPE_count1_a1_reg[20]}] +set_property LOC SLICE_X112Y102 [get_cells {LED_PIPE_count1_a1_reg[20]_i_1}] +set_property LOC SLICE_X112Y103 [get_cells {LED_PIPE_count1_a1_reg[21]}] +set_property LOC SLICE_X112Y103 [get_cells {LED_PIPE_count1_a1_reg[22]}] +set_property LOC SLICE_X112Y103 [get_cells {LED_PIPE_count1_a1_reg[23]}] +set_property LOC SLICE_X112Y103 [get_cells {LED_PIPE_count1_a1_reg[24]}] +set_property LOC SLICE_X112Y103 [get_cells {LED_PIPE_count1_a1_reg[24]_i_1}] +set_property LOC SLICE_X112Y104 [get_cells {LED_PIPE_count1_a1_reg[25]}] +set_property LOC SLICE_X112Y104 [get_cells {LED_PIPE_count1_a1_reg[26]}] +set_property LOC SLICE_X112Y104 [get_cells {LED_PIPE_count1_a1_reg[27]}] +set_property LOC SLICE_X112Y104 [get_cells {LED_PIPE_count1_a1_reg[28]}] +set_property LOC SLICE_X112Y104 [get_cells {LED_PIPE_count1_a1_reg[28]_i_1}] +set_property LOC SLICE_X112Y105 [get_cells {LED_PIPE_count1_a1_reg[29]}] +set_property LOC SLICE_X112Y98 [get_cells {LED_PIPE_count1_a1_reg[2]}] +set_property LOC SLICE_X112Y105 [get_cells {LED_PIPE_count1_a1_reg[30]}] +set_property LOC SLICE_X112Y105 [get_cells {LED_PIPE_count1_a1_reg[31]}] +set_property LOC SLICE_X112Y105 [get_cells {LED_PIPE_count1_a1_reg[31]_i_2}] +set_property LOC SLICE_X112Y98 [get_cells {LED_PIPE_count1_a1_reg[3]}] +set_property LOC SLICE_X112Y98 [get_cells {LED_PIPE_count1_a1_reg[4]}] +set_property LOC SLICE_X112Y98 [get_cells {LED_PIPE_count1_a1_reg[4]_i_1}] +set_property LOC SLICE_X112Y99 [get_cells {LED_PIPE_count1_a1_reg[5]}] +set_property LOC SLICE_X112Y99 [get_cells {LED_PIPE_count1_a1_reg[6]}] +set_property LOC SLICE_X112Y99 [get_cells {LED_PIPE_count1_a1_reg[7]}] +set_property LOC SLICE_X112Y99 [get_cells {LED_PIPE_count1_a1_reg[8]}] +set_property LOC SLICE_X112Y99 [get_cells {LED_PIPE_count1_a1_reg[8]_i_1}] +set_property LOC SLICE_X112Y100 [get_cells {LED_PIPE_count1_a1_reg[9]}] +set_property LOC SLICE_X113Y102 [get_cells LED_PIPE_rst1_a1_reg] +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] +set_property LOC SLICE_X109Y102 [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2}] +set_property LOC SLICE_X113Y104 [get_cells {gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_count1_a1[31]_i_3}] +set_property LOC SLICE_X111Y103 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg] +set_property LOC SLICE_X111Y103 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1] +set_property LOC SLICE_X113Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_10] +set_property LOC SLICE_X113Y102 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_11] +set_property LOC SLICE_X113Y101 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_12] +set_property LOC SLICE_X111Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_13] +set_property LOC SLICE_X111Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_14] +set_property LOC SLICE_X113Y103 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3] +set_property LOC SLICE_X113Y101 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_4] +set_property LOC SLICE_X113Y102 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_5] +set_property LOC SLICE_X111Y100 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_6] +set_property LOC SLICE_X113Y103 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_7] +set_property LOC SLICE_X113Y103 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8] +set_property LOC SLICE_X113Y103 [get_cells gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_9] +set_property LOC P16 [get_cells {led_OBUF[10]_inst}] +set_property LOC T18 [get_cells {led_OBUF[11]_inst}] +set_property LOC R18 [get_cells {led_OBUF[12]_inst}] +set_property LOC T19 [get_cells {led_OBUF[13]_inst}] +set_property LOC R19 [get_cells {led_OBUF[14]_inst}] +set_property LOC T17 [get_cells {led_OBUF[15]_inst}] +set_property LOC R15 [get_cells {led_OBUF[8]_inst}] +set_property LOC R16 [get_cells {led_OBUF[9]_inst}] +set_property LOC SLICE_X110Y96 [get_cells {led_reg[0]}] +set_property LOC SLICE_X111Y102 [get_cells {led_reg[10]}] +set_property LOC SLICE_X111Y102 [get_cells {led_reg[11]}] +set_property LOC SLICE_X111Y101 [get_cells {led_reg[12]}] +set_property LOC SLICE_X111Y101 [get_cells {led_reg[13]}] +set_property LOC SLICE_X111Y102 [get_cells {led_reg[14]}] +set_property LOC SLICE_X111Y102 [get_cells {led_reg[15]}] +set_property LOC SLICE_X111Y96 [get_cells {led_reg[1]}] +set_property LOC SLICE_X111Y96 [get_cells {led_reg[2]}] +set_property LOC SLICE_X111Y96 [get_cells {led_reg[3]}] +set_property LOC SLICE_X111Y96 [get_cells {led_reg[4]}] +set_property LOC SLICE_X111Y95 [get_cells {led_reg[5]}] +set_property LOC SLICE_X111Y95 [get_cells {led_reg[6]}] +set_property LOC SLICE_X111Y95 [get_cells {led_reg[7]}] +set_property LOC SLICE_X111Y101 [get_cells {led_reg[8]}] +set_property LOC SLICE_X111Y102 [get_cells {led_reg[9]}] +set_property PACKAGE_PIN P16 [get_ports {led[10]}] +set_property PACKAGE_PIN T18 [get_ports {led[11]}] +set_property PACKAGE_PIN R18 [get_ports {led[12]}] +set_property PACKAGE_PIN T19 [get_ports {led[13]}] +set_property PACKAGE_PIN R19 [get_ports {led[14]}] +set_property PACKAGE_PIN T17 [get_ports {led[15]}] +set_property PACKAGE_PIN R15 [get_ports {led[8]}] +set_property PACKAGE_PIN R16 [get_ports {led[9]}] + +# Vivado Generated miscellaneous constraints + +#revert back to original instance +current_instance -quiet diff --git a/out/zedboard/led_counter/Output/fpga_impl_netlist.v b/out/zedboard/led_counter/Output/fpga_impl_netlist.v new file mode 100644 index 0000000..bc59344 --- /dev/null +++ b/out/zedboard/led_counter/Output/fpga_impl_netlist.v @@ -0,0 +1,926 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +// Date : Sat Oct 30 02:51:02 2021 +// Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +// Command : write_verilog -force ./../out/zedboard/led_counter/Output/fpga_impl_netlist.v +// Design : top +// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an +// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input +// design files. +// Device : xc7z020clg484-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module clk_gate + (\LED_PIPE_count1_a1_reg[11] , + \LED_PIPE_count1_a1_reg[24] , + \LED_PIPE_count1_a1_reg[28] , + CLK, + LED_PIPE_count1_a1, + O, + latched_clk_en_reg_i_6_0, + latched_clk_en_reg_i_3_0, + latched_clk_en_reg_i_6_1, + latched_clk_en_reg_i_3_1, + latched_clk_en_reg_i_3_2, + latched_clk_en_reg_i_3_3, + latched_clk_en_reg_i_3_4, + LED_PIPE_rst1_a1, + clk_IBUF, + clk_IBUF_BUFG); + output \LED_PIPE_count1_a1_reg[11] ; + output \LED_PIPE_count1_a1_reg[24] ; + output \LED_PIPE_count1_a1_reg[28] ; + output CLK; + input [25:0]LED_PIPE_count1_a1; + input [3:0]O; + input [3:0]latched_clk_en_reg_i_6_0; + input [3:0]latched_clk_en_reg_i_3_0; + input [3:0]latched_clk_en_reg_i_6_1; + input [3:0]latched_clk_en_reg_i_3_1; + input [3:0]latched_clk_en_reg_i_3_2; + input [3:0]latched_clk_en_reg_i_3_3; + input [2:0]latched_clk_en_reg_i_3_4; + input LED_PIPE_rst1_a1; + input clk_IBUF; + input clk_IBUF_BUFG; + + wire CLK; + wire GND_1; + wire [25:0]LED_PIPE_count1_a1; + wire \LED_PIPE_count1_a1_reg[11] ; + wire \LED_PIPE_count1_a1_reg[24] ; + wire \LED_PIPE_count1_a1_reg[28] ; + wire LED_PIPE_refresh_a0; + wire LED_PIPE_rst1_a1; + wire [3:0]O; + wire VCC_1; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire latched_clk_en; + wire latched_clk_en_reg_i_10_n_0; + wire latched_clk_en_reg_i_11_n_0; + wire latched_clk_en_reg_i_12_n_0; + wire latched_clk_en_reg_i_13_n_0; + wire latched_clk_en_reg_i_14_n_0; + wire [3:0]latched_clk_en_reg_i_3_0; + wire [3:0]latched_clk_en_reg_i_3_1; + wire [3:0]latched_clk_en_reg_i_3_2; + wire [3:0]latched_clk_en_reg_i_3_3; + wire [2:0]latched_clk_en_reg_i_3_4; + wire latched_clk_en_reg_i_3_n_0; + wire [3:0]latched_clk_en_reg_i_6_0; + wire [3:0]latched_clk_en_reg_i_6_1; + wire latched_clk_en_reg_i_6_n_0; + wire latched_clk_en_reg_i_7_n_0; + wire latched_clk_en_reg_i_8_n_0; + wire latched_clk_en_reg_i_9_n_0; + + GND GND + (.G(GND_1)); + LUT2 #( + .INIT(4'h8)) + \LED_PIPE_Leds_a0[15]_i_2 + (.I0(latched_clk_en), + .I1(clk_IBUF), + .O(CLK)); + LUT6 #( + .INIT(64'h0000000000000001)) + \LED_PIPE_count1_a1[31]_i_3 + (.I0(LED_PIPE_count1_a1[22]), + .I1(LED_PIPE_count1_a1[23]), + .I2(LED_PIPE_count1_a1[20]), + .I3(LED_PIPE_count1_a1[21]), + .I4(LED_PIPE_count1_a1[25]), + .I5(LED_PIPE_count1_a1[24]), + .O(\LED_PIPE_count1_a1_reg[28] )); + VCC VCC + (.P(VCC_1)); + (* OPT_MODIFIED = "MLO" *) + (* XILINX_LEGACY_PRIM = "LD" *) + LDCE #( + .INIT(1'b0), + .IS_G_INVERTED(1'b1)) + latched_clk_en_reg + (.CLR(GND_1), + .D(LED_PIPE_refresh_a0), + .G(clk_IBUF_BUFG), + .GE(VCC_1), + .Q(latched_clk_en)); + LUT4 #( + .INIT(16'hA800)) + latched_clk_en_reg_i_1 + (.I0(latched_clk_en_reg_i_3_n_0), + .I1(\LED_PIPE_count1_a1_reg[11] ), + .I2(\LED_PIPE_count1_a1_reg[24] ), + .I3(latched_clk_en_reg_i_6_n_0), + .O(LED_PIPE_refresh_a0)); + LUT4 #( + .INIT(16'h0001)) + latched_clk_en_reg_i_10 + (.I0(LED_PIPE_count1_a1[2]), + .I1(LED_PIPE_count1_a1[1]), + .I2(LED_PIPE_count1_a1[4]), + .I3(LED_PIPE_count1_a1[3]), + .O(latched_clk_en_reg_i_10_n_0)); + LUT4 #( + .INIT(16'h7FFF)) + latched_clk_en_reg_i_11 + (.I0(LED_PIPE_count1_a1[14]), + .I1(LED_PIPE_count1_a1[13]), + .I2(LED_PIPE_count1_a1[16]), + .I3(LED_PIPE_count1_a1[15]), + .O(latched_clk_en_reg_i_11_n_0)); + LUT6 #( + .INIT(64'h15555555FFFFFFFF)) + latched_clk_en_reg_i_12 + (.I0(LED_PIPE_count1_a1[10]), + .I1(LED_PIPE_count1_a1[7]), + .I2(LED_PIPE_count1_a1[6]), + .I3(LED_PIPE_count1_a1[9]), + .I4(LED_PIPE_count1_a1[8]), + .I5(LED_PIPE_count1_a1[11]), + .O(latched_clk_en_reg_i_12_n_0)); + LUT6 #( + .INIT(64'h0000000000002000)) + latched_clk_en_reg_i_13 + (.I0(latched_clk_en_reg_i_6_1[1]), + .I1(latched_clk_en_reg_i_6_1[2]), + .I2(O[3]), + .I3(latched_clk_en_reg_i_6_1[0]), + .I4(latched_clk_en_reg_i_6_0[0]), + .I5(latched_clk_en_reg_i_6_1[3]), + .O(latched_clk_en_reg_i_13_n_0)); + LUT6 #( + .INIT(64'h0008000000000000)) + latched_clk_en_reg_i_14 + (.I0(latched_clk_en_reg_i_6_0[3]), + .I1(latched_clk_en_reg_i_3_0[0]), + .I2(latched_clk_en_reg_i_6_0[1]), + .I3(latched_clk_en_reg_i_6_0[2]), + .I4(latched_clk_en_reg_i_3_0[2]), + .I5(latched_clk_en_reg_i_3_0[1]), + .O(latched_clk_en_reg_i_14_n_0)); + LUT4 #( + .INIT(16'h8000)) + latched_clk_en_reg_i_3 + (.I0(latched_clk_en_reg_i_7_n_0), + .I1(\LED_PIPE_count1_a1_reg[28] ), + .I2(latched_clk_en_reg_i_8_n_0), + .I3(latched_clk_en_reg_i_9_n_0), + .O(latched_clk_en_reg_i_3_n_0)); + LUT5 #( + .INIT(32'h00010000)) + latched_clk_en_reg_i_4 + (.I0(LED_PIPE_count1_a1[5]), + .I1(LED_PIPE_count1_a1[10]), + .I2(LED_PIPE_count1_a1[12]), + .I3(LED_PIPE_count1_a1[18]), + .I4(latched_clk_en_reg_i_10_n_0), + .O(\LED_PIPE_count1_a1_reg[11] )); + LUT6 #( + .INIT(64'h45455545FFFFFFFF)) + latched_clk_en_reg_i_5 + (.I0(LED_PIPE_count1_a1[18]), + .I1(latched_clk_en_reg_i_11_n_0), + .I2(LED_PIPE_count1_a1[17]), + .I3(latched_clk_en_reg_i_12_n_0), + .I4(LED_PIPE_count1_a1[12]), + .I5(LED_PIPE_count1_a1[19]), + .O(\LED_PIPE_count1_a1_reg[24] )); + LUT5 #( + .INIT(32'h80000000)) + latched_clk_en_reg_i_6 + (.I0(latched_clk_en_reg_i_13_n_0), + .I1(O[2]), + .I2(O[1]), + .I3(O[0]), + .I4(latched_clk_en_reg_i_14_n_0), + .O(latched_clk_en_reg_i_6_n_0)); + LUT6 #( + .INIT(64'h0000000000000001)) + latched_clk_en_reg_i_7 + (.I0(latched_clk_en_reg_i_3_4[1]), + .I1(latched_clk_en_reg_i_3_4[2]), + .I2(latched_clk_en_reg_i_3_3[3]), + .I3(latched_clk_en_reg_i_3_4[0]), + .I4(LED_PIPE_count1_a1[0]), + .I5(LED_PIPE_rst1_a1), + .O(latched_clk_en_reg_i_7_n_0)); + LUT6 #( + .INIT(64'h0020000000000000)) + latched_clk_en_reg_i_8 + (.I0(latched_clk_en_reg_i_3_1[2]), + .I1(latched_clk_en_reg_i_3_1[1]), + .I2(latched_clk_en_reg_i_3_1[0]), + .I3(latched_clk_en_reg_i_3_0[3]), + .I4(latched_clk_en_reg_i_3_2[0]), + .I5(latched_clk_en_reg_i_3_1[3]), + .O(latched_clk_en_reg_i_8_n_0)); + LUT6 #( + .INIT(64'h0000000000002000)) + latched_clk_en_reg_i_9 + (.I0(latched_clk_en_reg_i_3_3[0]), + .I1(latched_clk_en_reg_i_3_2[3]), + .I2(latched_clk_en_reg_i_3_2[1]), + .I3(latched_clk_en_reg_i_3_2[2]), + .I4(latched_clk_en_reg_i_3_3[2]), + .I5(latched_clk_en_reg_i_3_3[1]), + .O(latched_clk_en_reg_i_9_n_0)); +endmodule + +(* ECO_CHECKSUM = "96723c4c" *) +(* STRUCTURAL_NETLIST = "yes" *) +module top + (clk, + reset, + led); + input clk; + input reset; + output [15:0]led; + + wire \ ; + wire \ ; + wire [15:0]LED_PIPE_Leds_a0; + wire \LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ; + wire \LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ; + wire \LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ; + wire [15:0]LED_PIPE_Leds_n10_in; + wire [31:0]LED_PIPE_count1_a1; + wire \LED_PIPE_count1_a1[0]_i_1_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_1_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_4_n_0 ; + wire \LED_PIPE_count1_a1[31]_i_5_n_0 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[12]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[16]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[20]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[24]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[28]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_5 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_6 ; + wire \LED_PIPE_count1_a1_reg[31]_i_2_n_7 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[4]_i_1_n_7 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_0 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_4 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_5 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_6 ; + wire \LED_PIPE_count1_a1_reg[8]_i_1_n_7 ; + wire LED_PIPE_rst1_a1; + wire clk; + wire clkF_LED_PIPE_refresh_a1; + wire clk_IBUF; + wire clk_IBUF_BUFG; + wire gen_clkF_LED_PIPE_refresh_a1_n_0; + wire gen_clkF_LED_PIPE_refresh_a1_n_1; + wire gen_clkF_LED_PIPE_refresh_a1_n_2; + wire [15:0]led; + wire [15:0]led_OBUF; + wire reset; + wire reset_IBUF; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[4]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_Leds_a0_reg[8]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[12]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[16]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[20]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[24]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[28]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[4]_i_1_CO_UNCONNECTED ; + wire [3:0]\NLW_LED_PIPE_count1_a1_reg[8]_i_1_CO_UNCONNECTED ; + + GND GND + (.G(\ )); + LUT1 #( + .INIT(2'h1)) + \LED_PIPE_Leds_a0[0]_i_1 + (.I0(LED_PIPE_Leds_a0[0]), + .O(LED_PIPE_Leds_n10_in[0])); + FDSE \LED_PIPE_Leds_a0_reg[0] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[0]), + .Q(LED_PIPE_Leds_a0[0]), + .S(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[10] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[10]), + .Q(LED_PIPE_Leds_a0[10]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[11] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[11]), + .Q(LED_PIPE_Leds_a0[11]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[12] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[12]), + .Q(LED_PIPE_Leds_a0[12]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[12]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ), + .CO({\LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[12]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[12:9]), + .S(LED_PIPE_Leds_a0[12:9])); + FDRE \LED_PIPE_Leds_a0_reg[13] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[13]), + .Q(LED_PIPE_Leds_a0[13]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[14] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[14]), + .Q(LED_PIPE_Leds_a0[14]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[15] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[15]), + .Q(LED_PIPE_Leds_a0[15]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[15]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[12]_i_1_n_0 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[15:13]), + .S({\ ,LED_PIPE_Leds_a0[15:13]})); + FDRE \LED_PIPE_Leds_a0_reg[1] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[1]), + .Q(LED_PIPE_Leds_a0[1]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[2] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[2]), + .Q(LED_PIPE_Leds_a0[2]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[3] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[3]), + .Q(LED_PIPE_Leds_a0[3]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[4] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[4]), + .Q(LED_PIPE_Leds_a0[4]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[4]_i_1 + (.CI(\ ), + .CO({\LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[4]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(LED_PIPE_Leds_a0[0]), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[4:1]), + .S(LED_PIPE_Leds_a0[4:1])); + FDRE \LED_PIPE_Leds_a0_reg[5] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[5]), + .Q(LED_PIPE_Leds_a0[5]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[6] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[6]), + .Q(LED_PIPE_Leds_a0[6]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[7] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[7]), + .Q(LED_PIPE_Leds_a0[7]), + .R(reset_IBUF)); + FDRE \LED_PIPE_Leds_a0_reg[8] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[8]), + .Q(LED_PIPE_Leds_a0[8]), + .R(reset_IBUF)); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_Leds_a0_reg[8]_i_1 + (.CI(\LED_PIPE_Leds_a0_reg[4]_i_1_n_0 ), + .CO({\LED_PIPE_Leds_a0_reg[8]_i_1_n_0 ,\NLW_LED_PIPE_Leds_a0_reg[8]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O(LED_PIPE_Leds_n10_in[8:5]), + .S(LED_PIPE_Leds_a0[8:5])); + FDRE \LED_PIPE_Leds_a0_reg[9] + (.C(clkF_LED_PIPE_refresh_a1), + .CE(\ ), + .D(LED_PIPE_Leds_n10_in[9]), + .Q(LED_PIPE_Leds_a0[9]), + .R(reset_IBUF)); + LUT1 #( + .INIT(2'h1)) + \LED_PIPE_count1_a1[0]_i_1 + (.I0(LED_PIPE_count1_a1[0]), + .O(\LED_PIPE_count1_a1[0]_i_1_n_0 )); + LUT5 #( + .INIT(32'hBBBFBFBF)) + \LED_PIPE_count1_a1[31]_i_1 + (.I0(LED_PIPE_rst1_a1), + .I1(gen_clkF_LED_PIPE_refresh_a1_n_2), + .I2(gen_clkF_LED_PIPE_refresh_a1_n_1), + .I3(gen_clkF_LED_PIPE_refresh_a1_n_0), + .I4(\LED_PIPE_count1_a1[31]_i_4_n_0 ), + .O(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + LUT4 #( + .INIT(16'hBFFF)) + \LED_PIPE_count1_a1[31]_i_4 + (.I0(\LED_PIPE_count1_a1[31]_i_5_n_0 ), + .I1(LED_PIPE_count1_a1[0]), + .I2(LED_PIPE_count1_a1[5]), + .I3(LED_PIPE_count1_a1[6]), + .O(\LED_PIPE_count1_a1[31]_i_4_n_0 )); + LUT4 #( + .INIT(16'h7FFF)) + \LED_PIPE_count1_a1[31]_i_5 + (.I0(LED_PIPE_count1_a1[2]), + .I1(LED_PIPE_count1_a1[1]), + .I2(LED_PIPE_count1_a1[4]), + .I3(LED_PIPE_count1_a1[3]), + .O(\LED_PIPE_count1_a1[31]_i_5_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[0] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1[0]_i_1_n_0 ), + .Q(LED_PIPE_count1_a1[0]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[10] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[10]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[11] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[11]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[12] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[12]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[12]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[8]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[12]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[12]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[12:9])); + FDRE \LED_PIPE_count1_a1_reg[13] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[13]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[14] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[14]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[15] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[15]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[16] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[16]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[16]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[12]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[16]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[16]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[16:13])); + FDRE \LED_PIPE_count1_a1_reg[17] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[17]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[18] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[18]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[19] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[19]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[1] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[1]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[20] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[20]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[20]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[16]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[20]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[20]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[20:17])); + FDRE \LED_PIPE_count1_a1_reg[21] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[21]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[22] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[22]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[23] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[23]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[24] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[24]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[24]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[20]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[24]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[24]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[24:21])); + FDRE \LED_PIPE_count1_a1_reg[25] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[25]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[26] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[26]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[27] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[27]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[28] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[28]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[28]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[24]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[28]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[28]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[28:25])); + FDRE \LED_PIPE_count1_a1_reg[29] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_7 ), + .Q(LED_PIPE_count1_a1[29]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[2] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[2]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[30] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ), + .Q(LED_PIPE_count1_a1[30]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[31] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ), + .Q(LED_PIPE_count1_a1[31]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[31]_i_2 + (.CI(\LED_PIPE_count1_a1_reg[28]_i_1_n_0 ), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_7 }), + .S({\ ,LED_PIPE_count1_a1[31:29]})); + FDRE \LED_PIPE_count1_a1_reg[3] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[3]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[4] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[4]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[4]_i_1 + (.CI(\ ), + .CO({\LED_PIPE_count1_a1_reg[4]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[4]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(LED_PIPE_count1_a1[0]), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[4:1])); + FDRE \LED_PIPE_count1_a1_reg[5] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[5]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[6] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ), + .Q(LED_PIPE_count1_a1[6]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[7] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ), + .Q(LED_PIPE_count1_a1[7]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + FDRE \LED_PIPE_count1_a1_reg[8] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ), + .Q(LED_PIPE_count1_a1[8]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* ADDER_THRESHOLD = "35" *) + (* OPT_MODIFIED = "SWEEP" *) + CARRY4 \LED_PIPE_count1_a1_reg[8]_i_1 + (.CI(\LED_PIPE_count1_a1_reg[4]_i_1_n_0 ), + .CO({\LED_PIPE_count1_a1_reg[8]_i_1_n_0 ,\NLW_LED_PIPE_count1_a1_reg[8]_i_1_CO_UNCONNECTED [2:0]}), + .CYINIT(\ ), + .DI({\ ,\ ,\ ,\ }), + .O({\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_7 }), + .S(LED_PIPE_count1_a1[8:5])); + FDRE \LED_PIPE_count1_a1_reg[9] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(\LED_PIPE_count1_a1_reg[12]_i_1_n_7 ), + .Q(LED_PIPE_count1_a1[9]), + .R(\LED_PIPE_count1_a1[31]_i_1_n_0 )); + (* \PinAttr:D:HOLD_DETOUR = "2607" *) + FDRE LED_PIPE_rst1_a1_reg + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(reset_IBUF), + .Q(LED_PIPE_rst1_a1), + .R(\ )); + VCC VCC + (.P(\ )); + BUFG clk_IBUF_BUFG_inst + (.I(clk_IBUF), + .O(clk_IBUF_BUFG)); + IBUF clk_IBUF_inst + (.I(clk), + .O(clk_IBUF)); + clk_gate gen_clkF_LED_PIPE_refresh_a1 + (.CLK(clkF_LED_PIPE_refresh_a1), + .LED_PIPE_count1_a1({LED_PIPE_count1_a1[31:7],LED_PIPE_count1_a1[0]}), + .\LED_PIPE_count1_a1_reg[11] (gen_clkF_LED_PIPE_refresh_a1_n_0), + .\LED_PIPE_count1_a1_reg[24] (gen_clkF_LED_PIPE_refresh_a1_n_1), + .\LED_PIPE_count1_a1_reg[28] (gen_clkF_LED_PIPE_refresh_a1_n_2), + .LED_PIPE_rst1_a1(LED_PIPE_rst1_a1), + .O({\LED_PIPE_count1_a1_reg[4]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[4]_i_1_n_7 }), + .clk_IBUF(clk_IBUF), + .clk_IBUF_BUFG(clk_IBUF_BUFG), + .latched_clk_en_reg_i_3_0({\LED_PIPE_count1_a1_reg[16]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[16]_i_1_n_7 }), + .latched_clk_en_reg_i_3_1({\LED_PIPE_count1_a1_reg[20]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[20]_i_1_n_7 }), + .latched_clk_en_reg_i_3_2({\LED_PIPE_count1_a1_reg[24]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[24]_i_1_n_7 }), + .latched_clk_en_reg_i_3_3({\LED_PIPE_count1_a1_reg[28]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[28]_i_1_n_7 }), + .latched_clk_en_reg_i_3_4({\LED_PIPE_count1_a1_reg[31]_i_2_n_5 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_6 ,\LED_PIPE_count1_a1_reg[31]_i_2_n_7 }), + .latched_clk_en_reg_i_6_0({\LED_PIPE_count1_a1_reg[12]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[12]_i_1_n_7 }), + .latched_clk_en_reg_i_6_1({\LED_PIPE_count1_a1_reg[8]_i_1_n_4 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_5 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_6 ,\LED_PIPE_count1_a1_reg[8]_i_1_n_7 })); + OBUF \led_OBUF[0]_inst + (.I(led_OBUF[0]), + .O(led[0])); + OBUF \led_OBUF[10]_inst + (.I(led_OBUF[10]), + .O(led[10])); + OBUF \led_OBUF[11]_inst + (.I(led_OBUF[11]), + .O(led[11])); + OBUF \led_OBUF[12]_inst + (.I(led_OBUF[12]), + .O(led[12])); + OBUF \led_OBUF[13]_inst + (.I(led_OBUF[13]), + .O(led[13])); + OBUF \led_OBUF[14]_inst + (.I(led_OBUF[14]), + .O(led[14])); + OBUF \led_OBUF[15]_inst + (.I(led_OBUF[15]), + .O(led[15])); + OBUF \led_OBUF[1]_inst + (.I(led_OBUF[1]), + .O(led[1])); + OBUF \led_OBUF[2]_inst + (.I(led_OBUF[2]), + .O(led[2])); + OBUF \led_OBUF[3]_inst + (.I(led_OBUF[3]), + .O(led[3])); + OBUF \led_OBUF[4]_inst + (.I(led_OBUF[4]), + .O(led[4])); + OBUF \led_OBUF[5]_inst + (.I(led_OBUF[5]), + .O(led[5])); + OBUF \led_OBUF[6]_inst + (.I(led_OBUF[6]), + .O(led[6])); + OBUF \led_OBUF[7]_inst + (.I(led_OBUF[7]), + .O(led[7])); + OBUF \led_OBUF[8]_inst + (.I(led_OBUF[8]), + .O(led[8])); + OBUF \led_OBUF[9]_inst + (.I(led_OBUF[9]), + .O(led[9])); + FDRE \led_reg[0] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[0]), + .Q(led_OBUF[0]), + .R(\ )); + FDRE \led_reg[10] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[10]), + .Q(led_OBUF[10]), + .R(\ )); + FDRE \led_reg[11] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[11]), + .Q(led_OBUF[11]), + .R(\ )); + FDRE \led_reg[12] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[12]), + .Q(led_OBUF[12]), + .R(\ )); + FDRE \led_reg[13] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[13]), + .Q(led_OBUF[13]), + .R(\ )); + FDRE \led_reg[14] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[14]), + .Q(led_OBUF[14]), + .R(\ )); + FDRE \led_reg[15] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[15]), + .Q(led_OBUF[15]), + .R(\ )); + FDRE \led_reg[1] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[1]), + .Q(led_OBUF[1]), + .R(\ )); + FDRE \led_reg[2] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[2]), + .Q(led_OBUF[2]), + .R(\ )); + FDRE \led_reg[3] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[3]), + .Q(led_OBUF[3]), + .R(\ )); + FDRE \led_reg[4] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[4]), + .Q(led_OBUF[4]), + .R(\ )); + FDRE \led_reg[5] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[5]), + .Q(led_OBUF[5]), + .R(\ )); + FDRE \led_reg[6] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[6]), + .Q(led_OBUF[6]), + .R(\ )); + FDRE \led_reg[7] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[7]), + .Q(led_OBUF[7]), + .R(\ )); + FDRE \led_reg[8] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[8]), + .Q(led_OBUF[8]), + .R(\ )); + FDRE \led_reg[9] + (.C(clk_IBUF_BUFG), + .CE(\ ), + .D(LED_PIPE_Leds_a0[9]), + .Q(led_OBUF[9]), + .R(\ )); + IBUF reset_IBUF_inst + (.I(reset), + .O(reset_IBUF)); +endmodule diff --git a/out/zedboard/led_counter/Output/place/post_place.dcp b/out/zedboard/led_counter/Output/place/post_place.dcp new file mode 100644 index 0000000..6e4a617 Binary files /dev/null and b/out/zedboard/led_counter/Output/place/post_place.dcp differ diff --git a/out/zedboard/led_counter/Output/place/reports/post_place_timing_summary.rpt b/out/zedboard/led_counter/Output/place/reports/post_place_timing_summary.rpt new file mode 100644 index 0000000..0b31b0d --- /dev/null +++ b/out/zedboard/led_counter/Output/place/reports/post_place_timing_summary.rpt @@ -0,0 +1,338 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:50:30 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/zedboard/led_counter/Output/place/reports/post_place_timing_summary.rpt +| Design : top +| Device : 7z020-clg484 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +------------------------------------------------------------------------------------------------------------------------------ + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.228 0.000 0 114 -4.790 -75.447 17 114 4.500 0.000 0 67 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.228 0.000 0 114 -4.790 -75.447 17 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.228ns, Total Violation 0.000ns +Hold : 17 Failing Endpoints, Worst Slack -4.790ns, Total Violation -75.447ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.228ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 4.745ns (logic 2.311ns (48.704%) route 2.434ns (51.296%)) + Logic Levels: 8 (CARRY4=5 LUT4=2 LUT6=1) + Clock Path Skew: 0.008ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 5.433ns = ( 10.433 - 5.000 ) + Source Clock Delay (SCD): 5.628ns + Clock Pessimism Removal (CPR): 0.203ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + Y9 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_IBUF_inst/O + net (fo=2, estimated) 2.171 3.661 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 3.762 r clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.866 5.628 clk_IBUF_BUFG + SLICE_X112Y98 FDRE r LED_PIPE_count1_a1_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y98 FDRE (Prop_fdre_C_Q) 0.518 6.146 r LED_PIPE_count1_a1_reg[1]/Q + net (fo=2, estimated) 0.619 6.765 LED_PIPE_count1_a1[1] + SLICE_X112Y98 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.637 7.402 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.402 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + SLICE_X112Y99 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 7.519 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.519 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + SLICE_X112Y100 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 7.636 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.636 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + SLICE_X112Y101 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 7.753 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, estimated) 0.000 7.753 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + SLICE_X112Y102 CARRY4 (Prop_carry4_CI_O[2]) + 0.256 8.009 r LED_PIPE_count1_a1_reg[20]_i_1/O[2] + net (fo=2, estimated) 0.956 8.965 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_1[2] + SLICE_X113Y103 LUT6 (Prop_lut6_I0_O) 0.301 9.266 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, estimated) 0.574 9.840 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + SLICE_X113Y103 LUT4 (Prop_lut4_I2_O) 0.124 9.964 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, estimated) 0.285 10.249 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + SLICE_X111Y103 LUT4 (Prop_lut4_I0_O) 0.124 10.373 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, routed) 0.000 10.373 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + SLICE_X111Y103 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + Y9 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + Y9 IBUF (Prop_ibuf_I_O) 1.420 6.420 f clk_IBUF_inst/O + net (fo=2, estimated) 2.062 8.482 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 8.573 f clk_IBUF_BUFG_inst/O + net (fo=50, estimated) 1.860 10.433 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + SLICE_X111Y103 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.203 10.636 + clock uncertainty -0.035 10.601 + ------------------------------------------------------------------- + required time 10.601 + arrival time -10.373 + ------------------------------------------------------------------- + slack 0.228 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -4.790ns (arrival time - required time) + Source: reset + (input port clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: LED_PIPE_Leds_a0_reg[13]/R + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.292ns (logic 1.416ns (61.786%) route 0.876ns (38.214%)) + Logic Levels: 1 (IBUF=1) + Input Delay: 0.000ns + Clock Path Skew: 7.066ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 7.066ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + input delay 0.000 0.000 + F22 0.000 0.000 r reset (IN) + net (fo=0) 0.000 0.000 reset + F22 IBUF (Prop_ibuf_I_O) 1.416 1.416 r reset_IBUF_inst/O + net (fo=17, estimated) 0.876 2.292 reset_IBUF + SLICE_X110Y103 FDRE r LED_PIPE_Leds_a0_reg[13]/R + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + Y9 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_IBUF_inst/O + net (fo=2, estimated) 4.773 6.263 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF + SLICE_X109Y102 LUT2 (Prop_lut2_I1_O) 0.124 6.387 r gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2/O + net (fo=16, estimated) 0.679 7.066 clkF_LED_PIPE_refresh_a1 + SLICE_X110Y103 FDRE r LED_PIPE_Leds_a0_reg[13]/C + clock pessimism 0.000 7.066 + clock uncertainty 0.035 7.102 + SLICE_X110Y103 FDRE (Hold_fdre_C_R) -0.020 7.082 LED_PIPE_Leds_a0_reg[13] + ------------------------------------------------------------------- + required time -7.082 + arrival time 2.292 + ------------------------------------------------------------------- + slack -4.790 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 clk_IBUF_BUFG_inst/I +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X113Y99 LED_PIPE_count1_a1_reg[0]/C +High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X110Y102 LED_PIPE_Leds_a0_reg[10]/C + + + diff --git a/out/zedboard/led_counter/Output/route/post_route.dcp b/out/zedboard/led_counter/Output/route/post_route.dcp new file mode 100644 index 0000000..a96e324 Binary files /dev/null and b/out/zedboard/led_counter/Output/route/post_route.dcp differ diff --git a/out/zedboard/led_counter/Output/route/reports/clock_util.rpt b/out/zedboard/led_counter/Output/route/reports/clock_util.rpt new file mode 100644 index 0000000..bdd8442 --- /dev/null +++ b/out/zedboard/led_counter/Output/route/reports/clock_util.rpt @@ -0,0 +1,160 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:50:51 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_clock_utilization -file ./../out/zedboard/led_counter/Output/route/reports/clock_util.rpt +| Design : top +| Device : 7z020-clg484 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X1Y1 +8. Clock Region Cell Placement per Global Clock: Region X1Y2 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 16 | 0 | 0 | 0 | +| BUFMR | 0 | 8 | 0 | 0 | 0 | +| BUFR | 0 | 16 | 0 | 0 | 0 | +| MMCM | 0 | 4 | 0 | 0 | 0 | +| PLL | 0 | 4 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 50 | 0 | 10.000 | clk | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 1 | 10.000 | clk | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 1000 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 17 | 2600 | 8 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 32 | 2600 | 23 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 1 | +| Y1 | 0 | 1 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | clk | 10.000 | {0.000 5.000} | 50 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+-----------------------+ +| | X0 | X1 | HORIZONTAL PROG DELAY | ++----+----+-----+-----------------------+ +| Y2 | 0 | 33 | 0 | +| Y1 | 0 | 17 | 0 | +| Y0 | 0 | 0 | 0 | ++----+----+-----+-----------------------+ + + +7. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 17 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +8. Clock Region Cell Placement per Global Clock: Region X1Y2 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 33 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y26 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2} +#endgroup diff --git a/out/zedboard/led_counter/Output/route/reports/post_imp_drc.rpt b/out/zedboard/led_counter/Output/route/reports/post_imp_drc.rpt new file mode 100644 index 0000000..f9cd67c --- /dev/null +++ b/out/zedboard/led_counter/Output/route/reports/post_imp_drc.rpt @@ -0,0 +1,78 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:51:01 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_drc -file ./../out/zedboard/led_counter/Output/route/reports/post_imp_drc.rpt +| Design : top +| Device : xc7z020clg484-1 +| Speed File : -1 +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 6 ++-------------+------------------+-------------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-------------+------------------+-------------------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| PDRC-153 | Warning | Gated clock check | 1 | +| PLHOLDVIO-2 | Warning | Non-Optimal connections which could lead to hold violations | 1 | +| PLIO-3 | Warning | Placement Constraints Check for IO constraints | 1 | +| ZPS7-1 | Warning | PS7 block required | 1 | ++-------------+------------------+-------------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +8 out of 18 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[10], led[11], led[12], led[13], led[14], led[15], led[8], led[9]. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +8 out of 18 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[10], led[11], led[12], led[13], led[14], led[15], led[8], led[9]. +Related violations: + +PDRC-153#1 Warning +Gated clock check +Net gen_clkF_LED_PIPE_refresh_a1/CLK is a gated clock net sourced by a combinational pin gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2/O, cell gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PLHOLDVIO-2#1 Warning +Non-Optimal connections which could lead to hold violations +A LUT gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_Leds_a0[15]_i_2 is driving clock pin of 16 cells. This could lead to large hold time violations. Involved cells are: +LED_PIPE_Leds_a0_reg[0], LED_PIPE_Leds_a0_reg[10], +LED_PIPE_Leds_a0_reg[11], LED_PIPE_Leds_a0_reg[12], +LED_PIPE_Leds_a0_reg[13], LED_PIPE_Leds_a0_reg[14], +LED_PIPE_Leds_a0_reg[15], LED_PIPE_Leds_a0_reg[1], LED_PIPE_Leds_a0_reg[2], +LED_PIPE_Leds_a0_reg[3], LED_PIPE_Leds_a0_reg[4], LED_PIPE_Leds_a0_reg[5], +LED_PIPE_Leds_a0_reg[6], LED_PIPE_Leds_a0_reg[7], LED_PIPE_Leds_a0_reg[8] + (the first 15 of 16 listed) +Related violations: + +PLIO-3#1 Warning +Placement Constraints Check for IO constraints +Partially locked IO Bus is found. Following components of the IO Bus led[15:0] are not locked: led[15] led[14] led[13] led[12] led[11] led[10] led[9] led[8] +Related violations: + +ZPS7-1#1 Warning +PS7 block required +The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +Related violations: + + diff --git a/out/zedboard/led_counter/Output/route/reports/post_route_power.rpt b/out/zedboard/led_counter/Output/route/reports/post_route_power.rpt new file mode 100644 index 0000000..d8918a1 --- /dev/null +++ b/out/zedboard/led_counter/Output/route/reports/post_route_power.rpt @@ -0,0 +1,153 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:50:52 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_power -file ./../out/zedboard/led_counter/Output/route/reports/post_route_power.rpt +| Design : top +| Device : xc7z020clg484-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------ + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.129 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.021 | +| Device Static (W) | 0.108 | +| Effective TJA (C/W) | 11.5 | +| Max Ambient (C) | 83.5 | +| Junction Temperature (C) | 26.5 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.002 | 3 | --- | --- | +| Slice Logic | <0.001 | 102 | --- | --- | +| LUT as Logic | <0.001 | 19 | 53200 | 0.04 | +| CARRY4 | <0.001 | 12 | 13300 | 0.09 | +| Register | <0.001 | 66 | 106400 | 0.06 | +| Others | 0.000 | 4 | --- | --- | +| Signals | <0.001 | 124 | --- | --- | +| I/O | 0.019 | 18 | 200 | 9.00 | +| Static Power | 0.108 | | | | +| Total | 0.129 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.010 | 0.002 | 0.007 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.011 | 0.001 | 0.010 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.006 | 0.005 | 0.001 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccpint | 1.000 | 0.016 | 0.000 | 0.016 | NA | Unspecified | NA | +| Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | NA | Unspecified | NA | +| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | NA | Unspecified | NA | +| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 11.5 | +| Airflow (LFM) | 250 | +| Heat Sink | none | +| ThetaSA (C/W) | 0.0 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 8to11 (8 to 11 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ +| clk | clk | 10.0 | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------+-----------+ +| Name | Power (W) | ++------+-----------+ +| top | 0.021 | ++------+-----------+ + + diff --git a/out/zedboard/led_counter/Output/route/reports/post_route_timing.rpt b/out/zedboard/led_counter/Output/route/reports/post_route_timing.rpt new file mode 100644 index 0000000..6639eda --- /dev/null +++ b/out/zedboard/led_counter/Output/route/reports/post_route_timing.rpt @@ -0,0 +1,119 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:50:51 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing -sort_by group -max_paths 100 -path_type summary -file ./../out/zedboard/led_counter/Output/route/reports/post_route_timing.rpt +| Design : top +| Device : 7z020-clg484 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +--------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Startpoint Endpoint Slack(ns) +---------------------------------------------------------------------------- +LED_PIPE_count1_a1_reg[2]/C gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + 0.166 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[17]/R 4.442 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[18]/R 4.442 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[19]/R 4.442 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[20]/R 4.442 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[10]/R 4.559 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[11]/R 4.559 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[12]/R 4.559 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[9]/R 4.559 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[1]/R 4.826 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[2]/R 4.826 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[3]/R 4.826 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[4]/R 4.826 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[21]/R 4.838 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[22]/R 4.838 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[23]/R 4.838 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[24]/R 4.838 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[5]/R 5.111 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[6]/R 5.111 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[7]/R 5.111 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[8]/R 5.111 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[29]/R 5.151 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[30]/R 5.151 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[31]/R 5.151 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[0]/R 5.206 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[25]/R 5.289 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[26]/R 5.289 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[27]/R 5.289 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[28]/R 5.289 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[13]/R 5.593 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[14]/R 5.593 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[15]/R 5.593 +LED_PIPE_count1_a1_reg[20]/C LED_PIPE_count1_a1_reg[16]/R 5.593 +reset LED_PIPE_Leds_a0_reg[10]/R 7.105 +reset LED_PIPE_Leds_a0_reg[11]/R 7.105 +reset LED_PIPE_Leds_a0_reg[12]/R 7.105 +reset LED_PIPE_Leds_a0_reg[9]/R 7.105 +LED_PIPE_Leds_a0_reg[0]/C led_reg[0]/D 7.169 +LED_PIPE_Leds_a0_reg[6]/C led_reg[6]/D 7.193 +reset LED_PIPE_Leds_a0_reg[13]/R 7.195 +reset LED_PIPE_Leds_a0_reg[14]/R 7.195 +reset LED_PIPE_Leds_a0_reg[15]/R 7.195 +reset LED_PIPE_Leds_a0_reg[1]/R 7.255 +reset LED_PIPE_Leds_a0_reg[2]/R 7.255 +reset LED_PIPE_Leds_a0_reg[3]/R 7.255 +reset LED_PIPE_Leds_a0_reg[4]/R 7.255 +reset LED_PIPE_Leds_a0_reg[0]/S 7.260 +LED_PIPE_Leds_a0_reg[5]/C led_reg[5]/D 7.265 +LED_PIPE_Leds_a0_reg[7]/C led_reg[7]/D 7.280 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[30]/D 7.305 +LED_PIPE_Leds_a0_reg[8]/C led_reg[8]/D 7.312 +LED_PIPE_Leds_a0_reg[9]/C led_reg[9]/D 7.326 +reset LED_PIPE_Leds_a0_reg[5]/R 7.371 +reset LED_PIPE_Leds_a0_reg[6]/R 7.371 +reset LED_PIPE_Leds_a0_reg[7]/R 7.371 +reset LED_PIPE_Leds_a0_reg[8]/R 7.371 +LED_PIPE_Leds_a0_reg[2]/C led_reg[2]/D 7.375 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[31]/D 7.386 +LED_PIPE_Leds_a0_reg[1]/C led_reg[1]/D 7.387 +LED_PIPE_Leds_a0_reg[3]/C led_reg[3]/D 7.400 +LED_PIPE_Leds_a0_reg[4]/C led_reg[4]/D 7.402 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[29]/D 7.410 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[26]/D 7.422 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[28]/D 7.428 +LED_PIPE_Leds_a0_reg[13]/C led_reg[13]/D 7.442 +LED_PIPE_Leds_a0_reg[14]/C led_reg[14]/D 7.443 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[27]/D 7.503 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[25]/D 7.527 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[22]/D 7.539 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[24]/D 7.545 +LED_PIPE_Leds_a0_reg[8]/C LED_PIPE_Leds_a0_reg[10]/D 7.594 +LED_PIPE_Leds_a0_reg[15]/C led_reg[15]/D 7.600 +reset LED_PIPE_rst1_a1_reg/D 7.612 +LED_PIPE_Leds_a0_reg[8]/C LED_PIPE_Leds_a0_reg[12]/D 7.615 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[23]/D 7.620 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[21]/D 7.644 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[18]/D 7.657 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[20]/D 7.663 +LED_PIPE_Leds_a0_reg[8]/C LED_PIPE_Leds_a0_reg[11]/D 7.689 +LED_PIPE_Leds_a0_reg[8]/C LED_PIPE_Leds_a0_reg[9]/D 7.705 +LED_PIPE_Leds_a0_reg[8]/C LED_PIPE_Leds_a0_reg[14]/D 7.708 +LED_PIPE_Leds_a0_reg[12]/C led_reg[12]/D 7.735 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[19]/D 7.738 +LED_PIPE_Leds_a0_reg[10]/C led_reg[10]/D 7.745 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[17]/D 7.762 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[14]/D 7.774 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[16]/D 7.780 +LED_PIPE_Leds_a0_reg[8]/C LED_PIPE_Leds_a0_reg[15]/D 7.803 +LED_PIPE_Leds_a0_reg[11]/C led_reg[11]/D 7.813 +LED_PIPE_Leds_a0_reg[8]/C LED_PIPE_Leds_a0_reg[13]/D 7.819 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[15]/D 7.855 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[13]/D 7.879 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[10]/D 7.891 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[12]/D 7.897 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[6]/D 7.899 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[8]/D 7.920 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[11]/D 7.972 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[6]/D 7.975 +LED_PIPE_count1_a1_reg[2]/C LED_PIPE_count1_a1_reg[8]/D 7.981 +LED_PIPE_Leds_a0_reg[0]/C LED_PIPE_Leds_a0_reg[7]/D 7.994 + + + diff --git a/out/zedboard/led_counter/Output/route/reports/post_route_timing_summary.rpt b/out/zedboard/led_counter/Output/route/reports/post_route_timing_summary.rpt new file mode 100644 index 0000000..9629599 --- /dev/null +++ b/out/zedboard/led_counter/Output/route/reports/post_route_timing_summary.rpt @@ -0,0 +1,342 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:50:50 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/zedboard/led_counter/Output/route/reports/post_route_timing_summary.rpt +| Design : top +| Device : 7z020-clg484 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +------------------------------------------------------------------------------------------------------------------------------ + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.166 0.000 0 114 0.056 0.000 0 114 4.500 0.000 0 67 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.166 0.000 0 114 0.056 0.000 0 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.166ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.056ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.166ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 4.807ns (logic 2.295ns (47.745%) route 2.512ns (52.255%)) + Logic Levels: 7 (CARRY4=4 LUT4=2 LUT6=1) + Clock Path Skew: 0.008ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 5.346ns = ( 10.346 - 5.000 ) + Source Clock Delay (SCD): 5.631ns + Clock Pessimism Removal (CPR): 0.294ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + Y9 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_IBUF_inst/O + net (fo=2, routed) 2.171 3.661 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 3.762 r clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.869 5.631 clk_IBUF_BUFG + SLICE_X112Y98 FDRE r LED_PIPE_count1_a1_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y98 FDRE (Prop_fdre_C_Q) 0.518 6.149 r LED_PIPE_count1_a1_reg[2]/Q + net (fo=2, routed) 0.552 6.701 LED_PIPE_count1_a1[2] + SLICE_X112Y98 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.657 7.358 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 7.358 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + SLICE_X112Y99 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 7.475 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.001 7.476 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + SLICE_X112Y100 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 7.593 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 7.593 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + SLICE_X112Y101 CARRY4 (Prop_carry4_CI_O[3]) + 0.331 7.924 f LED_PIPE_count1_a1_reg[16]_i_1/O[3] + net (fo=2, routed) 1.102 9.026 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_0[3] + SLICE_X113Y103 LUT6 (Prop_lut6_I3_O) 0.307 9.333 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, routed) 0.573 9.906 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + SLICE_X113Y103 LUT4 (Prop_lut4_I2_O) 0.124 10.030 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, routed) 0.284 10.314 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + SLICE_X111Y103 LUT4 (Prop_lut4_I0_O) 0.124 10.438 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, routed) 0.000 10.438 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + SLICE_X111Y103 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + Y9 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + Y9 IBUF (Prop_ibuf_I_O) 1.420 6.420 f clk_IBUF_inst/O + net (fo=2, routed) 1.972 8.392 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 8.483 f clk_IBUF_BUFG_inst/O + net (fo=50, routed) 1.863 10.346 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + SLICE_X111Y103 LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.294 10.639 + clock uncertainty -0.035 10.604 + ------------------------------------------------------------------- + required time 10.604 + arrival time -10.438 + ------------------------------------------------------------------- + slack 0.166 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.056ns (arrival time - required time) + Source: LED_PIPE_count1_a1_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: LED_PIPE_count1_a1_reg[9]/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 0.539ns (logic 0.413ns (76.598%) route 0.126ns (23.402%)) + Logic Levels: 3 (CARRY4=3) + Clock Path Skew: 0.353ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.191ns + Source Clock Delay (SCD): 1.586ns + Clock Pessimism Removal (CPR): 0.252ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + Y9 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_IBUF_inst/O + net (fo=2, routed) 0.663 0.921 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.947 r clk_IBUF_BUFG_inst/O + net (fo=50, routed) 0.639 1.586 clk_IBUF_BUFG + SLICE_X112Y98 FDRE r LED_PIPE_count1_a1_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y98 FDRE (Prop_fdre_C_Q) 0.164 1.750 r LED_PIPE_count1_a1_reg[3]/Q + net (fo=2, routed) 0.125 1.875 LED_PIPE_count1_a1[3] + SLICE_X112Y98 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.156 2.031 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.000 2.031 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + SLICE_X112Y99 CARRY4 (Prop_carry4_CI_CO[3]) + 0.040 2.071 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.001 2.072 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + SLICE_X112Y100 CARRY4 (Prop_carry4_CI_O[0]) + 0.053 2.125 r LED_PIPE_count1_a1_reg[12]_i_1/O[0] + net (fo=2, routed) 0.000 2.125 LED_PIPE_count1_a1_reg[12]_i_1_n_7 + SLICE_X112Y100 FDRE r LED_PIPE_count1_a1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + Y9 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_IBUF_inst/O + net (fo=2, routed) 0.719 1.165 clk_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.194 r clk_IBUF_BUFG_inst/O + net (fo=50, routed) 0.997 2.191 clk_IBUF_BUFG + SLICE_X112Y100 FDRE r LED_PIPE_count1_a1_reg[9]/C + clock pessimism -0.252 1.939 + SLICE_X112Y100 FDRE (Hold_fdre_C_D) 0.130 2.069 LED_PIPE_count1_a1_reg[9] + ------------------------------------------------------------------- + required time -2.069 + arrival time 2.125 + ------------------------------------------------------------------- + slack 0.056 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 clk_IBUF_BUFG_inst/I +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X110Y102 LED_PIPE_Leds_a0_reg[10]/C +High Pulse Width Fast FDSE/C n/a 0.500 5.000 4.500 SLICE_X111Y100 LED_PIPE_Leds_a0_reg[0]/C + + + diff --git a/out/zedboard/led_counter/Output/route/reports/post_route_util.rpt b/out/zedboard/led_counter/Output/route/reports/post_route_util.rpt new file mode 100644 index 0000000..cf733cb --- /dev/null +++ b/out/zedboard/led_counter/Output/route/reports/post_route_util.rpt @@ -0,0 +1,207 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:50:51 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_utilization -file ./../out/zedboard/led_counter/Output/route/reports/post_route_util.rpt +| Design : top +| Device : 7z020clg484-1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 19 | 0 | 53200 | 0.04 | +| LUT as Logic | 19 | 0 | 53200 | 0.04 | +| LUT as Memory | 0 | 0 | 17400 | 0.00 | +| Slice Registers | 66 | 0 | 106400 | 0.06 | +| Register as Flip Flop | 65 | 0 | 106400 | 0.06 | +| Register as Latch | 1 | 0 | 106400 | <0.01 | +| F7 Muxes | 0 | 0 | 26600 | 0.00 | +| F8 Muxes | 0 | 0 | 13300 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 1 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 64 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------------------------+------+-------+-----------+-------+ +| Slice | 27 | 0 | 13300 | 0.20 | +| SLICEL | 19 | 0 | | | +| SLICEM | 8 | 0 | | | +| LUT as Logic | 19 | 0 | 53200 | 0.04 | +| using O5 output only | 0 | | | | +| using O6 output only | 18 | | | | +| using O5 and O6 | 1 | | | | +| LUT as Memory | 0 | 0 | 17400 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 66 | 0 | 106400 | 0.06 | +| Register driven from within the Slice | 49 | | | | +| Register driven from outside the Slice | 17 | | | | +| LUT in front of the register is unused | 16 | | | | +| LUT in front of the register is used | 1 | | | | +| Unique Control Sets | 4 | | 13300 | 0.03 | ++--------------------------------------------+------+-------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 140 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 | +| RAMB18 | 0 | 0 | 280 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 220 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 18 | 10 | 200 | 9.00 | +| IOB Master Pads | 7 | | | | +| IOB Slave Pads | 8 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 4 | 0.00 | +| PHASER_REF | 0 | 0 | 4 | 0.00 | +| OUT_FIFO | 0 | 0 | 16 | 0.00 | +| IN_FIFO | 0 | 0 | 16 | 0.00 | +| IDELAYCTRL | 0 | 0 | 4 | 0.00 | +| IBUFDS | 0 | 0 | 192 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 | +| ILOGIC | 0 | 0 | 200 | 0.00 | +| OLOGIC | 0 | 0 | 200 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 16 | 0.00 | +| MMCME2_ADV | 0 | 0 | 4 | 0.00 | +| PLLE2_ADV | 0 | 0 | 4 | 0.00 | +| BUFMRCE | 0 | 0 | 8 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 16 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 64 | Flop & Latch | +| OBUF | 16 | IO | +| CARRY4 | 12 | CarryLogic | +| LUT6 | 8 | LUT | +| LUT4 | 6 | LUT | +| LUT5 | 3 | LUT | +| LUT1 | 2 | LUT | +| IBUF | 2 | IO | +| LUT2 | 1 | LUT | +| LDCE | 1 | Flop & Latch | +| FDSE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/out/zedboard/led_counter/Output/syn/post_synth.dcp b/out/zedboard/led_counter/Output/syn/post_synth.dcp new file mode 100644 index 0000000..d529cd7 Binary files /dev/null and b/out/zedboard/led_counter/Output/syn/post_synth.dcp differ diff --git a/out/zedboard/led_counter/Output/syn/reports/post_synth_power.rpt b/out/zedboard/led_counter/Output/syn/reports/post_synth_power.rpt new file mode 100644 index 0000000..569af87 --- /dev/null +++ b/out/zedboard/led_counter/Output/syn/reports/post_synth_power.rpt @@ -0,0 +1,153 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:50:05 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_power -file ./../out/zedboard/led_counter/Output/syn/reports/post_synth_power.rpt +| Design : top +| Device : xc7z020clg484-1 +| Design State : synthesized +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.133 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.025 | +| Device Static (W) | 0.108 | +| Effective TJA (C/W) | 11.5 | +| Max Ambient (C) | 83.5 | +| Junction Temperature (C) | 26.5 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.002 | 3 | --- | --- | +| Slice Logic | <0.001 | 102 | --- | --- | +| LUT as Logic | <0.001 | 19 | 53200 | 0.04 | +| CARRY4 | <0.001 | 12 | 13300 | 0.09 | +| Register | <0.001 | 66 | 106400 | 0.06 | +| Others | 0.000 | 4 | --- | --- | +| Signals | <0.001 | 127 | --- | --- | +| I/O | 0.023 | 18 | 200 | 9.00 | +| Static Power | 0.108 | | | | +| Total | 0.133 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.010 | 0.002 | 0.007 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.011 | 0.001 | 0.010 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.007 | 0.006 | 0.001 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.002 | 0.001 | 0.001 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccpint | 1.000 | 0.016 | 0.000 | 0.016 | NA | Unspecified | NA | +| Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | NA | Unspecified | NA | +| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | NA | Unspecified | NA | +| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | Low | Design is synthesized | Accuracy of the tool is not optimal until design is fully placed and routed | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 11.5 | +| Airflow (LFM) | 250 | +| Heat Sink | none | +| ThetaSA (C/W) | 0.0 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 8to11 (8 to 11 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ +| clk | clk | 10.0 | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------+-----------+ +| Name | Power (W) | ++------+-----------+ +| top | 0.025 | ++------+-----------+ + + diff --git a/out/zedboard/led_counter/Output/syn/reports/post_synth_timing_summary.rpt b/out/zedboard/led_counter/Output/syn/reports/post_synth_timing_summary.rpt new file mode 100644 index 0000000..023561b --- /dev/null +++ b/out/zedboard/led_counter/Output/syn/reports/post_synth_timing_summary.rpt @@ -0,0 +1,346 @@ +Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020 +| Date : Sat Oct 30 02:50:05 2021 +| Host : DESKTOP-D80LUPK running 64-bit Ubuntu 20.04.3 LTS +| Command : report_timing_summary -file ./../out/zedboard/led_counter/Output/syn/reports/post_synth_timing_summary.rpt +| Design : top +| Device : 7z020-clg484 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +---------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (16) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (16) +-------------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 0.000 0.000 0 114 -1.063 -15.363 17 114 4.500 0.000 0 67 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 0.000 0.000 0 114 -1.063 -15.363 17 114 4.500 0.000 0 67 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk + To Clock: clk + +Setup : 0 Failing Endpoints, Worst Slack 0.000ns, Total Violation 0.000ns +Hold : 17 Failing Endpoints, Worst Slack -1.063ns, Total Violation -15.363ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.000ns (required time - arrival time) + Source: LED_PIPE_count1_a1_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + (negative level-sensitive latch clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (clk fall@5.000ns - clk rise@0.000ns) + Data Path Delay: 5.647ns (logic 2.291ns (40.570%) route 3.356ns (59.430%)) + Logic Levels: 8 (CARRY4=5 LUT4=2 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.709ns = ( 7.709 - 5.000 ) + Source Clock Delay (SCD): 2.975ns + Clock Pessimism Removal (CPR): 0.121ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + Time Borrowing: + Nominal pulse width: 5.000ns + Library setup time: 0.051ns + Computed max time borrow: 5.051ns + Time borrowed from endpoint: 0.827ns + Open edge uncertainty: -0.035ns + Time given to startpoint: 0.792ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + Y9 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_IBUF_inst/O + net (fo=2, unplaced) 0.800 2.290 clk_IBUF + BUFG (Prop_bufg_I_O) 0.101 2.391 r clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.584 2.975 clk_IBUF_BUFG + FDRE r LED_PIPE_count1_a1_reg[2]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 3.453 r LED_PIPE_count1_a1_reg[2]/Q + net (fo=2, unplaced) 0.871 4.324 LED_PIPE_count1_a1[2] + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.657 4.981 r LED_PIPE_count1_a1_reg[4]_i_1/CO[3] + net (fo=1, unplaced) 0.009 4.990 LED_PIPE_count1_a1_reg[4]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 5.107 r LED_PIPE_count1_a1_reg[8]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.107 LED_PIPE_count1_a1_reg[8]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 5.224 r LED_PIPE_count1_a1_reg[12]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.224 LED_PIPE_count1_a1_reg[12]_i_1_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 5.341 r LED_PIPE_count1_a1_reg[16]_i_1/CO[3] + net (fo=1, unplaced) 0.000 5.341 LED_PIPE_count1_a1_reg[16]_i_1_n_0 + CARRY4 (Prop_carry4_CI_O[2]) + 0.256 5.597 r LED_PIPE_count1_a1_reg[20]_i_1/O[2] + net (fo=2, unplaced) 1.125 6.722 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_1[2] + LUT6 (Prop_lut6_I0_O) 0.301 7.023 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8/O + net (fo=1, unplaced) 0.902 7.925 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_8_n_0 + LUT4 (Prop_lut4_I2_O) 0.124 8.049 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3/O + net (fo=1, unplaced) 0.449 8.498 gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_3_n_0 + LUT4 (Prop_lut4_I0_O) 0.124 8.622 r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg_i_1/O + net (fo=1, unplaced) 0.000 8.622 gen_clkF_LED_PIPE_refresh_a1/LED_PIPE_refresh_a0 + LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk fall edge) 5.000 5.000 f + Y9 0.000 5.000 f clk (IN) + net (fo=0) 0.000 5.000 clk + Y9 IBUF (Prop_ibuf_I_O) 1.420 6.420 f clk_IBUF_inst/O + net (fo=2, unplaced) 0.760 7.179 clk_IBUF + BUFG (Prop_bufg_I_O) 0.091 7.270 f clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.439 7.709 gen_clkF_LED_PIPE_refresh_a1/clk_IBUF_BUFG + LDCE r gen_clkF_LED_PIPE_refresh_a1/latched_clk_en_reg/G (IS_INVERTED) + clock pessimism 0.121 7.830 + clock uncertainty -0.035 7.795 + time borrowed 0.827 8.622 + ------------------------------------------------------------------- + required time 8.622 + arrival time -8.622 + ------------------------------------------------------------------- + slack 0.000 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -1.063ns (arrival time - required time) + Source: reset + (input port clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: LED_PIPE_rst1_a1_reg/D + (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clk + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns) + Data Path Delay: 2.176ns (logic 1.416ns (65.084%) route 0.760ns (34.916%)) + Logic Levels: 1 (IBUF=1) + Input Delay: 0.000ns + Clock Path Skew: 2.975ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.975ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk rise edge) 0.000 0.000 r + input delay 0.000 0.000 + F22 0.000 0.000 r reset (IN) + net (fo=0) 0.000 0.000 reset + F22 IBUF (Prop_ibuf_I_O) 1.416 1.416 r reset_IBUF_inst/O + net (fo=17, unplaced) 0.760 2.176 reset_IBUF + FDRE r LED_PIPE_rst1_a1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk rise edge) 0.000 0.000 r + Y9 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 clk + Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_IBUF_inst/O + net (fo=2, unplaced) 0.800 2.290 clk_IBUF + BUFG (Prop_bufg_I_O) 0.101 2.391 r clk_IBUF_BUFG_inst/O + net (fo=50, unplaced) 0.584 2.975 clk_IBUF_BUFG + FDRE r LED_PIPE_rst1_a1_reg/C + clock pessimism 0.000 2.975 + clock uncertainty 0.035 3.010 + FDRE (Hold_fdre_C_D) 0.228 3.238 LED_PIPE_rst1_a1_reg + ------------------------------------------------------------------- + required time -3.238 + arrival time 2.176 + ------------------------------------------------------------------- + slack -1.063 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 clk_IBUF_BUFG_inst/I +Low Pulse Width Slow FDSE/C n/a 0.500 5.000 4.500 LED_PIPE_Leds_a0_reg[0]/C +High Pulse Width Slow FDSE/C n/a 0.500 5.000 4.500 LED_PIPE_Leds_a0_reg[0]/C + + + diff --git a/fpga/run.sh b/run.sh old mode 100755 new mode 100644 similarity index 55% rename from fpga/run.sh rename to run.sh index bf4015a..d7f25c0 --- a/fpga/run.sh +++ b/run.sh @@ -1,11 +1,10 @@ -# shell script to run complete FPGA flow +shell script to run complete FPGA flow echo "================================================" echo "WELCOME TO VIRTUAL FPGA LAB" echo "================================================" -#path=$(pwd) +# path=$(pwd) shell_path=$(cd "$(dirname "$0")" && pwd) - echo "================================================" echo "GOING TO THE REQUIRED DIRECTORY" echo "================================================" @@ -16,37 +15,60 @@ read -p "WHICH FILE YOU WANT TO UPLOAD ON VIVADO : " filename echo "================================================" echo "================================================" -echo "WHICH BOARD YOU WANT TO USE (basys3, edge_artix-7, zedboard)" +echo "WHICH BOARD YOU WANT TO USE (basys3, edge_artix-7, zedboard, nexys_A7_100T)" read -p "IF YOU HAVE A DIFFERENT BOARD , WRITE THE PART NO: " board echo "================================================" + if [ "$board" == "basys3" ]; then partname="xc7a35tcpg236-1" - cons_name="$shell_path/constraints/fpga_lab_constr_$board.xdc" + cons_name="$shell_path/fpga/constraints/fpga_lab_constr_$board.xdc" elif [ "$board" == "edge_artix-7" ]; then partname="xc7a35tftg256-1" - cons_name="$shell_path/constraints/fpga_lab_constr_$board.xdc" + cons_name="$shell_path/fpga/constraints/fpga_lab_constr_$board.xdc" elif [ "$board" == "zedboard" ]; then partname="xc7z020clg484-1" - cons_name="$shell_path/constraints/fpga_lab_constr_$board.xdc" + cons_name="$shell_path/fpga/constraints/fpga_lab_constr_$board.xdc" + +elif [ "$board" == "nexys_A7_100T" ]; then + partname="xc7a100tcsg324-1" + cons_name="$shell_path/fpga/constraints/fpga_lab_constr_$board.xdc" else partname=$board cons_name="${filename}_$board.xdc" fi -echo "================================================" -echo "DELETING THE PREVIOUS BUILD FOLDER" -rm -R out_"${filename}_$partname" -echo "================================================" +cd examples +# out=out_"${filename}_$partname" +if [ -d $out_"${filename}_$partname" ]; then + echo "================================================" + echo "DELETING THE PREVIOUS BUILD FOLDER" + rm -R out_"${filename}_$partname" + echo "================================================" +fi + +if [ -d out/$filename/$partname ]; then + echo "================================================" + echo "DELETING THE PREVIOUS BUILD FOLDER" + rm -R out/$filename/$partname + echo "================================================" +fi + +if [ -d ../out/$filename/$partname ]; then + echo "================================================" + echo "DELETING THE PREVIOUS BUILD FOLDER" + rm -R ../out/$filename/$partname + echo "================================================" +fi # Give the respective tlv file as top. For eg, for counter test case give it as counter.tlv echo "================================================" echo "PROCESSING .TLV USING SANDPIPER(TM) SaaS EDITION." echo "------------------------------------------------" -sandpiper-saas -i "$filename".tlv -o "$filename".v --iArgs --default_includes --outdir=out_"${filename}_$partname" +sandpiper-saas -i "$filename".tlv -o "$filename".v --iArgs --default_includes --outdir=../out/$board/$filename/Dependencies echo "================================================" echo "=================================================" @@ -62,17 +84,21 @@ echo "GENERATING CLOCK CONSTRAINTS" var1=$(expr "scale=3; $clock_rate/1" | bc) var2=$(expr "scale=3; $clock_rate/2" | bc) -echo "create_clock -period $var1 -name clk -waveform {0.000 $var2} [get_ports clk]" >>./out_"${filename}_$partname"/clock_constraints.xdc -echo "set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset]" >>./out_"${filename}_$partname"/clock_constraints.xdc -echo "set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset]" >>./out_"${filename}_$partname"/clock_constraints.xdc +# echo "create_clock -period $var1 -name clk -waveform {0.000 $var2} [get_ports clk]" >>./out_"${filename}_$partname"/clock_constraints.xdc +# echo "set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset]" >>./out_"${filename}_$partname"/clock_constraints.xdc +# echo "set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset]" >>./out_"${filename}_$partname"/clock_constraints.xdc +echo "create_clock -period $var1 -name clk -waveform {0.000 $var2} [get_ports clk]" >>./../out/$board/$filename/Dependencies/clock_constraints.xdc +echo "set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset]" >>./../out/$board/$filename/Dependencies/clock_constraints.xdc +echo "set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset]" >>./../out/$board/$filename/Dependencies/clock_constraints.xdc echo "===================================================" ## CREATING A COPY OF INPUT VARIABLES IN THE TCL FILE -echo "$filename" >>tmp.txt -echo "$partname" >>tmp.txt -echo "$cons_name" >>tmp.txt +echo "$filename" >>tmp.txt +echo "$partname" >>tmp.txt +echo "$cons_name" >>tmp.txt echo "$shell_path" >>tmp.txt +echo "$board" >>tmp.txt path=$PWD echo "================================================" @@ -82,12 +108,13 @@ echo "================================================" echo "SOURCING VIVADO" echo "================================================" -cd vivado +cd Vivado source Vivado/2020.2/settings64.sh cd cd "$path" -rm vivado* -rm usage_* -vivado -mode batch -source "$shell_path"/run.tcl + +vivado -mode batch -source "$shell_path"/fpga/run.tcl rm -f tmp.txt +rm vivado* +rm usage_*