From 4e7740fa52002b7c5878131bfe8081ebfb5c2d36 Mon Sep 17 00:00:00 2001 From: Bryan Perdrizat Date: Wed, 30 Oct 2024 18:10:45 +0100 Subject: [PATCH] fix: use PAGEMASK for perfect TLB (#76) The perfect TLB access are set to a 0xFFF.. Addresses, but this requires a page number instead, therefore a shift --- components/MMU/MMUImpl.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/components/MMU/MMUImpl.cpp b/components/MMU/MMUImpl.cpp index 7546e731..f6db841b 100644 --- a/components/MMU/MMUImpl.cpp +++ b/components/MMU/MMUImpl.cpp @@ -189,7 +189,7 @@ bool MMUComponent::cfg_mmu(index_t anIndex) theMMU->setupAddressSpaceSizesAndGranules(); DBG_Assert(theMMU->Gran0->getlogKBSize() == 12, (<< "TG0 has non-4KB size - unsupported")); DBG_Assert(theMMU->Gran1->getlogKBSize() == 12, (<< "TG1 has non-4KB size - unsupported")); - PAGEMASK = ~((1 << theMMU->Gran0->getlogKBSize()) - 1); + PAGEMASK = ~((1ULL << theMMU->Gran0->getlogKBSize()) - 1); ret = true; } @@ -279,6 +279,10 @@ void MMUComponent::initialize() mmu_is_init = false; theInstrTLB.resize(cfg.iTLBSize); theDataTLB.resize(cfg.dTLBSize); + + if (cfg.PerfectTLB) { + PAGEMASK = ~((1ULL << 12) - 1); + } } void MMUComponent::finalize() {}