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Description
LDR instruction with target register 31 should be regarded as zero register and discard the result. It is considered as SP now.
Steps to Reproduce
Run data caching image with 2 cores
After some time an instruction LDR xzr, ...
Expected Behavior
Load should be issued but the result should be discarded.
Actual Behavior
it will execute and save the result to SP and trigger validation failure
The text was updated successfully, but these errors were encountered:
Description
LDR instruction with target register 31 should be regarded as zero register and discard the result. It is considered as SP now.
Steps to Reproduce
Run data caching image with 2 cores
After some time an instruction LDR xzr, ...
Expected Behavior
Load should be issued but the result should be discarded.
Actual Behavior
it will execute and save the result to SP and trigger validation failure
The text was updated successfully, but these errors were encountered: