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Memory decoding #89

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BugraEryilmaz opened this issue Nov 26, 2024 · 2 comments
Open

Memory decoding #89

BugraEryilmaz opened this issue Nov 26, 2024 · 2 comments
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Description
There are a couple problematic cases for memory decoding. Namely prefetch instruction with register offset and atomic load stores (ldxr)

Expected Behavior
Prefetch instruction should be decoded as nop and ldxr register should be decoded with blackbox as it is not implemented.

Actual Behavior
They are decoded as normal load store instructions.
@BugraEryilmaz BugraEryilmaz self-assigned this Nov 26, 2024
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Fix: c72dcb5

branylagaffe pushed a commit that referenced this issue Nov 28, 2024
@xusine @branylagaffe
fix: LDXR decoding + drop prefetch #89
8bb9cdb 
*Description*
There are a couple problematic cases for memory decoding. Namely
prefetch instruction with register offset and atomic load stores (ldxr)

*Expected Behavior*
Prefetch instruction should be decoded as nop and ldxr register should
be decoded with blackbox as it is not implemented.

*Actual Behavior*
They are decoded as normal load store instructions.
@BugraEryilmaz
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The LDTR instruction was not decoded properly. It is a normal load with a signed offset, so everything is already implemented for it; we just need to check the opcode to set the offset type properly. (same for STTR btw)
Fix: 8e416b4

Deep note: What is the purpose of this instruction? ARM manual says it allows higher exception levels to read lower exception level data. But a normal load cannot do that?

branylagaffe pushed a commit that referenced this issue Dec 18, 2024
@BugraEryilmaz @branylagaffe
fix: LDXR decoding + drop prefetch #89
5f42f1d 
*Description*
There are a couple problematic cases for memory decoding. Namely
prefetch instruction with register offset and atomic load stores (ldxr)

*Expected Behavior*
Prefetch instruction should be decoded as nop and ldxr register should
be decoded with blackbox as it is not implemented.

*Actual Behavior*
They are decoded as normal load store instructions.
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