Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Router completed with failures #1

Open
jaschengWoodpeckerx opened this issue Sep 27, 2023 · 3 comments
Open

Router completed with failures #1

jaschengWoodpeckerx opened this issue Sep 27, 2023 · 3 comments

Comments

@jaschengWoodpeckerx
Copy link

After successfully completing the previous steps, this error occurs when trying to run make dcp:

ERROR: [Vivado 12-172] File or Directory '/home/centos/xsofs/fpga/src/firesim/../../../repo/aws_fpga/hdk/common/shell_stable/build/checkpoints/from_aws/SH_CL_BB_routed.dcp' does not exist

Please help.

Thanks!

@jaschengWoodpeckerx
Copy link
Author

jaschengWoodpeckerx commented Sep 28, 2023

After looking around, found this link to donwload: https://s3.amazonaws.com/aws-fpga-hdk-resources/hdk/shell_v04261818/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
However, dcp build shows this error:

INFO: [Route 35-77] Router completed with failures. Please check the log file for Critical Warnings and run report_route_status for a summary of routing status.
ERROR: [Constraints 18-1000] Routing results verification failed due to partially-conflicted nets (Up to first 10 of violated nets): WRAPPER_INST/CL/u_dut/top/sim/target/Dut_/u_top/core_with_l2/core/frontend/bpu/predictors/components_1/tables_3/table_banks_0_io_w_req_bits_data_0_tag[4] WRAPPER_INST/CL/u_dut/top/sim/target/Dut_/u_top/core_with_l2/core/frontend/bpu/predictors/components_1/tables_3/table_banks_0_io_w_req_bits_data_0_tag[6]

Vivado version: v2021.2

@goshuh goshuh changed the title xsofs/fpga/src/firesim/../../../repo/aws_fpga/hdk/common/shell_stable/build/checkpoints/from_aws/SH_CL_BB_routed.dcp does not exist Router completed with failures Sep 28, 2023
@goshuh
Copy link
Collaborator

goshuh commented Sep 28, 2023

Hi,

The root cause of this problem is that the XiangShan design is too big to be easily put on the AWS FPGA. You might need to have a look at this, where some high-fanout wires are promoted to use global clock routing resources to mitigate congestion. The magic numbers there are carefully chosen to only include wires that might later cause routing errors. In addition, you may also need to play with various strategies/directives here for synthesis/optimization/placement/routing. My experience is that even a single line of code modification can result in totally different strategies/magic numbers to successfully generate the final bitstream.

Hope this helps!

@jaschengWoodpeckerx
Copy link
Author

Actually I believe the first comment in the issue still stands.
You should provide that file in the repo, or at least specify the instructions to obtain that file. Otherwise, one still cannot run make dcp due to that error.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants