Vitis_Platform_Creation

Vitis™ Platform Creation Tutorials

Vitis Platform Creation Tutorials

What is a Platform

Before going to platform creation, Let's get an initial idea of platform.

Briefly speaking, platform is a package which contains the HPFM（XSA）file and SPFM (software components). When you input the XSA file and software components, Vitis IDE tool will package them together and generate platform XPFM file. where the XSA file is designed and exported from Vivado tool. Software components is prepared by AMD and ready to use for evaluation. Software components customization is also supported with Petalinux if needed.

Platform Creation Example Quick Access

• For first experience of platform, please refer to Vitis Platform Quick Start
• For ZYNQMP device family, please refer to ZCU104 platform tutorial
• For Versal device family, please refer to VCK190 platform tutorial
• For DFX platform, please refer to DFX platform tutorial
• For SOM series, please refer to KV260 platform tutorial
• For PetaLinux customization, please refer to PetaLinux customization

Platform Creation Tutorials

The tutorials under the Vitis Platform Creation category help you learn how to develop an extnsible platform for your own board, or customize the Vitis platform on Xilinx demo boards.

• The Design Tutorials showcase end-to-end workflow for creating the Vitis extensible platforms from scratch for different device families and boards.
• The Feature Tutorials highlight specific features and flows that help develop the platform.

Design Tutorials

Tutorial	Device Family	Board	Platform Type	IDE Flow	Design Target
Versal Platform Creation Quick Start	Versal AI Core	VCK190	Flat	Vivado & Vitis Unified IDE	Highlights: simplest Vitis Platform creation and usage flow. Hardware design: Using Vivado Customizable Example Design tempalte to quick start. Software design: Using `createdts` and Common Image to quick start. Verification: Vector Addition. Note: This design flow is applicable to most AMD demo boards.
Create a Vitis Platform for Custom Versal Boards	Versal AI Core	VCK190	Flat	Vivado & Vitis IDE	Highlights: Platform design flow for custom boards. Hardware design: Using Vivado Customizable Example Design (device part based) to create the hardware and do further customizations. Software design: Using `createdts` and Common Image to quick start. Verification: Vector Addition Note: This tutorial uses VCK190 board as a custom board. The design doesn't use any of its presets.
Versal DFX Platform Creation Tutorial	Versal AI Core	VCK190	DFX	Vivado & Vitis IDE	Highlights: Design flow for Vitis DFX (Dynamic Function eXchange) Platform. Hardware design: Using Vivado Customizable Example Design for DFX platform and doing further customizations. Software design: Using `createdts` and Common Image to quick start. Verification: Vector Addition
Create Vitis Platforms for Zynq UltraScale+ MPSoC	ZYNQ UltraScale+ MPSoC	ZCU104	Flat	Vivado & Vitis IDE	Highlights: Creating a Vitis platform for Zynq UltraScale+ MPSoC from scratch. Hardware design: Creating the hardware design from scratching without any help of Vivado example design templates. Software design: Using `createdts` and Common Image to quick start. Verification: Vector Addition and Vitis-AI
Custom Kria SOM Platform Creation Example	ZYNQ UltraScale+ MPSoC	KV260	Flat	Vivado & Vitis IDE	Highlights: Kria SOM Platform creation and usage flow Hardware design: Creating from scratch Software design: Using Common Image and showing device tree overlay (DTBO) creation flow Verification: Vector Addition and Kria SOM application loading procedure

Feature Tutorials

These tutorials illustrate various platform features and how you can incorporate them into your own custom platforms.

Tutorial	Device Family	Board	Platform Type	IDE Flow	Design Target
Incorporating Stream Interfaces	Generic but using Versal AI Core as example	VCK190	Flat	Vivado & Vitis IDE	Highlights: Adding custom IP into the platform hardware Using AXI Stream IP in platform and kernel
PetaLinux Building and System Customization	ZYNQ UltraScale+ MPSoC and Versal AI Core	ZCU104 and VCK190	Flat	Vivado & Vitis IDE	Highlights: Customize the software components with PetaLinux
Hardware Design Fast Iteration with Vitis Export to Vivado	Versal AI Core	VCK190	Block Design Container	Vivado & Vitis IDE	Highlights: Skipping creating the platform before v++ linking Using Vivado to do design implementation and timing closure Fast iteration for hardware design

Abbreviation

• XSA : Vivado exported archive file that contains hardware information required for Vitis and PetaLinux
• DFX ：Dynamic Functional Exchange
• SOM : System On Module
• DTB : Device Tree Binary
• DTBO : Device Tree Binary Overlay

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