From 6c3ece9c9ef73db5c0e02cc5a41c98f46b86c3e9 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 1 Oct 2021 14:10:19 -0600 Subject: [PATCH 001/320] Documentation: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078 Reviewed-by: Felix Held Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Documentation/RFC/chip.tex | 2 +- Documentation/acpi/devicetree.md | 2 +- Documentation/arch/x86/index.md | 4 ++-- Documentation/conf.py | 2 +- Documentation/contributing/coding_style.md | 2 +- Documentation/contributing/project_ideas.md | 4 ++-- Documentation/drivers/index.md | 2 +- Documentation/flash_tutorial/index.md | 2 +- Documentation/gcov.txt | 2 +- Documentation/getting_started/architecture.md | 4 ++-- Documentation/getting_started/writing_documentation.md | 2 +- Documentation/lib/payloads/fit.md | 2 +- Documentation/lib/timestamp.md | 2 +- Documentation/mainboard/amd/padmelon/padmelon.md | 2 +- Documentation/mainboard/emulation/qemu-aarch64.md | 2 +- Documentation/mainboard/lenovo/Ivy_Bridge_series.md | 2 +- Documentation/mainboard/lenovo/Sandy_Bridge_series.md | 2 +- Documentation/mainboard/lenovo/vboot.md | 2 +- Documentation/mainboard/ocp/tiogapass.md | 2 +- Documentation/mainboard/up/squared/index.md | 6 +++--- Documentation/northbridge/intel/sandybridge/nri.md | 4 ++-- Documentation/northbridge/intel/sandybridge/nri_freq.md | 2 +- .../northbridge/intel/sandybridge/nri_registers.md | 2 +- Documentation/releases/coreboot-4.13-relnotes.md | 2 +- Documentation/releases/coreboot-4.3-relnotes.md | 2 +- Documentation/security/intel/txt.md | 2 +- Documentation/security/smm.md | 4 ++-- Documentation/security/vboot/measured_boot.md | 2 +- Documentation/soc/cavium/cn81xx/index.md | 2 +- Documentation/superio/common/ssdt.md | 4 ++-- Documentation/superio/nuvoton/npcd378.md | 2 +- Documentation/technotes/2020-03-unit-testing-coreboot.md | 2 +- Documentation/tutorial/part1.md | 2 +- Documentation/util.md | 2 +- 34 files changed, 42 insertions(+), 42 deletions(-) diff --git a/Documentation/RFC/chip.tex b/Documentation/RFC/chip.tex index 01f40c1e803..c67109231f9 100644 --- a/Documentation/RFC/chip.tex +++ b/Documentation/RFC/chip.tex @@ -7,7 +7,7 @@ \section{Scope} This document defines how LinuxBIOS programmers can specify chips that -are used, specified, and initalized. The current scope is for superio +are used, specified, and initialized. The current scope is for superio chips, but the architecture should allow for specification of other chips such as southbridges. Multiple chips of same or different type are supported. diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md index 5cbaf152d27..41f59019994 100644 --- a/Documentation/acpi/devicetree.md +++ b/Documentation/acpi/devicetree.md @@ -5,7 +5,7 @@ ACPI exposes a platform-independent interface for operating systems to perform power management and other platform-level functions. Some operating systems also use ACPI to enumerate devices that are not immediately discoverable, such -as those behind I2C or SPI busses (in contrast to PCI). This document discusses +as those behind I2C or SPI buses (in contrast to PCI). This document discusses the way that coreboot uses the concept of a "device tree" to generate ACPI tables for usage by the operating system. diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 0e14115db8b..a30c5e25f83 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -92,6 +92,6 @@ Here's a list of known issues: page tables in ROM will be loaded and used, which breaks code and data as the page table doesn't contain the expected data. This in turn leads to undefined behaviour whenever the 'wrong' address is being read. -* Disabling paging in compability mode crashes the CPU. -* Returning from long mode to compability mode crashes the CPU. +* Disabling paging in compatibility mode crashes the CPU. +* Returning from long mode to compatibility mode crashes the CPU. * Entering long mode crashes on AMD host platforms. diff --git a/Documentation/conf.py b/Documentation/conf.py index 3180fd97200..70b189a7f36 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -185,7 +185,7 @@ enable_auto_toc_tree = True class MyCommonMarkParser(CommonMarkParser): - # remove this hack once upsteam RecommonMark supports inline code + # remove this hack once upstream RecommonMark supports inline code def visit_code(self, mdnode): from docutils import nodes n = nodes.literal(mdnode.literal, mdnode.literal) diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md index a8c7356bfeb..4980659cc0c 100644 --- a/Documentation/contributing/coding_style.md +++ b/Documentation/contributing/coding_style.md @@ -801,7 +801,7 @@ There are a LOT of cpu cycles that can go into these 5 milliseconds. A reasonable rule of thumb is to not put inline at functions that have more than 3 lines of code in them. An exception to this rule are the -cases where a parameter is known to be a compiletime constant, and as a +cases where a parameter is known to be a compile time constant, and as a result of this constantness you *know* the compiler will be able to optimize most of your function away at compile time. For a good example of this later case, see the kmalloc() inline function. diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 2f6f73825cf..75c78caee15 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -202,9 +202,9 @@ Build an open source replacement written in Golang using existing tools and libraries, consisting of a backend, a frontend and client side scripts. The backend should connect to an SQL database with can be controlled using a RESTful API. The RESTful API should have basic authentication -for managment tasks and new board status uploads. +for management tasks and new board status uploads. -At least one older test result should be keept in the database. +At least one older test result should be kept in the database. The frontend should use established UI libraries or frameworks (for example Angular) to display the current board status, that is if it's working or not diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 40d747da9de..1b8539d9e5d 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -2,7 +2,7 @@ The drivers can be found in `src/drivers`. They are intended for onboard and plugin devices, significantly reducing integration complexity and -they allow to easily reuse existing code accross platforms. +they allow to easily reuse existing code across platforms. * [Intel DPTF](dptf.md) * [IPMI KCS](ipmi_kcs.md) diff --git a/Documentation/flash_tutorial/index.md b/Documentation/flash_tutorial/index.md index 43382979d21..da3d7f098ff 100644 --- a/Documentation/flash_tutorial/index.md +++ b/Documentation/flash_tutorial/index.md @@ -7,7 +7,7 @@ flash IC. ## Contents -* [Flashing internaly](int_flashrom.md) +* [Flashing internally](int_flashrom.md) * [Flashing firmware standalone](ext_standalone.md) * [Flashing firmware externally supplying direct power](ext_power.md) * [Flashing firmware externally without supplying direct power](no_ext_power.md) diff --git a/Documentation/gcov.txt b/Documentation/gcov.txt index 896ec939d6e..750e883f915 100644 --- a/Documentation/gcov.txt +++ b/Documentation/gcov.txt @@ -19,7 +19,7 @@ time). The file gcov-io.c is unchanged. +#define BITS_PER_UNIT 8 +#define LONG_LONG_TYPE_SIZE 64 + -+/* There are many gcc_assertions. Set the vaule to 1 if we want a warning ++/* There are many gcc_assertions. Set the value to 1 if we want a warning + message if the assertion fails. */ +#ifndef ENABLE_ASSERT_CHECKING +#define ENABLE_ASSERT_CHECKING 1 diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md index 8d63ac2c75e..09fb96031fd 100644 --- a/Documentation/getting_started/architecture.md +++ b/Documentation/getting_started/architecture.md @@ -41,7 +41,7 @@ The bootblock loads the romstage or the verstage if verified boot is enabled. ### Cache-As-Ram The *Cache-As-Ram*, also called Non-Eviction mode, or *CAR* allows to use the -CPU cache like regular SRAM. This is particullary usefull for high level +CPU cache like regular SRAM. This is particullary useful for high level languages like `C`, which need RAM for heap and stack. The CAR needs to be activated using vendor specific CPU instructions. @@ -85,7 +85,7 @@ The ramstage does the main device init: * CPU init (like set up SMM) After initialization tables are written to inform the payload or operating system -about the current hardware existance and state. That includes: +about the current hardware existence and state. That includes: * ACPI tables (x86 specific) * SMBIOS tables (x86 specific) diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index 384fc6d1fca..480ad787247 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -6,7 +6,7 @@ That said please always try to write documentation! One problem in the firmware development is the missing documentation. In this document you will get a brief introduction how to write, submit and publish -documenation to coreboot. +documentation to coreboot. ## Preparations diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index ef5e892c36c..ac3c18341a7 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -25,7 +25,7 @@ The section must be named in order to be found by the FIT parser: ## Architecture specifics -The FIT parser needs architecure support. +The FIT parser needs architecture support. ### aarch32 The source code can be found in `src/arch/arm/fit_payload.c`. diff --git a/Documentation/lib/timestamp.md b/Documentation/lib/timestamp.md index d5dc8facf33..a769f990986 100644 --- a/Documentation/lib/timestamp.md +++ b/Documentation/lib/timestamp.md @@ -99,7 +99,7 @@ exist and an entry structure to hold variable number of entries. ### entries -This field holds the details of each timestamp entry, upto a maximum +This field holds the details of each timestamp entry, up to a maximum of `MAX_TIMESTAMP_CACHE` which is defined as 16 entries. Each entry is defined by: diff --git a/Documentation/mainboard/amd/padmelon/padmelon.md b/Documentation/mainboard/amd/padmelon/padmelon.md index 20b1b130523..975426d8c60 100644 --- a/Documentation/mainboard/amd/padmelon/padmelon.md +++ b/Documentation/mainboard/amd/padmelon/padmelon.md @@ -43,7 +43,7 @@ Three items are marked in this picture +---------------------+--------------------+ | Size | 8 MiB | +---------------------+--------------------+ -| Flash programing | dediprog header | +| Flash programming | dediprog header | +---------------------+--------------------+ | Package | SOIC-8 | +---------------------+--------------------+ diff --git a/Documentation/mainboard/emulation/qemu-aarch64.md b/Documentation/mainboard/emulation/qemu-aarch64.md index 4df36a99440..6db8cefef08 100644 --- a/Documentation/mainboard/emulation/qemu-aarch64.md +++ b/Documentation/mainboard/emulation/qemu-aarch64.md @@ -1,5 +1,5 @@ # QEMU AArch64 emulator -This page discribes how to build and run coreboot for QEMU/AArch64. +This page describes how to build and run coreboot for QEMU/AArch64. You can use LinuxBoot via `make menuconfig` or an arbitrary FIT image as a payload for QEMU/AArch64. diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index 0f3e4c3179b..ca02b3c69a7 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -76,7 +76,7 @@ region. The update is then written into the EC once. [fl]: flashlayout_Ivy_Bridge.svg -## Reducing Intel Managment Engine firmware size +## Reducing Intel Management Engine firmware size It is possible to reduce the Intel ME firmware size to free additional space for the `bios` region. This is usually referred to as *cleaning the ME* or diff --git a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md index 84bae4014d7..e1d9c775014 100644 --- a/Documentation/mainboard/lenovo/Sandy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Sandy_Bridge_series.md @@ -48,7 +48,7 @@ region. The update is then written into the EC once. [fl]: flashlayout_Sandy_Bridge.svg -## Reducing Intel Managment Engine firmware size +## Reducing Intel Management Engine firmware size It is possible to reduce the Intel ME firmware size to free additional space for the `bios` region. This is usually referred to as *cleaning the ME* or diff --git a/Documentation/mainboard/lenovo/vboot.md b/Documentation/mainboard/lenovo/vboot.md index 3f1536018f2..0a451ab7c4b 100644 --- a/Documentation/mainboard/lenovo/vboot.md +++ b/Documentation/mainboard/lenovo/vboot.md @@ -28,7 +28,7 @@ to boot and flash a working image to the A/B partition. ## 8 MiB ROM limitation *Lenovo* devices with 8 MiB ROM only have a `RO`+`A` partition enabled in the -default FMAP. They are missing the `B` partition, due to size constaints. +default FMAP. They are missing the `B` partition, due to size constraints. You can still provide your own FMAP if you need `RO`+`A`+`B` partitions. ## CMOS diff --git a/Documentation/mainboard/ocp/tiogapass.md b/Documentation/mainboard/ocp/tiogapass.md index 6d6afb19207..8c499237916 100644 --- a/Documentation/mainboard/ocp/tiogapass.md +++ b/Documentation/mainboard/ocp/tiogapass.md @@ -51,7 +51,7 @@ To connect to console through SOL (Serial Over Lan): ## Known issues / feature gaps - C6 state is not supported. Workaround is to disable C6 support through - target OS and Linuxboot kernel paramter, such as "cpuidle.off=1". + target OS and Linuxboot kernel parameter, such as "cpuidle.off=1". - SMI handlers are not implemented. - xSDT tables are not fully populated, such as processor/socket devices, PCIe bridge devices. diff --git a/Documentation/mainboard/up/squared/index.md b/Documentation/mainboard/up/squared/index.md index d07f1118a82..2895e1f6a0e 100644 --- a/Documentation/mainboard/up/squared/index.md +++ b/Documentation/mainboard/up/squared/index.md @@ -48,7 +48,7 @@ +---------------------+------------+ | Internal flashing | No | +---------------------+------------+ -| In curcuit flashing | Yes | +| In circuit flashing | Yes | +---------------------+------------+ ``` @@ -67,8 +67,8 @@ The GPIO header is located on the **bottom** side (see [here][overview_bottom_li The SPI header is located on the **bottom** side (see [here][overview_bottom_link]). ![][header_cn22] -### Preperations -In order to build coreboot, it's neccessary to extract some files from the vendor firmware. Make sure that you have a fully working dump. +### Preparations +In order to build coreboot, it's necessary to extract some files from the vendor firmware. Make sure that you have a fully working dump. ```bash [upsquared]$ ls firmware_vendor.rom diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index bf0b89f6a09..1cd5fb40149 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -40,7 +40,7 @@ The memory initialization code has to take care of lots of duties: +---------+-------------------------------------------------------------------+------------+--------------+ ``` -## (Unoffical) register documentation +## (Unofficial) register documentation - [Sandy Bridge - Register documentation](nri_registers.md) ## Frequency selection @@ -101,7 +101,7 @@ is stored to MRC cache. As of writing the only supported error handling is to disable the failing channel and restart the memory training sequence. It's very likely to succeed, as memory channels operate independent of each other. -In case no DIMM could be initilized coreboot will halt. The screen will stay +In case no DIMM could be initialized coreboot will halt. The screen will stay black until you power of your device. On some platforms there's additional feedback to indicate such an event. diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index 208c1cb13c4..8d66b5c234d 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -42,7 +42,7 @@ Only **XMP profile 1** is being used in case it advertises: * 1.5V operating voltage * The channel's installed DIMM count doesn't exceed the XMP coded limit -In case the XMP profile doesn't fullfill those limits, the regular SPD will be +In case the XMP profile doesn't fulfill those limits, the regular SPD will be used. > **Note:** XMP Profiles are supported since coreboot 4.4. diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index aae1205ec6e..32bd3d1e286 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1947,7 +1947,7 @@ Please handle with care! +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ -| 0:7| OREF_RI, Rank idle period that defines an oppertunity for | +| 0:7| OREF_RI, Rank idle period that defines an opportunity for | | | refresh | +-----------+------------------------------------------------------------------+ | 8:11| Refresh_HP_WM, tREFI count level that turns the refresh | diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 971d438ee04..600bf67433d 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -200,7 +200,7 @@ a bug in the more involved code to query options. ### Resource allocator v4 A new revision of resource allocator v4 is now added to coreboot that supports -mutiple ranges for allocating resources. Unlike the previous allocator (v3), it does +multiple ranges for allocating resources. Unlike the previous allocator (v3), it does not use the topmost available window for allocation. Instead, it uses the first window within the address space that is available and satisfies the resource request. This allows utilization of the entire available address space and also allows diff --git a/Documentation/releases/coreboot-4.3-relnotes.md b/Documentation/releases/coreboot-4.3-relnotes.md index c33c48a2bd1..c0dda6e7b5d 100644 --- a/Documentation/releases/coreboot-4.3-relnotes.md +++ b/Documentation/releases/coreboot-4.3-relnotes.md @@ -124,7 +124,7 @@ X86 Areas with significant work on updates and fixes ------------------------------------------------ * cpu/amd/model_fxx -* intel/fsp1_x: Fix timestanps & postcodes, add native CAR & microcode +* intel/fsp1_x: Fix timestamps & postcodes, add native CAR & microcode * nb/amd/amdfam10: Add S3, voltage & ACPI, speed fixes & MANY other changes * nb/amd/amdmct: Add S3, mem voltage, Fix performance & MANY other diff --git a/Documentation/security/intel/txt.md b/Documentation/security/intel/txt.md index f80a731e817..7a746ec6dec 100644 --- a/Documentation/security/intel/txt.md +++ b/Documentation/security/intel/txt.md @@ -37,7 +37,7 @@ More details can be found in the [Intel TXT IBB] chapter. ### Measurements The IBBs (Initial Boot Blocks) are measured into TPM's PCR0 by the BIOS [ACM] -before the CPU reset vector is executed. To indentify the regions that need +before the CPU reset vector is executed. To identify the regions that need to be measured, the [FIT] contains one ore multiple *Type 7* entries, that point to the IBBs. diff --git a/Documentation/security/smm.md b/Documentation/security/smm.md index 4e95427b866..397b7af5529 100644 --- a/Documentation/security/smm.md +++ b/Documentation/security/smm.md @@ -1,4 +1,4 @@ -# x86 System Managment Mode +# x86 System Management Mode ## Introduction @@ -6,7 +6,7 @@ The code running in System Management Mode (SMM) provides runtime services to applications running in [ring0]. It has a higher privilege level than [ring0] and resides in the SMRAM region which cannot be accessed from [ring0]. -SMM can be entered by issuing System Managment Interrupts (SMIs). +SMM can be entered by issuing System Management Interrupts (SMIs). ## Secure data exchange diff --git a/Documentation/security/vboot/measured_boot.md b/Documentation/security/vboot/measured_boot.md index df4cc680086..adfae46d60c 100644 --- a/Documentation/security/vboot/measured_boot.md +++ b/Documentation/security/vboot/measured_boot.md @@ -9,7 +9,7 @@ The "Initial Boot Block" or "Core Root of Trust for Measurement" is the first code block loaded at reset vector and measured by a DRTM solution. In case SRTM mode is active, the IBB measures itself before measuring the next code block. In coreboot, cbfs files which are part of the IBB are identified -by a metatdata tag. This makes it possible to have platform specific IBB +by a metadata tag. This makes it possible to have platform specific IBB measurements without hardcoding them. ## Known Limitations diff --git a/Documentation/soc/cavium/cn81xx/index.md b/Documentation/soc/cavium/cn81xx/index.md index 3063b946d03..684948cfd63 100644 --- a/Documentation/soc/cavium/cn81xx/index.md +++ b/Documentation/soc/cavium/cn81xx/index.md @@ -21,7 +21,7 @@ The SOC folder contains functions for: * Secondary CPUs * PCI -All other hardware is initilized by the BDK code, which is invoked from +All other hardware is initialized by the BDK code, which is invoked from ramstage. ## Notes about the hardware diff --git a/Documentation/superio/common/ssdt.md b/Documentation/superio/common/ssdt.md index 2f4049ef125..5f9e2f6298a 100644 --- a/Documentation/superio/common/ssdt.md +++ b/Documentation/superio/common/ssdt.md @@ -50,7 +50,7 @@ end The following methods are generated for each SuperIO: ## AMTX() Acquire the global mutex and enter config mode. -It's called this at the begining of an atomic operation to make sure +It's called this at the beginning of an atomic operation to make sure no other ACPI code messes with the config space while working on it. ## RMTX() @@ -63,7 +63,7 @@ This method isn't guarded with the global mutex. ## DLDN(Arg0) Disables the (virtual) LDN given as Arg0. -This method aquires the global mutex. +This method acquires the global mutex. ## QLDN(Arg0) Queries the state of the (virtual) LDN given as Arg0. diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md index f7fe1a56c67..11a0a88154a 100644 --- a/Documentation/superio/nuvoton/npcd378.md +++ b/Documentation/superio/nuvoton/npcd378.md @@ -4,7 +4,7 @@ This page describes the [Nuvoton] SuperIO chip that can be found on various [HP] mainboards. As no datasheet is available most of the functions have been reverse engineered and -might be inacurate or wrong. +might be inaccurate or wrong. ## LDNs diff --git a/Documentation/technotes/2020-03-unit-testing-coreboot.md b/Documentation/technotes/2020-03-unit-testing-coreboot.md index 02c2e30ee07..a4d283f693c 100644 --- a/Documentation/technotes/2020-03-unit-testing-coreboot.md +++ b/Documentation/technotes/2020-03-unit-testing-coreboot.md @@ -83,7 +83,7 @@ Requirements for unit testing frameworks: Compiler for the host _must_ support the same language standards as the target compiler. Ideally the same toolchain should be used for building firmware - executables and test binaries, however the host complier will be used to build + executables and test binaries, however the host compiler will be used to build unit tests, whereas the coreboot toolchain will be used for building the firmware executables. For some targets, the host compiler and the target compiler could be the same, but this is not a requirement. diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index e02812b68f9..870248847fc 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -123,7 +123,7 @@ are needed to build the coreboot toolchain. `gcc` and `gnat` have to be of the same version. If you started with a different distribution or package management system you -might need to install other packages. Most likely they are named sightly +might need to install other packages. Most likely they are named slightly different. If that is the case for you, we'd like to encourage you to contribute to the project and submit a pull request with an update for this documentation for your system. diff --git a/Documentation/util.md b/Documentation/util.md index 083401f0349..8c6bcb7fcad 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -57,7 +57,7 @@ even if hidden `C` hardware configuration (register contents, MSRs, etc). `C` * __intelvbttool__ - Parse VBT from VGA BIOS `C` * __ipqheader__ - * _createxbl.py_ - Concatentates XBL segments into one ELF + * _createxbl.py_ - Concatenates XBL segments into one ELF image `Python` * _ipqheader.py_ - Returns a packed MBN header image with the specified base and size `Python` From 0949e739066c3509e05db2b9ed71cefaaa62205f Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 1 Oct 2021 14:28:22 -0600 Subject: [PATCH 002/320] src/acpi to src/lib: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/acpi/acpi.c | 14 +++++++------- src/acpi/device.c | 2 +- src/arch/arm/armv7/cpu.S | 2 +- src/arch/arm64/include/arch/asm.h | 2 +- src/arch/riscv/fit_payload.c | 2 +- src/arch/riscv/opensbi.c | 2 +- src/arch/x86/c_start.S | 2 +- src/commonlib/bsd/include/commonlib/bsd/compiler.h | 2 +- src/commonlib/include/commonlib/iobuf.h | 4 ++-- src/console/Kconfig | 2 +- src/cpu/x86/64bit/exit32.inc | 4 ++-- src/cpu/x86/pae/pgtbl.c | 4 ++-- src/cpu/x86/sipi_vector.S | 2 +- src/device/Kconfig | 2 +- src/device/azalia_device.c | 2 +- src/device/dram/ddr4.c | 2 +- src/device/oprom/include/x86emu/regs.h | 2 +- src/device/oprom/x86emu/LICENSE | 2 +- src/device/oprom/x86emu/prim_ops.c | 2 +- src/device/pci_early.c | 2 +- src/device/pnp_device.c | 2 +- src/device/resource_allocator_v4.c | 2 +- src/drivers/amd/agesa/cache_as_ram.S | 2 +- src/drivers/crb/tpm.c | 2 +- src/drivers/generic/gpio_keys/chip.h | 2 +- src/drivers/i2c/lm96000/chip.h | 2 +- src/drivers/i2c/nct7802y/chip.h | 2 +- src/drivers/i2c/tpm/cr50.c | 2 +- src/drivers/i2c/tpm/tpm.c | 2 +- src/drivers/i2c/ww_ring/ww_ring_programs.c | 2 +- src/drivers/i2c/ww_ring/ww_ring_programs.h | 4 ++-- src/drivers/ipmi/ipmi_fru.c | 2 +- src/drivers/ipmi/supermicro_oem.c | 2 +- src/drivers/net/Kconfig | 2 +- src/drivers/net/atl1e.c | 2 +- src/drivers/net/r8168.c | 2 +- src/drivers/spi/spi_sdcard.c | 4 ++-- src/drivers/spi/tpm/tpm.c | 6 +++--- src/ec/compal/ene932/acpi/ec.asl | 2 +- src/ec/google/chromeec/ec.h | 4 ++-- src/ec/google/chromeec/ec_commands.h | 2 +- src/ec/google/wilco/commands.h | 2 +- src/ec/quanta/ene_kb3940q/acpi/ec.asl | 2 +- src/ec/quanta/it8518/acpi/battery.asl | 2 +- src/ec/quanta/it8518/acpi/ec.asl | 2 +- src/include/acpi/acpi.h | 2 +- src/include/cpu/x86/save_state.h | 2 +- src/include/device/i2c_simple.h | 2 +- src/lib/device_tree.c | 2 +- src/lib/edid.c | 6 +++--- src/lib/nhlt.c | 2 +- src/lib/region_file.c | 2 +- 52 files changed, 68 insertions(+), 68 deletions(-) diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 2e15ea9cc80..6417ef891e1 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1937,15 +1937,15 @@ int get_acpi_table_revision(enum acpi_tables table) return 2; case TPM2: return 4; - case SSDT: /* ACPI 3.0 upto 6.3: 2 */ + case SSDT: /* ACPI 3.0 up to 6.3: 2 */ return 2; - case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ + case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 up to 6.3: 3 */ return 1; /* TODO Should probably be upgraded to 2 */ case HMAT: /* ACPI 6.4: 2 */ return 2; case DMAR: return 1; - case SLIT: /* ACPI 2.0 upto 6.3: 1 */ + case SLIT: /* ACPI 2.0 up to 6.3: 1 */ return 1; case SPMI: /* IMPI 2.0 */ return 5; @@ -1957,13 +1957,13 @@ int get_acpi_table_revision(enum acpi_tables table) return IVRS_FORMAT_MIXED; case DBG2: return 0; - case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */ + case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 up to 6.3: 2 */ return 1; - case RSDT: /* ACPI 1.0 upto 6.3: 1 */ + case RSDT: /* ACPI 1.0 up to 6.3: 1 */ return 1; - case XSDT: /* ACPI 2.0 upto 6.3: 1 */ + case XSDT: /* ACPI 2.0 up to 6.3: 1 */ return 1; - case RSDP: /* ACPI 2.0 upto 6.3: 2 */ + case RSDP: /* ACPI 2.0 up to 6.3: 2 */ return 2; case EINJ: return 1; diff --git a/src/acpi/device.c b/src/acpi/device.c index 4b59990e5f0..1df179bad60 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -139,7 +139,7 @@ static ssize_t acpi_device_path_fill(const struct device *dev, char *buf, /* * Warning: just as with dev_path() this uses a static buffer - * so should not be called mulitple times in one statement + * so should not be called multiple times in one statement */ const char *acpi_device_path(const struct device *dev) { diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index c53119c8d1a..bc3ebd90a0d 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -16,7 +16,7 @@ * the LSB of the set field, but the latter contains the LSB of the way field * minus the highest valid set field... such that when you subtract it from a * [way:0:level] field you end up with a [way - 1:highest_set:level] field - * through the magic of double subtraction. It's quite ingenius, really. + * through the magic of double subtraction. It's quite ingenious, really. * Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without * needing to write to memory. * diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index e6246c39da3..df5952a576d 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -19,7 +19,7 @@ .size name, .-name /* - * Certain SoCs have an alignment requiremnt for the CPU reset vector. + * Certain SoCs have an alignment requirement for the CPU reset vector. * Align to a 64 byte typical cacheline for now. */ #define CPU_RESET_ENTRY(name) ENTRY_WITH_ALIGN(name, 6) diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index abce57ee08d..f7f4106cae3 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -7,7 +7,7 @@ #include #include -/* Implements a Berkley Boot Loader (BBL) compatible payload loading */ +/* Implements a Berkeley Boot Loader (BBL) compatible payload loading */ #define MAX_KERNEL_SIZE (64*MiB) diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c index e719560db3e..3a738ec83a5 100644 --- a/src/arch/riscv/opensbi.c +++ b/src/arch/riscv/opensbi.c @@ -2,7 +2,7 @@ #include #include -/* DO NOT INLCUDE COREBOOT HEADERS HERE */ +/* DO NOT INCLUDE COREBOOT HEADERS HERE */ void run_opensbi(const int hart_id, const void *fdt, diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index a4a7b28cbb4..cb7d5045ffb 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -217,7 +217,7 @@ SetCodeSelector: # use iret to jump to a 64-bit offset in a new code segment # iret will pop cs:rip, flags, then ss:rsp mov %ss, %ax # need to push ss.. - push %rax # push ss instuction not valid in x64 mode, + push %rax # push ss instruction not valid in x64 mode, # so use ax push %rsp pushfq diff --git a/src/commonlib/bsd/include/commonlib/bsd/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h index ee2ff88d108..4dd09bc90cb 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/compiler.h +++ b/src/commonlib/bsd/include/commonlib/bsd/compiler.h @@ -36,7 +36,7 @@ #endif /* This evaluates to the type of the first expression, unless that is constant - in which case it evalutates to the type of the second. This is useful when + in which case it evaluates to the type of the second. This is useful when assigning macro parameters to temporary variables, because that would normally circumvent the special loosened type promotion rules for integer literals. By using this macro, the promotion can happen at the time the diff --git a/src/commonlib/include/commonlib/iobuf.h b/src/commonlib/include/commonlib/iobuf.h index 472b3687b58..0de7d3e66c8 100644 --- a/src/commonlib/include/commonlib/iobuf.h +++ b/src/commonlib/include/commonlib/iobuf.h @@ -81,7 +81,7 @@ int ibuf_split(const struct ibuf *src, struct ibuf *a, struct ibuf *b, /* Out-of-band drain of ibuf by returning pointer to data of specified size. */ const void *ibuf_oob_drain(struct ibuf *ib, size_t sz); -/* Read arbitray data from input buffer. */ +/* Read arbitrary data from input buffer. */ int ibuf_read(struct ibuf *ib, void *data, size_t sz); /* Read big endian fixed size values. */ @@ -125,7 +125,7 @@ int obuf_split(const struct obuf *src, struct obuf *a, struct obuf *b, /* Fill the buffer out-of-band. The size is accounted for. */ void *obuf_oob_fill(struct obuf *ob, size_t sz); -/* Write arbitray data to output buffer. */ +/* Write arbitrary data to output buffer. */ int obuf_write(struct obuf *ob, const void *data, size_t sz); /* Write big endian fixed size values. */ diff --git a/src/console/Kconfig b/src/console/Kconfig index 4125e18dd92..4c2e7686857 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -193,7 +193,7 @@ config CONSOLE_NE2K help Send coreboot debug output to a Ethernet console, it works same way as Linux netconsole, packets are received to UDP - port 6666 on IP/MAC specified with options bellow. + port 6666 on IP/MAC specified with options below. Use following netcat command: nc -u -l -p 6666 config CONSOLE_NE2K_DST_MAC diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 91cccb535eb..4d1149ee6c7 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * For droping from long mode to protected mode. + * For dropping from long mode to protected mode. * * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2", * Document 24593-Rev. 3.31-July 2019 Chapter 5.3 @@ -47,7 +47,7 @@ SetCodeSelector32: # use iret to jump to a 32-bit offset in a new code segment # iret will pop cs:rip, flags, then ss:rsp - mov %ss, %ax # need to push ss, but push ss instuction + mov %ss, %ax # need to push ss, but push ss instruction push %rax # not valid in x64 mode, so use ax push %rdx # the rsp to load pushfq # push rflags diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 814dbf5c701..c8783d6234b 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -104,7 +104,7 @@ void paging_disable_pae(void) * Use PAE to map a page and then memset it with the pattern specified. * In order to use PAE pagetables for virtual addressing are set up and reloaded * on a 2MiB boundary. After the function is done, virtual addressing mode is - * disabled again. The PAT are set to all cachable, but MTRRs still apply. + * disabled again. The PAT are set to all cacheable, but MTRRs still apply. * * Requires a scratch memory for pagetables and a virtual address for * non identity mapped memory. @@ -124,7 +124,7 @@ void paging_disable_pae(void) * Content at physical address isn't preserved. * @param length The length of the memory segment to memset * @param dest Physical memory address to memset - * @param pat The pattern to write to the pyhsical memory + * @param pat The pattern to write to the physical memory * @return 0 on success, 1 on error */ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl, diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 44b772bcc22..496fd345ebf 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -57,7 +57,7 @@ _start: movw %cs, %ax movw %ax, %ds - /* The gdtaddr needs to be releative to the data segment in order + /* The gdtaddr needs to be relative to the data segment in order * to properly dereference it. The .text section comes first in an * rmodule so _start can be used as a proxy for the load address. */ movl $(gdtaddr), %ebx diff --git a/src/device/Kconfig b/src/device/Kconfig index 5ae3466d328..ea3e241c82a 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -166,7 +166,7 @@ config ALWAYS_RUN_OPROM def_bool n depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM help - Always uncondtionally run the option regardless of other + Always unconditionally run the option regardless of other policies. config ON_DEVICE_ROM_LOAD diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 9202f72a4e7..70f8348a7c1 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -289,7 +289,7 @@ void azalia_audio_init(struct device *dev) if (!res) return; - // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // NOTE this will break as soon as the azalia_audio gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base); diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 83beeafba12..c5a8d13f53c 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -205,7 +205,7 @@ int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd) /* Verify CRC of blocks that have them, do not step over 'used' length */ for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) { - /* this block is not checksumed */ + /* this block is not checksummed */ if (spd_blocks[i].crc_start == 0) continue; /* we shouldn't have this block */ diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index 7640c78896a..52f599dbdaa 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -54,7 +54,7 @@ * EAX & 0xff === AL * EAX & 0xffff == AX * - * etc. The result is that alot of the calculations can then be + * etc. The result is that a lot of the calculations can then be * done using the native instruction set fully. */ diff --git a/src/device/oprom/x86emu/LICENSE b/src/device/oprom/x86emu/LICENSE index f13d4188acf..f1c26ccf6a8 100644 --- a/src/device/oprom/x86emu/LICENSE +++ b/src/device/oprom/x86emu/LICENSE @@ -1,7 +1,7 @@ License information ------------------- -The x86emu library is under a BSD style license, comaptible +The x86emu library is under a BSD style license, compatible with the XFree86 and X licenses used by XFree86. The original x86emu libraries were under the GNU General Public License. Due to license incompatibilities between the GPL diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index d794ecb46c2..2350ac14909 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -2458,7 +2458,7 @@ void x86emu_cpuid(void) switch (feature) { case 0: /* Regardless if we have real data from the hardware, the emulator - * will only support upto feature 1, which we set in register EAX. + * will only support up to feature 1, which we set in register EAX. * Registers EBX:EDX:ECX contain a string identifying the CPU. */ M.x86.R_EAX = 1; diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 3a4d2e020ce..590b170142d 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -104,7 +104,7 @@ void pci_early_bridge_init(void) } /* FIXME: A lot of issues using the following, please avoid. - * Assumes 256 PCI busses, scans them all even when PCI bridges are still + * Assumes 256 PCI buses, scans them all even when PCI bridges are still * disabled. Probes all functions even if 0 is not present. */ pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 699007d9ba2..88072b9a775 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -238,7 +238,7 @@ static void pnp_get_ioresource(struct device *dev, u8 index, u16 mask) resource->limit = (1 << (bit + 1)) - 1; /* The block of ones in the mask is expected to be continuous. - If there is any zero inbetween the block of ones, it is ignored + If there is any zero in between the block of ones, it is ignored in the calculation of the resource size and limit. */ if (mask != (resource->limit ^ (resource->size - 1))) printk(BIOS_WARNING, diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index b94c295edcd..6f8159e1b12 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -637,7 +637,7 @@ static void allocate_domain_resources(const struct device *domain) * order to accomplish best fit for the resources, a list of ranges is maintained by each * resource type (i/o and mem). Domain does not differentiate between mem and prefmem. Since * they are allocated space from the same window, the resource allocator at the domain level - * ensures that the biggest requirement is selected indepedent of the prefetch type. Once the + * ensures that the biggest requirement is selected independent of the prefetch type. Once the * resource allocation for all immediate downstream devices is complete at the domain level, * resource allocator walks down the subtree for each downstream bridge to continue the * allocation process at the bridge level. Since bridges have separate windows for i/o, mem and diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 1e15eda017e..0d678d1889f 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -5,7 +5,7 @@ * * $Workfile:: cache_as_ram.S * - * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier + * Description: cache_as_ram.S - AGESA Module Entry Point for GCC compiler * ****************************************************************************** */ diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index fcefe96448f..9c8f2498dcf 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -6,7 +6,7 @@ * * TPM starts in IDLE Mode * - * IDLE --> READY --> Command Receiption + * IDLE --> READY --> Command Reception * ^ | * | v -- Cmd Complete <-- Command Execution diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h index 88dfe2ea714..01f4a1299c6 100644 --- a/src/drivers/generic/gpio_keys/chip.h +++ b/src/drivers/generic/gpio_keys/chip.h @@ -81,7 +81,7 @@ struct drivers_generic_gpio_keys_config { struct acpi_gpio gpio; /* Is this a polled GPIO button? - Optional */ bool is_polled; - /* Poll inverval - Mandatory only if GPIO is polled. */ + /* Poll interval - Mandatory only if GPIO is polled. */ uint32_t poll_interval; /* Details about the key - Mandatory */ struct key_info key; diff --git a/src/drivers/i2c/lm96000/chip.h b/src/drivers/i2c/lm96000/chip.h index 128d1ec4119..bb86f4e4656 100644 --- a/src/drivers/i2c/lm96000/chip.h +++ b/src/drivers/i2c/lm96000/chip.h @@ -90,7 +90,7 @@ struct lm96000_temp_zone { enum { /* turn fan off below `low_temp - hysteresis` */ LM96000_LOW_TEMP_OFF = 0, - /* keep PWM at mininum duty cycle */ + /* keep PWM at minimum duty cycle */ LM96000_LOW_TEMP_MIN = 1, } min_off; u8 hysteresis; diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h index 03c464af82a..c4a767debfa 100644 --- a/src/drivers/i2c/nct7802y/chip.h +++ b/src/drivers/i2c/nct7802y/chip.h @@ -37,7 +37,7 @@ enum nct7802y_fan_mode { enum nct7802y_fan_smartmode { SMART_FAN_DUTY = 0, /* Target values given in duty cycle %. */ - SMART_FAN_RPM, /* Target valuse given in RPM. */ + SMART_FAN_RPM, /* Target values given in RPM. */ }; enum nct7802y_fan_speed { diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 8e12d1f044c..a8a310fc7f9 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -3,7 +3,7 @@ /* Based on Linux Kernel TPM driver */ /* - * cr50 is a TPM 2.0 capable device that requries special + * cr50 is a TPM 2.0 capable device that requires special * handling for the I2C interface. * * - Use an interrupt for transaction status instead of hardcoded delays diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index ee23ea7c440..b96099ccccc 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -35,7 +35,7 @@ /* max. number of iterations after I2C NAK for 'long' commands * we need this especially for sending TPM_READY, since the cleanup after the - * transtion to the ready state may take some time, but it is unpredictable + * transition to the ready state may take some time, but it is unpredictable * how long it will take. */ #define MAX_COUNT_LONG 50 diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index 7576a3bfb76..73dd4dabf16 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -91,7 +91,7 @@ static const TiLp55231Program solid_000000_program = { * * When solid patterns are deployed with instanteneous color intensity * changes, all three LEDs can be controlled by one engine in sequential - * accesses. But the controllers still neeed to be synchronized. + * accesses. But the controllers still need to be synchronized. * * The maximum timer duration of lp55231 is .48 seconds. To achieve longer * blinking intervals the loops delays are deployed. Only the first controller diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index 4f936515d06..47d1c77339a 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -21,7 +21,7 @@ #include #include "drivers/i2c/ww_ring/ww_ring.h" -/* There are threee independent engines/cores in the controller. */ +/* There are three independent engines/cores in the controller. */ #define LP55231_NUM_OF_ENGINES 3 /* Number of lp55321 controllers on the ring */ @@ -29,7 +29,7 @@ /* * Structure to describe an lp55231 program: pointer to the text of the - * program, its size and load address (load addr + size sould not exceed + * program, its size and load address (load addr + size should not exceed * LP55231_MAX_PROG_SIZE), and start addresses for all of the three * engines. */ diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 976df1cb9e8..31ac6c0d9c7 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -525,7 +525,7 @@ void print_fru_areas(struct fru_info_str *fru_info_str) if (prod_info.product_name != NULL) printk(BIOS_DEBUG, "product name: %s\n", prod_info.product_name); if (prod_info.product_partnumber != NULL) - printk(BIOS_DEBUG, "product part numer: %s\n", prod_info.product_partnumber); + printk(BIOS_DEBUG, "product part number: %s\n", prod_info.product_partnumber); if (prod_info.product_version != NULL) printk(BIOS_DEBUG, "product version: %s\n", prod_info.product_version); if (prod_info.serial_number != NULL) diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c index 87b7fe243a7..9d5ffc77a46 100644 --- a/src/drivers/ipmi/supermicro_oem.c +++ b/src/drivers/ipmi/supermicro_oem.c @@ -26,7 +26,7 @@ static void set_coreboot_ver(const uint16_t kcs_port) int ret; size_t i; - /* Only 8 charactars are visible in UI. Cut of on first dash */ + /* Only 8 characters are visible in UI. Cut of on first dash */ for (i = 0; i < 15; i++) { if (coreboot_ver[i] == '-') break; diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig index 282075b31d3..7e111f65691 100644 --- a/src/drivers/net/Kconfig +++ b/src/drivers/net/Kconfig @@ -33,7 +33,7 @@ config RT8168_SET_LED_MODE select REALTEK_8168_RESET help This is to set a customized LED mode to distinguish 10/100/1000 - link and speed status with limited LEDs avaiable on a board. + link and speed status with limited LEDs available on a board. Please refer to RTL811x datasheet section 7.2 Customizable LED Configuration for details. With this flag enabled, the customized_leds variable will be read from devicetree setting. diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 9b1b2ab9530..97ad14091da 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -127,7 +127,7 @@ static void atl1e_init(struct device *dev) /* Check if the base is invalid */ if (!mem_base) { - printk(BIOS_ERR, "atl1e: Error cant find MEM resource\n"); + printk(BIOS_ERR, "atl1e: Error can't find MEM resource\n"); return; } /* Enable but do not set bus master */ diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 398b15d93ca..1fd6eddbb32 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -280,7 +280,7 @@ static void r8168_init(struct device *dev) /* Check if the base is invalid */ if (!io_base) { - printk(BIOS_ERR, "r8168: Error cant find IO resource\n"); + printk(BIOS_ERR, "r8168: Error can't find IO resource\n"); return; } /* Enable but do not set bus master */ diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c index a670111891f..0a18953395e 100644 --- a/src/drivers/spi/spi_sdcard.c +++ b/src/drivers/spi/spi_sdcard.c @@ -683,7 +683,7 @@ int spi_sdcard_single_write(const struct spi_sdcard *card, spi_sdcard_sendbyte(card, 0xff & (c >> 8)); spi_sdcard_sendbyte(card, 0xff & (c >> 0)); - /* recevie and verify data response token */ + /* receive and verify data response token */ c = spi_sdcard_recvbyte(card); if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) { spi_sdcard_disable_cs(card); @@ -742,7 +742,7 @@ int spi_sdcard_multiple_write(const struct spi_sdcard *card, spi_sdcard_sendbyte(card, 0xff & (c >> 8)); spi_sdcard_sendbyte(card, 0xff & (c >> 0)); - /* recevie and verify data response token */ + /* receive and verify data response token */ c = spi_sdcard_recvbyte(card); if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) break; diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 1ad1eaac486..30b18761ef8 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -3,7 +3,7 @@ * * It assumes that the required SPI interface has been initialized before the * driver is started. A 'sruct spi_slave' pointer passed at initialization is - * used to direct traffic to the correct SPI interface. This dirver does not + * used to direct traffic to the correct SPI interface. This driver does not * provide a way to instantiate multiple TPM devices. Also, to keep things * simple, the driver unconditionally uses of TPM locality zero. * @@ -159,7 +159,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) /* * The first byte of the frame header encodes the transaction type - * (read or write) and transfer size (set to lentgh - 1), limited to + * (read or write) and transfer size (set to length - 1), limited to * 64 bytes. */ header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1); @@ -188,7 +188,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr) * the last clock of the byte) is set to 1. * * Due to some SPI controllers' shortcomings (Rockchip comes to - * mind...) we trasmit the 4 byte header without checking the byte + * mind...) we transmit the 4 byte header without checking the byte * transmitted by the TPM during the transaction's last byte. * * We know that cr50 is guaranteed to set the flow control bit to 0 diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index f3fb9979fee..3242cceb36b 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -118,7 +118,7 @@ Device (EC0) SWTO, 1, // SW Throttling (1=Active) ; AEh.6 TTHR, 1, // HW (THRM#) Throttling (1=Active) ; AEh.7 TTHM, 1, // TS_THERMAL(1:Throttling for thermal) ; AFh.0 - THTL, 1, // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1 + THTL, 1, // THROTTLING(1:Ctrl H/W throttling act); AFh.1 , 2, // Reserved ; AFh.2-3 NPST, 4, // Number of P-State level ; AFh.4-7 CTMP, 8, // Current CPU Temperature ; B0h diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index ed9f4e43ba0..743651b0f99 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -161,7 +161,7 @@ int crosec_command_proto(struct chromeec_command *cec_command, crosec_io_t crosec_io, void *context); /** - * Performs light verification of the EC<->AP communcation channel. + * Performs light verification of the EC<->AP communication channel. * * @return 0 on success, -1 on error */ @@ -330,7 +330,7 @@ struct usb_pd_port_caps { * Get role-based capabilities for a USB-PD port * * @param port Which port to get information about - * @param *power_role_cap The power-role capabillity of the port + * @param *power_role_cap The power-role capability of the port * @param *try_power_role_cap The Try-power-role capability of the port * @param *data_role_cap The data role capability of the port * @param *port_location Location of the port on the device diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index e8b028f8226..bbe34be71a2 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -2856,7 +2856,7 @@ struct ec_params_motion_sense { */ struct __ec_todo_unpacked { /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. - * kb_wake_angle: angle to wakup AP. + * kb_wake_angle: angle to wake up AP. */ int16_t data; } kb_wake_angle; diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index a2163459e11..b70f949fcbb 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -10,7 +10,7 @@ enum { KB_POWER_SMI = 0x04, /* Read but do not clear power state information */ KB_POWER_STATUS = 0x05, - /* Inform the EC aboout the reason host is turning off */ + /* Inform the EC about the reason host is turning off */ KB_POWER_OFF = 0x08, /* Control wireless radios */ KB_RADIO_CONTROL = 0x2b, diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 9d8cc281f62..a14c737aad1 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -75,7 +75,7 @@ Device (EC0) KBID, 1, // 0=EN KBD, 1=JP KBD ; 80h.1 , 6, // Reserved ; 80h.2-7 NPST, 8, // Number of P-State level ; 81h - MPST, 8, // Maxumum P-State ; 82h + MPST, 8, // Maximum P-State ; 82h KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; 83h.0 TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; 83h.1 , 1, // Reserved ; 83h.2 diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl index 79a1da30e18..768f2b12e47 100644 --- a/src/ec/quanta/it8518/acpi/battery.asl +++ b/src/ec/quanta/it8518/acpi/battery.asl @@ -23,7 +23,7 @@ Device (BATX) 0, // 0: Power Unit 0xFFFFFFFF, // 1: Design Capacity 0xFFFFFFFF, // 2: Last Full Charge Capacity - 1, // 3: Battery Technology(Rechargable) + 1, // 3: Battery Technology(Rechargeable) 10800, // 4: Design Voltage 10.8V 0, // 5: Design capacity of warning 0, // 6: Design capacity of low diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index 093593cfce7..36f966f94d5 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -444,7 +444,7 @@ Device (EC0) MBTH, 4, // bit 3-0: battery 0 highest level SBTH, 4, // bit 7-4: battery 1 highest level // note: if highest level is 0 or 0xF, it means not defined - // (in this case, use default hightest level, it is 6) + // (in this case, use default highest level, it is 6) Offset(0xEF), // [EC Function Specification Major Version] Offset(0xF0), // [Build ID]~ offset:0F7h diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 01d10c2b204..2c9af3a56fe 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1267,7 +1267,7 @@ void acpi_create_slit(acpi_slit_t *slit, * proximimity domain for the memory. */ int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory); -/* Create Heterogenous Memory Attribute Table */ +/* Create Heterogeneous Memory Attribute Table */ void acpi_create_hmat(acpi_hmat_t *hmat, unsigned long (*acpi_fill_hmat)(unsigned long current)); diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h index d6fcf63d79a..139a5fa7504 100644 --- a/src/include/cpu/x86/save_state.h +++ b/src/include/cpu/x86/save_state.h @@ -26,7 +26,7 @@ struct smm_save_state_ops { /* Return -1 on failure, otherwise returns which CPU node issued an APMC IO write */ int get_apmc_node(u8 cmd); -/* Return -1 on failure, 0 on succes. +/* Return -1 on failure, 0 on success. Accessors for the SMM save state CPU registers RAX, RBX, RCX and RDX */ int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length); int set_save_state_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length); diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index de1c0eb4b89..8f389b31072 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -35,7 +35,7 @@ int i2c_write_field(unsigned int bus, uint8_t slave, uint8_t reg, uint8_t data, /* * software_i2c is supposed to be a debug feature. It's usually not compiled in, - * but when it is it can be dynamically enabled at runtime for certain busses. + * but when it is it can be dynamically enabled at runtime for certain buses. * Need this ugly stub to arbitrate since I2C device drivers hardcode * 'i2c_transfer()' as their entry point. */ diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 1fd8874047c..3821e5cced5 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -758,7 +758,7 @@ struct device_tree_node *dt_find_compat(struct device_tree_node *parent, } /* - * Find the next compatible child of a given parent. All children upto the + * Find the next compatible child of a given parent. All children up to the * child passed in by caller are ignored. If child is NULL, it considers all the * children to find the first child which is compatible. * diff --git a/src/lib/edid.c b/src/lib/edid.c index cd7a47ac787..55876e8a7c6 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -433,7 +433,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, /* * Slightly weird to return a global, but I've never - * seen any EDID block wth two range descriptors, so + * seen any EDID block with two range descriptors, so * it's harmless. */ return 1; @@ -481,7 +481,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension, We have no samples between those values, so put a threshold at 95000 kHz. If we get anything over 95000 kHz with single channel, we can make this - more sofisticated but it's currently not needed. + more sophisticated but it's currently not needed. */ out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000); extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); @@ -1094,7 +1094,7 @@ int set_display_mode(struct edid *edid, enum edid_modes mode) } /* - * Given a raw edid bloc, decode it into a form + * Given a raw edid block, decode it into a form * that other parts of coreboot can use -- mainly * graphics bringup functions. The raw block is * required to be 128 bytes long, per the standard, diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 90a6cd9eef7..a061b828646 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -126,7 +126,7 @@ struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endp, wave->channel_mask = speaker_mask; memcpy(&wave->sub_format, &pcm_subformat, sizeof(wave->sub_format)); - /* Calculate the dervied fields. */ + /* Calculate the derived fields. */ wave->block_align = wave->num_channels * wave->bits_per_sample / 8; wave->bytes_per_second = wave->block_align * wave->samples_per_second; diff --git a/src/lib/region_file.c b/src/lib/region_file.c index 4fe91b62bf1..f3e66bfcfb4 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -9,7 +9,7 @@ * A region file provides generic support for appending new data * within a storage region. The book keeping is tracked in metadata * blocks where an offset pointer points to the last byte of a newly - * allocated byte sequence. Thus, by taking 2 block offets one can + * allocated byte sequence. Thus, by taking 2 block offsets one can * determine start and size of the latest update. The data does not * have to be the same consistent size, but the data size has be small * enough to fit a metadata block and one data write within the region. From 50863daef8ed75c0cb3dfd375e7622c898de5821 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 1 Oct 2021 14:37:30 -0600 Subject: [PATCH 003/320] src/mainboard to src/security: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/mainboard/amd/bilby/devicetree.cb | 2 +- src/mainboard/amd/mandolin/variants/cereme/devicetree.cb | 2 +- src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb | 2 +- src/mainboard/asrock/b75pro3-m/devicetree.cb | 2 +- .../asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb | 2 +- src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb | 2 +- src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb | 2 +- src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb | 2 +- .../asus/p8x7x-series/variants/p8z77-m_pro/early_init.c | 4 ++-- src/mainboard/emulation/qemu-armv7/memlayout.ld | 2 +- src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h | 2 +- src/mainboard/emulation/qemu-q35/bootblock.c | 2 +- src/mainboard/facebook/fbg1701/ramstage.c | 2 +- .../facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex | 2 +- .../facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex | 2 +- .../facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex | 2 +- src/mainboard/google/daisy/mainboard.c | 4 ++-- src/mainboard/google/foster/bct/jtag.cfg | 2 +- src/mainboard/google/gru/pwm_regulator.c | 2 +- .../google/guybrush/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/kahlee/mainboard.c | 2 +- src/mainboard/google/mistral/romstage.c | 2 +- src/mainboard/google/oak/mainboard.c | 2 +- src/mainboard/google/octopus/mainboard.c | 2 +- src/mainboard/google/octopus/variants/baseboard/gpio.c | 2 +- src/mainboard/google/octopus/variants/yorp/gpio.c | 2 +- src/mainboard/google/peach_pit/mainboard.c | 2 +- .../variants/baseboard/include/baseboard/acpi/camera_pmic.asl | 2 +- src/mainboard/google/smaug/bct/jtag.cfg | 2 +- src/mainboard/google/stout/dsdt.asl | 2 +- .../google/zork/variants/baseboard/devicetree_dalboz.cb | 4 ++-- .../google/zork/variants/baseboard/devicetree_trembyle.cb | 4 ++-- .../zork/variants/baseboard/include/baseboard/variants.h | 2 +- src/mainboard/intel/dcp847ske/devicetree.cb | 2 +- src/mainboard/intel/dg41wv/devicetree.cb | 2 +- src/mainboard/intel/kblrvp/acpi/mipi_camera.asl | 4 ++-- src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c | 2 +- src/mainboard/lenovo/s230u/acpi/ec.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 +- .../portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex | 2 +- .../portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex | 2 +- .../portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex | 2 +- src/mainboard/protectli/vault_bsw/romstage.c | 2 +- src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl | 2 +- src/mainboard/roda/rk9/acpi/ec.asl | 2 +- src/mainboard/roda/rk9/acpi/thermal.asl | 2 +- src/northbridge/intel/haswell/northbridge.c | 2 +- src/northbridge/intel/i945/Kconfig | 2 +- src/northbridge/intel/ironlake/bootblock.c | 2 +- src/northbridge/intel/sandybridge/raminit_common.c | 2 +- src/security/intel/cbnt/logging.c | 2 +- src/security/intel/stm/SmmStm.c | 2 +- src/security/intel/txt/common.c | 2 +- src/security/memory/memory_clear.c | 2 +- src/security/tpm/tspi.h | 2 +- src/security/tpm/tss/tcg-2.0/tss.c | 4 ++-- src/security/tpm/tss/tcg-2.0/tss_marshaling.h | 2 +- 58 files changed, 64 insertions(+), 64 deletions(-) diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 6ecdaf49107..c3ba99c9057 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -127,7 +127,7 @@ chip soc/amd/picasso .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_OFF" register "gpp_clk_config[1]" = "GPP_CLK_OFF" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 6342c29f668..167c3667ab9 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -118,7 +118,7 @@ chip soc/amd/picasso .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 035bb7015b9..1bc5498e3ca 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -118,7 +118,7 @@ chip soc/amd/picasso .flash_ch_en = 0, }" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 83b6597337c..93d37dcac03 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -129,7 +129,7 @@ chip northbridge/intel/sandybridge irq 0xe9 = 0x02 irq 0xf0 = 0x20 end - device pnp 2e.b off end # HWM, front pannel LED + device pnp 2e.b off end # HWM, front panel LED device pnp 2e.d on end # VID device pnp 2e.e off end # CIR WAKE-UP device pnp 2e.f on end # GPIO Push-Pull or Open-drain diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index a50c2aca371..ff0503066ca 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -105,7 +105,7 @@ chip northbridge/intel/x4x # Northbridge irq 0xe9 = 0x02 irq 0xf0 = 0x20 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 io 0x62 = 0x200 irq 0x70 = 0 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 7ceefaabe84..89e6ebb8fce 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -99,7 +99,7 @@ chip northbridge/intel/x4x # Northbridge device pnp 2e.a on # ACPI irq 0xe4 = 0x10 # Power dram during s3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index e583f7f763d..c3c6b1b17ab 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -100,7 +100,7 @@ chip northbridge/intel/x4x # Northbridge device pnp 2e.a on # ACPI irq 0xe4 = 0x10 # Power dram during s3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index 48376ff8bdd..5efb74959f8 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -34,7 +34,7 @@ chip northbridge/intel/x4x # Northbridge irq 0x70 = 0 irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index 78ad8777152..8653cec2c56 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -106,9 +106,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 1, 0x0080 }, /* USB3 ETH top connector */ - { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 1, 0x0080 }, /* USB3 ETH bottom connector */ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 5f32d8b7cce..387a6674247 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -18,7 +18,7 @@ * with -bios option which neatly puts coreboot into flash and so payloads * can find CBFS and we don't risk overwriting CBFS. * - * Prior to Jul 2014 qemu aliased 0 to begining of RAM instead of flash + * Prior to Jul 2014 qemu aliased 0 to beginning of RAM instead of flash * and -bios was unusable as $pc pointed to 0 which was zero-filled as a * workaround we suggested using -kernel but this still had all the issues * of having fake-ROM in RAM. In fact it was even worse as fake ROM ends diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index a239590e1e6..e972f542618 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -2,7 +2,7 @@ /* * These are the qemu firmware config interface defines and structs. - * Copied over from qemu soure tree, + * Copied over from qemu source tree, * include/standard-headers/linux/qemu_fw_cfg.h and modified accordingly. */ #ifndef FW_CFG_IF_H diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 4a9a52fb421..ec86c70a3c8 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -16,7 +16,7 @@ static void bootblock_northbridge_init(void) * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index be995731ecb..cdd34a464e3 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -181,7 +181,7 @@ static const struct edp_data b101uan08_table[] = { {6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00} }, {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00} }, {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF} }, - /* Additional Settng for eDP */ + /* Additional Setting for eDP */ {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00} }, {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00} }, /* DPRX CAD Register Setting */ diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c51a5b901c6..5a81678f1f7 100644 --- a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex index 5007a26c9a1..f0dc7fb0d7c 100644 --- a/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index c3b71d6f8eb..2a03e0480fa 100644 --- a/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -38,7 +38,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 04 # 5 SDRAM Addressing diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 1df786db83c..8e2bbe8a255 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -202,7 +202,7 @@ static void setup_storage(void) static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c0(); exynos_pinmux_i2c1(); exynos_pinmux_i2c2(); @@ -222,7 +222,7 @@ static void gpio_init(void) gpio_direction_output(GPIO_X17, 1); gpio_direction_output(GPIO_X15, 1); - /* Set up the I2S busses. */ + /* Set up the I2S buses. */ exynos_pinmux_i2s0(); exynos_pinmux_i2s1(); } diff --git a/src/mainboard/google/foster/bct/jtag.cfg b/src/mainboard/google/foster/bct/jtag.cfg index e9bbd024a57..58186b23779 100644 --- a/src/mainboard/google/foster/bct/jtag.cfg +++ b/src/mainboard/google/foster/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set DebugCtrl to 1 to reenable Jtag +# Set DebugCtrl to 1 to re-enable Jtag # DebugCtrl = 0; # diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 5dddab5584d..3aafa9eeeb9 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -60,7 +60,7 @@ int pwm_enum_to_pwm_number[] = { void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) { int duty_ns, voltage_max, voltage_min; - int voltage = millivolt * 10; /* for higer calculation accuracy */ + int voltage = millivolt * 10; /* for higher calculation accuracy */ int pwm_number = pwm_enum_to_pwm_number[pwm]; voltage_min = pwm_design_voltage[pwm][0]; diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 260e9340bd8..381cbaaab81 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -80,7 +80,7 @@ chip soc/amd/cezanne register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index f78d42096d3..a84eabde5c7 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/cannonlake register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" - # SD card WP pin confguration + # SD card WP pin configuration register "ScsSdCardWpPinEnabled" = "0" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 59c49590a36..ffec6a5396b 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -117,7 +117,7 @@ static void mainboard_init(void *chip_info) gpios = variant_gpio_table(&num_gpios); gpio_configure_pads(gpios, num_gpios); - /* Initialize i2c busses that were not initialized in bootblock */ + /* Initialize i2c buses that were not initialized in bootblock */ i2c_soc_init(); /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */ diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 1816dafc4aa..728487a4316 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -7,7 +7,7 @@ static void prepare_usb(void) { /* * Do DWC3 core and phy reset. Kick these resets off early - * so they get atleast 1msec to settle. + * so they get at least 1msec to settle. */ reset_usb(HSUSB_HS_PORT_1); } diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 0e9dc1359c4..afbea9c7700 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -231,7 +231,7 @@ static void display_startup(void) static void mainboard_init(struct device *dev) { /* TP_SHIFT_EN: Enables the level shifter for I2C bus 4 (TPAD), which - * also contains the PS8640 eDP brige and the USB hub. + * also contains the PS8640 eDP bridge and the USB hub. */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) mt6391_gpio_output(MT6391_KP_ROW2, 1); diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 65bf286f08a..9ffd6337386 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -69,7 +69,7 @@ static void gpio_modification_by_ssfc(struct pad_config *table, size_t num) /* * Currently we only have the case of RT5682 as the second source. And * in case of Ampton which used RT5682 as the default source, it didn't - * provide override_table right now so it will be returned ealier since + * provide override_table right now so it will be returned earlier since * table above is NULL. */ if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682) diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 85b0cc0afc6..6878cadf972 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -324,7 +324,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index e6b83599966..63763b34aaa 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -25,7 +25,7 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index c279777e47f..9cefb81bf85 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -330,7 +330,7 @@ static void setup_storage(void) static void gpio_init(void) { - /* Set up the I2C busses. */ + /* Set up the I2C buses. */ exynos_pinmux_i2c2(); exynos_pinmux_i2c4(); exynos_pinmux_i2c7(); diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 4b1254da958..d588d575dc1 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -262,7 +262,7 @@ Scope (\_SB.PCI0.I2C2) * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) diff --git a/src/mainboard/google/smaug/bct/jtag.cfg b/src/mainboard/google/smaug/bct/jtag.cfg index 4f2c36c2231..c48e54a1918 100644 --- a/src/mainboard/google/smaug/bct/jtag.cfg +++ b/src/mainboard/google/smaug/bct/jtag.cfg @@ -1,5 +1,5 @@ # -# Set JtagCtrl to 1 to reenable Jtag +# Set JtagCtrl to 1 to re-enable Jtag # JtagCtrl = 0; # diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 8e2d8590a69..89958c92565 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include "acpi/platform.asl" #include "acpi/mainboard.asl" - // Thermal handeler + // Thermal handler #include "acpi/thermal.asl" // global NVS and variables diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 94767237350..68eb6ea5887 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -21,7 +21,7 @@ chip soc/amd/picasso }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -232,7 +232,7 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index ce0121593bb..4bb42dea1c9 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -19,7 +19,7 @@ chip soc/amd/picasso }" # Start : OPN Performance Configuration - # (Configuratin that is common for all variants) + # (Configuration that is common for all variants) # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time @@ -230,7 +230,7 @@ chip soc/amd/picasso register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - # genral purpose PCIe clock output configuration + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader register "gpp_clk_config[2]" = "GPP_CLK_OFF" diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 43ae7150ddf..3f7e5d1c340 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -49,7 +49,7 @@ void variant_touchscreen_update(void); void variant_pcie_gpio_configure(void); /* Per variant FSP-S initialization, default implementation in baseboard and - * overrideable by the variant. */ + * overridable by the variant. */ void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 389b44e1e19..f7821d0e98b 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -81,7 +81,7 @@ chip northbridge/intel/sandybridge device pnp 4e.609 off end # GPIO6 device pnp 4e.709 off end # GPIO7 device pnp 4e.a on end # ACPI - device pnp 4e.b on # HWM, front pannel LED + device pnp 4e.b on # HWM, front panel LED io 0x60 = 0xa30 io 0x62 = 0 # unused end diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 9b1aeb02529..5f945c1c337 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -129,7 +129,7 @@ chip northbridge/intel/x4x # Northbridge irq 0xe4 = 0x10 # Power dram during s3 irq 0xe6 = 0x8c end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0xa00 irq 0x70 = 0 end diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl index 26108a2592a..0d1158dd370 100644 --- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl +++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl @@ -108,7 +108,7 @@ Scope (\_SB.PCI0.I2C2) * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) @@ -613,7 +613,7 @@ Scope (\_SB.PCI0.I2C3) * AX1V: Auxiliary LDO1 VR voltage value * AX2V: Auxiliary LDO2 VR voltage value * ACVA: Analog LDO VR voltage - * DCVA: Core buck VR volatage + * DCVA: Core buck VR voltage */ OperationRegion (PWR2, 0xB1, Zero, 0x0100) Field (PWR2, DWordAcc, NoLock, Preserve) diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index 4d4b5789d3b..3f420c0d344 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -104,7 +104,7 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) } /** - * @brief Customer Overides Memory Table + * @brief Customer Overrides Memory Table * * Platform Specific Overriding Table allows IBV/OEM to pass in platform * information to AGESA diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 7365d748253..22c88e0c49c 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -144,7 +144,7 @@ Device (EC0) ^HKEY.MHKQ (0x6040) } - /* Lid openend */ + /* Lid opened */ Method (_Q2A, 0, NotSerialized) { LIDS = 1 diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 5d1e2613ba6..e35a70b8ae1 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -535,7 +535,7 @@ DefinitionBlock ( * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex index c51a5b901c6..5a81678f1f7 100644 --- a/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex +++ b/src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex index 5007a26c9a1..f0dc7fb0d7c 100644 --- a/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex +++ b/src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex @@ -39,7 +39,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 05 # 5 SDRAM Addressing diff --git a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex index c3b71d6f8eb..2a03e0480fa 100644 --- a/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex +++ b/src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex @@ -38,7 +38,7 @@ # 4 SDRAM CHIP Density and Banks # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) -# bits[7]: reserverd +# bits[7]: reserved 04 # 5 SDRAM Addressing diff --git a/src/mainboard/protectli/vault_bsw/romstage.c b/src/mainboard/protectli/vault_bsw/romstage.c index 07453525820..33519b9d424 100644 --- a/src/mainboard/protectli/vault_bsw/romstage.c +++ b/src/mainboard/protectli/vault_bsw/romstage.c @@ -12,7 +12,7 @@ void mainboard_after_memory_init(void) { /* - * FSP enables internal UART. Disable it and reenable Super I/O UART to + * FSP enables internal UART. Disable it and re-enable Super I/O UART to * prevent loss of debug information on serial. */ pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0); diff --git a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl index 72eaca4bebd..73255623073 100644 --- a/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl +++ b/src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl @@ -32,7 +32,7 @@ Device (EC) BIF0, 16, BDCP, 16, // BAT Design Capacity BFCP, 16, // BAT Full Capacity - BRCH, 16, // BAT Rechargable + BRCH, 16, // BAT Rechargeable BDVT, 16, // BAT Design Voltage BIF5, 16, BIF6, 16, diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl index 720f92f9747..fbe4173cb74 100644 --- a/src/mainboard/roda/rk9/acpi/ec.asl +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -42,7 +42,7 @@ Device(EC0) FDDI, 1, // floppy on lpt indicator? LIDC, 1, // LID switch Offset(0xd0), - TCPU, 8, // T_CPU in deg Celcius + TCPU, 8, // T_CPU in deg Celsius Offset(0xd6), /* exact purpose of these three is guessed, but it's something about cooling */ diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index 907edc1adf3..5c298468915 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -4,7 +4,7 @@ Scope (\_TZ) { - /* degree Celcius to deci-Kelvin (ACPI temperature unit) */ + /* degree Celsius to deci-Kelvin (ACPI temperature unit) */ Method(C2dK, 1) { Add (2732, Multiply (Arg0, 10), Local0) Return (Local0) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 02799d3f118..23220976dd9 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -35,7 +35,7 @@ static const char *northbridge_acpi_name(const struct device *dev) } /* - * TODO: We could determine how many PCIe busses we need in the bar. + * TODO: We could determine how many PCIe buses we need in the bar. * For now, that number is hardcoded to a max of 64. */ static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 51ee3203429..ac19fccfc8a 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -63,7 +63,7 @@ config MAXIMUM_SUPPORTED_FREQUENCY config CHECK_SLFRCS_ON_RESUME def_bool n help - On some boards it may be neccessary to hard reset early + On some boards it may be necessary to hard reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other boards the check always creates a false positive, diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 6610a3e38c9..241eb430212 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -22,7 +22,7 @@ void bootblock_early_northbridge_init(void) { /* * The QuickPath bus number is the topmost bus number, as per the value - * of the SAD_PCIEXBAR register. The register defaults to 256 busses on + * of the SAD_PCIEXBAR register. The register defaults to 256 buses on * reset. Thus, hardcode the bus number when first setting up PCIEXBAR. */ const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4b5f2b3a242..9ef491baedb 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2437,7 +2437,7 @@ int aggressive_write_training(ramctr_timing *ctrl) if (enable_iosav_opt) mchbar_write32(MCMNTS_SPARE, 1); - printram("Aggresive write training:\n"); + printram("Aggressive write training:\n"); for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) { FOR_ALL_POPULATED_CHANNELS { diff --git a/src/security/intel/cbnt/logging.c b/src/security/intel/cbnt/logging.c index 55354b4ce8c..514e5ac6660 100644 --- a/src/security/intel/cbnt/logging.c +++ b/src/security/intel/cbnt/logging.c @@ -123,7 +123,7 @@ void intel_cbnt_log_registers(void) LOG("SACM INFO MSR (0x13A) raw: 0x%016llx\n", acm_info.raw); LOG(" NEM status: %u\n", acm_info.nem_enabled); LOG(" TPM type: %s\n", tpm_type[acm_info.tpm_type]); - LOG(" TPM succes: %u\n", acm_info.tpm_success); + LOG(" TPM success: %u\n", acm_info.tpm_success); LOG(" FACB: %u\n", acm_info.facb); LOG(" measured boot: %u\n", acm_info.measured_boot); LOG(" verified boot: %u\n", acm_info.verified_boot); diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index e2fab0c063f..1ebe77d2f1a 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -668,7 +668,7 @@ bool stm_check_stm_image(void *stm_image, uint32_t stm_imagesize) /* * This function return BIOS STM resource. * Produced by SmmStm. - * Comsumed by SmmMpService when Init. + * Consumed by SmmMpService when Init. * * @return BIOS STM resource */ diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 2b7d92627c5..e3e2f5c4695 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -150,7 +150,7 @@ static struct acm_info_table *find_info_table(const void *ptr) } /** - * Validate that the provided ACM is useable on this platform. + * Validate that the provided ACM is usable on this platform. */ static int validate_acm(const void *ptr) { diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 557125dcf81..03c6f8bd75a 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -98,7 +98,7 @@ static void clear_memory(void *unused) __func__, (void *)pgtbl, (void *)vmem_addr); } - /* Now clear all useable DRAM */ + /* Now clear all usable DRAM */ memranges_each_entry(r, &mem) { if (range_entry_tag(r) != BM_MEM_RAM) continue; diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index e040d806116..ed642c33b59 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -55,7 +55,7 @@ uint32_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo, const char *name); /** - * Issue a TPM_Clear and reenable/reactivate the TPM. + * Issue a TPM_Clear and re-enable/reactivate the TPM. * @return TPM_SUCCESS on success. If not a tpm error is returned */ uint32_t tpm_clear_and_reenable(void); diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index f464fe19e7f..cfa533b880c 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -273,7 +273,7 @@ uint32_t tlcl_self_test_full(void) uint32_t tlcl_lock_nv_write(uint32_t index) { struct tpm2_response *response; - /* TPM Wll reject attempts to write at non-defined index. */ + /* TPM Will reject attempts to write at non-defined index. */ struct tpm2_nv_write_lock_cmd nv_wl = { .nvIndex = HR_NV_INDEX + index, }; @@ -372,7 +372,7 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size, if (!response) return TPM_E_NO_DEVICE; - /* Map TPM2 retrun codes into common vboot represenation. */ + /* Map TPM2 return codes into common vboot representation. */ switch (response->hdr.tpm_code) { case TPM2_RC_SUCCESS: return TPM_SUCCESS; diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h index ae0b7fdca53..3ae48eb4843 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.h +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.h @@ -28,7 +28,7 @@ int tpm_marshal_command(TPM_CC command, const void *tpm_command_body, * tpm_unmarshal_response * * Given a buffer received from the TPM in response to a certain command, - * deserialize the buffer into the expeced response structure. + * deserialize the buffer into the expected response structure. * * struct tpm2_response is a union of all possible responses. * From 26f97f9532933da3c1d72a7918c8a24457bbc1c0 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 1 Oct 2021 14:53:22 -0600 Subject: [PATCH 004/320] src/soc to src/superio: Fix spelling errors These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/fch.c | 2 +- src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 2 +- src/soc/amd/picasso/chip.h | 4 ++-- src/soc/amd/picasso/fch.c | 2 +- src/soc/amd/picasso/include/soc/platform_descriptors.h | 2 +- src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 2 +- src/soc/amd/stoneyridge/chip.h | 2 +- src/soc/amd/stoneyridge/northbridge.c | 8 ++++---- src/soc/cavium/cn81xx/bootblock_custom.S | 2 +- src/soc/intel/alderlake/acpi/tcss.asl | 2 +- src/soc/intel/apollolake/acpi/northbridge.asl | 4 ++-- src/soc/intel/apollolake/romstage.c | 2 +- src/soc/intel/baytrail/Kconfig | 2 +- src/soc/intel/braswell/northcluster.c | 2 +- src/soc/intel/broadwell/Kconfig | 2 +- src/soc/intel/cannonlake/chip.h | 2 +- src/soc/intel/common/Makefile.inc | 2 +- src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 +- src/soc/intel/common/block/fast_spi/fast_spi.c | 2 +- src/soc/intel/common/block/include/intelblocks/tcss.h | 2 +- src/soc/intel/common/block/pmc/Kconfig | 2 +- src/soc/intel/common/block/usb4/Kconfig | 2 +- src/soc/intel/denverton_ns/include/soc/pmc.h | 2 +- src/soc/intel/quark/Kconfig | 2 +- src/soc/intel/quark/chip.h | 2 +- src/soc/intel/quark/include/soc/QuarkNcSocId.h | 4 ++-- src/soc/intel/quark/reg_access.c | 2 +- src/soc/intel/quark/spi_debug.c | 2 +- src/soc/intel/skylake/acpi.c | 2 +- src/soc/intel/skylake/include/soc/nhlt.h | 2 +- src/soc/intel/tigerlake/acpi/tcss.asl | 2 +- src/soc/intel/xeon_sp/util.c | 2 +- src/soc/mediatek/common/include/soc/eint_event.h | 2 +- src/soc/mediatek/common/mmu_operations.c | 2 +- src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 2 +- src/soc/mediatek/mt8192/pll.c | 2 +- src/soc/mediatek/mt8195/pll.c | 2 +- src/soc/nvidia/tegra124/chip.h | 2 +- src/soc/nvidia/tegra124/dp.c | 2 +- src/soc/nvidia/tegra210/Kconfig | 2 +- src/soc/nvidia/tegra210/Makefile.inc | 2 +- src/soc/nvidia/tegra210/dp.c | 2 +- src/soc/nvidia/tegra210/include/soc/addressmap.h | 2 +- src/soc/nvidia/tegra210/mipi_dsi.c | 2 +- src/soc/nvidia/tegra210/sdram.c | 4 ++-- src/soc/qualcomm/ipq40xx/gpio.c | 4 ++-- src/soc/qualcomm/ipq40xx/spi.c | 4 ++-- src/soc/qualcomm/ipq806x/gpio.c | 4 ++-- src/soc/qualcomm/ipq806x/i2c.c | 2 +- src/soc/qualcomm/ipq806x/spi.c | 2 +- src/soc/qualcomm/ipq806x/uart.c | 2 +- src/soc/qualcomm/qcs405/spi.c | 2 +- src/soc/samsung/exynos5250/dmc_init_ddr3.c | 2 +- src/soc/samsung/exynos5250/include/soc/gpio.h | 2 +- src/soc/samsung/exynos5420/dmc_init_ddr3.c | 2 +- src/soc/sifive/fu540/ux00ddr.h | 6 +++--- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 2 +- src/southbridge/amd/cimx/sb800/acpi/fch.asl | 2 +- src/southbridge/amd/pi/hudson/acpi/fch.asl | 2 +- src/southbridge/intel/bd82x6x/azalia.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/i82371eb/acpi_tables.c | 2 +- src/southbridge/intel/i82371eb/smbus.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 2 +- src/southbridge/intel/i82801gx/azalia.c | 2 +- src/southbridge/intel/i82801ix/azalia.c | 2 +- src/southbridge/intel/i82801jx/azalia.c | 2 +- src/southbridge/intel/ibexpeak/azalia.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- src/southbridge/intel/lynxpoint/me_status.c | 2 +- src/southbridge/intel/lynxpoint/pch.h | 2 +- src/superio/acpi/pnp_config.asl | 2 +- src/superio/ite/it8772f/it8772f.h | 2 +- src/superio/winbond/w83627hf/acpi/superio.asl | 10 +++++----- 75 files changed, 91 insertions(+), 91 deletions(-) diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 80ce9466ec1..ac79cc9e115 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -127,7 +127,7 @@ static void fch_init_resets(void) pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); } -/* configure the genral purpose PCIe clock outputs according to the devicetree settings */ +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { const struct soc_amd_cezanne_config *cfg = config_of_soc(); diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index e948bca903b..292cdd83186 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -29,7 +29,7 @@ Name(CRES, ResourceTemplate() { * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 63898308e75..4fcd3f71a33 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -22,7 +22,7 @@ struct __packed usb2_phy_tune { uint8_t sq_rx_tune; /* FS/LS Source Impedance Adjustment. Range 0 - 0xF */ uint8_t tx_fsls_tune; - /* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */ + /* HS Transmitter Pre-Emphasis Current Control. Range 0 - 0x3 */ uint8_t tx_pre_emp_amp_tune; /* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */ uint8_t tx_pre_emp_pulse_tune; @@ -99,7 +99,7 @@ struct soc_amd_picasso_config { * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. * For example, should we need I2C0 and I2C3 have their peripheral - * devices reseted by toggling SCL, use: + * devices reset by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 711091c5c5c..44acc817ef1 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -175,7 +175,7 @@ static void al2ahb_clock_gate(void) write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); } -/* configure the genral purpose PCIe clock outputs according to the devicetree settings */ +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { const struct soc_amd_picasso_config *cfg = config_of_soc(); diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 28062b689ef..2ea35a940b6 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -7,7 +7,7 @@ #include #include -/* These tempory macros apply to emmc0_mode field in FSP_S_CONFIG. +/* These temporary macros apply to emmc0_mode field in FSP_S_CONFIG. * TODO: Remove when official definitions arrive. */ #define SD_DISABLE 0 #define SD_LOW_SPEED 1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 78ce889e5df..f7ea782da93 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -56,7 +56,7 @@ Name(CRES, ResourceTemplate() { * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 82c54371c55..b870baeb88b 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -46,7 +46,7 @@ struct soc_amd_stoneyridge_config { * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. * For example, should we need I2C0 and I2C3 have their peripheral - * devices reseted by toggling SCL, use: + * devices reset by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d80aeb2a092..d5231ad5d5c 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -400,19 +400,19 @@ void domain_read_resources(struct device *dev) reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); /* - * 0x100000 (1MiB) -> low top useable RAM + * 0x100000 (1MiB) -> low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ ram_resource(dev, idx++, (1 * MiB) / KiB, (mem_useable - (1 * MiB)) / KiB); - /* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */ + /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_resource(dev, idx++, mem_useable / KiB, (tom.lo - mem_useable) / KiB); /* If there is memory above 4GiB */ if (high_tom.hi) { - /* 4GiB -> high top useable */ + /* 4GiB -> high top usable */ if (uma_base >= (4ull * GiB)) high_mem_useable = uma_base; else @@ -422,7 +422,7 @@ void domain_read_resources(struct device *dev) ram_resource(dev, idx++, (4ull * GiB) / KiB, ((high_mem_useable - (4ull * GiB)) / KiB)); - /* High top useable RAM -> high top RAM */ + /* High top usable RAM -> high top RAM */ if (uma_base >= (4ull * GiB)) { reserved_ram_resource(dev, idx++, uma_base / KiB, uma_size / KiB); diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S index 03d91da948b..318c4d71b1c 100644 --- a/src/soc/cavium/cn81xx/bootblock_custom.S +++ b/src/soc/cavium/cn81xx/bootblock_custom.S @@ -130,7 +130,7 @@ ENTRY(_setup_car) thunder1_cache_setup: /** * Setup L2 cache to allow secure access to all of the address space - * thunder1 compability list: + * thunder1 compatibility list: * - CN81XX * - CN83XX * - CN88XX diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 82cbad63a81..81c2432f661 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -511,7 +511,7 @@ Scope (\_SB.PCI0) TACK, 1, /* [16:16] IOM Acknowledge bit */ DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ /* display is OFF, clear otherwise */ - Offset(0x70), /* Pyhsical addr is offset 0x70. */ + Offset(0x70), /* Physical addr is offset 0x70. */ IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ } diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 6a71900e7f0..f6b337c0f6a 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -18,7 +18,7 @@ Device (MCHC) Offset(0xB4), BGSM, 32, /* Base of Graphics Stolen Memory */ Offset(0xBC), - TLUD, 32, /* Top of Low Useable DRAM */ + TLUD, 32, /* Top of Low Usable DRAM */ } } @@ -58,7 +58,7 @@ Method (_CRS, 0, Serialized) * PCI MMIO Region (TOLUD - PCI extended base MMCONF) * This assumes that MMCONF is placed after PCI config space, * and that no resources are allocated after the MMCONF region. - * This works, sicne MMCONF is hardcoded to 0xe00000000. + * This works, since MMCONF is hardcoded to 0xe00000000. */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1c92b893472..c4d7977c41f 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -119,7 +119,7 @@ static bool punit_init(void) /* * Poll for bit 8 to check if PCODE has completed its action - * in reponse to BIOS Reset complete. + * in response to BIOS Reset complete. * We wait here till 1 ms for the bit to get set. */ stopwatch_init_msecs_expire(&sw, 1); diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index e5c003af08c..dca95e35180 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -136,7 +136,7 @@ config HAVE_REFCODE_BLOB bool "Use a binary refcode blob instead of native ModPHY init" default n help - Use the ChromeBook refcode to intitialize high-speed PHYs instead of + Use the ChromeBook refcode to initialize high-speed PHYs instead of native code. if HAVE_REFCODE_BLOB diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index b7ddee42b2c..76d532b5cb6 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -93,7 +93,7 @@ static void nc_read_resources(struct device *dev) if (fsp_reserved_memory_area) { fsp_res_base_k = RES_IN_KiB((unsigned int)fsp_reserved_memory_area); } else { - /* If no FSP reserverd area */ + /* If no FSP reserved area */ fsp_res_base_k = tseg_base_k; } diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index fbd7aea26b9..f02e810b232 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -23,7 +23,7 @@ config BROADWELL_VBOOT_IN_BOOTBLOCK Broadwell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. - Broadwell however uses a mrc.bin to initialse memory which + Broadwell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b8dfafde46c..774b5268dbb 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -436,7 +436,7 @@ struct soc_intel_cannonlake_config { * * In general descriptor provides option to set default cpu flex ratio. * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. - * Thats the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. * * Only override CPU flex ratio if don't want to boot with non-turbo max. */ diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 56e3336fd7b..ad987dddccc 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -41,7 +41,7 @@ MMA_TEST_CONFIG_NAMES = $(notdir $(wildcard $(MMA_BLOBS_PATH)/configs/*)) # $(3) is file type, efi for test names (all .EFI files under $(MMA_BLOBS_PATH)/tests ) # , mma for test param (all .BIN files under $(MMA_BLOBS_PATH)/configs/) # -# $(MMA_BLOBS_PATH)/tests/.efi has coresponding test params +# $(MMA_BLOBS_PATH)/tests/.efi has corresponding test params # at $(MMA_BLOBS_PATH)/configs//.bin # diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index f0c31498331..cac7854d349 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -545,7 +545,7 @@ program_sf2: /* * Calculate the SF Mask 1: - * 1. Calcuate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0] + * 1. Calculate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0] * 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: SFWayCnt = SFWayCnt / 2 * 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - IA32_CR_SF_QOS_MASK_2 */ diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 843071e2a81..93de2ecb872 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -325,7 +325,7 @@ static void fast_spi_enable_ext_bios(void) "Only 32MiB windows are supported for extended BIOS!"); #endif - /* Confgiure DMI Source decode for Extended BIOS Region */ + /* Configure DMI Source decode for Extended BIOS Region */ if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, soc_get_spi_dmi_destination_id()) == CB_ERR) return; diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 97d63af41a1..c07c96cd825 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -130,7 +130,7 @@ enum pmc_ipc_command_type { struct tcss_mux_info { bool dp; /* DP connected */ bool usb; /* USB connected */ - bool cable; /* Activ/Passive Cable */ + bool cable; /* Active/Passive Cable */ bool polarity; /* polarity of connected device */ bool hpd_lvl; /* HPD Level assert */ bool hpd_irq; /* HPD IRQ assert */ diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index aaf4479745e..e3978e29dd5 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -17,7 +17,7 @@ config SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE bool help Select this on platforms where the PMC device is discoverable - when scanning busses. + when scanning buses. config SOC_INTEL_COMMON_BLOCK_PMC_EPOC bool diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig index d4e1c25aa16..bc1eb19d49b 100644 --- a/src/soc/intel/common/block/usb4/Kconfig +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -25,4 +25,4 @@ config SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES depends on SOC_INTEL_COMMON_BLOCK_USB4 select PCIEXP_HOTPLUG help - Enable USB4 PCIe resources for reserving hotplug busses and memory. + Enable USB4 PCIe resources for reserving hotplug buses and memory. diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 512f7f5c647..fdb1028f1f8 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -11,7 +11,7 @@ #define MASK_PMC_ACPI_BASE 0xfffc #define PMC_ACPI_CNT 0x44 #define PMC_ACPI_CNT_PWRM_EN (1 << 8) /* PWRM enable */ -#define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI eanble */ +#define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI enable */ #define PMC_ACPI_CNT_SCIS ((1 << 2) | (1 << 1) | (1 << 0)) /* SCI IRQ select \ */ #define PMC_ACPI_CNT_SCIS_MASK 0x07 diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2d09f516a50..1a9bfef9429 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -222,7 +222,7 @@ config STORAGE_TEST select COMMONLIB_STORAGE select SDHCI_CONTROLLER help - Read block 0 from each parition of the storage device. User + Read block 0 from each partition of the storage device. User must also enable one or both of COMMONLIB_STORAGE_SD or COMMONLIB_STORAGE_MMC. diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 40e823ff920..7308712180f 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -87,7 +87,7 @@ struct soc_intel_quark_config { uint8_t DramDensity; uint8_t tCL; /* DRAM CAS Latency in clocks */ - /* ECC scrub interval in miliseconds 1..255 (0 works as feature + /* ECC scrub interval in milliseconds 1..255 (0 works as feature * disable) */ uint8_t EccScrubInterval; diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h index c7db8d50b93..e4015a2e7c7 100644 --- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -55,7 +55,7 @@ // // -// DEVICE 0 (Memroy Controller Hub) +// DEVICE 0 (Memory Controller Hub) // #define MC_BUS PCI_BUS_NUMBER_QNC #define MC_DEV 0x00 @@ -729,7 +729,7 @@ #define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset #define R_QNC_PCIE_SLCTL 0x58 //~ 59h #define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug intr enable -#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect enable +#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presence detect enable #define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attn Btn Pressed Enable #define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh #define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 86713987c05..604561ac477 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -69,7 +69,7 @@ static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) { uint32_t offset; - /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */ + /* Convert from MTRR index to host bridge offset (Datasheet 12.7.2) */ if (index == MTRR_CAP_MSR) offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; else if (index == MTRR_DEF_TYPE_MSR) diff --git a/src/soc/intel/quark/spi_debug.c b/src/soc/intel/quark/spi_debug.c index b24906515b2..a6b5e692ec1 100644 --- a/src/soc/intel/quark/spi_debug.c +++ b/src/soc/intel/quark/spi_debug.c @@ -79,7 +79,7 @@ void spi_display(volatile struct flash_ctrlr *ctrlr) printk(BIOS_DEBUG, "0x%08x: BIOS Base Address\n", ctrlr->bbar); /* Display the protection ranges */ - printk(BIOS_DEBUG, "BIOS Protected Range Regsiters\n"); + printk(BIOS_DEBUG, "BIOS Protected Range Registers\n"); for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) { status = ctrlr->pbr[index]; printk(BIOS_DEBUG, " %d: 0x%08x: 0x%08x - 0x%08x %s\n", diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 7e06ffa15d5..72c5e472de0 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -36,7 +36,7 @@ #define CPUID_6_EAX_ISST (1 << 7) /* - * List of suported C-states in this processor. + * List of supported C-states in this processor. */ enum { C_STATE_C0, /* 0 */ diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 3d128611390..dd2825590c8 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -30,7 +30,7 @@ enum { int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); /* - * Add nau88l25 headset codec on provided SSP link. Return 0 on succes, < 0 + * Add nau88l25 headset codec on provided SSP link. Return 0 on success, < 0 * on error. */ int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink); diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 98938339bf5..2a71b31cae9 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -511,7 +511,7 @@ Scope (\_SB.PCI0) TACK, 1, /* [16:16] IOM Acknowledge bit */ DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ /* display is OFF, clear otherwise */ - Offset(0x70), /* Pyhsical addr is offset 0x70. */ + Offset(0x70), /* Physical addr is offset 0x70. */ IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ } diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index ce0b1a6fc48..579ebbcfcda 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -168,7 +168,7 @@ void xeonsp_init_cpu_config(void) unsigned int num_sockets; /* - * sort APIC ids in asending order to identify apicid ranges for + * sort APIC ids in ascending order to identify apicid ranges for * each numa domain */ for (dev = all_devices; dev; dev = dev->next) { diff --git a/src/soc/mediatek/common/include/soc/eint_event.h b/src/soc/mediatek/common/include/soc/eint_event.h index 98db7b04e8f..6d544b4e7a9 100644 --- a/src/soc/mediatek/common/include/soc/eint_event.h +++ b/src/soc/mediatek/common/include/soc/eint_event.h @@ -6,7 +6,7 @@ #include #include -/* eint event mask cler register */ +/* eint event mask clear register */ struct eint_event_reg { uint32_t eint_event_mask_clr[7]; }; diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index 960d742d63d..340f9ec9893 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -50,6 +50,6 @@ void mtk_mmu_disable_l2c_sram(void) mtk_soc_disable_l2c_sram(); - /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ + /* Re-enable MMU with now enlarged L2 cache. Page tables still valid. */ mmu_enable(); } diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 009d03a1545..23a9403acf1 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -777,7 +777,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, * ISI 0 | 0 * AUD 0 | 1 * XTALK 1 | 0 - * UNKNOW 1 | 1 + * UNKNOWN 1 | 1 */ switch (testaudpat) { case XTALK: diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index f0a9509173f..e49e222c7ce 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -524,7 +524,7 @@ u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, CLK_MISC_CFG_0_METER_DIV, 0); } else { - die("unsupport fmeter type\n"); + die("unsupported fmeter type\n"); } /* enable frequency meter */ diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 74dd1509f31..8fd424dc49c 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -844,7 +844,7 @@ u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, CLK_MISC_CFG_0_METER_DIV, 0); } else { - die("unsupport fmeter type\n"); + die("unsupported fmeter type\n"); } /* enable frequency meter */ diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 0d1fb19dd2f..bc033c9f350 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -54,7 +54,7 @@ struct soc_nvidia_tegra124_config { /* Delay before from power on asserting vdd */ int vdd_delay_ms; - /* Delay beween pwm and backlight_en_gpio is asserted */ + /* Delay between pwm and backlight_en_gpio is asserted */ int pwm_to_bl_delay_ms; /* Delay before HPD high */ diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 4155c34b219..5da2c066f55 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -465,7 +465,7 @@ static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp, return (cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; } -/* Calcuate if given cfg can meet the mode request. */ +/* Calculate if given cfg can meet the mode request. */ /* Return true if mode is possible, false otherwise. */ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, const struct soc_nvidia_tegra124_config *config, diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 4fcbaffbee4..0244b47deff 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -79,7 +79,7 @@ config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE help - Map the UART names to the respective MMIO addres. + Map the UART names to the respective MMIO addresses. config BOOTROM_SDRAM_INIT bool "SoC BootROM does SDRAM init with full BCT" diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index f76ab347e03..5846be9809a 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -137,7 +137,7 @@ req_tz_size=$(shell expr $(ttb_size) + $(sec_size)) tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1) - $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be atleast as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") + $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be at least as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") endif # BL31 component is placed towards the end of 32-bit address space. This assumes diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index 9c55242765c..a2b06b160e5 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -477,7 +477,7 @@ static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp, return (link_cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; } -/* Calcuate if given cfg can meet the mode request. */ +/* Calculate if given cfg can meet the mode request. */ /* Return true if mode is possible, false otherwise. */ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, const struct soc_nvidia_tegra210_config *config, diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index 31ed4f256ca..bd9a25c3e61 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -94,7 +94,7 @@ enum { /* Return total size of DRAM memory configured on the platform. */ int sdram_size_mb(void); -/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */ +/* Find memory below and above 4GiB boundary respectively. All units 1MiB. */ void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib); void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib); diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c index cd1b822a059..067dc6d6187 100644 --- a/src/soc/nvidia/tegra210/mipi_dsi.c +++ b/src/soc/nvidia/tegra210/mipi_dsi.c @@ -193,7 +193,7 @@ ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd, /* * DCS long write packets contain the word count in the header * bytes 1 and 2 and have a payload containing the DCS command - * byte folowed by word count minus one bytes. + * byte followed by word count minus one bytes. * * DCS short write packets encode the DCS command and up to * one parameter in header bytes 1 and 2. diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index 8ffa0e500ab..702897f1aef 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -155,7 +155,7 @@ static void sdram_set_pad_macros(const struct sdram_params *param, /* * Program CMD mapping. Required before brick mapping, else - * we can't gaurantee CK will be differential at all times. + * we can't guarantee CK will be differential at all times. */ write32(®s->fbio_cfg7, param->EmcFbioCfg7); @@ -979,7 +979,7 @@ static void sdram_set_refresh(const struct sdram_params *param, /* Enable EMC pipe clock gating */ write32(®s->cfg_pipe_clk, param->EmcCfgPipeClk); - /* Depending on freqency, enable CMD/CLK fdpd */ + /* Depending on frequency, enable CMD/CLK fdpd */ write32(®s->fdpd_ctrl_cmd_no_ramp, param->EmcFdpdCtrlCmdNoRamp); } diff --git a/src/soc/qualcomm/ipq40xx/gpio.c b/src/soc/qualcomm/ipq40xx/gpio.c index e7874a786a7..8e248c50cdf 100644 --- a/src/soc/qualcomm/ipq40xx/gpio.c +++ b/src/soc/qualcomm/ipq40xx/gpio.c @@ -18,7 +18,7 @@ static inline int gpio_not_valid(gpio_t gpio) } /******************************************************* -Function description: configure GPIO functinality +Function description: configure GPIO functionality Arguments : gpio_t gpio - Gpio number unsigned func - Functionality number @@ -77,7 +77,7 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, } /******************************************************* -Function description: get GPIO IO functinality details +Function description: get GPIO IO functionality details Arguments : gpio_t gpio - Gpio number unsigned *in - Value of GPIO input diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index da7a6d35608..31677e460f3 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -328,7 +328,7 @@ static unsigned char spi_read_byte(struct ipq_spi_slave *ds) } /* - * Function to check wheather Input or Output FIFO + * Function to check whether Input or Output FIFO * has data to be serviced */ static int check_fifo_status(void *reg_addr) @@ -627,7 +627,7 @@ static int spi_ctrlr_setup(const struct spi_slave *slave) || ((bus == BLSP0_SPI) && (cs > 2)) || ((bus == BLSP1_SPI) && (cs > 0))) { printk(BIOS_ERR, - "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " + "SPI error: unsupported bus %d (Supported buses 0, 1 and 2) " "or chipselect\n", bus); return -1; } diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index e7874a786a7..8e248c50cdf 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -18,7 +18,7 @@ static inline int gpio_not_valid(gpio_t gpio) } /******************************************************* -Function description: configure GPIO functinality +Function description: configure GPIO functionality Arguments : gpio_t gpio - Gpio number unsigned func - Functionality number @@ -77,7 +77,7 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func, } /******************************************************* -Function description: get GPIO IO functinality details +Function description: get GPIO IO functionality details Arguments : gpio_t gpio - Gpio number unsigned *in - Value of GPIO input diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index ce420af46e7..cce7ed94c76 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -84,7 +84,7 @@ static int i2c_init(unsigned int bus) qup_config = &gsbi7_qup_config; break; default: - printk(BIOS_ERR, "QUP configuration not defind for GSBI%d.\n", + printk(BIOS_ERR, "QUP configuration not defined for GSBI%d.\n", gsbi_id); return 1; } diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 2b18bda6087..c538c279e89 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -758,7 +758,7 @@ static int spi_ctrlr_setup(const struct spi_slave *slave) || ((bus == GSBI6_SPI) && (cs > 0)) || ((bus == GSBI7_SPI) && (cs > 0))) { printk(BIOS_ERR, "SPI error: unsupported bus %d " - "(Supported busses 0,1 and 2) or chipselect\n", bus); + "(Supported buses 0,1 and 2) or chipselect\n", bus); } for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 3a3a8bf27b7..15a0998fb51 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -367,7 +367,7 @@ uint8_t uart_rx_byte(unsigned int idx) return byte; } -/* TODO: Implement fuction */ +/* TODO: Implement function */ void uart_fill_lb(void *data) { } diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 4607dc1ec39..e212b84421e 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -376,7 +376,7 @@ static unsigned char spi_read_byte(struct qcs_spi_slave *ds) } /* - * Function to check wheather Input or Output FIFO + * Function to check whether Input or Output FIFO * has data to be serviced */ static int check_fifo_status(void *reg_addr) diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index f4150203ea9..33725bcd6a4 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -124,7 +124,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, if (mem_reset) { /* Send NOP, MRS and ZQINIT commands. * Sending MRS command will reset the DRAM. We should not be - * reseting the DRAM after resume, this will lead to memory + * resetting the DRAM after resume, this will lead to memory * corruption as DRAM content is lost after DRAM reset */ dmc_config_mrs(mem, exynos_dmc); diff --git a/src/soc/samsung/exynos5250/include/soc/gpio.h b/src/soc/samsung/exynos5250/include/soc/gpio.h index 5a58b292f61..ede70d3b20a 100644 --- a/src/soc/samsung/exynos5250/include/soc/gpio.h +++ b/src/soc/samsung/exynos5250/include/soc/gpio.h @@ -546,7 +546,7 @@ int gpio_set_value(unsigned int gpio, int value); enum mvl3 { LOGIC_0, LOGIC_1, - LOGIC_Z, /* high impedence / tri-stated / floating */ + LOGIC_Z, /* high impedance / tri-stated / floating */ }; #endif /* CPU_SAMSUNG_EXYNOS5250_GPIO_H */ diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index b1eae898178..a187f6e090d 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -147,7 +147,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) if (reset) { /* Send NOP, MRS and ZQINIT commands. * Sending MRS command will reset the DRAM. We should not be - * reseting the DRAM after resume, this will lead to memory + * resetting the DRAM after resume, this will lead to memory * corruption as DRAM content is lost after DRAM reset. */ dmc_config_mrs(mem, exynos_drex0); diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h index 14a628d4415..cc675080dcd 100644 --- a/src/soc/sifive/fu540/ux00ddr.h +++ b/src/soc/sifive/fu540/ux00ddr.h @@ -82,14 +82,14 @@ static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) { static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) { // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status - // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured - // Bit [1] A memory access outside the defined PHYSICAL memory space has occured + // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occurred + // Bit [1] A memory access outside the defined PHYSICAL memory space has occurred _REG32(136<<2, ahbregaddr) |= ((1<progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 598c2dc7b21..7d9fc6d6afd 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -647,7 +647,7 @@ void mainboard_config_rcba(void); #define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET) #define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET) -/* Reigsters within the SPIBAR */ +/* Registers within the SPIBAR */ #define SSFC 0x91 #define FDOC 0xb0 #define FDOD 0xb4 diff --git a/src/superio/acpi/pnp_config.asl b/src/superio/acpi/pnp_config.asl index 0257cc7959e..7ce8fd5fc43 100644 --- a/src/superio/acpi/pnp_config.asl +++ b/src/superio/acpi/pnp_config.asl @@ -26,7 +26,7 @@ Mutex(CONF_MODE_MUTEX, 1) /* - * Enter configuration mode (and aquire mutex) + * Enter configuration mode (and acquire mutex) * Method must be run before accessing the configuration region. * Parameter is the LDN which should be accessed. Values >= 0xFF mean * no LDN switch should be done. diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 949ec116f5b..38cfe3b20ee 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -103,7 +103,7 @@ enum thermal_mode { /* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ #define GPIO_REG_POLARITY(x) (0xb0 + (x)) -/* GPIO Inernal Pull-up: 1: Enable, 0: Disable */ +/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ #define GPIO_REG_PULLUP(x) (0xb8 + (x)) /* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 5e23cb0a96d..20610301d6a 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -33,10 +33,10 @@ * NO_W83627HF_GAME: don't expose the game port * NO_W83627HF_MIDI: don't expose the MIDI port * NO_W83627HF_HWMON: don't expose the hardware monitor as - * PnP "Motherboard Ressource" + * PnP "Motherboard Resource" * W83627HF_KBC_COMPAT: show the keyboard controller and the PS/2 mouse as * enabled if it is disabled but an address is assigned - * to it. This may be neccessary in some cases. + * to it. This may be necessary in some cases. * * Datasheet: "W83627HF/F WINBOND I/O" rev. 6.0 * http://www.itox.com/pages/support/wdt/W83627HF.pdf @@ -115,14 +115,14 @@ Device(SIO) { Offset (0x74), DMA0, 8, /* DMA */ Offset (0xE0), - /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ + /* CRE0-CRE4: function logical device dependent, seems to be reserved for ACPI settings */ CRE0, 8, CRE1, 8, CRE2, 8, CRE3, 8, CRE4, 8, Offset (0xF0), - /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ + /* OPT1-OPTA aka CRF0-CRF9: function logical device dependent */ OPT1, 8, OPT2, 8, OPT3, 8, @@ -143,7 +143,7 @@ Device(SIO) { }) } - /* Enter configuration mode (and aquire mutex) + /* Enter configuration mode (and acquire mutex) Method must be run before accessing the configuration region. Parameter is the LDN which should be accessed. Values >= 0xFF mean no LDN switch should be done. From 9990866fcf9627a3ebf5724c9ed04d52104d22cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Oct 2021 21:05:20 +0200 Subject: [PATCH 005/320] drivers/intel/fsp2_0: don't force-use `python2` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some distributions (e.g. NixOS, Debian) are actively working on getting rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and Python 3 as of upstream commit 0bc2b07, use whatever version is present by utilizing `python`. Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Singer --- src/drivers/intel/fsp2_0/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 01b4c9ec1d1..92ebf24e5de 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -78,7 +78,7 @@ endif ifeq ($(CONFIG_FSP_FULL_FD),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG) - python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" + python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true From b2346a56f135924214761f55e6a3b9ff8056dee7 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 22 Sep 2021 14:56:51 -0600 Subject: [PATCH 006/320] arch/x86,cpu/x86: Introduce new method for accessing cpu_info There is currently a fundamental flaw in the current cpu_info() implementation. It assumes that current stack is CONFIG_STACK_SIZE aligned. This assumption breaks down when performing SMM relocation. The first step in performing SMM relocation is changing the SMBASE. This is accomplished by installing the smmstub at 0x00038000, which is the default SMM entry point. The stub is configured to set up a new stack with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point of smm_do_relocation located in RAMSTAGE RAM. This means that when smm_do_relocation is executed, it is running in SMM with a different sized stack. When cpu_info() gets called it will be using CONFIG_STACK_SIZE to calculate the location of the cpu_info struct. This results in reading random memory. Since cpu_info() has to run in multiple environments, we can't use a compile time constant to locate the cpu_info struct. This CL introduces a new way of locating cpu_info. It uses a per-cpu segment descriptor that points to a per-cpu segment that is allocated on the stack. By using a segment descriptor to point to the per-cpu data, we no longer need to calculate the location of the cpu_info struct. This has the following advantages: * Stacks no longer need to be CONFIG_STACK_SIZE aligned. * Accessing an unconfigured segment will result in an exception. This ensures no one can call cpu_info() from an unsupported environment. * Segment selectors are cleared when entering SMM and restored when leaving SMM. * There is a 1:1 mapping between cpu and cpu_info. When using COOP_MULTITASKING, a new cpu_info is currently allocated at the top of each thread's stack. This no longer needs to happen. This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so reviewers can feel more comfortable knowing most of the CL is a no-op. I would eventually like to remove most of the guards though. This CL does not touch the LEGACY_SMP_INIT code path. I don't have any way of testing it. The %gs segment was chosen over the %fs segment because it's what the linux kernel uses for per-cpu data in x86_64 mode. BUG=b:194391185, b:179699789 TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct %gs segment. Verify cpu_info looks sane. Verify booting to the OS works correctly with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627 Tested-by: build bot (Jenkins) Reviewed-by: Eric Peers Reviewed-by: Karthik Ramasubramanian --- src/arch/x86/c_start.S | 35 +++++++++++++++++++++++- src/arch/x86/include/arch/cpu.h | 29 ++++++++++++++++++++ src/cpu/x86/Kconfig | 8 ++++++ src/cpu/x86/cpu_info.S.inc | 47 +++++++++++++++++++++++++++++++++ src/cpu/x86/mp_init.c | 16 +++++++++-- src/cpu/x86/sipi_vector.S | 22 +++++++++++++++ src/cpu/x86/smm/smm_stub.S | 30 +++++++++++++++++++++ src/include/cpu/x86/gdt.h | 2 ++ 8 files changed, 186 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index cb7d5045ffb..9e718fcab05 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -80,6 +80,20 @@ _start: push_cpu_info +#if CONFIG(CPU_INFO_V2) + /* Allocate the per_cpu_segment_data on the stack */ + push_per_cpu_segment_data + + /* + * Update the BSP's per_cpu_segment_descriptor to point to the + * per_cpu_segment_data that was allocated on the stack. + */ + set_segment_descriptor_base $per_cpu_segment_descriptors, %esp + + mov per_cpu_segment_selector, %eax + mov %eax, %gs +#endif + /* * Now we are finished. Memory is up, data is copied and * bss is cleared. Now we call the main routine and @@ -127,6 +141,7 @@ gdb_stub_breakpoint: #endif .globl gdt, gdt_end + .global per_cpu_segment_descriptors, per_cpu_segment_selector gdtaddr: .word gdt_end - gdt - 1 @@ -136,7 +151,7 @@ gdtaddr: .long gdt /* we know the offset */ #endif - .data + .data /* This is the gdt for GCC part of coreboot. * It is different from the gdt in ASM part of coreboot @@ -206,8 +221,26 @@ gdt: .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0xaf, 0x00 #endif +#if CONFIG(CPU_INFO_V2) +per_cpu_segment_descriptors: + .rept CONFIG_MAX_CPUS + /* flat data segment */ + .word 0xffff, 0x0000 +#if ENV_X86_64 + .byte 0x00, 0x92, 0xcf, 0x00 +#else + .byte 0x00, 0x93, 0xcf, 0x00 +#endif + .endr +#endif /* CPU_INFO_V2 */ gdt_end: +#if CONFIG(CPU_INFO_V2) +/* Segment selector pointing to the first per_cpu_segment_descriptor. */ +per_cpu_segment_selector: + .long per_cpu_segment_descriptors - gdt +#endif /* CPU_INFO_V2 */ + .section ".text._start", "ax", @progbits #if ENV_X86_64 SetCodeSelector: diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index f736a147fef..8e96fae2c2b 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -236,11 +236,40 @@ struct cpu_info { #endif }; +/* + * This structure describes the data allocated in the %gs segment for each CPU. + * In order to read from this structure you will need to use assembly to + * reference the segment. + * + * e.g., Reading the cpu_info pointer: + * %%gs:0 + */ +struct per_cpu_segment_data { + /* + * Instead of keeping a `struct cpu_info`, we actually keep a pointer + * pointing to the cpu_info struct located in %ds. This prevents + * needing specific access functions to read the fields in the cpu_info. + */ + struct cpu_info *cpu_info; +}; + static inline struct cpu_info *cpu_info(void) { +/* We use a #if because we don't want to mess with the &s below. */ +#if CONFIG(CPU_INFO_V2) + struct cpu_info *ci = NULL; + + __asm__("mov %%gs:%c[offset], %[ci]" + : [ci] "=r" (ci) + : [offset] "i" (offsetof(struct per_cpu_segment_data, cpu_info)) + ); + + return ci; +#else char s; uintptr_t info = ALIGN_UP((uintptr_t)&s, CONFIG_STACK_SIZE) - sizeof(struct cpu_info); return (struct cpu_info *)info; +#endif /* CPU_INFO_V2 */ } struct cpuinfo_x86 { diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index a5c2a4df47c..99e33bb570f 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -193,3 +193,11 @@ config RESERVE_MTRRS_FOR_OS the system BIOS and the last 2 are to be reserved for OS usage. However, modern OSes use PAT to control cacheability instead of using MTRRs. + +config CPU_INFO_V2 + bool + depends on PARALLEL_MP + help + Enables the new method of locating struct cpu_info. This new method + uses the %gs segment to locate the cpu_info pointer. The old method + relied on the stack being CONFIG_STACK_SIZE aligned. diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc index 62b47ca52a5..dffd1bc3467 100644 --- a/src/cpu/x86/cpu_info.S.inc +++ b/src/cpu/x86/cpu_info.S.inc @@ -8,3 +8,50 @@ push \index /* index */ push $0 /* *cpu */ .endm + +/* Push struct per_cpu_segment_data */ +.macro push_per_cpu_segment_data cpu_info_pointer=%esp + push \cpu_info_pointer /* *cpu_info */ +.endm + +/* + * Sets the base address in the segment descriptor array. + * + * A segment descriptor has the following structure: + * struct { + * uint16_t segment_limit_0_15; + * uint16_t base_address_0_15; + * uint8_t base_address_16_23; + * uint8_t attrs[2]; + * uint8_t base_address_24_31; + * }; + * + * @desc_array: Address of the descriptor table + * @base: Address to set in the descriptor + * @desc_index: Index of the descriptor in the table. Defaults to 0. Must be a + * register if specified. + * + * Clobbers %eax. + */ +.macro set_segment_descriptor_base desc_array:req, base:req, desc_index + mov \base, %eax + + push %ebx /* preserve ebx */ + mov \desc_array, %ebx + +.ifb \desc_index + movw %ax, 2(%ebx) + shr $16, %eax + movb %al, 4(%ebx) + shr $8, %eax + movb %al, 7(%ebx) +.else + movw %ax, 2(%ebx, \desc_index, 8) + shr $16, %eax + movb %al, 4(%ebx, \desc_index, 8) + shr $8, %eax + movb %al, 7(%ebx, \desc_index, 8) +.endif + + pop %ebx +.endm diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 93c143ec85c..123b2b5eb5c 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -89,6 +89,8 @@ struct sipi_params { uint32_t gdt; uint16_t unused; uint32_t idt_ptr; + uint32_t per_cpu_segment_descriptors; + uint32_t per_cpu_segment_selector; uint32_t stack_top; uint32_t stack_size; uint32_t microcode_lock; /* 0xffffffff means parallel loading. */ @@ -215,10 +217,20 @@ static void setup_default_sipi_vector_params(struct sipi_params *sp) sp->gdt = (uintptr_t)&gdt; sp->gdtlimit = (uintptr_t)&gdt_end - (uintptr_t)&gdt - 1; sp->idt_ptr = (uintptr_t)&idtarg; + if (CONFIG(CPU_INFO_V2)) { + sp->per_cpu_segment_descriptors = (uintptr_t)&per_cpu_segment_descriptors; + sp->per_cpu_segment_selector = per_cpu_segment_selector; + } sp->stack_size = CONFIG_STACK_SIZE; sp->stack_top = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE); - /* Adjust the stack top to take into account cpu_info. */ - sp->stack_top -= sizeof(struct cpu_info); + /* + * In the CPU_INFO_V2 case, we don't need to pre-allocate the space on the stack. + * Instead we push them onto the top of the stack in the sipi vector. + */ + if (!CONFIG(CPU_INFO_V2)) { + /* Adjust the stack top to take into account cpu_info. */ + sp->stack_top -= sizeof(struct cpu_info); + } } #define NUM_FIXED_MTRRS 11 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 496fd345ebf..491f1de4354 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -19,6 +20,10 @@ gdtaddr: .word 0 /* unused */ idt_ptr: .long 0 +per_cpu_segment_descriptors: +.long 0 +per_cpu_segment_selector: +.long 0 stack_top: .long 0 stack_size: @@ -98,6 +103,23 @@ _start: movl stack_top, %edx subl %eax, %edx mov %edx, %esp + +#if CONFIG(CPU_INFO_V2) + push_cpu_info index=%ecx + push_per_cpu_segment_data + + /* + * Update the AP's per_cpu_segment_descriptor to point to the + * per_cpu_segment_data that was allocated on the stack. + */ + set_segment_descriptor_base per_cpu_segment_descriptors, %esp, %ecx + + mov %ecx, %eax + shl $3, %eax /* The index is << 3 in the segment selector */ + add per_cpu_segment_selector, %eax + mov %eax, %gs +#endif + andl $0xfffffff0, %esp /* ensure stack alignment */ /* Save CPU number. */ diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index aa48ab69ec2..e409983eaee 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -9,6 +9,7 @@ * found in smm.h. */ +#include #include #include #include @@ -82,8 +83,21 @@ smm_relocate_gdt: /* gdt selector 0x20 tss segment */ .word 0xffff, 0x0000 .byte 0x00, 0x8b, 0x80, 0x00 + +#if CONFIG(CPU_INFO_V2) +per_cpu_segment_descriptors: + .rept CONFIG_MAX_CPUS + /* selgdt 0x28, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + .endr +#endif /* CPU_INFO_V2 */ smm_relocate_gdt_end: +#if CONFIG(CPU_INFO_V2) +.set per_cpu_segment_selector, per_cpu_segment_descriptors - smm_relocate_gdt +#endif /* CPU_INFO_V2 */ + .align 4 .code32 .global smm_trampoline32 @@ -153,6 +167,22 @@ apicid_end: movl $0, 4(%ebx) #endif +#if CONFIG(CPU_INFO_V2) + push_cpu_info index=%ecx + push_per_cpu_segment_data + + /* + * Update the AP's per_cpu_segment_descriptor to point to the + * per_cpu_segment_data that was allocated on the stack. + */ + set_segment_descriptor_base $per_cpu_segment_descriptors, %esp, %ecx + + mov %ecx, %eax + shl $3, %eax /* The index is << 3 in the segment selector */ + add $per_cpu_segment_selector, %eax + mov %eax, %gs +#endif + /* Create stack frame by pushing a NULL stack base pointer */ pushl $0x0 mov %esp, %ebp diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h index bc4eaad0ca0..27a863ee330 100644 --- a/src/include/cpu/x86/gdt.h +++ b/src/include/cpu/x86/gdt.h @@ -5,6 +5,8 @@ /* These symbols are defined in c_start.S. */ extern char gdt[]; +extern char per_cpu_segment_descriptors[]; +extern uint32_t per_cpu_segment_selector; extern char gdt_end[]; extern char idtarg[]; From c842c59b3eb8f9df42779bf9bf8fdd2c4136319c Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Mon, 13 Sep 2021 14:24:55 -0600 Subject: [PATCH 007/320] lib/thread: Switch to using CPU_INFO_V2 CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1 cpu_info struct per cpu. This means that we no longer need to allocate it at the top of each threads stack. We can now in theory remove the CONFIG_STACK_SIZE alignment on the thread stack sizes. We can also in theory use threads in SMM if you are feeling venturesome. BUG=b:194391185, b:179699789 TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628 Tested-by: build bot (Jenkins) Reviewed-by: Eric Peers Reviewed-by: Karthik Ramasubramanian --- src/Kconfig | 2 +- src/lib/thread.c | 27 +++++---------------------- 2 files changed, 6 insertions(+), 23 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 09bc22dad16..ea05215bdd4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -677,7 +677,7 @@ config TIMER_QUEUE config COOP_MULTITASKING def_bool n - depends on TIMER_QUEUE && ARCH_X86 + depends on TIMER_QUEUE && ARCH_X86 && CPU_INFO_V2 help Cooperative multitasking allows callbacks to be multiplexed on the main thread of ramstage. With this enabled it allows for multiple diff --git a/src/lib/thread.c b/src/lib/thread.c index 2ff09a50d5d..ac8460c964d 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -36,28 +36,17 @@ static struct thread all_threads[TOTAL_NUM_THREADS]; static struct thread *runnable_threads; static struct thread *free_threads; -static inline struct cpu_info *thread_cpu_info(const struct thread *t) -{ - return (void *)(t->stack_orig); -} - static inline int thread_can_yield(const struct thread *t) { return (t != NULL && t->can_yield > 0); } -/* Assumes current CPU info can switch. */ -static inline struct thread *cpu_info_to_thread(const struct cpu_info *ci) -{ - return ci->thread; -} - static inline struct thread *current_thread(void) { if (!initialized) return NULL; - return cpu_info_to_thread(cpu_info()); + return cpu_info()->thread; } static inline int thread_list_empty(struct thread **list) @@ -94,21 +83,12 @@ static inline struct thread *pop_runnable(void) static inline struct thread *get_free_thread(void) { struct thread *t; - struct cpu_info *ci; - struct cpu_info *new_ci; if (thread_list_empty(&free_threads)) return NULL; t = pop_thread(&free_threads); - ci = cpu_info(); - - /* Initialize the cpu_info structure on the new stack. */ - new_ci = thread_cpu_info(t); - *new_ci = *ci; - new_ci->thread = t; - /* Reset the current stack value to the original. */ t->stack_current = t->stack_orig; @@ -134,6 +114,7 @@ __noreturn static enum cb_err idle_thread(void *unused) static void schedule(struct thread *t) { struct thread *current = current_thread(); + struct cpu_info *ci = cpu_info(); /* If t is NULL need to find new runnable thread. */ if (t == NULL) { @@ -148,6 +129,8 @@ static void schedule(struct thread *t) if (t->handle) t->handle->state = THREAD_STARTED; + ci->thread = t; + switch_to_thread(t->stack_current, ¤t->stack_current); } @@ -279,7 +262,7 @@ static void threads_initialize(void) t->id = 0; t->can_yield = 1; - stack_top = &thread_stacks[CONFIG_STACK_SIZE] - sizeof(struct cpu_info); + stack_top = &thread_stacks[CONFIG_STACK_SIZE]; for (i = 1; i < TOTAL_NUM_THREADS; i++) { t = &all_threads[i]; t->stack_orig = (uintptr_t)stack_top; From 968f140ecbde7bbf71b6b71d392bb0db97ccf64e Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 18 Aug 2021 11:06:57 -0600 Subject: [PATCH 008/320] Revert "soc/amd/cezanne: Disable Co-op multitasking" This reverts commit 5f80e7c764b9a1cb46beeaa490a4f60be04abcd4. The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2 into this patch to satisfy the dependency. BUG=b:194391185, b:179699789 TEST=reboot stress test guybrush for 50 iterations. Signed-off-by: Raul E Rangel Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894 Tested-by: build bot (Jenkins) Reviewed-by: Eric Peers Reviewed-by: Karthik Ramasubramanian --- src/soc/amd/cezanne/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 487b9f5b79f..ae2f61f983f 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -16,8 +16,10 @@ config SOC_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select CPU_INFO_V2 select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE + select COOP_MULTITASKING select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA @@ -30,6 +32,7 @@ config SOC_SPECIFIC_OPTIONS select IDT_IN_EVERY_STAGE select IOAPIC select PARALLEL_MP_AP_WORK + select PAYLOAD_PRELOAD select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK From db16ac95789d5ecc736c586c261c5e87358b718b Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 24 Sep 2021 14:00:56 -0600 Subject: [PATCH 009/320] lib/thread: Remove thread stack alignment requirement CPU_INFO_V2 now encapsulates the cpu_info requirements. They no longer need to leak through to thread.c. This allows us to remove the alignment requirement. BUG=b:179699789 TEST=Reboot stress test guybrush 50 times. Signed-off-by: Raul E Rangel Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef Reviewed-on: https://review.coreboot.org/c/coreboot/+/57928 Tested-by: build bot (Jenkins) Reviewed-by: Eric Peers Reviewed-by: Karthik Ramasubramanian --- src/lib/thread.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/src/lib/thread.c b/src/lib/thread.c index ac8460c964d..9008147eaeb 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -11,16 +11,7 @@ #include #include -/* Can't use the IS_POWER_OF_2 in _Static_assert */ -_Static_assert((CONFIG_STACK_SIZE & (CONFIG_STACK_SIZE - 1)) == 0, - "`cpu_info()` requires the stack size to be a power of 2"); - -/* - * struct cpu_info lives at the top of each thread's stack. `cpu_info()` locates this struct by - * taking the current stack pointer and masking off CONFIG_STACK_SIZE. This requires the stack - * to be STACK_SIZE aligned. - */ -static u8 thread_stacks[CONFIG_STACK_SIZE * CONFIG_NUM_THREADS] __aligned(CONFIG_STACK_SIZE); +static u8 thread_stacks[CONFIG_STACK_SIZE * CONFIG_NUM_THREADS] __aligned(sizeof(uint64_t)); static bool initialized; static void idle_thread_init(void); @@ -90,6 +81,9 @@ static inline struct thread *get_free_thread(void) t = pop_thread(&free_threads); /* Reset the current stack value to the original. */ + if (!t->stack_orig) + die("%s: Invalid stack value\n", __func__); + t->stack_current = t->stack_orig; return t; @@ -250,15 +244,10 @@ static void threads_initialize(void) if (initialized) return; - /* `cpu_info()` requires the stacks to be STACK_SIZE aligned */ - assert(IS_ALIGNED((uintptr_t)thread_stacks, CONFIG_STACK_SIZE)); - - /* Initialize the BSP thread first. The cpu_info structure is assumed - * to be just under the top of the stack. */ t = &all_threads[0]; ci = cpu_info(); ci->thread = t; - t->stack_orig = (uintptr_t)ci; + t->stack_orig = (uintptr_t)NULL; /* We never free the main thread */ t->id = 0; t->can_yield = 1; From c6e2552ce6f97033f0da735e53407fd5663d2816 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 30 Sep 2021 18:14:09 +0530 Subject: [PATCH 010/320] soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch ensures to pass cse device function number as argument for `set_cse_device_state()` to allow coreboot to perform enable/disable of D0i3 bit for all CSE devices to put the CSE device to Idle state or Active state. BUG=b:200644229 TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is able to put the CSE device toidle state or active state based on `devfn` as argument. Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/58039 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/cse.c | 73 +++++++++---------- src/soc/intel/common/block/cse/cse_eop.c | 5 +- .../common/block/include/intelblocks/cse.h | 4 +- 3 files changed, 41 insertions(+), 41 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d3b7d9ba13a..471bc1b341a 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __SIMPLE_DEVICE__ + #include #include #include @@ -65,11 +67,11 @@ #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) /* Get HECI BAR 0 from PCI configuration space */ -static uintptr_t get_cse_bar(void) +static uintptr_t get_cse_bar(pci_devfn_t dev) { uintptr_t bar; - bar = pci_read_config32(PCH_DEV_CSE, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); assert(bar != 0); /* * Bits 31-12 are the base address as per EDS for SPI, @@ -85,15 +87,12 @@ static uintptr_t get_cse_bar(void) */ void heci_init(uintptr_t tempbar) { -#if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_CSE; -#else - struct device *dev = PCH_DEV_CSE; -#endif + u16 pcireg; /* Assume it is already initialized, nothing else to do */ - if (get_cse_bar()) + if (get_cse_bar(dev)) return; /* Use default pre-ram bar */ @@ -114,29 +113,29 @@ void heci_init(uintptr_t tempbar) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -static uint32_t read_bar(uint32_t offset) +static uint32_t read_bar(pci_devfn_t dev, uint32_t offset) { - return read32p(get_cse_bar() + offset); + return read32p(get_cse_bar(dev) + offset); } -static void write_bar(uint32_t offset, uint32_t val) +static void write_bar(pci_devfn_t dev, uint32_t offset, uint32_t val) { - return write32p(get_cse_bar() + offset, val); + return write32p(get_cse_bar(dev) + offset, val); } static uint32_t read_cse_csr(void) { - return read_bar(MMIO_CSE_CSR); + return read_bar(PCH_DEV_CSE, MMIO_CSE_CSR); } static uint32_t read_host_csr(void) { - return read_bar(MMIO_HOST_CSR); + return read_bar(PCH_DEV_CSE, MMIO_HOST_CSR); } static void write_host_csr(uint32_t data) { - write_bar(MMIO_HOST_CSR, data); + write_bar(PCH_DEV_CSE, MMIO_HOST_CSR, data); } static size_t filled_slots(uint32_t data) @@ -170,12 +169,12 @@ static void clear_int(void) static uint32_t read_slot(void) { - return read_bar(MMIO_CSE_CB_RW); + return read_bar(PCH_DEV_CSE, MMIO_CSE_CB_RW); } static void write_slot(uint32_t val) { - write_bar(MMIO_CSE_CB_WW, val); + write_bar(PCH_DEV_CSE, MMIO_CSE_CB_WW, val); } static int wait_write_slots(size_t cnt) @@ -887,16 +886,16 @@ void cse_trigger_vboot_recovery(enum csme_failure_reason reason) die("cse: Failed to trigger recovery mode(recovery subcode:%d)\n", reason); } -static bool disable_cse_idle(void) +static bool disable_cse_idle(pci_devfn_t dev) { struct stopwatch sw; - uint32_t dev_idle_ctrl = read_bar(MMIO_CSE_DEVIDLE); + uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); dev_idle_ctrl &= ~CSE_DEV_IDLE; - write_bar(MMIO_CSE_DEVIDLE, dev_idle_ctrl); + write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); stopwatch_init_usecs_expire(&sw, HECI_CIP_TIMEOUT_US); do { - dev_idle_ctrl = read_bar(MMIO_CSE_DEVIDLE); + dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); if ((dev_idle_ctrl & CSE_DEV_CIP) == CSE_DEV_CIP) return true; udelay(HECI_DELAY_US); @@ -905,51 +904,51 @@ static bool disable_cse_idle(void) return false; } -static void enable_cse_idle(void) +static void enable_cse_idle(pci_devfn_t dev) { - uint32_t dev_idle_ctrl = read_bar(MMIO_CSE_DEVIDLE); + uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); dev_idle_ctrl |= CSE_DEV_IDLE; - write_bar(MMIO_CSE_DEVIDLE, dev_idle_ctrl); + write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); } -enum cse_device_state get_cse_device_state(void) +enum cse_device_state get_cse_device_state(unsigned int devfn) { - uint32_t dev_idle_ctrl = read_bar(MMIO_CSE_DEVIDLE); + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); if ((dev_idle_ctrl & CSE_DEV_IDLE) == CSE_DEV_IDLE) return DEV_IDLE; return DEV_ACTIVE; } -static enum cse_device_state ensure_cse_active(void) +static enum cse_device_state ensure_cse_active(pci_devfn_t dev) { - if (!disable_cse_idle()) + if (!disable_cse_idle(dev)) return DEV_IDLE; - pci_or_config32(PCH_DEV_CSE, PCI_COMMAND, PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); + pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); return DEV_ACTIVE; } -static void ensure_cse_idle(void) +static void ensure_cse_idle(pci_devfn_t dev) { - enable_cse_idle(); + enable_cse_idle(dev); - pci_and_config32(PCH_DEV_CSE, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER)); + pci_and_config32(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); } -bool set_cse_device_state(enum cse_device_state requested_state) +bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state) { - enum cse_device_state current_state = get_cse_device_state(); + enum cse_device_state current_state = get_cse_device_state(devfn); + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); if (current_state == requested_state) return true; if (requested_state == DEV_ACTIVE) - return ensure_cse_active() == requested_state; + return ensure_cse_active(dev) == requested_state; else - ensure_cse_idle(); + ensure_cse_idle(dev); return true; } diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index c9bbfff5868..1f544694b62 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -174,13 +175,13 @@ static void handle_cse_eop_result(enum cse_eop_result result) static void set_cse_end_of_post(void *unused) { - set_cse_device_state(DEV_ACTIVE); + set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); timestamp_add_now(TS_ME_BEFORE_END_OF_POST); handle_cse_eop_result(cse_send_eop()); timestamp_add_now(TS_ME_AFTER_END_OF_POST); - set_cse_device_state(DEV_IDLE); + set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); } /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c00e227c8d7..076f29465c3 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -287,9 +287,9 @@ enum cse_device_state { }; /* Function to get the current CSE device state as per `cse_device_state` */ -enum cse_device_state get_cse_device_state(void); +enum cse_device_state get_cse_device_state(unsigned int devfn); /* Function that put the CSE into desired state based on `requested_state` */ -bool set_cse_device_state(enum cse_device_state requested_state); +bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state); #endif // SOC_INTEL_COMMON_CSE_H From 3710e9972bc9e35e8389bb3b47d443e3c5e01859 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 30 Sep 2021 16:59:09 +0530 Subject: [PATCH 011/320] soc/intel/common: Helper function to check CSE device `devfn` status This patch creates a helper function in cse common code block to check the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and CSE_4. Currently cse common code is only able to read the device state of `PCH_DEVFN_CSE` CSE device alone. Additionally, print `slot` and 'func' number of CSE devices in case the device is either disable or hidden. BUG=b:200644229 TEST=Able to build and boot ADLRVP-P with this patch where the serial message listed the CSE devices that are disabled in the device tree as below: HECI: CSE device 16.01 is disabled HECI: CSE device 16.04 is disabled HECI: CSE device 16.05 is disabled Signed-off-by: Subrata Banik Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/cse.c | 18 ++++++++++++------ .../common/block/include/intelblocks/cse.h | 6 ++++++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 471bc1b341a..e41e3375501 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -581,23 +581,29 @@ int heci_reset(void) return 0; } -bool is_cse_enabled(void) +bool is_cse_devfn_visible(unsigned int devfn) { - const struct device *cse_dev = pcidev_path_on_root(PCH_DEVFN_CSE); + int slot = PCI_SLOT(devfn); + int func = PCI_FUNC(devfn); - if (!cse_dev || !cse_dev->enabled) { - printk(BIOS_WARNING, "HECI: No CSE device\n"); + if (!is_devfn_enabled(devfn)) { + printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is disabled\n", slot, func); return false; } - if (pci_read_config16(PCH_DEV_CSE, PCI_VENDOR_ID) == 0xFFFF) { - printk(BIOS_WARNING, "HECI: CSE device is hidden\n"); + if (pci_read_config16(PCI_DEV(0, slot, func), PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is hidden\n", slot, func); return false; } return true; } +bool is_cse_enabled(void) +{ + return is_cse_devfn_visible(PCH_DEVFN_CSE); +} + uint32_t me_read_config32(int offset) { return pci_read_config32(PCH_DEV_CSE, offset); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 076f29465c3..f162d485fde 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -152,6 +152,12 @@ void heci_disable(void); /* Reads config value from a specified offset in the CSE PCI Config space. */ uint32_t me_read_config32(int offset); +/* + * Check if the CSE device as per function argument `devfn` is enabled in device tree + * and also visible on the PCI bus. + */ +bool is_cse_devfn_visible(unsigned int devfn); + /* * Check if the CSE device is enabled in device tree. Also check if the device * is visible on the PCI bus by reading config space. From 78e66ad63b41316d268d33e1a68eeffe06b85baf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 30 Sep 2021 20:32:50 +0530 Subject: [PATCH 012/320] soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS `heci_finalize` ensures to put all heci devices to D3 by setting the D0i3 bit prior to booting to the OS. BUG=b:200644229 TEST=Verified D0i3 bit is set for all HECI devices prior to booting to OS. Signed-off-by: Subrata Banik Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58040 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/finalize.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 6e2406ae53e..c821e25769f 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -90,6 +91,23 @@ static void sa_finalize(void) sa_lock_pam(); } +static void heci_finalize(void) +{ + unsigned int cse_dev[] = { + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4 + }; + + for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) { + if (!is_cse_devfn_visible(cse_dev[i])) + continue; + + set_cse_device_state(cse_dev[i], DEV_IDLE); + } +} + static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); @@ -98,6 +116,7 @@ static void soc_finalize(void *unused) apm_control(APM_CNT_FINALIZE); tbt_finalize(); sa_finalize(); + heci_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); From d6da4ef69e4ec8decbaee41297c3a96686021567 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 7 Oct 2021 00:39:31 +0530 Subject: [PATCH 013/320] soc/intel/alderlake: Skip setting D0I3 bit for HECI devices This patch skips setting D0I3 bit for all HECI devices by FSP. BUG=b:200644229 TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is set to `1`. Change-Id: I86d61c49b8f187611efd495712ad901184665f31 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/fsp_params.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 4ae25371cbd..333957f2eaa 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -599,6 +599,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { + /* Skip setting D0I3 bit for all HECI devices */ + s_cfg->DisableD0I3SettingForHeci = 1; /* * Power Optimizer for DMI * DmiPwrOptimizeDisable is default to 0. From 89d8260e3f64a0aa9117f5d39a92743146048348 Mon Sep 17 00:00:00 2001 From: Derek Huang Date: Mon, 27 Sep 2021 14:31:26 +0800 Subject: [PATCH 014/320] include/device: Generic interface for USB-C mux operations Create a generic interface to allow any of the EC or other drivers to provide set of USB-C mux operations. Signed-off-by: Derek Huang Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58002 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/include/device/usbc_mux.h | 69 +++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 src/include/device/usbc_mux.h diff --git a/src/include/device/usbc_mux.h b/src/include/device/usbc_mux.h new file mode 100644 index 00000000000..e395d2dd628 --- /dev/null +++ b/src/include/device/usbc_mux.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* struct to hold all USB-C mux related variables */ +struct usbc_mux_info { + bool dp; /* DP connected */ + bool usb; /* USB connected */ + bool cable; /* 0 = Passive cable, 1 = Active cable */ + bool polarity; /* Polarity of connected device. 0 = Normal, 1 = Flipped */ + bool hpd_lvl; /* HPD Level assert */ + bool hpd_irq; /* HPD IRQ assert */ + bool ufp; /* 0 = DFP, 1 = UFP */ + bool dbg_acc; /* Debug Accessory. 0 = Disable, 1 = Enable */ + uint8_t dp_pin_mode; /* DP pin assignments + 0h: Reserved. + 1h: Pin Assignment A. + 2h: Pin Assignment B. + 3h: Pin Assignment C. + 4h: Pin Assignment D. + 5h: Pin Assignment E. + 6h: Pin Assignment F. + 7-Fh: Reserved. */ +}; +struct usbc_mux_ops { + /* + * Get mux information on a given port. + * + * Return value: + * -1 = error + * 0 = success + */ + int (*get_mux_info)(int port, struct usbc_mux_info *info); +}; + +struct usbc_dp_ops { + /* + * Wait up to `timeout_ms` for DP connection to be ready on any available port. + * + * Return value: + * -1 = error + * 0 = no DP connection + * = mask for ports that are ready in DP mode. + */ + int (*wait_for_connection)(long timeout_ms); + + /* + * Enter DP mode on a given `port`. + * + * Return value: + * -1 = error + * 0 = success + */ + int (*enter_dp_mode)(int port); + + /* + * Wait up to `timeout_ms` for HPD on a given port. + * + * Return value: + * -1 = timeout + * 0 = success + */ + int (*wait_for_hpd)(int port, long timeout_ms); +}; + +struct usbc_ops { + struct usbc_mux_ops mux_ops; + struct usbc_dp_ops dp_ops; +}; + +const struct usbc_ops *usbc_get_ops(void); From f1f9b3d5f5661fda4176b05528b37cb8951785c3 Mon Sep 17 00:00:00 2001 From: Derek Huang Date: Wed, 29 Sep 2021 16:39:01 +0800 Subject: [PATCH 015/320] ec/google/chromeec: Update google_chromeec_usb_pd_control() Add parameter `active_cable` to obtain the cable type (active or passive) which is needed for USB-C configuration for some SoCs (at least Intel TGL and ADL), change the function name to google_chromeec_usb_pd_get_info() for better understanding. BUG=b:192947843 Signed-off-by: Derek Huang Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58057 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec.c | 4 +++- src/ec/google/chromeec/ec.h | 4 ++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 29d04119b87..650fd14fec3 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1477,7 +1477,8 @@ int google_ec_running_ro(void) return (google_chromeec_get_current_image() == EC_IMAGE_RO); } -int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode) +int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, + bool *active_cable, uint8_t *dp_mode) { struct ec_params_usb_pd_control pd_control = { .port = port, @@ -1501,6 +1502,7 @@ int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t * *ufp = (resp.cc_state == PD_CC_DFP_ATTACHED); *dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC); + *active_cable = !!(resp.control_flags & USB_PD_CTRL_ACTIVE_CABLE); *dp_mode = resp.dp_mode; return 0; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 743651b0f99..ebb7ae24a13 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -34,8 +34,8 @@ int google_chromeec_pd_get_amode(uint16_t svid); */ int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); /* Returns data role and type of device connected */ -int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, - uint8_t *dp_mode); +int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, + bool *active_cable, uint8_t *dp_mode); int google_chromeec_wait_for_displayport(long timeout); /* Device events */ From c0f005a5d6e26c29bd1379163b890331ba8b38d0 Mon Sep 17 00:00:00 2001 From: Derek Huang Date: Wed, 29 Sep 2021 17:38:31 +0800 Subject: [PATCH 016/320] ec/google/chromeec: Update some PD and DisplayPort APIs 1. Update google_chromeec_pd_get_amode() to return bitmask. 2. Update google_chromeec_wait_for_displayport() to handle the updated return value of google_chromeec_pd_get_amode(). 3. Drop google_chromeec_pd_get_amode() from ec.h and make it static because it's not used outside of ec.c. BUG=b:192947843 Signed-off-by: Derek Huang Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58058 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec.c | 35 ++++++++++++++++++++++++----------- src/ec/google/chromeec/ec.h | 7 +++++-- 2 files changed, 29 insertions(+), 13 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 650fd14fec3..9086693770e 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1542,9 +1542,10 @@ int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags) * Check if EC/TCPM is in an alternate mode or not. * * @param svid SVID of the alternate mode to check - * @return 0: Not in the mode. -1: Error. 1: Yes. + * @return 0: Not in the mode. -1: Error. + * >=1: bitmask of the ports that are in the mode. */ -int google_chromeec_pd_get_amode(uint16_t svid) +static int google_chromeec_pd_get_amode(uint16_t svid) { struct ec_response_usb_pd_ports resp; struct chromeec_command cmd = { @@ -1557,6 +1558,7 @@ int google_chromeec_pd_get_amode(uint16_t svid) .cmd_dev_index = 0, }; int i; + int ret = 0; if (google_chromeec_command(&cmd) < 0) return -1; @@ -1582,12 +1584,12 @@ int google_chromeec_pd_get_amode(uint16_t svid) if (google_chromeec_command(&cmd) < 0) return -1; if (resp2.svid == svid) - return 1; + ret |= BIT(i); svid_idx++; } while (resp2.svid); } - return 0; + return ret; } #define USB_SID_DISPLAYPORT 0xff01 @@ -1595,20 +1597,31 @@ int google_chromeec_pd_get_amode(uint16_t svid) /** * Wait for DisplayPort to be ready * - * @param timeout Wait aborts after ms. - * @return 1: Success or 0: Timeout. + * @param timeout_ms Wait aborts after ms. + * @return -1: Error. 0: Timeout. + * >=1: Bitmask of the ports that DP device is connected */ -int google_chromeec_wait_for_displayport(long timeout) +int google_chromeec_wait_for_displayport(long timeout_ms) { struct stopwatch sw; + int ret = 0; printk(BIOS_INFO, "Waiting for DisplayPort\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (google_chromeec_pd_get_amode(USB_SID_DISPLAYPORT) != 1) { + stopwatch_init_msecs_expire(&sw, timeout_ms); + while (1) { + ret = google_chromeec_pd_get_amode(USB_SID_DISPLAYPORT); + if (ret > 0) + break; + + if (ret < 0) { + printk(BIOS_ERR, "Can't get alternate mode!\n"); + return ret; + } + if (stopwatch_expired(&sw)) { printk(BIOS_WARNING, "DisplayPort not ready after %ldms. Abort.\n", - timeout); + timeout_ms); return 0; } mdelay(200); @@ -1616,7 +1629,7 @@ int google_chromeec_wait_for_displayport(long timeout) printk(BIOS_INFO, "DisplayPort ready after %lu ms\n", stopwatch_duration_msecs(&sw)); - return 1; + return ret; } int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index ebb7ae24a13..6fa58a9a1e8 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -26,7 +26,6 @@ bool google_chromeec_is_uhepi_supported(void); int google_ec_running_ro(void); enum ec_image google_chromeec_get_current_image(void); void google_chromeec_init(void); -int google_chromeec_pd_get_amode(uint16_t svid); /* Check for the current mux state in EC * in: int port physical port number of the type-c port * out: uint8_t flags representing the status of the mux such as @@ -36,7 +35,11 @@ int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); /* Returns data role and type of device connected */ int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, bool *active_cable, uint8_t *dp_mode); -int google_chromeec_wait_for_displayport(long timeout); +/* Poll (up to `timeout_ms` ms) for DisplayPort to be ready + * Return: -1: Error. 0: Timeout. + * >=1: Bitmask of the ports that DP device is connected + */ +int google_chromeec_wait_for_displayport(long timeout_ms); /* Device events */ uint64_t google_chromeec_get_device_enabled_events(void); From c0bd123408680d3d7b0bb2c64acd103e2f13ec17 Mon Sep 17 00:00:00 2001 From: Derek Huang Date: Wed, 25 Aug 2021 17:19:39 +0800 Subject: [PATCH 017/320] ec/google/chromeec: Add APIs for USB-C DP ALT mode Add API to allow AP to send the command to EC to enter DP ALT mode and API to wait for DP HPD event. BUG=b:192947843 TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build coreboot and update your system. Boot the system you will find below message in the coreboot log with or without USB-C display connected: 'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'. Signed-off-by: Derek Huang Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec.c | 46 +++++++++++++++++++++++++++++++++++++ src/ec/google/chromeec/ec.h | 8 +++++++ 2 files changed, 54 insertions(+) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 9086693770e..5a8e4f6cd30 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1508,6 +1508,33 @@ int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, return 0; } +int google_chromeec_typec_control_enter_dp_mode(int port) +{ + if (!google_chromeec_check_feature(EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY)) + return 0; + + struct ec_params_typec_control typec_control = { + .port = port, + .command = TYPEC_CONTROL_COMMAND_ENTER_MODE, + .mode_to_enter = TYPEC_MODE_DP, + }; + + struct chromeec_command cmd = { + .cmd_code = EC_CMD_TYPEC_CONTROL, + .cmd_version = 0, + .cmd_data_in = &typec_control, + .cmd_size_in = sizeof(typec_control), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + return 0; +} + /** * Check for the current mux state in EC. Flags representing the mux state found * in ec_commands.h @@ -1632,6 +1659,25 @@ int google_chromeec_wait_for_displayport(long timeout_ms) return ret; } +int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms) +{ + uint8_t mux_flags; + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + do { + google_chromeec_usb_get_pd_mux_info(port, &mux_flags); + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, "HPD not ready after %ldms. Abort.\n", timeout_ms); + return -1; + } + mdelay(100); + } while (!(mux_flags & USB_PD_MUX_HPD_LVL) || !(mux_flags & USB_PD_MUX_DP_ENABLED)); + printk(BIOS_INFO, "HPD ready after %lu ms\n", stopwatch_duration_msecs(&sw)); + + return 0; +} + int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd) { struct chromeec_command cmd = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 6fa58a9a1e8..a06dfa19c05 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -40,6 +40,14 @@ int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, * >=1: Bitmask of the ports that DP device is connected */ int google_chromeec_wait_for_displayport(long timeout_ms); +/* Poll (up to `timeout_ms` ms) for a Hot-Plug Detect (HPD) + * event on the specified port. + * Return: 0 on HPD ready, -1 on timeout */ +int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms); +/* Send command to EC to request to enter DisplayPort ALT mode on the + * specified port. + * Return: 0 on success, -1 on error */ +int google_chromeec_typec_control_enter_dp_mode(int port); /* Device events */ uint64_t google_chromeec_get_device_enabled_events(void); From 63ffc1adc0407be878019e33e2ae38e72d00a65e Mon Sep 17 00:00:00 2001 From: Derek Huang Date: Wed, 29 Sep 2021 21:59:45 +0800 Subject: [PATCH 018/320] ec/google/chromeec: Add new API for USB-C mux handling Add google_chromeec_get_usbc_mux_info() to obtain USB-C mux related information. BUG=b:192947843 Signed-off-by: Derek Huang Change-Id: Idc27f23214c2d5b91334ae3efe248100329964ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/58059 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec.c | 36 ++++++++++++++++++++++++++++++++++++ src/ec/google/chromeec/ec.h | 8 ++++++++ 2 files changed, 44 insertions(+) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5a8e4f6cd30..e27ad9e938e 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1565,6 +1565,42 @@ int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags) return 0; } +/* + * Obtain any USB-C mux data needed for the specified port + * in: physical port number of the type-c port + * out: struct usbc_mux_info mux_info stores USB-C mux data + * Return: 0 on success, -1 on error +*/ +int google_chromeec_get_usbc_mux_info(int port, struct usbc_mux_info *mux_info) +{ + uint8_t mux_flags; + uint8_t dp_pin_mode; + bool ufp, dbg_acc, active_cable; + + if (google_chromeec_usb_get_pd_mux_info(port, &mux_flags) < 0) { + printk(BIOS_ERR, "Port C%d: get_pd_mux_info failed\n", port); + return -1; + } + + if (google_chromeec_usb_pd_get_info(port, &ufp, &dbg_acc, + &active_cable, &dp_pin_mode) < 0) { + printk(BIOS_ERR, "Port C%d: pd_control failed\n", port); + return -1; + } + + mux_info->usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED); + mux_info->dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED); + mux_info->polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED); + mux_info->hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ); + mux_info->hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL); + mux_info->ufp = !!ufp; + mux_info->dbg_acc = !!dbg_acc; + mux_info->cable = !!active_cable; + mux_info->dp_pin_mode = dp_pin_mode; + + return 0; +} + /** * Check if EC/TCPM is in an alternate mode or not. * diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index a06dfa19c05..f4090fe9417 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -9,6 +9,7 @@ #include #include #include "ec_commands.h" +#include /* Fill in base and size of the IO port resources used. */ void google_chromeec_ioport_range(uint16_t *base, size_t *size); @@ -48,6 +49,13 @@ int google_chromeec_wait_for_dp_hpd(int port, long timeout_ms); * specified port. * Return: 0 on success, -1 on error */ int google_chromeec_typec_control_enter_dp_mode(int port); +/* + * Obtain any USB-C mux data needed for the specified port + * in: int port physical port number of the type-c port + * out: struct usbc_mux_info mux_info stores USB-C mux data + * Return: 0 on success, -1 on error + */ +int google_chromeec_get_usbc_mux_info(int port, struct usbc_mux_info *mux_info); /* Device events */ uint64_t google_chromeec_get_device_enabled_events(void); From 796ea820f2f97546775917b8a80d602bb7361740 Mon Sep 17 00:00:00 2001 From: Derek Huang Date: Wed, 29 Sep 2021 22:05:04 +0800 Subject: [PATCH 019/320] ec/google/chromeec: Update google_chromeec_usb_pd_get_info() google_chromeec_usb_pd_get_info() is used in ec.c only. Make it static and drop from ec.h. BUG=b:192947843 Signed-off-by: Derek Huang Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58060 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec.c | 3 ++- src/ec/google/chromeec/ec.h | 3 --- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index e27ad9e938e..642c31385ae 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1477,7 +1477,8 @@ int google_ec_running_ro(void) return (google_chromeec_get_current_image() == EC_IMAGE_RO); } -int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, +/* Returns data role and type of device connected */ +static int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, bool *active_cable, uint8_t *dp_mode) { struct ec_params_usb_pd_control pd_control = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f4090fe9417..131a46067eb 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -33,9 +33,6 @@ void google_chromeec_init(void); * usb capability, dp capability, cable type, etc */ int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); -/* Returns data role and type of device connected */ -int google_chromeec_usb_pd_get_info(int port, bool *ufp, bool *dbg_acc, - bool *active_cable, uint8_t *dp_mode); /* Poll (up to `timeout_ms` ms) for DisplayPort to be ready * Return: -1: Error. 0: Timeout. * >=1: Bitmask of the ports that DP device is connected From 1a368769b905ff5ed2a2ca9ddc1c473f8a2b44ad Mon Sep 17 00:00:00 2001 From: Derek Huang Date: Thu, 30 Sep 2021 21:20:02 +0800 Subject: [PATCH 020/320] ec/google/chromeec: Register USB-C mux operations Register USB-C mux operations to the generic interface. BUG=b:192947843 Signed-off-by: Derek Huang Change-Id: I576c9e4c6c82d6b4055b0a0a9a75c677d4b05220 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58061 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/Makefile.inc | 2 +- src/ec/google/chromeec/usbc_mux.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 src/ec/google/chromeec/usbc_mux.c diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index cb3b97e610a..23e7b3d479c 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -20,7 +20,7 @@ endif bootblock-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c -ramstage-y += ec.c crosec_proto.c vstore.c +ramstage-y += ec.c crosec_proto.c vstore.c usbc_mux.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c diff --git a/src/ec/google/chromeec/usbc_mux.c b/src/ec/google/chromeec/usbc_mux.c new file mode 100644 index 00000000000..64195428b09 --- /dev/null +++ b/src/ec/google/chromeec/usbc_mux.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct usbc_ops google_chromeec_usbc_ops = { + .mux_ops = { + .get_mux_info = google_chromeec_get_usbc_mux_info, + }, + .dp_ops = { + .wait_for_connection = google_chromeec_wait_for_displayport, + .enter_dp_mode = google_chromeec_typec_control_enter_dp_mode, + .wait_for_hpd = google_chromeec_wait_for_dp_hpd, + }, +}; + +const struct usbc_ops *usbc_get_ops(void) +{ + return &google_chromeec_usbc_ops; +} From 86b0609c2871a5e73f0db7013f0cf00e1cb3fc26 Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Tue, 6 Apr 2021 17:01:05 +0530 Subject: [PATCH 021/320] sc7280: Enable bootblock compression This patch enables bootblock compression on SC7280. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Ref link: https://review.coreboot.org/c/coreboot/+/45855 BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0 Signed-off-by: Ravi Kumar Bokka Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/soc/qualcomm/sc7280/Kconfig | 1 + src/soc/qualcomm/sc7280/Makefile.inc | 3 +++ src/soc/qualcomm/sc7280/decompressor.c | 9 +++++++++ 3 files changed, 13 insertions(+) create mode 100644 src/soc/qualcomm/sc7280/decompressor.c diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index fad3040dcf8..a65a3eea376 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -13,6 +13,7 @@ config SOC_QUALCOMM_SC7280 select SOC_QUALCOMM_COMMON select CACHE_MRC_SETTINGS select HAS_RECOVERY_MRC_CACHE + select COMPRESS_BOOTBLOCK if SOC_QUALCOMM_SC7280 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index c4e3f3ea042..420e0cad600 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -1,5 +1,8 @@ ifeq ($(CONFIG_SOC_QUALCOMM_SC7280),y) +decompressor-y += decompressor.c +decompressor-y += mmu.c +decompressor-y += ../common/timer.c all-y += ../common/timer.c all-y += ../common/gpio.c all-y += ../common/clock.c diff --git a/src/soc/qualcomm/sc7280/decompressor.c b/src/soc/qualcomm/sc7280/decompressor.c new file mode 100644 index 00000000000..3108b044d20 --- /dev/null +++ b/src/soc/qualcomm/sc7280/decompressor.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void decompressor_soc_init(void) +{ + sc7280_mmu_init(); +} From acd2218bc320de57d2b6eb5d2829fa5dba027785 Mon Sep 17 00:00:00 2001 From: Roja Rani Yarubandi Date: Mon, 9 Nov 2020 18:41:24 +0530 Subject: [PATCH 022/320] libpayload: Enable UART driver for sc7280 Add Qualcomm's QUPV3 serial driver for herobrine board BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Change-Id: I3a745afd7bbabdd29f1f369612c990526e5a2335 Signed-off-by: Roja Rani Yarubandi Reviewed-on: https://review.coreboot.org/c/coreboot/+/47527 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- payloads/libpayload/configs/config.herobrine | 1 + 1 file changed, 1 insertion(+) diff --git a/payloads/libpayload/configs/config.herobrine b/payloads/libpayload/configs/config.herobrine index e87f71af109..18ca19dc003 100644 --- a/payloads/libpayload/configs/config.herobrine +++ b/payloads/libpayload/configs/config.herobrine @@ -2,3 +2,4 @@ CONFIG_LP_CHROMEOS=y CONFIG_LP_ARCH_ARM64=y CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y From c003ea6d2b33f4ecb091aa631569792a287043a0 Mon Sep 17 00:00:00 2001 From: Rajesh Patil Date: Fri, 18 Jun 2021 09:16:01 +0530 Subject: [PATCH 023/320] sc7280: Enable UART driver Enable common Uart driver on sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil Change-Id: I015e21081391bfe85edf667685bf117401a9ec00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963 Reviewed-by: Julius Werner Reviewed-by: Shelley Chen Tested-by: build bot (Jenkins) --- src/soc/qualcomm/sc7280/Kconfig | 7 +++++++ src/soc/qualcomm/sc7280/Makefile.inc | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index a65a3eea376..24d5c207b48 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -14,6 +14,7 @@ config SOC_QUALCOMM_SC7280 select CACHE_MRC_SETTINGS select HAS_RECOVERY_MRC_CACHE select COMPRESS_BOOTBLOCK + select HAVE_UART_SPECIAL if SOC_QUALCOMM_SC7280 @@ -36,4 +37,10 @@ config BOOT_DEVICE_SPI_FLASH_BUS int default 16 +config UART_FOR_CONSOLE + int + default 5 + help + Select the QUP instance to be used for UART console output. + endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 420e0cad600..9214152964a 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -20,15 +20,21 @@ all-y += ../common/qupv3_spi.c bootblock-y += bootblock.c bootblock-y += mmu.c bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart_bitbang.c + +################################################################################ +verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c + ################################################################################ romstage-y += cbmem.c romstage-y += ../common/qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c +romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ ramstage-y += soc.c ramstage-y += cbmem.c +ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ From fba1475f25948aebd0590436e33bb266d6e714d9 Mon Sep 17 00:00:00 2001 From: Dmitry Ponamorev Date: Wed, 15 Sep 2021 03:28:52 -0700 Subject: [PATCH 024/320] soc/intel/denverton_ns: Always enable SpeedStep MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When "SpeedStep" is disabled on an Intel Atom C3538, the maximum CPU clock speed is always 800 MHz(min CPU clock). Оperating system cannot change the frequency. Avoid this issue allow "Intel Speed step" technology for processors that do not have "Intel Turbo Boost". Signed-off-by: Dmitry Ponamorev Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57669 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Angel Pons Reviewed-by: King Sumo --- src/soc/intel/denverton_ns/cpu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 10e79be3b5d..95f164d1c54 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -90,12 +90,10 @@ static void denverton_core_init(struct device *cpu) /* Enable Turbo */ enable_turbo(); - /* Enable speed step. */ - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= SPEED_STEP_ENABLE_BIT; - wrmsr(IA32_MISC_ENABLE, msr); - } + /* Enable speed step. Always ON.*/ + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= SPEED_STEP_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); } static struct device_operations cpu_dev_ops = { From a78ab4b0af72240fa4dba5a520c635d44b97eff2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Oct 2021 17:46:45 +0200 Subject: [PATCH 025/320] soc/intel/dnv_ns: correct size of GPE0 registers in FADT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC code sets a GPE0 block size of 4 byte length instead of 32 byte. The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit instead of 256 bit). Drop the overrides and let common ACPI code set the correct values based on `GPE0_REG_MAX`. Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/soc/intel/denverton_ns/acpi.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index aa59aa8c813..574d106fa00 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -101,7 +101,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) /* Control Registers - Length */ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -149,14 +148,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; } static acpi_tstate_t denverton_tss_table[] = { From 2a634ab560089a43dee0a22fcf67e42135238300 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Mon, 4 Oct 2021 13:38:51 +0800 Subject: [PATCH 026/320] security/vboot: Remove vb2ex_hwcrypto stubs Now that the vb2ex_hwcrypto_* stub functions are included in vboot fwlib (CL:2353775), we can remove the same stubs from coreboot. BUG=none TEST=emerge-brya coreboot TEST=emerge-cherry coreboot BRANCH=none Change-Id: I62bdc647eb3e34c581cc1b8d15e7f271211e6156 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/58095 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Werner Zeh --- src/security/vboot/vboot_logic.c | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index ff93d0b7641..91d42b2c7f8 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -54,27 +54,6 @@ vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, return VB2_SUCCESS; } -/* No-op stubs that can be overridden by SoCs with hardware crypto support. */ -__weak vb2_error_t vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, - uint32_t data_size) -{ - return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; -} - -__weak vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, - uint32_t size) -{ - BUG(); /* Should never get called if init() returned an error. */ - return VB2_ERROR_UNKNOWN; -} - -__weak vb2_error_t vb2ex_hwcrypto_digest_finalize(uint8_t *digest, - uint32_t digest_size) -{ - BUG(); /* Should never get called if init() returned an error. */ - return VB2_ERROR_UNKNOWN; -} - static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) { int is_resume; From 4dc9e5b3c71ba85e3aa19a98c58a86194a3fd8f5 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 3 Oct 2021 12:02:49 +0200 Subject: [PATCH 027/320] soc/intel/cannonlake: Enable x86_64 support Select HAVE_EXP_X86_64_SUPPORT. Tested on prodrive/hermes: Boots into Linux. Change-Id: I033ccd5dc793b637a2ac4271b450335464564885 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/58089 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel --- src/soc/intel/cannonlake/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 88c914d06c8..227f680bcca 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -7,6 +7,7 @@ config SOC_INTEL_COFFEELAKE select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select HAVE_EXP_X86_64_SUPPORT config SOC_INTEL_WHISKEYLAKE bool From 5afeba30a3637792d8619d52572f95b3e80e76fb Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Mon, 4 Jan 2021 14:28:14 +0530 Subject: [PATCH 028/320] sc7280: Add SHRM firmware support SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/mainboard/google/herobrine/romstage.c | 2 ++ .../common/include/soc/symbols_common.h | 1 + src/soc/qualcomm/sc7280/Makefile.inc | 9 ++++++++ src/soc/qualcomm/sc7280/include/soc/shrm.h | 8 +++++++ src/soc/qualcomm/sc7280/memlayout.ld | 2 ++ src/soc/qualcomm/sc7280/shrm_load_reset.c | 22 +++++++++++++++++++ 6 files changed, 44 insertions(+) create mode 100644 src/soc/qualcomm/sc7280/include/soc/shrm.h create mode 100644 src/soc/qualcomm/sc7280/shrm_load_reset.c diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index 64aeaaad147..ad2d2a0c467 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -3,9 +3,11 @@ #include #include #include "board.h" +#include void platform_romstage_main(void) { + shrm_fw_load_reset(); /* QCLib: DDR init & train */ qclib_load_and_run(); diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index 60c1069aa1d..953acc26576 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -23,5 +23,6 @@ DECLARE_REGION(dram_modem_wifi_only) DECLARE_REGION(dram_modem_extra) DECLARE_REGION(dram_wlan) DECLARE_REGION(dram_wpss) +DECLARE_REGION(shrm) #endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_ diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 9214152964a..364c987dc60 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -26,6 +26,7 @@ verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ romstage-y += cbmem.c +romstage-y += shrm_load_reset.c romstage-y += ../common/qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c @@ -101,4 +102,12 @@ $(I2C_FW_CBFS)-type := raw $(I2C_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) cbfs-files-y += $(I2C_FW_CBFS) +################################################################################ +SHRM_FILE := $(SC7280_BLOB)/shrm/shrm.elf +SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm +$(SHRM_CBFS)-file := $(SHRM_FILE) +$(SHRM_CBFS)-type := payload +$(SHRM_CBFS)-compression := none +cbfs-files-y += $(SHRM_CBFS) + endif diff --git a/src/soc/qualcomm/sc7280/include/soc/shrm.h b/src/soc/qualcomm/sc7280/include/soc/shrm.h new file mode 100644 index 00000000000..59661a8831a --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/shrm.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_SHRM_H__ +#define _SOC_QUALCOMM_SC7280_SHRM_H__ + +void shrm_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_SC7280_SHRM_H__ diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 64e500861c7..6398dbabeae 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -17,6 +17,8 @@ SECTIONS { + REGION(shrm, 0x09060000, 64K , 4K) + AOPSRAM_START(0x0B000000) REGION(aop, 0x0B000000, 0x100000, 4096) AOPSRAM_END(0x0B100000) diff --git a/src/soc/qualcomm/sc7280/shrm_load_reset.c b/src/soc/qualcomm/sc7280/shrm_load_reset.c new file mode 100644 index 00000000000..78830a2df1c --- /dev/null +++ b/src/soc/qualcomm/sc7280/shrm_load_reset.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void shrm_fw_load_reset(void) +{ + bool shrm_fw_entry; + struct prog shrm_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/shrm"); + + shrm_fw_entry = selfload(&shrm_fw_prog); + if (!shrm_fw_entry) + die("SOC image: SHRM load failed"); + + clock_reset_shrm(); + + printk(BIOS_DEBUG, "\nSOC:SHRM brought out of reset.\n"); +} From 1724b57729795f4eed9fb401572f634aa286ab0c Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Tue, 21 Sep 2021 21:50:49 -0600 Subject: [PATCH 029/320] soc/intel/tigerlake: Hook up GMA ACPI brightness controls Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/gaze16 and booting Windows. Display settings has a brightness setting, and can change the brightness level. Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373 Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/57823 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/tigerlake/Kconfig | 12 ++++++++++++ src/soc/intel/tigerlake/Makefile.inc | 1 + src/soc/intel/tigerlake/chip.h | 4 ++++ src/soc/intel/tigerlake/graphics.c | 11 +++++++++++ 4 files changed, 28 insertions(+) create mode 100644 src/soc/intel/tigerlake/graphics.c diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 83d2e9f64ec..37391782d21 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -305,4 +305,16 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES +config INTEL_GMA_BCLV_OFFSET + default 0xc8258 + +config INTEL_GMA_BCLV_WIDTH + default 32 + +config INTEL_GMA_BCLM_OFFSET + default 0xc8254 + +config INTEL_GMA_BCLM_WIDTH + default 32 + endif diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 91464b3f506..bce36538ee1 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c +ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += lpm.c ramstage-y += me.c diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index b63ff01fda3..465dea279a4 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include +#include #include #include #include @@ -532,6 +533,9 @@ struct soc_intel_tigerlake_config { * */ bool external_bypass; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c new file mode 100644 index 00000000000..1696d520538 --- /dev/null +++ b/src/soc/intel/tigerlake/graphics.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *const dev) +{ + const struct soc_intel_tigerlake_config *const chip = dev->chip_info; + return &chip->gfx; +} From e5824ff2a90199b32941fe136d080f3f753c3b7f Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Mon, 4 Oct 2021 15:02:38 +0800 Subject: [PATCH 030/320] libpayload: cbgfx: Clear screen by memcpy Instead of setting each pixel in the framebuffer, use memcpy() to clear screen faster. As this method should be fast enough, remove the fast path using memset(). The speed of clear_screen() on brya (x_resolution = 1920, bytes_per_line = 7680): - Using memset(): 15ms - Setting each pixel: 25ms - Using memcpy(): 14ms Also remove set_pixel_raw() since it's now used in only one place. BUG=none TEST=emerge-brya libpayload TEST=Saw developer screen on brya BRANCH=none Change-Id: I5f08fb50faab48d3db6b61ae022af3226914f72b Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/58128 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Tim Wawrzynczak Reviewed-by: Julius Werner Reviewed-by: Hung-Te Lin --- payloads/libpayload/drivers/video/graphics.c | 38 ++++++++++---------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 53de3024f9b..7f08d40ea20 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -274,19 +274,12 @@ static inline uint32_t calculate_color(const struct rgb_color *rgb, * Plot a pixel in a framebuffer. This is called from tight loops. Keep it slim * and do the validation at callers' site. */ -static inline void set_pixel_raw(struct vector *rcoord, uint32_t color) +static inline void set_pixel(struct vector *coord, uint32_t color) { const int bpp = fbinfo->bits_per_pixel; const int bpl = fbinfo->bytes_per_line; - int i; - uint8_t * const pixel = FB + rcoord->y * bpl + rcoord->x * bpp / 8; - for (i = 0; i < bpp / 8; i++) - pixel[i] = (color >> (i * 8)); -} - -static inline void set_pixel(struct vector *coord, uint32_t color) -{ struct vector rcoord; + int i; switch (fbinfo->orientation) { case CB_FB_ORIENTATION_NORMAL: @@ -308,7 +301,9 @@ static inline void set_pixel(struct vector *coord, uint32_t color) break; } - set_pixel_raw(&rcoord, color); + uint8_t * const pixel = FB + rcoord.y * bpl + rcoord.x * bpp / 8; + for (i = 0; i < bpp / 8; i++) + pixel[i] = (color >> (i * 8)); } /* @@ -625,22 +620,25 @@ int clear_screen(const struct rgb_color *rgb) if (cbgfx_init()) return CBGFX_ERROR_INIT; - struct vector p; + int x, y, i; uint32_t color = calculate_color(rgb, 0); const int bpp = fbinfo->bits_per_pixel; const int bpl = fbinfo->bytes_per_line; + uint8_t *line = malloc(bpl); - /* If all significant bytes in color are equal, fastpath through memset. - * We assume that for 32bpp the high byte gets ignored anyway. */ - if ((((color >> 8) & 0xff) == (color & 0xff)) && (bpp == 16 || - (((color >> 16) & 0xff) == (color & 0xff)))) { - memset(FB, color & 0xff, fbinfo->y_resolution * bpl); - } else { - for (p.y = 0; p.y < fbinfo->y_resolution; p.y++) - for (p.x = 0; p.x < fbinfo->x_resolution; p.x++) - set_pixel_raw(&p, color); + if (!line) { + LOG("Failed to allocate line buffer (%u bytes)\n", bpl); + return CBGFX_ERROR_UNKNOWN; } + /* Set line buffer pixels, then memcpy to framebuffer */ + for (x = 0; x < fbinfo->x_resolution; x++) + for (i = 0; i < bpp / 8; i++) + line[x * bpp / 8 + i] = (color >> (i * 8)); + for (y = 0; y < fbinfo->y_resolution; y++) + memcpy(FB + y * bpl, line, bpl); + + free(line); return CBGFX_SUCCESS; } From a45377e83e720886616ed50ebf32bdcbb9d945cb Mon Sep 17 00:00:00 2001 From: Ryan Lin Date: Tue, 5 Oct 2021 11:38:22 +0800 Subject: [PATCH 031/320] mb/google/brya: Add PsysPmax setting to 145W This patch adds the setting of PsysPmax to 145W according to the brya board design. BUG=b:195615830 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Signed-off-by: Ryan Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/brya0/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 41d1018727a..ad2399bb11a 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -32,6 +32,8 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" + register "PsysPmax" = "145" + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port From bd4487c86911a62138352c310c2e4bbdbd054453 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Fri, 1 Oct 2021 13:56:13 +0900 Subject: [PATCH 032/320] mb/google/dedede/var/bugzzy: Update GPP_D5 configuration As we checked the panel doesn't display firmware screen if we hold GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy uses the built-in touch screen on the panel, the panel seems like under reset state by the TOUCHSCREEN_RESET signal. This change sets default GPP_D5 level to high for bugzzy. BUG=b:None BRANCH=dedede TEST=built and verified bugzzy showed firmware screen Signed-off-by: Seunghwan Kim Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073 Tested-by: build bot (Jenkins) Reviewed-by: Edward Doan Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/bugzzy/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/dedede/variants/bugzzy/gpio.c b/src/mainboard/google/dedede/variants/bugzzy/gpio.c index ce88b5e56b6..d089162db3f 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/gpio.c +++ b/src/mainboard/google/dedede/variants/bugzzy/gpio.c @@ -21,6 +21,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D1, NONE), /* D3 : WLAN_PCIE_WAKE_ODL ==> NC */ PAD_NC(GPP_D3, NONE), + /* D5 : TOUCHSCREEN_RESET */ + PAD_CFG_GPO(GPP_D5, 1, DEEP), /* D7 : EMR_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST, LEVEL, INVERT), /* D13 : EN_PP3300_CAMERA */ From 1de90868b7bd9650c71eb4e0fca8b7d18b337055 Mon Sep 17 00:00:00 2001 From: Sugnan Prabhu S Date: Wed, 6 Oct 2021 18:42:43 +0530 Subject: [PATCH 033/320] mb/google/brya: Disable unused i2s pins for BT offload BT offload hardware design is using only i2s0 pins. Need to disable i2s2 pins which are not used. As per the hardware spec there is an OR operation between vgpio and physical gpio pins related to i2s2. During BT offload configuring the i2s2 pins to its native function is causing offload issue on proto 2 boards. BUG=b:201736222 TEST=Verified BT offload on brya on proto 1 and proto 2. Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d Signed-off-by: Sugnan Prabhu S Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: EricR Lai --- .../google/brya/variants/brya0/fw_config.c | 22 ++++++++++++++----- 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/brya/variants/brya0/fw_config.c b/src/mainboard/google/brya/variants/brya0/fw_config.c index 97b460f6a7f..17d284aa297 100644 --- a/src/mainboard/google/brya/variants/brya0/fw_config.c +++ b/src/mainboard/google/brya/variants/brya0/fw_config.c @@ -33,22 +33,28 @@ static const struct pad_config sndw_disable_pads[] = { PAD_NC(GPP_S5, NONE), }; -static const struct pad_config i2s_enable_pads[] = { +static const struct pad_config i2s0_enable_pads[] = { PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ +}; + +static const struct pad_config i2s2_enable_pads[] = { PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */ }; -static const struct pad_config i2s_disable_pads[] = { +static const struct pad_config i2s0_disable_pads[] = { PAD_NC(GPP_R0, NONE), PAD_NC(GPP_R1, NONE), PAD_NC(GPP_R2, NONE), PAD_NC(GPP_R3, NONE), +}; + +static const struct pad_config i2s2_disable_pads[] = { PAD_NC(GPP_R4, NONE), PAD_NC(GPP_R5, NONE), PAD_NC(GPP_R6, NONE), @@ -80,7 +86,8 @@ static const struct pad_config bt_i2s_disable_pads[] = { static void enable_i2s(void) { gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); - gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); + gpio_configure_pads(i2s2_enable_pads, ARRAY_SIZE(i2s2_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } @@ -88,7 +95,8 @@ static void fw_config_handle(void *unused) { if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); - gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads)); + gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); return; @@ -99,11 +107,13 @@ static void fw_config_handle(void *unused) gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads)); printk(BIOS_INFO, "BT offload enabled\n"); - gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); + gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } else { printk(BIOS_INFO, "BT offload disabled\n"); - gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads)); + gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); } From dc9abea4fc3f2b0028e083817b4b148596c6e744 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 15 Jul 2021 17:46:15 +0800 Subject: [PATCH 034/320] payloads: Allow selecting UefiPayload on ARM64 platforms Some ARM64 platforms (e.g., MT8195) are now able to compile and run EDK2 (UefiPayload). As a result, we should allow selecting PAYLOAD_TIANOCORE for ARM64 platforms. TEST=show strings correctly. 1. make menuconfig 2. select Mainboard -> Vendor=Google, model=Cherry 3. select Payload -> Add a payload -> Tianocorepayload 4. make -j 5. build/cbfstool build/coreboot.rom extract --name fallback/payload --file out.elf -m arm64 6. file out.elf # ELF 64-bit LSB executable, ARM aarch64 7. strings out.elf | grep tianocore # lots of tianocore stuff Signed-off-by: Rex-BC Chen Change-Id: I10777a341d46240b91ceeeb1be26c33a0c5db839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58054 Reviewed-by: Rex-BC Chen Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- payloads/external/tianocore/Kconfig.name | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/tianocore/Kconfig.name b/payloads/external/tianocore/Kconfig.name index 7b0b300351b..771800cd141 100644 --- a/payloads/external/tianocore/Kconfig.name +++ b/payloads/external/tianocore/Kconfig.name @@ -1,6 +1,6 @@ config PAYLOAD_TIANOCORE bool "Tianocore payload" - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_ARM64 help Select this option if you want to build a coreboot image with a Tianocore payload. If you don't know what this is From 1259da13e37434a3a6d606a7dd55d4b23c8063a8 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Wed, 6 Oct 2021 20:26:58 +0800 Subject: [PATCH 035/320] vc/mediatek/mt8195: fix misleading-indentation error Fix misleading-indentation error in dramc_pi_calibration_api.c. Signed-off-by: Rex-BC Chen Change-Id: I680e9e6fffaebb23bf1f156a7f614345e952ed95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58136 Tested-by: build bot (Jenkins) Reviewed-by: Rex-BC Chen Reviewed-by: Yu-Ping Wu --- .../mediatek/mt8195/dramc/dramc_pi_calibration_api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index a95546b554c..e73e6e5358a 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -1040,11 +1040,11 @@ static void O1PathOnOff(DRAMC_CTX_T *p, U8 u1OnOff) // VREF_UNTERM_EN vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_VREF), 1, SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0); if (!isLP4_DSC) - vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF), 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1); + vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_VREF), 1, SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1); else vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_VREF), 1, SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA); - u1VrefSel = 0x37;//unterm LP4 + u1VrefSel = 0x37;//unterm LP4 vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL), P_Fld(u1VrefSel, SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0) | From f6a54d22290f98f1d1c930fc84203057374a729e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 22 Sep 2021 15:50:22 +0200 Subject: [PATCH 036/320] mb/prodrive/hermes: Enable SATA power optimizer Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD is still detected correctly by SeaBIOS (version 1.14.1). Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../prodrive/hermes/variants/baseboard/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 4d35c47ddba..0690167b01a 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -8,6 +8,7 @@ chip soc/intel/cannonlake register "SataMode" = "0" # AHCI register "SataSalpSupport" = "0" + register "satapwroptimize" = "1" register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1 register "SataPortsEnable[0]" = "1" @@ -163,7 +164,6 @@ chip soc/intel/cannonlake register "DisableHeciRetry" = "1" - device domain 0 on device pci 02.0 on end # Integrated Graphics Device device pci 14.3 on From 953a8762f8c0d512fae1d2947b8db85652771e71 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Wed, 1 Sep 2021 16:08:23 -0700 Subject: [PATCH 037/320] mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-M RVP This patch enables eNEM flow for ADL-M TEST=Able to build and boot ADL-M RVP using eNEM mode. Signed-off-by: Bora Guvendik Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Subrata Banik --- src/mainboard/intel/adlrvp/Kconfig.name | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name index 95fe0e8b242..af6ac480a5a 100644 --- a/src/mainboard/intel/adlrvp/Kconfig.name +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -18,9 +18,7 @@ config BOARD_INTEL_ADLRVP_M bool "Alderlake-M RVP" select DRIVERS_UART_8250IO select MAINBOARD_USES_IFD_EC_REGION - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED config BOARD_INTEL_ADLRVP_M_EXT_EC bool "Alderlake-M RVP with Chrome EC" select INTEL_LPSS_UART_FOR_CONSOLE - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED From ab088c9345dc03698211c443fd53bf9158dd4ef0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 23 Sep 2021 17:04:35 +0200 Subject: [PATCH 038/320] acpi: add macros for MSR and `unsupported` register resource types MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These will be used in the follow-up change. Change-Id: I4723ffaf0adff8cb5b1717600ed4d1634768e2b7 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57887 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/include/acpi/acpi.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 2c9af3a56fe..e35accdf789 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -128,6 +128,18 @@ typedef struct acpi_gen_regaddr { #define ACPI_ACCESS_SIZE_DWORD_ACCESS 3 #define ACPI_ACCESS_SIZE_QWORD_ACCESS 4 +/* Macros for common resource types */ +#define ACPI_REG_MSR(address, offset, width) \ + { \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \ + .addrl = address, \ + .bit_offset = offset, \ + .bit_width = width, \ + } + +#define ACPI_REG_UNSUPPORTED {0} + /* Common ACPI HIDs */ #define ACPI_HID_FDC "PNP0700" #define ACPI_HID_KEYBOARD "PNP0303" From 3394f4a8f688dcc4daaa47f9c65c6d7c5fa8fcd2 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 6 Oct 2021 21:33:01 +0200 Subject: [PATCH 039/320] Documentation: Explain how to join Slack Change-Id: I6a4d5011ea47576c9a459f20e0b368cff8a326c2 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/58150 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- Documentation/community/forums.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md index 2ad69e1fe19..91cadcab262 100644 --- a/Documentation/community/forums.md +++ b/Documentation/community/forums.md @@ -17,7 +17,9 @@ We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot), also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a [Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on [OSF Slack](https://osfw.slack.com/), which has channels on many open source -firmware related topics. +firmware related topics. Slack requires that people come from specific domains +or are explicitly invited. To work around that, there's an +[invite bot](https://slack.osfw.dev/) to let people in. ## Fortnightly coreboot leadership meeting From 36721a483b9dffbae7cab37b18ae18a70c986af2 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 7 Oct 2021 16:02:11 -0600 Subject: [PATCH 040/320] mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables Before attempting another commit 6260bf71 ("vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants all program EC_IN_RW as an input GPIO in bootblock so that it can be read from in verstage. Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: EricR Lai Reviewed-by: Hsuan-ting Chen --- src/mainboard/google/brya/variants/anahera/gpio.c | 2 ++ src/mainboard/google/brya/variants/brask/gpio.c | 2 ++ src/mainboard/google/brya/variants/brya0/gpio.c | 4 ++++ src/mainboard/google/brya/variants/felwinter/gpio.c | 2 ++ src/mainboard/google/brya/variants/gimble/gpio.c | 2 ++ src/mainboard/google/brya/variants/kano/gpio.c | 2 ++ src/mainboard/google/brya/variants/primus/gpio.c | 2 ++ src/mainboard/google/brya/variants/redrix/gpio.c | 2 ++ src/mainboard/google/brya/variants/taeko/gpio.c | 2 ++ 9 files changed, 20 insertions(+) diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index 1ce98e4d104..9344d4c0ad9 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -118,6 +118,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c index 7bbe15551bc..1f1d409f25a 100644 --- a/src/mainboard/google/brya/variants/brask/gpio.c +++ b/src/mainboard/google/brya/variants/brask/gpio.c @@ -27,6 +27,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D2, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index 274ddbeb426..c3cfc0c3d4f 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -58,6 +58,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ @@ -101,6 +103,8 @@ static const struct pad_config early_gpio_table_id2[] = { PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ PAD_CFG_GPO(GPP_F21, 0, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index 62610aced5b..d30dd21f4f6 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -127,6 +127,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c index b1c4ba058e5..505a9a613e4 100644 --- a/src/mainboard/google/brya/variants/gimble/gpio.c +++ b/src/mainboard/google/brya/variants/gimble/gpio.c @@ -143,6 +143,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 0842433cdb8..161ddf1c85d 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -124,6 +124,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index 33a0f025cc5..714494923fa 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -106,6 +106,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index 5e13576fc5a..83d4a2fdba4 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -100,6 +100,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index 17004eea493..b67cc49e415 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -162,6 +162,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ From ef353e03c2db07463a61be960f3c1f2a8a881b0f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 26 Sep 2021 15:28:06 +0200 Subject: [PATCH 041/320] soc/intel/dnv_ns: add the Kconfig value for CPU_XTAL_HZ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reference: Intel doc#558579 rev2.2 Change-Id: Iab5dca6eb42abc00bc7da33f640350e994f0bd02 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57945 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/denverton_ns/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index e8e563c3174..c657285a252 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -93,6 +93,9 @@ config CPU_BCLK_MHZ int default 100 +config CPU_XTAL_HZ + default 24000000 + config SMM_TSEG_SIZE hex default 0x200000 From ca1851dc1c57407e25f75e7562a688a5cdcd8e49 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 22 Sep 2021 07:48:41 -0600 Subject: [PATCH 042/320] mb/system76: tgl-u: Add gfx register for GMA ACPI Add gfx register to System76 TGL-U boards so GMA ACPI data is generated. Change-Id: If944a90921b518efdcd5f0e0998bddb4f56e5764 Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/57835 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/system76/darp7/devicetree.cb | 2 ++ src/mainboard/system76/galp5/devicetree.cb | 2 ++ src/mainboard/system76/lemp10/devicetree.cb | 2 ++ 3 files changed, 6 insertions(+) diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 43bbdb8ff47..c5297dce377 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -106,6 +106,8 @@ chip soc/intel/tigerlake register "DdiPortBConfig" = "0" register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" + + register "gfx" = "GMA_DEFAULT_PANEL(0)" end device ref dptf on register "Device4Enable" = "1" diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 12f67df9d33..322a2e10490 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -106,6 +106,8 @@ chip soc/intel/tigerlake register "DdiPortBConfig" = "0" register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" + + register "gfx" = "GMA_DEFAULT_PANEL(0)" end device ref dptf on register "Device4Enable" = "1" diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 45d40168188..f286ab50a02 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -106,6 +106,8 @@ chip soc/intel/tigerlake register "DdiPortBConfig" = "0" register "DdiPortBHpd" = "1" register "DdiPortBDdc" = "1" + + register "gfx" = "GMA_DEFAULT_PANEL(0)" end device ref dptf on register "Device4Enable" = "1" From 45ce84113eee59ca0be53436105a05633b78315f Mon Sep 17 00:00:00 2001 From: Felix Friedlander Date: Fri, 8 Jan 2021 16:37:40 +1100 Subject: [PATCH 043/320] payloads/tianocore/Kconfig: Extend help for bootsplash file Add more detail as to why a smaller-than-screen-size image is to be preferred, in contrast to other payloads' bootsplash images. Signed-off-by: Felix Friedlander Signed-off-by: Matt DeVillier Change-Id: Ib4c6666bb0e49369fe8fe2ae3dc12c023f668da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49233 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- payloads/external/tianocore/Kconfig | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 5349f25c096..a3c9981294a 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -76,8 +76,18 @@ config TIANOCORE_BOOTSPLASH_FILE default "bootsplash.bmp" help The path and filename of the file to use as graphical bootsplash - screen. The file format must be uncompressed BMP, and the file's - resolution must be less than the native resolution of the display. + image. The file must be an uncompressed BMP. + + This image will also be used as the BGRT boot image, which may + persist through your OS boot process, and will be displayed + vertically centered 38.2% from the top of the display. + + See ACPI spec 6.3, 5.2.22 Boot Graphics Resource Table (BGRT), and + Microsoft's documentation on BGRT positioning: + Docs/Windows/Windows Drivers/Bring up guide/Boot screen components + + Accordingly, the image used should be no taller/wider than 40% of + the display panel's native pixel height/width (or resolution set). If an absolute path is not given, the path will assumed to be relative to the coreboot root directory. From 607a266acc5da89a669b9144b051b1c1009412e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Oct 2021 18:00:04 +0200 Subject: [PATCH 044/320] soc/intel/dnv_ns: drop redundancies from soc_fill_fadt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop overrides from `soc_fill_fadt` that do not differ from what common ACPI code already sets. Change-Id: I7a5f43f844b12ff0e9bc5c7426170383209c8e0a Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58087 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/denverton_ns/acpi.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 574d106fa00..4384cadd9e7 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -104,35 +104,9 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 1; - fadt->duty_width = 0; - /* RTC Registers */ - fadt->day_alrm = 0x0D; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - /* PM2 Control Registers */ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = 8; From 7cbeaff5dee24b8c03ffc17a453830d8ae4c0a75 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Wed, 6 Oct 2021 19:02:56 +0800 Subject: [PATCH 045/320] mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe nipperkin has different H/W topology to guybrush that the eMMC device is on a different GPP: guybrush: GPP3 nipperkin: GPP2 Hence we need to enable RTD3 for nipperkin additionally which refers to this one: https://review.coreboot.org/c/coreboot/+/54967 BUG=b:200246826 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage run suspend test on eMMC sku Signed-off-by: Kevin Chiu Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- .../google/guybrush/variants/nipperkin/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index ecaf0cd2df2..a53a6e57955 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -32,6 +32,13 @@ end chip soc/amd/cezanne device domain 0 on + device ref gpp_bridge_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref acp on chip drivers/amd/i2s_machine_dev From 16fc6221b60fbffe2459dbfb0245b441f36b17ba Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Tue, 5 Oct 2021 10:55:23 +0800 Subject: [PATCH 046/320] mb/google/dedede/var/corori: Add ssfc codec ALC5682-VS support Add ALC5682-VS codec support in corori. ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO field of ssfc. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:201372531, b:194436265 TEST=ALC5682-VD/ALC5682-VS audio codec can work. Signed-off-by: Ian Feng Change-Id: I2f3edb0b594066714b42050a411103a215e68b12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102 Tested-by: build bot (Jenkins) Reviewed-by: Aseda Aboagye Reviewed-by: Karthik Ramasubramanian Reviewed-by: Shou-Chieh Hsu --- .../dedede/variants/corori/overridetree.cb | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/corori/overridetree.cb b/src/mainboard/google/dedede/variants/corori/overridetree.cb index 33c054293b9..d322000cbd2 100644 --- a/src/mainboard/google/dedede/variants/corori/overridetree.cb +++ b/src/mainboard/google/dedede/variants/corori/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end + chip soc/intel/jasperlake # USB Port Configuration @@ -124,7 +132,24 @@ chip soc/intel/jasperlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end end end #I2C 4 device pci 1e.2 off end # GSPI 0 From 14886aec990bb7dcf4ecc479985c4f23413c925b Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Thu, 7 Oct 2021 19:21:26 +0600 Subject: [PATCH 047/320] mb/google/brya/var/redrix: select CHROMEOS_DSM_PARAM_FILE_NAME Enable CHROMEOS_DSM_PARAM_FILE_NAME to report dsm parameter file name. BUG=b:197076844 TEST=build and check SSDT. Change-Id: I726e5854bc6a8fb125cb3b7572ddedff49c3c403 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/58175 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/Kconfig.name | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 51bc8e1744f..7d9500221ba 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -31,6 +31,7 @@ config BOARD_GOOGLE_REDRIX bool "-> Redrix" select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS select DRIVERS_I2C_MAX98390 select DRIVERS_INTEL_MIPI_CAMERA select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG From e0bff814da754f4c44fb5702fb9cfb70f02c1611 Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Thu, 23 Sep 2021 21:49:29 +0530 Subject: [PATCH 048/320] drivers/intel/dptf: Add support for PCH methods Add various methods support for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/drivers/intel/dptf/dptf.c | 157 ++++++++++++++++++++++++++++++--- src/drivers/intel/dptf/dptf.h | 11 ++- src/soc/intel/alderlake/dptf.c | 14 ++- 3 files changed, 162 insertions(+), 20 deletions(-) diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index a202a271299..4a65127dd60 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -5,16 +5,21 @@ #include #include #include +#include #include "chip.h" #include "dptf.h" /* Generic DPTF participants have a PTYP field to distinguish them */ enum dptf_generic_participant_type { DPTF_GENERIC_PARTICIPANT_TYPE_TSR = 0x3, + DPTF_GENERIC_PARTICIPANT_TYPE_TPCH = 0x5, DPTF_GENERIC_PARTICIPANT_TYPE_CHARGER = 0xB, }; #define DEFAULT_CHARGER_STR "Battery Charger" +#define DEFAULT_TPCH_STR "Intel PCH FIVR Participant" + +#define PMC_IPC_COMMAND_FIVR_SIZE 0x8 /* * Helper method to determine if a device is "used" (called out anywhere as a source or a target @@ -195,19 +200,31 @@ static void write_generic_devices(const struct drivers_intel_dptf_config *config } } -/* \_SB.DPTF.TPCH.RFC methods */ -static void write_tpch_rfc_methods(const char *tpch_rfc_method_name, +static const char *get_pmc_ipcs_method(void) +{ + const char *method = acpi_device_path_join( + pcidev_path_on_root(PCH_DEVFN_PMC), "IPCS"); + if (!method) { + printk(BIOS_ERR, "%s: Unable to find PMC device IPCS method\n", __func__); + return NULL; + } + return method; +} + +static void write_tpch_write_method(const char *tpch_write_method_name, unsigned int ipc_subcmd_ctrl_value) { - acpigen_write_method_serialized(tpch_rfc_method_name, 1); - acpigen_emit_namestring("IPCS"); + /* Get IPCS method from the PMC device */ + const char *ipcs = get_pmc_ipcs_method(); + acpigen_write_method_serialized(tpch_write_method_name, 1); + acpigen_emit_namestring(ipcs); acpigen_write_integer(PMC_IPC_CMD_COMMAND_FIVR); acpigen_write_integer(PMC_IPC_CMD_CMD_ID_FIVR_WRITE); - acpigen_write_integer(0x8); + acpigen_write_integer(PMC_IPC_COMMAND_FIVR_SIZE); acpigen_write_integer(ipc_subcmd_ctrl_value); acpigen_emit_byte(ARG0_OP); - acpigen_write_dword(0); - acpigen_write_dword(0); + acpigen_write_zero(); + acpigen_write_zero(); /* The reason for returning a value here is a W/A for the ESIF shell */ acpigen_emit_byte(RETURN_OP); acpigen_write_package(0); @@ -215,12 +232,78 @@ static void write_tpch_rfc_methods(const char *tpch_rfc_method_name, acpigen_write_method_end(); } +static void write_ppkg_package(const uint8_t i) +{ + acpigen_write_store(); + acpigen_emit_byte(DEREF_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_integer(i); + acpigen_emit_byte(ZERO_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring("PPKG"); + acpigen_write_integer(i); + acpigen_emit_byte(ZERO_OP); +} + +/* + * Truncate Package received from IPC + * Arguments: + * Arg0: Package returned from the IPCS read call from the Pmc + * Return Value: + * Return Package with just the Status and ReadBuf0 + * Status returns 0 for success and 2 for device error + */ +static void write_pkgc_method(void) +{ + acpigen_write_method_serialized("PKGC", 1); + acpigen_write_name("PPKG"); + acpigen_write_package(2); + acpigen_write_zero(); + acpigen_write_zero(); + acpigen_write_package_end(); + + write_ppkg_package(0); + write_ppkg_package(1); + + acpigen_write_return_namestr("PPKG"); + acpigen_write_method_end(); +} + +static void write_tpch_read_method(const char *tpch_read_method_name, + unsigned int ipc_subcmd_ctrl_value) +{ + /* Get IPCS method from the PMC device */ + const char *ipcs = get_pmc_ipcs_method(); + acpigen_write_method_serialized(tpch_read_method_name, 0); + acpigen_write_store(); + acpigen_emit_namestring(ipcs); + acpigen_write_integer(PMC_IPC_CMD_COMMAND_FIVR); + acpigen_write_integer(PMC_IPC_CMD_CMD_ID_FIVR_READ); + acpigen_write_integer(PMC_IPC_COMMAND_FIVR_SIZE); + acpigen_write_integer(ipc_subcmd_ctrl_value); + acpigen_write_zero(); + acpigen_write_zero(); + acpigen_write_zero(); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_write_store(); + acpigen_emit_namestring("PKGC"); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_byte(LOCAL1_OP); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_method_end(); +} + static void write_create_tpch(const struct dptf_platform_info *platform_info) { acpigen_write_device("TPCH"); acpigen_write_name("_HID"); dptf_write_hid(platform_info->use_eisa_hids, platform_info->tpch_device_hid); - acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_STR", DEFAULT_TPCH_STR); + acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_TPCH); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); } @@ -228,12 +311,58 @@ static void write_tpch_methods(const struct dptf_platform_info *platform_info) { write_create_tpch(platform_info); - /* Create RFC0 method */ - write_tpch_rfc_methods(platform_info->tpch_rfc0_method, - PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC); - /* Create RFC1 method */ - write_tpch_rfc_methods(platform_info->tpch_rfc1_method, - PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC); + const struct { + enum { READ, WRITE } type; + const char *method_name; + unsigned int subcommand; + } tpch_methods[] = { + { .type = WRITE, + .method_name = + platform_info->tpch_method_names.set_fivr_low_clock_method, + .subcommand = PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC + }, + { .type = WRITE, + .method_name = + platform_info->tpch_method_names.set_fivr_high_clock_method, + .subcommand = PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC + }, + { .type = READ, + .method_name = + platform_info->tpch_method_names.get_fivr_low_clock_method, + .subcommand = PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC + }, + { .type = READ, + .method_name = + platform_info->tpch_method_names.get_fivr_high_clock_method, + .subcommand = PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC + }, + { .type = READ, + .method_name = + platform_info->tpch_method_names.get_fivr_ssc_method, + .subcommand = PMC_IPC_SUBCMD_EMI_CTRL0_LOGIC + }, + { .type = READ, + .method_name = + platform_info->tpch_method_names.get_fivr_switching_fault_status, + .subcommand = PMC_IPC_SUBCMD_FFFC_FAULT_STATUS + }, + { .type = READ, + .method_name = + platform_info->tpch_method_names.get_fivr_switching_freq_mhz, + .subcommand = PMC_IPC_SUBCMD_FFFC_RFI_STATUS + }, + }; + + write_pkgc_method(); + for (size_t i = 0; i < ARRAY_SIZE(tpch_methods); i++) { + if (tpch_methods[i].type == READ) { + write_tpch_read_method(tpch_methods[i].method_name, + tpch_methods[i].subcommand); + } else if (tpch_methods[i].type == WRITE) { + write_tpch_write_method(tpch_methods[i].method_name, + tpch_methods[i].subcommand); + } + } acpigen_write_device_end(); /* TPCH Device */ } diff --git a/src/drivers/intel/dptf/dptf.h b/src/drivers/intel/dptf/dptf.h index f23ae257216..877aad98e12 100644 --- a/src/drivers/intel/dptf/dptf.h +++ b/src/drivers/intel/dptf/dptf.h @@ -15,8 +15,15 @@ struct dptf_platform_info { const char *generic_hid; const char *fan_hid; const char *tpch_device_hid; - const char *tpch_rfc0_method; - const char *tpch_rfc1_method; + struct { + const char *set_fivr_low_clock_method; + const char *set_fivr_high_clock_method; + const char *get_fivr_low_clock_method; + const char *get_fivr_high_clock_method; + const char *get_fivr_ssc_method; + const char *get_fivr_switching_fault_status; + const char *get_fivr_switching_freq_mhz; + } tpch_method_names; }; const struct dptf_platform_info *get_dptf_platform_info(void); diff --git a/src/soc/intel/alderlake/dptf.c b/src/soc/intel/alderlake/dptf.c index ba604cae884..37754dbfaee 100644 --- a/src/soc/intel/alderlake/dptf.c +++ b/src/soc/intel/alderlake/dptf.c @@ -12,10 +12,16 @@ static const struct dptf_platform_info adl_dptf_platform_info = { .fan_hid = "INTC1048", /* _HID for the toplevel TPCH device, typically \_SB.TPCH */ .tpch_device_hid = "INTC1049", - /* RFC0 method name */ - .tpch_rfc0_method = "RFC0", - /* RFC1 method name */ - .tpch_rfc1_method = "RFC1", + + .tpch_method_names = { + .set_fivr_low_clock_method = "RFC0", + .set_fivr_high_clock_method = "RFC1", + .get_fivr_low_clock_method = "GFC0", + .get_fivr_high_clock_method = "GFC1", + .get_fivr_ssc_method = "GEMI", + .get_fivr_switching_fault_status = "GFFS", + .get_fivr_switching_freq_mhz = "GFCS", + }, }; const struct dptf_platform_info *get_dptf_platform_info(void) From 7227cef0d7baafdabf9294ad577c09a5d4e93e43 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Mon, 13 Sep 2021 12:31:39 -0700 Subject: [PATCH 049/320] soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency optimization. This change adds additional ACPI DSM function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the USB4/TBT topology. The OS is informed to reduce latency for upstream ports while connecting USB4/TBT devices. BUG=b:199757442 TEST=It was validated that the first connected device waits only 50ms instead of 100ms and all functions work on Voxel board. Signed-off-by: John Zhao Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 59 ++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 847d87ea6e4..7576564dfb5 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -1,5 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency + * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream + * port of the USB4/TBT topology. + */ +/* Number of microseconds to wait after a conventional reset */ +#define FW_RESET_TIME 50000 + +/* Number of microseconds to wait after data link layer active report */ +#define FW_DL_UP_TIME 1 + +/* Number of microseconds to wait after a function level reset */ +#define FW_FLR_RESET_TIME 1 + +/* Number of microseconds to wait from D3 hot to D0 transition */ +#define FW_D3HOT_TO_D0_TIME 50000 + +/* Number of microseconds to wait after setting the VF enable bit */ +#define FW_VF_ENABLE_TIME 1 + OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) Field (PXCS, AnyAcc, NoLock, Preserve) { @@ -64,10 +84,49 @@ Method (_DSM, 4, Serialized) Return (Buffer() { 0x00 }) } +/* + * A bitmask of functions support + */ +Name(OPTS, Buffer(2) {0, 0}) + Device (PXSX) { Name (_ADR, 0x00000000) + /* + * _DSM Device Specific Method + * + * Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D + * Arg1: Revision ID: 3 + * Arg2: Function index: 0, 9 + * Arg3: Empty package + */ + Method (_DSM, 4, Serialized) + { + If (Arg0 == ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) { + If (Arg1 >= 3) { + If (Arg2 == 0) { + /* + * Function index: 0 + * Standard query - A bitmask of functions supported + */ + CreateBitField(OPTS, 9, FUN9) + FUN9 = 1 + Return (OPTS) + } ElseIf (Arg2 == 9) { + /* + * Function index: 9 + * Specifying device readiness durations + */ + Return (Package() { FW_RESET_TIME, FW_DL_UP_TIME, + FW_FLR_RESET_TIME, FW_D3HOT_TO_D0_TIME, + FW_VF_ENABLE_TIME }) + } + } + } + Return (Buffer() { 0x0 }) + } + Method (_PRW, 0) { Return (Package() { 0x69, 4 }) From 7c1ce19abd16a2125e0ccb00fdea26c08dbb0a8f Mon Sep 17 00:00:00 2001 From: Sumeet Pawnikar Date: Thu, 7 Oct 2021 18:00:57 +0530 Subject: [PATCH 050/320] drivers/intel/dptf: return package with value Return the package with a value for the dptf user space service. This is required in write tpch method for pch device under dptf driver. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba Signed-off-by: Sumeet Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/drivers/intel/dptf/dptf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 4a65127dd60..c6ead0f6ed7 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -227,7 +227,8 @@ static void write_tpch_write_method(const char *tpch_write_method_name, acpigen_write_zero(); /* The reason for returning a value here is a W/A for the ESIF shell */ acpigen_emit_byte(RETURN_OP); - acpigen_write_package(0); + acpigen_write_package(1); + acpigen_write_zero(); acpigen_write_package_end(); acpigen_write_method_end(); } From 70a8c046c9aa25c4d4660c5185aaeee1bc72c189 Mon Sep 17 00:00:00 2001 From: Alex1 Kao Date: Fri, 24 Sep 2021 18:39:00 +0800 Subject: [PATCH 051/320] mb/google/dedede/var/pirika: Add Synaptics I2C touchpad device Add Synaptics touchpad device support in devicetree. BUG=b:201043984 BRANCH=dedede TEST=Touchpad device function is OK Change-Id: Ifb240d7113e401de827384697fc752a76fbf7ac7 Signed-off-by: Alex1 Kao Reviewed-on: https://review.coreboot.org/c/coreboot/+/57921 Tested-by: build bot (Jenkins) Reviewed-by: Kirk Wang Reviewed-by: Shou-Chieh Hsu Reviewed-by: Karthik Ramasubramanian --- .../google/dedede/variants/pirika/overridetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/dedede/variants/pirika/overridetree.cb b/src/mainboard/google/dedede/variants/pirika/overridetree.cb index fbbea1deb29..c93ae33db82 100644 --- a/src/mainboard/google/dedede/variants/pirika/overridetree.cb +++ b/src/mainboard/google/dedede/variants/pirika/overridetree.cb @@ -117,6 +117,15 @@ chip soc/intel/jasperlake register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end end device pci 19.0 on chip drivers/i2c/generic From 670462c7c62a8df829e5d370f3cb59e5b6928b93 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 24 Aug 2021 11:23:31 +0200 Subject: [PATCH 052/320] mb/siemens/mc_ehl2: Update SPD for DDR4 devices Since this variant uses different DDR4 devices compared to mc_ehl1 in a memory down configuration, the SPD data file must be adapted. In a first configuration we use Micron MT53D512M32D2NP modules. Following values were adjusted according to this board characteristic and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules JEDEC Spec and the Specification for this Micron modules itself: - SPD Byte 4 - only 4Gb density instead of 8Gb for mc_ehl1 - SPD Byte 5 - different Row and Column Address Bits - SPD Byte 29/30 - 4Gb LPDDR4 needs 130ns tRFCab - SPD Byte 31/32 - 4Gb LPDDR4 needs 60ns tRFCpb Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58111 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- .../siemens/mc_ehl/variants/mc_ehl2/spd/mc_ehl2.spd.hex | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/spd/mc_ehl2.spd.hex b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/spd/mc_ehl2.spd.hex index 71e5456542e..eff68b3a380 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/spd/mc_ehl2.spd.hex +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/spd/mc_ehl2.spd.hex @@ -1,6 +1,6 @@ -23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 -00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 -04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +23 11 11 0E 14 19 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 10 04 E0 +01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From d3e6574b667756b7fe88c40b2bed3dacac1ad898 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 24 Aug 2021 11:34:51 +0200 Subject: [PATCH 053/320] mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2 This board has the RTC RX6110SA connected to the I2C2 instead of SMBus as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC only supports the standard speed. TEST: - Console Log shows no errors for RX6110SA during I2C2 init - Finalize device for I2C 00:32 shows correct date and time Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58112 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- .../mc_ehl/variants/mc_ehl2/devicetree.cb | 40 +++++++++++-------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index be98a157003..859f08b3a8c 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -135,6 +135,12 @@ chip soc/intel/elkhartlake register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" register "PchTsnGbeSgmiiEnable" = "1" + register "common_soc_config" = "{ + .i2c[2] = { + .speed = I2C_SPEED_STANDARD, + }, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -173,7 +179,22 @@ chip soc/intel/elkhartlake device pci 15.0 off end # I2C0 device pci 15.1 on end # I2C1 - device pci 15.2 off end # I2C2 + device pci 15.2 on # I2C2 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "bus_speed" = "I2C_SPEED_STANDARD" + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end device pci 15.3 off end # I2C3 device pci 16.0 on end # Management Engine Interface 1 @@ -240,22 +261,7 @@ chip soc/intel/elkhartlake device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 off end # Intel cAVS/HDA - device pci 1f.4 on # SMBus - # Enable external RTC chip - chip drivers/i2c/rx6110sa - register "bus_speed" = "I2C_SPEED_STANDARD" - register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" - register "user_weekday" = "4" - device i2c 0x32 on end # RTC RX6110 SA - end - end + device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI (flash & TPM) device pci 1f.7 off end # PCH Intel Trace Hub end From 5cb62f1aa3ff6a96592152add83f9c52cc42f4b8 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 24 Aug 2021 11:37:06 +0200 Subject: [PATCH 054/320] mb/siemens/mc_ehl2: Enable SD-Card This mainboard has SD slot available and therefore it should be enabled. Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58166 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 859f08b3a8c..21f462612a1 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -217,7 +217,7 @@ chip soc/intel/elkhartlake device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC - device pci 1a.1 off end # SD + device pci 1a.1 on end # SD device pci 1a.3 off end # Intel Safety Island device pci 1b.0 off end # Intel PSE I2C0 From 6deadeeeca7931807b2fc915d7ea263606f1a1e1 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 24 Aug 2021 11:45:39 +0200 Subject: [PATCH 055/320] mb/siemens/mc_ehl2: Disable SATA Port 0 This mainboard has only SATA Port 1 available with no device sleep feature. Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 21f462612a1..062ac5ff835 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -87,7 +87,7 @@ chip soc/intel/elkhartlake # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" From 4951fe1fb7cb50058aeb80f49403509caa263541 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 24 Aug 2021 12:20:15 +0200 Subject: [PATCH 056/320] mb/siemens/mc_ehl2: Adjust GPIOs Set the GPIOs according to the circuit diagram for this mainboard. Change-Id: I19dc24a16ee9f533b45879bf60fb441e24018cc8 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58168 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- .../siemens/mc_ehl/variants/mc_ehl2/gpio.c | 89 ++++++++----------- 1 file changed, 35 insertions(+), 54 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c index 91c041756fb..b83fabc1594 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c @@ -3,12 +3,13 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { + /* Community 0 - GpioGroup GPP_B */ PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */ PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */ - PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF4), /* ESPI_ALERT1_N */ + PAD_NC(GPP_B4, NONE), /* Not connected */ PAD_NC(GPP_B9, NONE), /* Not connected */ PAD_NC(GPP_B10, NONE), /* Not connected */ PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */ @@ -16,14 +17,11 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5), /* ESPI_CS1_N */ PAD_NC(GPP_B18, NONE), /* Not connected */ PAD_NC(GPP_B19, NONE), /* Not connected */ - PAD_NC(GPP_B20, NONE), /* Not connected */ - PAD_NC(GPP_B21, NONE), /* Not connected */ - PAD_NC(GPP_B22, NONE), /* Not connected */ PAD_NC(GPP_B23, NONE), /* Not connected */ /* Community 0 - GpioGroup GPP_T */ - PAD_CFG_NF(GPP_T4, UP_20K, DEEP, NF1), /* PSE_GBE0_INT */ - PAD_CFG_NF(GPP_T5, DN_20K, DEEP, NF1), /* PSE_GBE0_RST_N */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), /* PSE_GBE0_INT */ + PAD_CFG_GPO(GPP_T5, 1, DEEP), /* PSE_GBE0_RST_N */ PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */ @@ -32,15 +30,7 @@ static const struct pad_config gpio_table[] = { /* Community 0 - GpioGroup GPP_G */ PAD_NC(GPP_G8, NONE), /* Not connected */ PAD_NC(GPP_G9, NONE), /* Not connected */ - PAD_NC(GPP_G12, NONE), /* Not connected */ - PAD_CFG_NF(GPP_G15, NONE, DEEP, NF1), /* ESPI_IO_0 */ - PAD_CFG_NF(GPP_G16, NONE, DEEP, NF1), /* ESPI_IO_1 */ - PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* ESPI_IO_2 */ - PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* ESPI_IO_3 */ PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */ - PAD_CFG_NF(GPP_G20, NONE, DEEP, NF1), /* ESPI_CSO_N */ - PAD_CFG_NF(GPP_G21, NONE, DEEP, NF1), /* ESPI_CLK */ - PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1), /* ESPI_RST0_N */ /* Community 1 - GpioGroup GPP_V */ PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), /* EMMC_CMD */ @@ -54,36 +44,36 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */ PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */ - PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET_N */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET */ /* Community 1 - GpioGroup GPP_H */ - PAD_CFG_NF(GPP_H0, DN_20K, DEEP, NF1), /* PSE_GBE1_INT */ - PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF1), /* PSE_GBE1_RST_N */ + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), /* PSE_GBE1_INT */ + PAD_CFG_GPO(GPP_H1, 1, DEEP), /* PSE_GBE1_RST_N */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */ PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */ - PAD_CFG_NF(GPP_H8, UP_20K, DEEP, NF1), /* SIO_I2C4_SDA */ - PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1), /* SIO_I2C4_SCL */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /* PCIE_CLKREQ4_N */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* PCIE_CLKREQ5_N */ /* Community 1 - GpioGroup GPP_D */ - PAD_CFG_GPO(GPP_D16, 0, DEEP), /* EMMC_PWR_EN_N */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCIE_CLKREQ0_N */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCIE_CLKREQ1_N */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* PCIE_CLKREQ2_N */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* PCIE_CLKREQ3_N */ /* Community 1 - GpioGroup GPP_U */ - PAD_CFG_NF(GPP_U0, DN_20K, DEEP, NF1), /* GBE_INT */ - PAD_CFG_NF(GPP_U1, DN_20K, DEEP, NF1), /* GBE_RST_N */ - PAD_CFG_NF(GPP_U2, NONE, DEEP, NF1), /* GBE_PPS */ - PAD_CFG_NF(GPP_U3, NONE, DEEP, NF1), /* GBE_AUXTS */ + PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1), /* GBE_INT */ + PAD_CFG_GPO(GPP_U1, 1, DEEP), /* GBE_RST_N */ PAD_NC(GPP_U12, NONE), /* Not connected */ PAD_NC(GPP_U13, NONE), /* Not connected */ PAD_NC(GPP_U16, NONE), /* Not connected */ PAD_NC(GPP_U17, NONE), /* Not connected */ PAD_NC(GPP_U18, NONE), /* Not connected */ - PAD_CFG_GPO(GPP_U19, 1, DEEP), /* UPD_REQ_N */ /* Community 2 - GpioGroup DSW */ - PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), /* SLP_S3 */ - PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), /* SLP_S4 */ - PAD_NC(GPD7, NONE), /* Not connected */ - PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), /* SLP_S5 */ + PAD_CFG_NF(GPD1, NONE, PLTRST, NF1), /* ACPRESENT */ + PAD_NC(GPD9, NONE), /* Not connected */ + /* ONBOARD_X4_PCIE_SLOT1_RESET_N */ + PAD_CFG_GPO(GPD11, 1, PLTRST), /* Community 3 - GpioGroup GPP_S */ PAD_NC(GPP_S0, NONE), /* Not connected */ @@ -101,32 +91,34 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD3 */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD2 */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD1 */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD0 */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCLK */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXCTL */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCLK */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXCTL */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD3 */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD2 */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD1 */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD0 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */ /* Community 4 - GpioGroup GPP_C */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */ - PAD_NC(GPP_C5, NONE), /* Not connected */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */ - PAD_NC(GPP_C8, NONE), /* Not connected */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF4), /* SIO_I2C1_SDA */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF4), /* SIO_I2C1_SCL */ /* Community 4 - GpioGroup GPP_F */ - PAD_NC(GPP_F0, NONE), /* Not connected */ PAD_NC(GPP_F1, NONE), /* Not connected */ - PAD_NC(GPP_F2, NONE), /* Not connected */ PAD_NC(GPP_F3, NONE), /* Not connected */ - PAD_NC(GPP_F4, NONE), /* Not connected */ - PAD_NC(GPP_F5, NONE), /* Not connected */ - PAD_NC(GPP_F7, NONE), /* Not connected */ PAD_NC(GPP_F8, NONE), /* Not connected */ - PAD_NC(GPP_F10, NONE), /* Not connected */ PAD_NC(GPP_F11, NONE), /* Not connected */ PAD_NC(GPP_F12, NONE), /* Not connected */ PAD_NC(GPP_F13, NONE), /* Not connected */ @@ -134,35 +126,24 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F15, NONE), /* Not connected */ PAD_NC(GPP_F16, NONE), /* Not connected */ PAD_NC(GPP_F17, NONE), /* Not connected */ - PAD_NC(GPP_F20, NONE), /* Not connected */ - PAD_NC(GPP_F21, NONE), /* Not connected */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), /* LED_BIOS_DONE */ /* Community 4 - GpioGroup GPP_E */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */ - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* DDI1_HPD */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DDI1_DDC_SDA */ - PAD_NC(GPP_E6, NONE), /* Not connected */ - PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), /* DDI1_DDC_SCL */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), /* M.2_SSD_SATA_DEVSLP_1 */ PAD_NC(GPP_E15, NONE), /* Not connected */ PAD_NC(GPP_E16, NONE), /* Not connected */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDI0_DDC_SDA */ + PAD_NC(GPP_E18, NONE), /* Not connected */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */ PAD_NC(GPP_E23, NONE), /* Not connected */ /* Community 5 - GpioGroup GPP_R */ PAD_NC(GPP_R1, NONE), /* Not connected */ - PAD_NC(GPP_R2, NONE), /* Not connected */ PAD_NC(GPP_R3, NONE), /* Not connected */ }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ - PAD_CFG_NF(GPP_C2, NONE, DEEP, NF2), /* SMB_ALERT_N */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), /* SIO_UART2_RXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), /* SIO_UART2_TXD */ }; const struct pad_config *variant_gpio_table(size_t *num) From 645b4d6efcd827a6333bfd9c9c229ba8a48b8226 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Thu, 7 Oct 2021 12:44:21 +0200 Subject: [PATCH 057/320] mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLE This mainboard uses an eSPI-to-LPC bridge for console output. For this reason, the internal LPSS UART must be disabled. Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58169 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig index f577b243e9a..0dbb800da0e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig @@ -3,7 +3,6 @@ if BOARD_SIEMENS_MC_EHL2 config BOARD_SPECIFIC_OPTIONS def_bool y select DRIVER_INTEL_I210 - select INTEL_LPSS_UART_FOR_CONSOLE config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" From 93b537f907ddfd080fa90f7bdd9eb3f66d030be5 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 24 Aug 2021 12:39:36 +0200 Subject: [PATCH 058/320] mb/siemens/mc_ehl2: Enable LPC ComB Enable LPC ComB on this mainboard. TEST: - Boot Linux and check with 'dmesg | grep tty' Change-Id: I7ec58685a723c177df18144011934b206e6425d0 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58170 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig index 0dbb800da0e..b3d42ff3de2 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig @@ -3,6 +3,7 @@ if BOARD_SIEMENS_MC_EHL2 config BOARD_SPECIFIC_OPTIONS def_bool y select DRIVER_INTEL_I210 + select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" From d7f45ea87b996d5aec76fa550b1b05fb89ae276d Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 24 Aug 2021 12:43:45 +0200 Subject: [PATCH 059/320] mb/siemens/mc_ehl: Add variant_mainboard_final() In upcoming patches, we need mainboard specific adjustments. Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58171 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_ehl/mainboard.c | 8 ++++++++ .../variants/baseboard/include/baseboard/variants.h | 3 +++ 2 files changed, 11 insertions(+) diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index d3475678bc3..e64dbda54fe 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -127,6 +127,9 @@ static void mainboard_final(void *chip_info) { struct device *dev; + /* Do board specific things */ + variant_mainboard_final(); + if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) { /* Set Master Enable for on-board PCI devices if allowed. */ dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); @@ -139,6 +142,11 @@ static void mainboard_final(void *chip_info) } } +/* The following function performs board specific things. */ +void __weak variant_mainboard_final(void) +{ +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .final = mainboard_final diff --git a/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h index bf057651d39..0893d99e03d 100644 --- a/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h @@ -15,4 +15,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num); /* This function returns SPD related FSP-M mainboard configs */ const struct mb_cfg *variant_memcfg_config(void); +/* The following function performs board specific things. */ +void variant_mainboard_final(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ From 08d304f05b1a1871014bf149c1982985b0feed87 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 25 Aug 2021 09:42:50 +0200 Subject: [PATCH 060/320] mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devices On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason, we have to adjust the PIR8 register (0x3150) which is responsible for PCIe device 25h. The bridge is connected to PCIe root port 7. The following routing is required: INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# TEST: - Boot into system software Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- .../siemens/mc_ehl/variants/mc_ehl2/Makefile.inc | 1 + .../siemens/mc_ehl/variants/mc_ehl2/mainboard.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) create mode 100644 src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc index 9cb0f1d4d4f..2903dd1ac04 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += mainboard.c SPD_SOURCES = mc_ehl2 # 0b000 LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c new file mode 100644 index 00000000000..4ae857c69ab --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void variant_mainboard_final(void) +{ + /* PIR8 register mapping for PCIe root ports + INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */ + pcr_write16(PID_ITSS, 0x3150, 0x1032); +} From cfe15a20880ecb873942c4c272b6464448137d24 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Tue, 5 Oct 2021 08:33:08 +0800 Subject: [PATCH 061/320] mb/ocp/deltalake: Fix SMBIOS type 9 bugs 1. Fix PCIe slot capabilities not being really read from an IIO root port device. The Hot-Plug capability of IIO root port cannot be enabled due to FSP limitation (v2.1-0.2.2.0), but the code should reflect the true capabilities by reading the root port device's CSR. 2. Initialize the characteristics flags to 0 in the for-loop to fix the issue of the flags values persists to the next iterations. Tested=On OCP Delta Lake, dmidecode -t 9 shows the expected results. For example without the fix it shows 'Hot-plug devices are supported' but in fact it's not: System Slot Information Designation: SSD1_M2_Data_Drive Type: x4 PCI Express 3 x4 Current Usage: Available Length: Short ID: 1 Characteristics: 3.3 V is provided PME signal is supported Hot-plug devices are supported Bus Address: 0000:00:1d.0 With the fix it shows the correct result: Handle 0x0016, DMI type 9, 19 bytes System Slot Information Designation: SSD1_M2_Data_Drive Type: x4 PCI Express 3 x4 Current Usage: Available Length: Short ID: 1 Characteristics: 3.3 V is provided PME signal is supported Bus Address: 0000:00:1d.0 Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9 Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/58100 Reviewed-by: Johnny Lin Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Jonathan Zhang Tested-by: build bot (Jenkins) --- src/mainboard/ocp/deltalake/ramstage.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 8d9de82751b..d8653b9002b 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -194,11 +194,9 @@ static int create_smbios_type9(int *handle, unsigned long *current) uint8_t sec_bus; uint8_t slot_usage; uint8_t pcie_config = 0; - uint8_t characteristics_1 = 0; - uint8_t characteristics_2 = 0; uint32_t vendor_device_id; uint8_t stack_busnos[MAX_IIO_STACK]; - pci_devfn_t pci_dev; + pci_devfn_t pci_dev_slot, pci_dev = 0; unsigned int cap; uint16_t sltcap; @@ -209,6 +207,9 @@ static int create_smbios_type9(int *handle, unsigned long *current) stack_busnos[index] = get_stack_busno(index); for (index = 0; index < ARRAY_SIZE(slotinfo); index++) { + uint8_t characteristics_1 = 0; + uint8_t characteristics_2 = 0; + if (pcie_config == PCIE_CONFIG_A) { if (index == 0 || index == 1 || index == 2) printk(BIOS_INFO, "Find Config-A slot: %s\n", @@ -251,14 +252,14 @@ static int create_smbios_type9(int *handle, unsigned long *current) else slot_length = SlotLengthShort; - pci_dev = PCI_DEV(stack_busnos[slotinfo[index].stack], + pci_dev_slot = PCI_DEV(stack_busnos[slotinfo[index].stack], slotinfo[index].dev_func >> 3, slotinfo[index].dev_func & 0x7); - sec_bus = pci_s_read_config8(pci_dev, PCI_SECONDARY_BUS); + sec_bus = pci_s_read_config8(pci_dev_slot, PCI_SECONDARY_BUS); if (sec_bus == 0xFF) { slot_usage = SlotUsageUnknown; } else { - /* Checking for Slot device availability */ + /* Checking for downstream device availability */ pci_dev = PCI_DEV(sec_bus, 0, 0); vendor_device_id = pci_s_read_config32(pci_dev, 0); if (vendor_device_id == 0xFFFFFFFF) @@ -269,13 +270,16 @@ static int create_smbios_type9(int *handle, unsigned long *current) characteristics_1 |= SMBIOS_SLOT_3P3V; // Provides33Volts characteristics_2 |= SMBIOS_SLOT_PME; // PmeSiganalSupported - - cap = pci_s_find_capability(pci_dev, PCI_CAP_ID_PCIE); - sltcap = pci_s_read_config16(pci_dev, cap + PCI_EXP_SLTCAP); + /* Read IIO root port device CSR for slot capabilities */ + cap = pci_s_find_capability(pci_dev_slot, PCI_CAP_ID_PCIE); + sltcap = pci_s_read_config16(pci_dev_slot, cap + PCI_EXP_SLTCAP); if (sltcap & PCI_EXP_SLTCAP_HPC) characteristics_2 |= SMBIOS_SLOT_HOTPLUG; const uint16_t slot_id = index + 1; + /* According to SMBIOS spec, the BDF number should be the end + point on the slot, for now we keep using the root port's BDF to + be aligned with our UEFI reference BIOS. */ length += smbios_write_type9(current, handle, slotinfo[index].slot_designator, slotinfo[index].slot_type, From d6606f1745de4ca2a1539e3d188dce5a11a3b384 Mon Sep 17 00:00:00 2001 From: FrankChu Date: Thu, 7 Oct 2021 17:13:30 +0800 Subject: [PATCH 062/320] mb/google/dedede/var/galtic: Add fw_config probe for ALC5682-VD & VS ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:198713670 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: FrankChu Change-Id: Iaba136a836b89f42411474ae733380e345cce687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58162 Reviewed-by: Henry Sun Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- .../dedede/variants/galtic/overridetree.cb | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index ba1c4b29897..150bfe33313 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end + chip soc/intel/jasperlake # Intel Common SoC Config @@ -167,7 +175,23 @@ chip soc/intel/jasperlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end end chip drivers/i2c/generic register "hid" = ""10EC1015"" From 3bfe46c2b09360eea5e5482245d8239d1c194334 Mon Sep 17 00:00:00 2001 From: Hsuan Ting Chen Date: Fri, 8 Oct 2021 15:31:00 +0800 Subject: [PATCH 063/320] mb/google/guybrush: Add GPIO EC in RW to early GPIO tables Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush programs GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in verstage. Signed-off-by: Hsuan Ting Chen Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58192 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Karthik Ramasubramanian Reviewed-by: Yu-Ping Wu --- src/mainboard/google/guybrush/variants/baseboard/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 98780404fb1..2fa525486e7 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -226,6 +226,10 @@ static const struct soc_amd_gpio early_gpio_table[] = { PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), /* UART0_TXD */ PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + +/* Support EC trusted */ + /* SD_EX_PRSNT_L(Guybrush BoardID 1 only) / EC_IN_RW_OD */ + PAD_GPI(GPIO_91, PULL_NONE), }; /* Power-on timing requirements: From 3a30cf951d69f845335f057575f12994c6730442 Mon Sep 17 00:00:00 2001 From: Hsuan Ting Chen Date: Fri, 8 Oct 2021 16:33:46 +0800 Subject: [PATCH 064/320] mb/google/guybrush: Build chromeos.c in verstage Before attempting another commit 6260bf71 (vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush builds chromeos.c in verstage to call get_ec_is_trusted() in vboot verstage_main(). Signed-off-by: Hsuan Ting Chen Change-Id: Ic22519fdde1b18f6ce0237022dee02ca37181a74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58193 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Karthik Ramasubramanian Reviewed-by: Yu-Ping Wu Reviewed-by: Paul Menzel --- src/mainboard/google/guybrush/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index 85649b6363f..f3140ddbdb2 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -18,6 +18,7 @@ ramstage-y += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += verstage.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard subdirs-y += variants/$(VARIANT_DIR) From 78a6cae9beb52ff0bab93198063a66872926463e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 1 Apr 2021 07:04:04 -0500 Subject: [PATCH 065/320] mb/google/caroline: Update _HID for digitizer Caroline uses a Wacom digitizer, so adjust the ACPI HID so that the proper drivers attach under Windows/Linux. Change-Id: I732b09001dc41a91a32a5f9260abdab435b28b8a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/58186 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- .../glados/variants/caroline/include/variant/acpi/mainboard.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl index f382e086382..7d1196e942d 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl @@ -55,7 +55,7 @@ Scope (\_SB.PCI0.I2C2) { Device (DIGI) { - Name (_HID, "ACPI0C50") + Name (_HID, "WCOM005C") Name (_CID, "PNP0C50") Name (_UID, 1) Name (_S0W, 4) From 64fb9fc53e6fbadc91cadfb823a6c34d89eb8f72 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 22 Aug 2019 11:12:15 -0500 Subject: [PATCH 066/320] purism/librem_bdw: add support for ACPI brightness controls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Test: build/boot Purism Librem 13v1, verify brightness controls work under Windows 10/11 with Tianocore payload. Change-Id: I27d04655adcd4a5dd42b025cfccb508cfd7aaeae Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/58187 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel --- src/mainboard/purism/librem_bdw/devicetree.cb | 3 +++ src/mainboard/purism/librem_bdw/dsdt.asl | 1 + 2 files changed, 4 insertions(+) diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index b35d98469c5..e8a03a3f6b9 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/broadwell + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 2ef008573bd..1179f0cc05d 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -24,6 +24,7 @@ DefinitionBlock( { #include #include + #include } } From 4d9694e6bc39b0447d70e96186b9bf707a08f038 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Thu, 7 Oct 2021 09:06:42 +0000 Subject: [PATCH 067/320] tests: Fix JUNIT_OUTPUT=y to write to files instead of stderr CB:57144 broke JUNIT_OUTPUT=y, and unit-tests were writing to stderr instead of selected XML files, because test name used for XML file creation contains test path. Build system did not create necessary directiories, which CMocka required to create output files. This commit fixes writing to XML files with JUNIT_OUTPUT=y, but had to sacrifice path in test name, as it was causing a lot of problems (because CMocka does not know, how to write multiple test groups to one XML file, so it uses test group name [here __TEST_NAME__(test_group)] as part of output filename). Example: Test: tests/lib/rtc-test Output file: `build/tests/junit-tests_lib_rtc-test(tests).xml Change-Id: I09891aca923bf1271cafeaa09f89b6539022709c Signed-off-by: Jakub Czapiga Reviewed-on: https://review.coreboot.org/c/coreboot/+/58163 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- tests/Makefile.inc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 5027dd894bd..982f42baf7a 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -141,7 +141,7 @@ $$($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER) $($(1)-objs): TEST_CFLAGS += -I$$(dir $$($(1)-config-file)) \ -D__$$(shell echo $$($(1)-stage) | tr '[:lower:]' '[:upper:]')__ \ - -D__TEST_NAME__=\"$(1)\" + -D__TEST_NAME__=\"$(subst /,_,$(1))\" # Give us a way to distinguish between coreboot source files and test files in code. $($(1)-srcobjs): TEST_CFLAGS += -D__TEST_SRCOBJ__ @@ -220,13 +220,17 @@ $(TEST_KCONFIG_AUTOCONFIG): $(TEST_KCONFIG_AUTOHEADER) .PHONY: $(alltests) $(addprefix clean-,$(alltests)) .PHONY: unit-tests build-unit-tests run-unit-tests clean-unit-tests +# %g in CMOCKA_XML_FILE will be replaced with "__TEST_NAME__()" +# by macro cb_run_group_tests(), which should be used for running tests. +# __TEST_NAME__ contains test name including path e.g. tests_lib_rtc-test ifeq ($(JUNIT_OUTPUT),y) $(alltests): export CMOCKA_MESSAGE_OUTPUT=xml -$(alltests): export CMOCKA_XML_FILE=$(testobj)/junit-$(subst /,_,$^)-%g.xml +$(alltests): export CMOCKA_XML_FILE=$(testobj)/junit-%g.xml endif $(alltests): $$($$(@)-bin) - rm -f $(testobj)/junit-$(subst /,_,$^).xml $(testobj)/$(subst /,_,$^).failed + rm -f $(testobj)/junit-$(subst /,_,$(patsubst $(testobj)/%/,%,$(dir $^)))\(*\).xml + rm -f $(testobj)/$(subst /,_,$^).failed -./$^ || echo failed > $(testobj)/$(subst /,_,$^).failed # Build a code coverage report by collecting all the gcov files into a single From ff1ef8db4a383ff04d6ca4c4c464a06055f51137 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 24 Dec 2016 15:36:24 -0600 Subject: [PATCH 068/320] nb/intel/sandybridge: Populate meminfo when using MRC Populate a memory_info struct with PEI and SPD data, in order to inject the CBMEM_INFO table necessary to populate a type17 SMBIOS table. On Broadwell, this is done by the MRC binary, but the older Sandy Bridge MRC binary doesn't populate the pei_data struct with all the info needed, so we have to pull it from the SPD. Some values are hardcoded based on platform specifications. Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/58188 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/raminit.h | 1 + .../intel/sandybridge/raminit_mrc.c | 76 +++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index c5d881a1966..dd4e572119d 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -13,5 +13,6 @@ void sdram_initialize(struct pei_data *pei_data); void save_mrc_data(struct pei_data *pei_data); void mainboard_fill_pei_data(struct pei_data *pei_data); int fixup_sandybridge_errata(void); +void setup_sdram_meminfo(struct pei_data *pei_data); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index fc143f67a61..ee5f1c94fa4 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -23,6 +23,7 @@ #include "chip.h" #include #include +#include /* Management Engine is in the southbridge */ #include @@ -382,4 +383,79 @@ void perform_raminit(int s3resume) /* Failed S3 resume, reset to come up cleanly */ system_reset(); } + setup_sdram_meminfo(&pei_data); +} + +void setup_sdram_meminfo(struct pei_data *pei_data) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + struct memory_info *mem_info; + struct dimm_info *dimm; + int dimm_size; + int i; + int dimm_cnt = 0; + + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + memset(mem_info, 0, sizeof(struct memory_info)); + + addr_decoder_common = mchbar_read32(MAD_CHNL); + addr_decode_ch[0] = mchbar_read32(MAD_DIMM_CH0); + addr_decode_ch[1] = mchbar_read32(MAD_DIMM_CH1); + + const int refclk = mchbar_read32(MC_BIOS_REQ) & 0x100 ? 100 : 133; + const int ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100; + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + + /* DIMM-A */ + dimm_size = ((ch_conf >> 0) & 0xff) * 256; + if (dimm_size) { + dimm = &mem_info->dimm[dimm_cnt]; + dimm->dimm_size = dimm_size; + dimm->ddr_type = 0x18; /* DDR3 */ + dimm->ddr_frequency = ddr_frequency; + dimm->rank_per_dimm = 1 + ((ch_conf >> 17) & 1); + dimm->channel_num = i; + dimm->dimm_num = 0; + dimm->bank_locator = i * 2; + memcpy(dimm->serial, /* bytes 122-125 */ + &pei_data->spd_data[0][122], + sizeof(uint8_t) * 4); + memcpy(dimm->module_part_number, /* bytes 128-145 */ + &pei_data->spd_data[0][128], + sizeof(uint8_t) * 18); + dimm->mod_id = /* bytes 117/118 */ + (pei_data->spd_data[0][118] << 8) | + (pei_data->spd_data[0][117] & 0xFF); + dimm->mod_type = 3; /* SPD_SODIMM */ + dimm->bus_width = 0x3; /* 64-bit */ + dimm_cnt++; + } + /* DIMM-B */ + dimm_size = ((ch_conf >> 8) & 0xff) * 256; + if (dimm_size) { + dimm = &mem_info->dimm[dimm_cnt]; + dimm->dimm_size = dimm_size; + dimm->ddr_type = 0x18; /* DDR3 */ + dimm->ddr_frequency = ddr_frequency; + dimm->rank_per_dimm = 1 + ((ch_conf >> 18) & 1); + dimm->channel_num = i; + dimm->dimm_num = 1; + dimm->bank_locator = i * 2; + memcpy(dimm->serial, /* bytes 122-125 */ + &pei_data->spd_data[0][122], + sizeof(uint8_t) * 4); + memcpy(dimm->module_part_number, /* bytes 128-145 */ + &pei_data->spd_data[0][128], + sizeof(uint8_t) * 18); + dimm->mod_id = /* bytes 117/118 */ + (pei_data->spd_data[0][118] << 8) | + (pei_data->spd_data[0][117] & 0xFF); + dimm->mod_type = 3; /* SPD_SODIMM */ + dimm->bus_width = 0x3; /* 64-bit */ + dimm_cnt++; + } + } + mem_info->dimm_cnt = dimm_cnt; } From 8feb8669dd09b122bc92b2afcf3794afc40a6df2 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 7 Oct 2021 18:11:12 -0500 Subject: [PATCH 069/320] mb/google/fizz: Drop broken USB ACPI code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fizz's USB ACPI code is intended to allow the OS to control port charging power, but since Fizz's ports are dumb (vs smart), it controls power to the port itself. The end result is that active ports become disabled when rebooting from Windows (10/11), and power is not restored until the device is powered down (a warm reboot is not sufficient). Subsequent Chromebox models (eg, Puff-based variants) don't bother with EC-controlled USB port power, so just drop it since it's problematic and provides no benefit. Test: boot Windows 10/11, reboot, observe active USB ports still functional (eg, USB KB still works) Change-Id: I2c13d49b3ce8de8b0a38512db3c57d0c8ecbf0ad Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/58185 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/mainboard/google/fizz/acpi/usb.asl | 112 ------------------------- src/mainboard/google/fizz/dsdt.asl | 3 - 2 files changed, 115 deletions(-) delete mode 100644 src/mainboard/google/fizz/acpi/usb.asl diff --git a/src/mainboard/google/fizz/acpi/usb.asl b/src/mainboard/google/fizz/acpi/usb.asl deleted file mode 100644 index 1aa145ffe6f..00000000000 --- a/src/mainboard/google/fizz/acpi/usb.asl +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.XHCI.RHUB.HS02) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (2) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (2) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.HS03) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (3) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (3) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.HS04) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (4) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (4) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.HS05) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (0) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (0) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.HS06) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (1) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (1) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS02) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (2) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (2) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS03) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (3) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (3) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS04) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (4) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (4) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS05) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (0) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (0) - } -} -Scope (\_SB.PCI0.XHCI.RHUB.SS06) -{ - Method (_PS0) - { - \_SB.PCI0.LPCB.EC0.UPPS (1) - } - Method (_PS3) - { - \_SB.PCI0.LPCB.EC0.UPPC (1) - } -} diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 4ca771e09ea..9800126ed1c 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -47,7 +47,4 @@ DefinitionBlock( /* Dynamic Platform Thermal Framework */ #include } - - /* USB port entries */ - #include "acpi/usb.asl" } From b40fdbaa648639c2922732e2fa137c3ebcc78e4e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 5 Oct 2021 21:34:02 -0700 Subject: [PATCH 070/320] Makefile: Add src/soc/* to subdirs This change adds src/soc/* to subdirs before src/soc/*/* to allow Makefile in src/soc/* to provide any common helpers that will be useful for any src/soc/*/*. This is done to primarily ensure that the helpers are defined before being invoked by the SoC Makefile.inc. This is utilized by Intel CSE stitching mechanism in following changes. BUG=b:189177580 Change-Id: I91579a87016fdc2b9ca2d798b81969c21c18b4a3 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58124 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 59aa1ababa2..501fc598079 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -81,7 +81,7 @@ PHONY+= clean-abuild coreboot check-style build_complete # root source directories of coreboot subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) -subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) +subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += $(wildcard src/superio/*) $(wildcard src/superio/*/*) subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) subdirs-y += src/cpu src/vendorcode From 3d91b47b425ffb880c0ed6c45fd04ba48d95ca8d Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Wed, 15 Sep 2021 14:52:45 +0200 Subject: [PATCH 071/320] libpayload: Add mock architecture Mock architecture can be used to build libpayload using host compiler. It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs. Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools provided by xcompile. Mock architecture configuration can be used by payloads for testing purposes. Thanks to it, tests can be architecture-independent, and can be executed without requiring compatible Kconfig options, e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide implementation for most architecture-specific functions present in arch/* directories. Signed-off-by: Jakub Czapiga Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- payloads/libpayload/Kconfig | 10 ++++ payloads/libpayload/Makefile | 41 +++++++++++++++- payloads/libpayload/Makefile.inc | 1 + payloads/libpayload/arch/mock/Kconfig | 16 +++++++ payloads/libpayload/arch/mock/Makefile.inc | 7 +++ payloads/libpayload/arch/mock/head.c | 3 ++ .../libpayload/arch/mock/libpayload.ldscript | 3 ++ payloads/libpayload/arch/mock/mock_media.c | 10 ++++ payloads/libpayload/arch/mock/virtual.c | 10 ++++ payloads/libpayload/bin/lpgcc | 13 ++++- .../libpayload/include/mock/arch/barrier.h | 13 +++++ payloads/libpayload/include/mock/arch/cache.h | 18 +++++++ payloads/libpayload/include/mock/arch/io.h | 29 +++++++++++ payloads/libpayload/include/mock/arch/types.h | 33 +++++++++++++ .../libpayload/include/mock/arch/virtual.h | 15 ++++++ payloads/libpayload/sample/Makefile | 5 ++ payloads/libpayload/sample/arch_mock/Makefile | 48 +++++++++++++++++++ payloads/libpayload/sample/arch_mock/hello.c | 13 +++++ .../libpayload/sample/arch_mock/hello_mocks.c | 43 +++++++++++++++++ 19 files changed, 329 insertions(+), 2 deletions(-) create mode 100644 payloads/libpayload/arch/mock/Kconfig create mode 100644 payloads/libpayload/arch/mock/Makefile.inc create mode 100644 payloads/libpayload/arch/mock/head.c create mode 100644 payloads/libpayload/arch/mock/libpayload.ldscript create mode 100644 payloads/libpayload/arch/mock/mock_media.c create mode 100644 payloads/libpayload/arch/mock/virtual.c create mode 100644 payloads/libpayload/include/mock/arch/barrier.h create mode 100644 payloads/libpayload/include/mock/arch/cache.h create mode 100644 payloads/libpayload/include/mock/arch/io.h create mode 100644 payloads/libpayload/include/mock/arch/types.h create mode 100644 payloads/libpayload/include/mock/arch/virtual.h create mode 100644 payloads/libpayload/sample/arch_mock/Makefile create mode 100644 payloads/libpayload/sample/arch_mock/hello.c create mode 100644 payloads/libpayload/sample/arch_mock/hello_mocks.c diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index f7d78e069d2..382f5af7511 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -121,6 +121,14 @@ config ARCH_ARM64 help Support the ARM64 architecture +config ARCH_MOCK + bool "Mock architecture (for unit tests)" + help + This enables the mock architecture (for unit tests) that is intended + to be used for testing purposes, to either test payloads or libpayload itself. + It provides necessary headers, but requires mocking (providing implementation + for) arch-specific functions. + endchoice config MULTIBOOT @@ -150,6 +158,7 @@ config BASE_ADDRESS default 0x04000000 if ARCH_ARM default 0x80100000 if ARCH_ARM64 default 0x00100000 if ARCH_X86 + default 0x00000000 if ARCH_MOCK help This is the base address for the payload. @@ -480,3 +489,4 @@ config IO_ADDRESS_SPACE source "arch/arm/Kconfig" source "arch/arm64/Kconfig" source "arch/x86/Kconfig" +source "arch/mock/Kconfig" diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 90f6b23836d..923106248cd 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -74,6 +74,14 @@ HOSTCC = gcc HOSTCXX = g++ HOSTCFLAGS := -I$(srck) -I$(objk) -g HOSTCXXFLAGS := -I$(srck) -I$(objk) +HOSTAS ?= as +HOSTLD ?= ld +HOSTNM ?= nm +HOSTOBJCOPY ?= objcopy +HOSTOBJDUMP ?= objdump +HOSTREADELF ?= readelf +HOSTSTRIP ?= strip +HOSTAR ?= ar DOXYGEN := doxygen DOXYGEN_OUTPUT_DIR := doxygen @@ -95,6 +103,7 @@ include $(HAVE_DOTCONFIG) ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 +ARCHDIR-$(CONFIG_LP_ARCH_MOCK) := mock ARCH-y := $(ARCHDIR-y) @@ -103,6 +112,7 @@ ARCH-y := $(ARCHDIR-y) ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 +ARCH-$(CONFIG_LP_ARCH_MOCK) := mock # Three cases where we don't need fully populated $(obj) lists: # 1. when no .config exists @@ -129,6 +139,31 @@ real-all: config else +ifeq ($(CONFIG_LP_ARCH_MOCK),y) + +# Create empty xcompile to satisfy install script +$(shell echo '' > $(xcompile)) + +CC := $(HOSTCC) +CC-mock := $(HOSTCC) +AS := $(HOSTAS) +AS-mock := $(HOSTAS) +LD := $(HOSTLD) +LD-mock := $(HOSTLD) +NM := $(HOSTNM) +NM-mock := $(HOSTNM) +OBJCOPY := $(HOSTOBJCOPY) +OBJCOPY-mock := $(HOSTOBJCOPY) +OBJDUMP := $(HOSTOBJDUMP) +OBJDUMP-mock := $(HOSTOBJDUMP) +READELF := $(HOSTREADELF) +READELF-mock := $(HOSTEADELF) +STRIP := $(HOSTSTRIP) +STRIP-mock := $(HOSTSTRIP) +AR := $(HOSTAR) +AR-mock := $(HOSTAR) +else + # in addition to the dependency below, create the file if it doesn't exist # to silence stupid warnings about a file that would be generated anyway. $(if $(wildcard $(xcompile)),,$(shell \ @@ -152,12 +187,16 @@ OBJDUMP := $(OBJDUMP_$(ARCH-y)) READELF := $(READELF_$(ARCH-y)) STRIP := $(STRIP_$(ARCH-y)) AR := $(AR_$(ARCH-y)) +endif CFLAGS += -std=gnu11 $(CFLAGS_$(ARCH-y)) ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y) -CC:=clang -m32 +CC:=clang +ifneq ($(CONFIG_LP_ARCH_MOCK),y) +CC += -m32 +endif HOSTCC:=clang endif endif diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index a67ba77b67e..df0f14298f6 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -33,6 +33,7 @@ export KERNELVERSION := 0.2.0 ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 +ARCHDIR-$(CONFIG_LP_ARCH_MOCK) := mock DESTDIR ?= install real-target: lib diff --git a/payloads/libpayload/arch/mock/Kconfig b/payloads/libpayload/arch/mock/Kconfig new file mode 100644 index 00000000000..3903a76005f --- /dev/null +++ b/payloads/libpayload/arch/mock/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if ARCH_MOCK + +config ARCH_MOCK_BIG_ENDIAN + bool "Use big-endian for mock architecture" + default n + help + This option enables big-endinan support in the code. + +config ARCH_SPECIFIC_OPTIONS + def_bool y + select LITTLE_ENDIAN if !ARCH_MOCK_BIG_ENDIAN + select BIG_ENDIAN if ARCH_MOCK_BIG_ENDIAN + +endif diff --git a/payloads/libpayload/arch/mock/Makefile.inc b/payloads/libpayload/arch/mock/Makefile.inc new file mode 100644 index 00000000000..f15f0f9f1df --- /dev/null +++ b/payloads/libpayload/arch/mock/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +head.o-y += head.c + +libc-y += virtual.c + +libcbfs-$(CONFIG_LP_CBFS) += mock_media.c diff --git a/payloads/libpayload/arch/mock/head.c b/payloads/libpayload/arch/mock/head.c new file mode 100644 index 00000000000..55a691f9102 --- /dev/null +++ b/payloads/libpayload/arch/mock/head.c @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is empty on purpose. It should not be used. */ diff --git a/payloads/libpayload/arch/mock/libpayload.ldscript b/payloads/libpayload/arch/mock/libpayload.ldscript new file mode 100644 index 00000000000..6842c9ad5ca --- /dev/null +++ b/payloads/libpayload/arch/mock/libpayload.ldscript @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is empty on purpose. It is present only to satisfy install script */ diff --git a/payloads/libpayload/arch/mock/mock_media.c b/payloads/libpayload/arch/mock/mock_media.c new file mode 100644 index 00000000000..2bb06edc290 --- /dev/null +++ b/payloads/libpayload/arch/mock/mock_media.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +int libpayload_init_default_cbfs_media(struct cbfs_media *media); + +__attribute__((weak)) int libpayload_init_default_cbfs_media(struct cbfs_media *media) +{ + return -1; +} diff --git a/payloads/libpayload/arch/mock/virtual.c b/payloads/libpayload/arch/mock/virtual.c new file mode 100644 index 00000000000..6f369d2dcba --- /dev/null +++ b/payloads/libpayload/arch/mock/virtual.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +unsigned long virtual_offset = 0; + +int getpagesize(void) +{ + return 4096; +} diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index c0fe56adf59..3a76f13d17e 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -91,13 +91,24 @@ if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then _ARCHEXTRA="-m32 " _ARCH=x86 fi +if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then + _ARCHINCDIR=$_INCDIR/mock + _ARCHLIBDIR=$_LIBDIR/mock + _ARCHEXTRA="" + _ARCH=mock +fi if [ -f $_LIBDIR/libpayload.ldscript ]; then _LDDIR=$_LIBDIR elif [ -f $BASE/../arch/$_ARCH/libpayload.ldscript ]; then _LDDIR=$BASE/../arch/$_ARCH fi -_LDSCRIPT="-Wl,-T,$_LDDIR/libpayload.ldscript" +# Host arch should youse default linker script +if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then + _LDSCRIPT="" +else + _LDSCRIPT="-Wl,-T,$_LDDIR/libpayload.ldscript" +fi trygccoption() { $DEFAULT_CC $1 -S -xc /dev/null -o /dev/null &> /dev/null diff --git a/payloads/libpayload/include/mock/arch/barrier.h b/payloads/libpayload/include/mock/arch/barrier.h new file mode 100644 index 00000000000..aed115bb64a --- /dev/null +++ b/payloads/libpayload/include/mock/arch/barrier.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARCH_BARRIER_H__ +#define __ARCH_BARRIER_H__ + +/* No memory barrier on mock build */ +#define mb() +/* No read memory barrier on mock build */ +#define rmb() +/* No write memory barrier on mock build */ +#define wmb() + +#endif /* __ARCH_BARRIER_H__ */ diff --git a/payloads/libpayload/include/mock/arch/cache.h b/payloads/libpayload/include/mock/arch/cache.h new file mode 100644 index 00000000000..1e71d5e0e29 --- /dev/null +++ b/payloads/libpayload/include/mock/arch/cache.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARCH_CACHE_H__ +#define __ARCH_CACHE_H__ + +/* No support for cache in the mock architecture */ + +#define dmb() +#define dsb() +#define dcache_clean_all() +#define dcache_clean_by_mva(addr, len) +#define dcache_invalidate_all() +#define dcache_invalidate_by_mva(addr, len) +#define dcache_clean_invalidate_all() +#define dcache_clean_invalidate_by_mva(addr, len) +#define cache_sync_instructions() + +#endif /* __ARCH_CACHE_H__ */ diff --git a/payloads/libpayload/include/mock/arch/io.h b/payloads/libpayload/include/mock/arch/io.h new file mode 100644 index 00000000000..2bb625562e3 --- /dev/null +++ b/payloads/libpayload/include/mock/arch/io.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ARCH_IO_H +#define _ARCH_IO_H + +#include + +/* Functions in this file are unimplemented by default. Tests are expected to implement + mocks for these functions, if tests will call functions using functions listed below. */ + +uint8_t readb(volatile const void *_a); +uint16_t readw(volatile const void *_a); +uint32_t readl(volatile const void *_a); + +void writeb(uint8_t _v, volatile void *_a); +void writew(uint16_t _v, volatile void *_a); +void writel(uint32_t _v, volatile void *_a); + +uint8_t read8(volatile const void *addr); +uint16_t read16(volatile const void *addr); +uint32_t read32(volatile const void *addr); +uint64_t read64(volatile const void *addr); + +void write8(volatile void *addr, uint8_t val); +void write16(volatile void *addr, uint16_t val); +void write32(volatile void *addr, uint32_t val); +void write64(volatile void *addr, uint64_t val); + +#endif /* _ARCH_IO_H */ diff --git a/payloads/libpayload/include/mock/arch/types.h b/payloads/libpayload/include/mock/arch/types.h new file mode 100644 index 00000000000..8f090caa9b9 --- /dev/null +++ b/payloads/libpayload/include/mock/arch/types.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ARCH_TYPES_H +#define _ARCH_TYPES_H + +typedef unsigned char uint8_t; +typedef unsigned char u8; +typedef signed char int8_t; +typedef signed char s8; + +typedef unsigned short uint16_t; +typedef unsigned short u16; +typedef signed short int16_t; +typedef signed short s16; + +typedef unsigned int uint32_t; +typedef unsigned int u32; +typedef signed int int32_t; +typedef signed int s32; + +typedef unsigned long long uint64_t; +typedef unsigned long long u64; +typedef signed long long int64_t; +typedef signed long long s64; + +typedef long time_t; +typedef long suseconds_t; + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#endif /* _ARCH_TYPES_H */ diff --git a/payloads/libpayload/include/mock/arch/virtual.h b/payloads/libpayload/include/mock/arch/virtual.h new file mode 100644 index 00000000000..bf786d52564 --- /dev/null +++ b/payloads/libpayload/include/mock/arch/virtual.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ARCH_VIRTUAL_H +#define _ARCH_VIRTUAL_H + +/* virtual_offset has to be declared if used */ +extern unsigned long virtual_offset; + +#define virt_to_phys(virt) ((unsigned long)(virt) + virtual_offset) +#define phys_to_virt(phys) ((void *)((unsigned long)(phys) - virtual_offset)) + +#define virt_to_bus(addr) virt_to_phys(addr) +#define bus_to_virt(addr) phys_to_virt(addr) + +#endif diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile index 637e45dee1d..1249e9a0176 100644 --- a/payloads/libpayload/sample/Makefile +++ b/payloads/libpayload/sample/Makefile @@ -26,8 +26,13 @@ ## SUCH DAMAGE. ## + # Sample libpayload Makefile. include ../.config +ifeq ($(CONFIG_LP_ARCH_MOCK),y) +$(error This sample program does not support ARCH_MOCK. Use sample/arch_mock instead) +endif + include ../build/xcompile ARCH-$(CONFIG_LP_ARCH_ARM) := arm diff --git a/payloads/libpayload/sample/arch_mock/Makefile b/payloads/libpayload/sample/arch_mock/Makefile new file mode 100644 index 00000000000..a1e748111e1 --- /dev/null +++ b/payloads/libpayload/sample/arch_mock/Makefile @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# Sample libpayload Makefile for ARCH_MOCK +# ARCH_MOCK is not intended to be used with xcompile +include ../../.config + +ifneq ($(CONFIG_LP_ARCH_MOCK),y) +$(error This example supports ARCH_MOCK only.) +endif + +CC := gcc +AS := as +OBJCOPY := objcopy +LIBPAYLOAD_DIR := ../../install/libpayload +CFLAGS := -fno-builtin -Wall -Werror -Os \ + -include $(LIBPAYLOAD_DIR)/include/kconfig.h \ + -include $(LIBPAYLOAD_DIR)/include/compiler.h \ + -I $(LIBPAYLOAD_DIR)/include \ + -I $(LIBPAYLOAD_DIR)/include/mock \ + -ffunction-sections \ + -fdata-sections -g3 +LDFLAGS := -Wl,--gc-sections +TARGET := hello +OBJS := $(TARGET).o +OBJS-mock := $(TARGET)_mocks.o +LIBPAYLOAD-local := libpayload.a +mocks := console_write + +all: $(TARGET).elf + +$(TARGET).elf: $(OBJS) $(OBJS-mock) $(LIBPAYLOAD-local) + $(CC) $(LDFLAGS) -o $@ $(OBJS) $(LIBPAYLOAD-local) \ + -Wl,--exclude-libs,ALL -lc $(OBJS-mock) + +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +%.S.o: %.S + $(AS) --32 -o $@ $< + +# Copy libpayload and weaken all mocked symbols +$(LIBPAYLOAD-local): $(LIBPAYLOAD_DIR)/lib/libpayload.a + $(OBJCOPY) $(foreach mock,$(mocks),--weaken-symbol=$(mock)) $< $@ + +clean: + rm -f $(TARGET).elf *.o $(LIBPAYLOAD-local) + +distclean: clean diff --git a/payloads/libpayload/sample/arch_mock/hello.c b/payloads/libpayload/sample/arch_mock/hello.c new file mode 100644 index 00000000000..5a96e42e757 --- /dev/null +++ b/payloads/libpayload/sample/arch_mock/hello.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Example file for libpayload. */ + +#include +#include + +int main(void) +{ + printf("Hello world!\n"); + halt(); + return 0; +} diff --git a/payloads/libpayload/sample/arch_mock/hello_mocks.c b/payloads/libpayload/sample/arch_mock/hello_mocks.c new file mode 100644 index 00000000000..84e86ff257f --- /dev/null +++ b/payloads/libpayload/sample/arch_mock/hello_mocks.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* Use libc version. calling exit() or abort() would cause infinite recursion */ +__attribute__((noreturn)) +void _exit(int); + +__attribute__((noreturn)) +void halt(void) +{ + _exit(0); +} + +#define TEST_SYMBOL(symbol, value) asm(".set " #symbol ", " #value "\n\t.globl " #symbol) + +#define TEST_REGION(region, size) uint8_t _##region[size]; \ + TEST_SYMBOL(_e##region, _##region + size); \ + TEST_SYMBOL(_##region##_size, size) + +TEST_REGION(heap, CONFIG_LP_HEAP_SIZE); + +uint64_t timer_raw_value(void) +{ + return 0; +} + +uint64_t timer_hz(void) +{ + return 0; +} + +/* Not present in libpayload. Can be used to write to real stdout. */ +ssize_t write(int fildes, const void *buf, size_t nbyte); + +void console_write(const void *buffer, size_t count) +{ + write(1, buffer, count); +} From 0c5885cd94ad8135c0187e5038c0690eb3550047 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 2 Jun 2021 15:51:49 +0200 Subject: [PATCH 072/320] soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits The definitions of bit 9 and 10 somehow got swapped between Picasso and Renoir/Cezanne, so put those in the Cezanne-specific header file. The reference code writes the same values to the raw bits in both, so we probably would still get away with putting this into the common header, but it's better to keep the defines consistent with the documentation in all cases. Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03 and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16. Signed-off-by: Felix Held Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/include/soc/lpc.h | 6 ++++++ src/soc/amd/common/block/include/amdblocks/lpc.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/src/soc/amd/cezanne/include/soc/lpc.h b/src/soc/amd/cezanne/include/soc/lpc.h index fcdcd969395..123a13fc891 100644 --- a/src/soc/amd/cezanne/include/soc/lpc.h +++ b/src/soc/amd/cezanne/include/soc/lpc.h @@ -3,6 +3,12 @@ #ifndef AMD_CEZANNE_LPC_H #define AMD_CEZANNE_LPC_H +/* LPC_MISC_CONTROL_BITS at D14F3x078 */ +/* The definitions of bits 9 and 10 are swapped on Picasso and older compared to Renoir/Cezanne + and newer, so we need to keep those in a SoC-specific header file. */ +#define LPC_LDRQ0_PU_EN BIT(10) +#define LPC_LDRQ0_PD_EN BIT(9) + #define SPIROM_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(8) #define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index aa483e4df78..daa51f11450 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -105,6 +105,8 @@ #define LPC_ALT_WIDEIO0_ENABLE BIT(0) #define LPC_MISC_CONTROL_BITS 0x78 +#define LPC_LDRQ1_EN BIT(3) +#define LPC_LDRQ0_EN BIT(2) #define LPC_NOHOG BIT(0) #define LPC_TRUSTED_PLATFORM_MODULE 0x7c From 3df6f4192835d1a15c2d08a74de9b1ce05528b65 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 30 Sep 2021 17:44:08 +0200 Subject: [PATCH 073/320] soc/amd/cezanne/include/southbridge: add some more PM register defines Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03. Signed-off-by: Felix Held Change-Id: Ib109efe679560604ff8209b4177611eb2aa9ebdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58068 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/include/soc/southbridge.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 31387b695d9..8a1150e0ae8 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -47,11 +47,15 @@ #define PM_ACPI_BIOS_RLS BIT(7) #define PM_ACPI_PWRBTNEN_EN BIT(8) #define PM_ACPI_REDUCED_HW_EN BIT(9) +#define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10) +#define PM_ACPI_S5_LPC_PIN_MODE BIT(11) #define PM_ACPI_BLOCK_PCIE_PME BIT(24) #define PM_ACPI_PCIE_WAK_MASK BIT(25) #define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_SPI_PAD_PU_PD 0x90 +#define PM_ESPI_CS_USE_DATA2 BIT(16) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) From abbb5b58ec191ac73b4cbfd5ce5a5bd529958cf9 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 19 Aug 2021 11:43:29 -0600 Subject: [PATCH 074/320] mb/google/guybrush: Use register and bit defines for eSPI setup It's hard to understand what this code is doing because it uses hard coded values, so use the register and bit defines instead. BUG=none TEST=Timeless build for guybrush results in identical binary. Signed-off-by: Raul E Rangel Signed-off-by: Felix Held Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051 Tested-by: build bot (Jenkins) --- src/mainboard/google/guybrush/bootblock.c | 28 +++++++++++++---------- src/mainboard/google/guybrush/verstage.c | 13 ++++++----- 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index cd276324983..5857d85b1bc 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -2,12 +2,15 @@ #include #include +#include #include #include #include #include #include +#include #include +#include #include #define FC350_PCIE_INIT_DELAY_US (20 * USECS_PER_MSEC) @@ -31,12 +34,13 @@ void bootblock_mainboard_early_init(void) size_t base_num_gpios, override_num_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios; - dword = pci_read_config32(SOC_LPC_DEV, 0x78); - dword &= 0xFFFFF9F3; - dword |= 0x200; - pci_write_config32(SOC_LPC_DEV, 0x78, dword); - pci_write_config32(SOC_LPC_DEV, 0x44, 0); - pci_write_config32(SOC_LPC_DEV, 0x48, 0); + dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); + dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ0_PD_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); + dword |= LPC_LDRQ0_PD_EN; + pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); + + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); + pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0); if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) return; @@ -53,13 +57,13 @@ void bootblock_mainboard_early_init(void) stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); - dword = pm_read32(0x90); - dword |= 1 << 16; - pm_write32(0x90, dword); + dword = pm_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_write32(PM_SPI_PAD_PU_PD, dword); - dword = pm_read32(0x74); - dword |= 3 << 10; - pm_write32(0x74, dword); + dword = pm_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_write32(PM_ACPI_CONF, dword); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index aaaaf038dec..a8c162f59b6 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -5,6 +5,7 @@ #include #include #include +#include static void setup_gpio(void) { @@ -29,12 +30,12 @@ void verstage_mainboard_early_init(void) if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { uint32_t dword; printk(BIOS_DEBUG, "Verstage configure eSPI\n"); - dword = pm_io_read32(0x90); - dword |= 1 << 16; - pm_io_write32(0x90, dword); + dword = pm_io_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_io_write32(PM_SPI_PAD_PU_PD, dword); - dword = pm_io_read32(0x74); - dword |= 3 << 10; - pm_io_write32(0x74, dword); + dword = pm_io_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_io_write32(PM_ACPI_CONF, dword); } } From 0cd81c325c631108db255546229a95ec2c4fd82b Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 30 Sep 2021 18:01:18 +0200 Subject: [PATCH 075/320] mb/google/guybrush: simplify LPC_MISC_CONTROL_BITS update Since the LPC_LDRQ0_PD_EN gets set right after it got cleared, we can remove the clearing of that bit. This is split off from the previous patch to be able to use timeless build to verify that the previous patch didn't change any behavior. Signed-off-by: Felix Held Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58069 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/google/guybrush/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 5857d85b1bc..3f7d5a1bf52 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -35,7 +35,7 @@ void bootblock_mainboard_early_init(void) const struct soc_amd_gpio *base_gpios, *override_gpios; dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); - dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ0_PD_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); + dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); dword |= LPC_LDRQ0_PD_EN; pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); From c3a9e5371453c9ce713ce6625105bde66ff28d76 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 30 Sep 2021 20:46:15 +0200 Subject: [PATCH 076/320] mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF write Document what setting the PM_ACPI_S5_LPC_PIN_MODE and PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will eventually be factored out and moved to the Cezanne SoC code. Signed-off-by: Felix Held Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/google/guybrush/bootblock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 3f7d5a1bf52..9c9fce7e8d9 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -61,6 +61,7 @@ void bootblock_mainboard_early_init(void) dword |= PM_ESPI_CS_USE_DATA2; pm_write32(PM_SPI_PAD_PU_PD, dword); + /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ dword = pm_read32(PM_ACPI_CONF); dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; pm_write32(PM_ACPI_CONF, dword); From 8b17cb8a8c92a8cd13d2a75c5c5a1b0fe5e1191f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 1 Oct 2021 20:59:25 +0200 Subject: [PATCH 077/320] mb/google/guybrush: drop printk in bootblock_mainboard_early_init bootblock_mainboard_early_init gets called before console_init. Signed-off-by: Felix Held Change-Id: Ia5a1da336e8dfc451177a5319a656c407c9fef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58077 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/google/guybrush/bootblock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 9c9fce7e8d9..040bc52441e 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -55,7 +55,8 @@ void bootblock_mainboard_early_init(void) * the Fibocom 350 PCIe init */ stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); - printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); + + /* Early eSPI interface configuration */ dword = pm_read32(PM_SPI_PAD_PU_PD); dword |= PM_ESPI_CS_USE_DATA2; From 0367c47eb08422c0b7364e5864d4e80199ea3699 Mon Sep 17 00:00:00 2001 From: Matt Papageorge Date: Fri, 8 Oct 2021 13:08:46 -0500 Subject: [PATCH 078/320] vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne Update UPD to include option for FSP to de-assert PCIe reset GPIOs as specified in the DXIO descriptors. This change requires FSP version 1.0.4 revision 2 otherwise setting this value does affect any FSP behavior. BUG=b:199780346 TEST=Verify toggling this value is reflected in FSP Cq-Depend: chrome-internal:4170351 Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a Signed-off-by: Matt Papageorge Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Karthik Ramasubramanian --- src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 7cb788e1751..f21ca42169a 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -26,7 +26,8 @@ typedef struct __packed { /** Offset 0x0078**/ uint32_t serial_port_refclk; /** Offset 0x007C**/ uint32_t serial_reserved; /** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52]; - /** Offset 0x0358**/ uint8_t pcie_reserved[52]; + /** Offset 0x0358**/ uint8_t fsp_owns_pcie_resets; + /** Offset 0x0359**/ uint8_t pcie_reserved[51]; /** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT]; /** Offset 0x03A0**/ uint8_t ddi_reserved[6]; /** Offset 0x03A6**/ uint8_t ccx_down_core_mode; From cc2fa98c586cadc2105172767e0b65cffff4026e Mon Sep 17 00:00:00 2001 From: Matt Papageorge Date: Fri, 8 Oct 2021 13:30:23 -0500 Subject: [PATCH 079/320] mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor coreboot normally owns PCIe resets for all Cezanne based systems. However during S0i3 resume coreboot cannot intervene for S0 GPIOs (S5 carry over fine) so we needed an alternate way to de-assert this reset on guybrush. This change feeds in the given S0 reset GPIO (69 in this case) so that SMU may de-assert this reset on S0i3 resume. BUG=b:199780346 TEST=With latest FSP verify SD device trains each of 10 cycles Cq-Depend: chrome-internal:4157948 Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356 Signed-off-by: Matt Papageorge Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/guybrush/port_descriptors.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index b745fc1317d..09bded05ce8 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -34,6 +34,7 @@ static const fsp_dxio_descriptor guybrush_czn_pci_wwan_descriptors[] = { .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, + .gpio_group_id = GPIO_69, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* WWAN */ @@ -116,6 +117,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, + .gpio_group_id = GPIO_69, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} }, { /* WWAN */ From fcc556f88e4ba7d61fb7656bdc09c5e2582e3e90 Mon Sep 17 00:00:00 2001 From: Patrick Huang Date: Tue, 5 Oct 2021 15:57:50 +0800 Subject: [PATCH 080/320] mb/google/guybrush/var/nipperkin: update MAX98360 HID to MX98360A Update MAX98360 ACPI HID from "MX98357A" to "MX98360A" BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Cq-Depend: chromium:3195465 Signed-off-by: Patrick Huang Change-Id: I8a1155848856db0cc4f42cfee0d914f8d1186b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58106 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- .../google/guybrush/variants/nipperkin/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index a53a6e57955..05ef586c7a6 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -143,7 +143,7 @@ chip soc/amd/cezanne end chip drivers/generic/max98357a - register "hid" = ""MX98357A"" + register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_31)" register "sdmode_delay" = "5" device generic 0.1 on end From 4d794bd4ec669966803a260c0056808ead4bb408 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 11 Oct 2021 14:00:54 +0200 Subject: [PATCH 081/320] soc/intel/*/cpu.c: Add missing space in comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a space before the `*/` C-style comment ending. Change-Id: Ic8928286c8237808b9e380e4393078792589615d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Reviewed-by: Michael Niewöhner --- src/soc/intel/alderlake/cpu.c | 2 +- src/soc/intel/cannonlake/cpu.c | 2 +- src/soc/intel/elkhartlake/cpu.c | 2 +- src/soc/intel/icelake/cpu.c | 2 +- src/soc/intel/jasperlake/cpu.c | 2 +- src/soc/intel/skylake/cpu.c | 2 +- src/soc/intel/tigerlake/cpu.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 2f1ac8ea0cd..801d10dd00d 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -55,7 +55,7 @@ static void configure_misc(void) /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 5ac7d5a405d..821694eb533 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -50,7 +50,7 @@ static void configure_misc(void) /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 6d86b0c3ced..0788c679f38 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -48,7 +48,7 @@ static void configure_misc(void) /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 6c3365b9cc8..3ca2172212c 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -48,7 +48,7 @@ static void configure_misc(void) /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 86077ff2d06..a58fe559690 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -48,7 +48,7 @@ static void configure_misc(void) /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 19f2e3a0bfb..3abf19b747b 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -49,7 +49,7 @@ static void configure_misc(void) wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */ msr.lo |= (1 << 23); /* Lock it */ diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 7bb9e611af2..084b5d64845 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -54,7 +54,7 @@ static void configure_misc(void) /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } From 0c7a25069e0d855013d082a87b5810c60336acb9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 11 Oct 2021 13:53:15 +0200 Subject: [PATCH 082/320] soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only. Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 821694eb533..99fcadd5818 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -62,8 +62,9 @@ static void configure_c_states(const config_t *const cfg) msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) { msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf); - wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); } + msr.lo |= CST_CFG_LOCK_MASK; + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* C-state Interrupt Response Latency Control 0 - package C3 latency */ msr.hi = 0; From 87e0b5b1d741179e4ce63c9950ad91f265417283 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Sat, 9 Oct 2021 14:11:42 -0600 Subject: [PATCH 083/320] util/autoport/bd82x6x.go: Fix includes Fix include of nvs.h to reflect commit 661ad4666c (ACPI: Select ACPI_SOC_NVS only where suitable); and re-add , removed in commit 0aad0531dc (util/autoport/bd82x6x.go: Drop unused includes), as the generated early_init.c uses pci_write_config16(). Signed-off-by: Nicholas Chin Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58210 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- util/autoport/bd82x6x.go | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index ad8918a041c..f00c89fb476 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -296,6 +296,7 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { sb.WriteString(` #include +#include #include #include @@ -359,7 +360,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) Add_gpl(gnvs) gnvs.WriteString(`#include -#include +#include /* FIXME: check this function. */ void mainboard_fill_gnvs(struct global_nvs *gnvs) From d2fadda52a5df72dbaedeed5c7f1c94bedbfd898 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 27 Sep 2021 19:26:20 +0200 Subject: [PATCH 084/320] soc/intel: replace dt option PmTimerDisabled by Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak Reviewed-by: Tim Crawford Reviewed-by: Nico Huber --- src/mainboard/system76/darp7/Kconfig | 4 ++++ src/mainboard/system76/darp7/devicetree.cb | 4 ---- src/mainboard/system76/galp5/Kconfig | 4 ++++ src/mainboard/system76/galp5/devicetree.cb | 4 ---- src/mainboard/system76/lemp10/Kconfig | 4 ++++ src/mainboard/system76/lemp10/devicetree.cb | 4 ---- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/chip.h | 2 +- src/soc/intel/alderlake/finalize.c | 7 +++---- src/soc/intel/elkhartlake/Kconfig | 1 + src/soc/intel/elkhartlake/chip.h | 2 -- src/soc/intel/elkhartlake/finalize.c | 12 ++---------- src/soc/intel/icelake/Kconfig | 1 + src/soc/intel/icelake/chip.h | 2 -- src/soc/intel/icelake/finalize.c | 12 +++--------- src/soc/intel/jasperlake/Kconfig | 1 + src/soc/intel/jasperlake/chip.h | 2 -- src/soc/intel/jasperlake/finalize.c | 12 +++--------- src/soc/intel/tigerlake/Kconfig | 1 + src/soc/intel/tigerlake/chip.h | 2 +- src/soc/intel/tigerlake/finalize.c | 10 +--------- 21 files changed, 31 insertions(+), 61 deletions(-) diff --git a/src/mainboard/system76/darp7/Kconfig b/src/mainboard/system76/darp7/Kconfig index 4af67681637..2c9cbc45bcb 100644 --- a/src/mainboard/system76/darp7/Kconfig +++ b/src/mainboard/system76/darp7/Kconfig @@ -52,4 +52,8 @@ config POST_DEVICE config UART_FOR_CONSOLE default 2 +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index c5297dce377..13970973372 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -26,10 +26,6 @@ chip soc/intel/tigerlake .tdp_pl2_override = 40, }" -# Finalize (soc/intel/tigerlake/finalize.c) - # PM Timer Disabled, saves power - register "PmTimerDisabled" = "1" - # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/galp5/Kconfig b/src/mainboard/system76/galp5/Kconfig index 79978c9a5d7..534c25319f0 100644 --- a/src/mainboard/system76/galp5/Kconfig +++ b/src/mainboard/system76/galp5/Kconfig @@ -53,4 +53,8 @@ config POST_DEVICE config UART_FOR_CONSOLE default 2 +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 322a2e10490..cf3a75e50f9 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -26,10 +26,6 @@ chip soc/intel/tigerlake .tdp_pl2_override = 51, }" -# Finalize (soc/intel/tigerlake/finalize.c) - # PM Timer Disabled, saves power - register "PmTimerDisabled" = "1" - # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/lemp10/Kconfig b/src/mainboard/system76/lemp10/Kconfig index 637c90285dc..1b6eec4a771 100644 --- a/src/mainboard/system76/lemp10/Kconfig +++ b/src/mainboard/system76/lemp10/Kconfig @@ -52,4 +52,8 @@ config POST_DEVICE config UART_FOR_CONSOLE default 2 +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + endif diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index f286ab50a02..1362b3d81ae 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -26,10 +26,6 @@ chip soc/intel/tigerlake .tdp_pl2_override = 30, }" -# Finalize (soc/intel/tigerlake/finalize.c) - # PM Timer Disabled, saves power - register "PmTimerDisabled" = "1" - # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) # Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index d3a41ee7339..e98878f14ee 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 270400b3412..699626b767f 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -286,7 +286,7 @@ struct soc_intel_alderlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; + /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index c821e25769f..4ef572b5f69 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -50,7 +50,7 @@ static void pch_handle_sideband(config_t *config) static void pch_finalize(void) { - config_t *config; + config_t *config = config_of_soc(); /* TCO Lock down */ tco_lockdown(); @@ -58,13 +58,12 @@ static void pch_finalize(void) /* TODO: Add Thermal Configuration */ /* - * Disable ACPI PM timer based on dt policy + * Disable ACPI PM timer based on Kconfig * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pch_handle_sideband(config); diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 6d44cd649cf..07af2faf663 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index b36d67a55f1..e18e52db945 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -236,8 +236,6 @@ struct soc_intel_elkhartlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; - /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index 3d1430fbe3a..ad3b4ef8673 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -24,26 +24,18 @@ static void pch_finalize(void) { - config_t *config; - /* TCO Lock down */ tco_lockdown(); /* TODO: Add Thermal Configuration */ /* - * Disable ACPI PM timer based on dt policy + * Disable ACPI PM timer based on Kconfig * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO - * - * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is - * just required to get to chip config. PCH_DEV_PMC is hidden by this - * point and hence removed from the root bus. pcidev_path_on_root thus - * returns NULL for PCH_DEV_PMC device. */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 8f6303de80b..74bae9c433c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index bef9adb4e2b..9adc5b05656 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -144,8 +144,6 @@ struct soc_intel_icelake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; - /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index bc8386abcc1..f828cc461dd 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -40,7 +40,7 @@ static void pch_handle_sideband(config_t *config) static void pch_finalize(void) { - config_t *config; + config_t *config = config_of_soc(); /* TCO Lock down */ tco_lockdown(); @@ -55,18 +55,12 @@ static void pch_finalize(void) pch_thermal_configuration(); /* - * Disable ACPI PM timer based on dt policy + * Disable ACPI PM timer based on Kconfig * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO - * - * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is - * just required to get to chip config. PCH_DEV_PMC is hidden by this - * point and hence removed from the root bus. pcidev_path_on_root thus - * returns NULL for PCH_DEV_PMC device. */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pch_handle_sideband(config); diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 3f9014cbacb..690df0cf2dd 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 3d680d3b7e7..87a98fb3518 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -152,8 +152,6 @@ struct soc_intel_jasperlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; - /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index a60e71916e5..9aef9eb5d90 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -44,7 +44,7 @@ static void pch_finalize(void) { uint32_t reg32; uint8_t *pmcbase; - config_t *config; + config_t *config = config_of_soc(); /* TCO Lock down */ tco_lockdown(); @@ -52,18 +52,12 @@ static void pch_finalize(void) /* TODO: Add Thermal Configuration */ /* - * Disable ACPI PM timer based on dt policy + * Disable ACPI PM timer based on Kconfig * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO - * - * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is - * just required to get to chip config. PCH_DEV_PMC is hidden by this - * point and hence removed from the root bus. pcidev_path_on_root thus - * returns NULL for PCH_DEV_PMC device. */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pmcbase = pmc_mmio_regs(); diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 37391782d21..fe7805ae708 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -40,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_2 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 465dea279a4..f0858db1b80 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -289,7 +289,7 @@ struct soc_intel_tigerlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; + /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 6ed60e7eefc..26cba964918 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -30,8 +30,6 @@ static void pch_finalize(void) { - config_t *config; - /* TCO Lock down */ tco_lockdown(); @@ -42,14 +40,8 @@ static void pch_finalize(void) * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO - * - * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is - * just required to get to chip config. PCH_DEV_PMC is hidden by this - * point and hence removed from the root bus. pcidev_path_on_root thus - * returns NULL for PCH_DEV_PMC device. */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pmc_clear_pmcon_sts(); From e240f8761f6ffb4bad8582a740a9a2aa25cd2c97 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 1 Oct 2021 20:11:45 +0200 Subject: [PATCH 085/320] soc/amd/common/block/include/psp_efs: use unsigned type for bitfield For 1 bit long bit fields an unsigned type should be used. In this case uint32_t is used instead of a generic unsigned int for both consistency reasons with the rest of the file and to clarify that the bits will be packed into a 32 bit memory location. TEST=Resulting image of a timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held Change-Id: Ic630d1709174d90336746bc37da504437c12643c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58224 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/include/amdblocks/psp_efs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index 7afd295df32..77da70a06f8 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -26,8 +26,8 @@ struct second_gen_efs { /* todo: expand for Server products */ - int gen:1; /* Client products only use bit 0 */ - int reserved:31; + uint32_t gen:1; /* Client products only use bit 0 */ + uint32_t reserved:31; } __attribute__((packed)); /* Copied from coreboot/util/amdfwtool.h */ From bf766832c5b29c2c7608ac3909d3222b283d4363 Mon Sep 17 00:00:00 2001 From: Zhi Li Date: Fri, 8 Oct 2021 18:48:03 +0800 Subject: [PATCH 086/320] mb/google/dedede/var/sasukette: Generate SPD ID for Samsung K4U6E3S4AB-MGCL Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=b:202480992 TEST=emerge-dedede coreboot Signed-off-by: Zhi Li Change-Id: I811f32defd50a940a09f238d38c962d2caf42855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58196 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Weimin Wu Reviewed-by: Paul Menzel --- .../google/dedede/variants/sasukette/memory/Makefile.inc | 2 +- .../dedede/variants/sasukette/memory/dram_id.generated.txt | 1 + .../google/dedede/variants/sasukette/memory/mem_parts_used.txt | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc b/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc index 490e591fd83..05ff3044779 100644 --- a/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/sasukette/memory/Makefile.inc @@ -4,4 +4,4 @@ # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/sasukette/memory src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt index b02dcd7dd25..cb4801e90b8 100644 --- a/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/sasukette/memory/dram_id.generated.txt @@ -5,3 +5,4 @@ DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) diff --git a/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt index be1daedfeb7..476f0f5736a 100644 --- a/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/sasukette/memory/mem_parts_used.txt @@ -10,3 +10,4 @@ # Part Name K4U6E3S4AA-MGCR +K4U6E3S4AB-MGCL From 59a8355e5f75c7e488efd8f7449a2a3e24dbf3dc Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 7 Oct 2021 16:12:06 +0200 Subject: [PATCH 087/320] mb/siemens/mc_ehl: Use SPD data from HW-Info in the first place The preferred location for the SPD data on mc_ehl based boards is the HW-Info data structure. Inside this structure there is a field of 128 bytes available for the SPD data. So in order to use it construct a buffer in memory which is 256 bytes long (as FSP requests minimum 256 bytes for the SPD data) and where the upper 128 bytes are taken from HW-Info holding the needed timing parameters for LPDDR4. If there is a case where HW-Info is not accessible or where the contained SPD data is not valid (by checking the CRC in HW-Info SPD) fall back to fixed SPD data set in CBFS. Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Paul Menzel --- .../siemens/mc_ehl/romstage_fsp_params.c | 25 ++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index 259870a8f47..a6ed234170c 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -1,20 +1,39 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include +#include +#include #include #include +#include +#include void mainboard_memory_init_params(FSPM_UPD *memupd) { static struct spd_info spd_info; const struct mb_cfg *board_cfg = variant_memcfg_config(); + static uint8_t spd_data[0x100]; + const char *cbfs_hwi_name = "hwinfo.hex"; /* TODO: Read the resistor strap to get number of memory segments */ bool half_populated = false; - /* Initialize spd information for LPDDR4x board */ - spd_info.read_type = READ_SPD_CBFS; - spd_info.spd_spec.spd_index = 0x00; + /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to + spd.bin in the case where the SPD data in HW-Info is not available or invalid. */ + memset(spd_data, 0, sizeof(spd_data)); + if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && + (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && + (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { + spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; + spd_info.spd_spec.spd_data_ptr_info.spd_data_len = sizeof(spd_data); + spd_info.read_type = READ_SPD_MEMPTR; + } else { + printk(BIOS_WARNING, "SPD in HW-Info not valid, fall back to spd.bin!\n"); + spd_info.read_type = READ_SPD_CBFS; + spd_info.spd_spec.spd_index = 0x00; + } /* Initialize variant specific configurations */ memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); } From 9cae17d028d4bd3b278fc89ada8e06287917e213 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 7 Oct 2021 16:22:51 +0200 Subject: [PATCH 088/320] mb/siemens/mc_ehl: Remove unneeded 'half_populated' variable Since the DRAM population is fixed to both channels on all mc_ehl boards there is no need to have this 'half_populated' variable at all. Simply use a fixed 'false' in the call of 'memcfg_init()' and delete this variable here. Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58177 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_ehl/romstage_fsp_params.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index a6ed234170c..f93e0affe8a 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -17,9 +17,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) static uint8_t spd_data[0x100]; const char *cbfs_hwi_name = "hwinfo.hex"; - /* TODO: Read the resistor strap to get number of memory segments */ - bool half_populated = false; - /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to spd.bin in the case where the SPD data in HW-Info is not available or invalid. */ memset(spd_data, 0, sizeof(spd_data)); @@ -35,5 +32,5 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) spd_info.spd_spec.spd_index = 0x00; } /* Initialize variant specific configurations */ - memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); + memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false); } From f72c7b154dfbbe7bc456d30ee80a875e2cb1c656 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 5 Oct 2021 21:42:57 +0200 Subject: [PATCH 089/320] soc/amd/cezanne,soc/intel/common: rework CPPC table generation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make use of the newly introduced ACPI macros for CPPC table generation that currently exists of a bunch of confusing assignments of structs that only get partially filled. Test: dumped SSDT before and after do not differ. Change-Id: I844d191b1134b98e409240ede71e2751e51e2159 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57888 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Lance Zhao Reviewed-by: Felix Held --- src/cpu/intel/common/common_init.c | 204 +++++------------------------ src/include/acpi/acpi.h | 4 +- src/soc/amd/cezanne/cppc.c | 177 ++++--------------------- 3 files changed, 63 insertions(+), 322 deletions(-) diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index c5f43ef22ea..6203922fd82 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -103,184 +103,44 @@ void set_feature_ctrl_lock(void) */ void cpu_init_cppc_config(struct cppc_config *config, u32 version) { - acpi_addr_t msr = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 8, - .bit_offset = 0, - .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, - .addrl = 0, - .addrh = 0, - }; - static const acpi_addr_t unsupported = { - .space_id = ACPI_ADDRESS_SPACE_MEMORY, - .bit_width = 0, - .bit_offset = 0, - .access_size = ACPI_ACCESS_SIZE_UNDEFINED, - .addrl = 0, - .addrh = 0, - }; - config->version = version; - msr.addrl = IA32_HWP_CAPABILITIES; - - /* - * Highest Performance: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x771, 0x04,)}, - */ - config->regs[CPPC_HIGHEST_PERF] = msr; - - /* - * Lowest Nonlinear Performance -> Most Efficient Performance: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)}, - */ - msr.bit_offset = 16; - config->regs[CPPC_LOWEST_NONL_PERF] = msr; - - /* - * Lowest Performance: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x771, 0x04,)}, - */ - msr.bit_offset = 24; - config->regs[CPPC_LOWEST_PERF] = msr; - - /* - * Guaranteed Performance Register: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, - */ - msr.bit_offset = 8; - config->regs[CPPC_GUARANTEED_PERF] = msr; - - msr.addrl = MSR_PLATFORM_INFO; - - /* - * Nominal Performance -> Maximum Non-Turbo Ratio: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)}, - */ - msr.bit_offset = 8; - config->regs[CPPC_NOMINAL_PERF] = msr; - - msr.addrl = IA32_HWP_REQUEST; - - /* - * Desired Performance Register: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x774, 0x04,)}, - */ - msr.bit_offset = 16; - config->regs[CPPC_DESIRED_PERF] = msr; - - /* - * Minimum Performance Register: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x774, 0x04,)}, - */ - msr.bit_offset = 0; - config->regs[CPPC_MIN_PERF] = msr; - - /* - * Maximum Performance Register: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x774, 0x04,)}, - */ - msr.bit_offset = 8; - config->regs[CPPC_MAX_PERF] = msr; - - /* - * Performance Reduction Tolerance Register: - * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, - */ - config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported; - - /* - * Time Window Register: - * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, - */ - config->regs[CPPC_TIME_WINDOW] = unsupported; - - /* - * Counter Wraparound Time: - * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, - */ - config->regs[CPPC_COUNTER_WRAP] = unsupported; - - msr.addrl = IA32_MPERF; - - /* - * Reference Performance Counter Register: - * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E7, 0x04,)}, - */ - msr.bit_width = 64; - msr.bit_offset = 0; - config->regs[CPPC_REF_PERF_COUNTER] = msr; - - msr.addrl = IA32_APERF; - - /* - * Delivered Performance Counter Register: - * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E8, 0x04,)}, - */ - config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr; - - msr.addrl = IA32_HWP_STATUS; - - /* - * Performance Limited Register: - * ResourceTemplate(){Register(FFixedHW, 0x01, 0x02, 0x777, 0x04,)}, - */ - msr.bit_width = 1; - msr.bit_offset = 2; - config->regs[CPPC_PERF_LIMITED] = msr; - - msr.addrl = IA32_PM_ENABLE; - - /* - * CPPC Enable Register: - * ResourceTemplate(){Register(FFixedHW, 0x01, 0x00, 0x770, 0x04,)}, - */ - msr.bit_offset = 0; - config->regs[CPPC_ENABLE] = msr; - - if (version >= 2) { - /* Autonomous Selection Enable is populated below */ + config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8); + config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_PLATFORM_INFO, 8, 8); + config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8); + config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8); + config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8); + config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 16, 8); + config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 0, 8); + config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 8, 8); + config->regs[CPPC_PERF_REDUCE_TOLERANCE] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_TIME_WINDOW] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_COUNTER_WRAP] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(IA32_MPERF, 0, 64); + config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(IA32_APERF, 0, 64); + config->regs[CPPC_PERF_LIMITED] = ACPI_REG_MSR(IA32_HWP_STATUS, 2, 1); + config->regs[CPPC_ENABLE] = ACPI_REG_MSR(IA32_PM_ENABLE, 0, 1); + + if (version < 2) + return; - msr.addrl = IA32_HWP_REQUEST; + config->regs[CPPC_AUTO_SELECT] = (acpi_addr_t){ + .space_id = ACPI_ADDRESS_SPACE_MEMORY, + .bit_width = 32, + .bit_offset = 0, + .access_size = ACPI_ACCESS_SIZE_UNDEFINED, + .addrl = 1, + }; - /* - * Autonomous Activity Window Register - * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)}, - */ - msr.bit_width = 10; - msr.bit_offset = 32; - config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = msr; + config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10); + config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 24, 8); + config->regs[CPPC_REF_PERF] = ACPI_REG_UNSUPPORTED; - /* - * Autonomous Energy Performance Preference Register - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)}, - */ - msr.bit_width = 8; - msr.bit_offset = 24; - config->regs[CPPC_PERF_PREF] = msr; - - /* Reference Performance */ - config->regs[CPPC_REF_PERF] = unsupported; - - if (version >= 3) { - /* Lowest Frequency */ - config->regs[CPPC_LOWEST_FREQ] = unsupported; - /* Nominal Frequency */ - config->regs[CPPC_NOMINAL_FREQ] = unsupported; - } + if (version < 3) + return; - /* - * Autonomous Selection Enable = 1 - * This field is actually the first addition in version 2 but - * it's so unlike the others I'm populating it last. - */ - msr.space_id = ACPI_ADDRESS_SPACE_MEMORY; - msr.bit_width = 32; - msr.bit_offset = 0; - msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED; - msr.addrl = 1; - config->regs[CPPC_AUTO_SELECT] = msr; - } + config->regs[CPPC_LOWEST_FREQ] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_NOMINAL_FREQ] = ACPI_REG_UNSUPPORTED; } void set_aesni_lock(void) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index e35accdf789..bc0b30c720a 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -130,7 +130,7 @@ typedef struct acpi_gen_regaddr { /* Macros for common resource types */ #define ACPI_REG_MSR(address, offset, width) \ - { \ + (acpi_addr_t){ \ .space_id = ACPI_ADDRESS_SPACE_FIXED, \ .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, \ .addrl = address, \ @@ -138,7 +138,7 @@ typedef struct acpi_gen_regaddr { .bit_width = width, \ } -#define ACPI_REG_UNSUPPORTED {0} +#define ACPI_REG_UNSUPPORTED (acpi_addr_t){0} /* Common ACPI HIDs */ #define ACPI_HID_FDC "PNP0700" diff --git a/src/soc/amd/cezanne/cppc.c b/src/soc/amd/cezanne/cppc.c index 79292a4153b..9d681c6ba74 100644 --- a/src/soc/amd/cezanne/cppc.c +++ b/src/soc/amd/cezanne/cppc.c @@ -13,156 +13,37 @@ */ void cpu_init_cppc_config(struct cppc_config *config, u32 version) { - acpi_addr_t msr = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 8, - .bit_offset = 0, - .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, - .addrl = 0, - .addrh = 0, - }; - static const acpi_addr_t unsupported = { - .space_id = ACPI_ADDRESS_SPACE_MEMORY, - .bit_width = 0, - .bit_offset = 0, - .access_size = ACPI_ACCESS_SIZE_UNDEFINED, - .addrl = 0, - .addrh = 0, - }; - config->version = version; - /* - * Highest Performance: - */ - msr.addrl = MSR_CPPC_CAPABILITY_1; - msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF; - config->regs[CPPC_HIGHEST_PERF] = msr; - - /* - * Lowest Nonlinear Performance -> Most Efficient Performance: - */ - msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF; - config->regs[CPPC_LOWEST_NONL_PERF] = msr; - - /* - * Lowest Performance: - */ - msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF; - config->regs[CPPC_LOWEST_PERF] = msr; - - /* - * Guaranteed Performance Register: - */ - config->regs[CPPC_GUARANTEED_PERF] = unsupported; - - /* - * Nominal Performance -> Maximum Non-Turbo Ratio: - */ - msr.bit_offset = SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF; - config->regs[CPPC_NOMINAL_PERF] = msr; - - /* - * Desired Performance Register: - */ - msr.addrl = MSR_CPPC_REQUEST; - msr.bit_offset = SHIFT_CPPC_REQUEST_DES_PERF; - config->regs[CPPC_DESIRED_PERF] = msr; - - /* - * Minimum Performance Register: - */ - msr.bit_offset = SHIFT_CPPC_REQUEST_MIN_PERF; - config->regs[CPPC_MIN_PERF] = msr; - - /* - * Maximum Performance Register: - */ - msr.bit_offset = SHIFT_CPPC_REQUEST_MAX_PERF; - config->regs[CPPC_MAX_PERF] = msr; - - /* - * Performance Reduction Tolerance Register: - */ - config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported; - - /* - * Time Window Register: - */ - config->regs[CPPC_TIME_WINDOW] = unsupported; - - /* - * Counter Wraparound Time: - */ - config->regs[CPPC_COUNTER_WRAP] = unsupported; - - /* - * Reference Performance Counter Register: - */ - msr.addrl = MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT; - msr.bit_width = 64; - msr.bit_offset = 0; - config->regs[CPPC_REF_PERF_COUNTER] = msr; - - /* - * Delivered Performance Counter Register: - */ - msr.addrl = MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT; - config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr; - - /* - * Performance Limited Register: - */ - msr.bit_width = 1; - msr.addrl = MSR_CPPC_STATUS; - msr.bit_offset = 1; - config->regs[CPPC_PERF_LIMITED] = msr; - - /* - * CPPC Enable Register: - */ - msr.addrl = MSR_CPPC_ENABLE; - msr.bit_offset = 0; - config->regs[CPPC_ENABLE] = msr; - - if (version >= 2) { - /* Autonomous Selection Enable is populated below */ - - /* - * Autonomous Activity Window Register - */ - config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported; - - /* - * Autonomous Energy Performance Preference Register - */ - msr.addrl = MSR_CPPC_REQUEST; - msr.bit_width = 8; - msr.bit_offset = SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF; - config->regs[CPPC_PERF_PREF] = msr; - - /* Reference Performance */ - config->regs[CPPC_REF_PERF] = unsupported; - - if (version >= 3) { - /* Lowest Frequency */ - config->regs[CPPC_LOWEST_FREQ] = unsupported; - /* Nominal Frequency */ - config->regs[CPPC_NOMINAL_FREQ] = unsupported; - } - - /* - * Autonomous Selection Enable = 1 - * This field is actually the first addition in version 2 but - * it's so unlike the others I'm populating it last. - */ - msr.space_id = ACPI_ADDRESS_SPACE_MEMORY; - msr.bit_width = 32; - msr.bit_offset = 0; - msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED; - msr.addrl = 1; - config->regs[CPPC_AUTO_SELECT] = unsupported; - } + config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); + config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8); + config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8); + config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8); + config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8); + config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8); + config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8); + config->regs[CPPC_PERF_REDUCE_TOLERANCE] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_TIME_WINDOW] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_COUNTER_WRAP] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); + config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); + config->regs[CPPC_PERF_LIMITED] = ACPI_REG_MSR(MSR_CPPC_STATUS, 1, 1); + config->regs[CPPC_ENABLE] = ACPI_REG_MSR(MSR_CPPC_ENABLE, 0, 1); + + if (version < 2) + return; + + config->regs[CPPC_AUTO_SELECT] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8); + config->regs[CPPC_REF_PERF] = ACPI_REG_UNSUPPORTED; + + if (version < 3) + return; + + config->regs[CPPC_LOWEST_FREQ] = ACPI_REG_UNSUPPORTED; + config->regs[CPPC_NOMINAL_FREQ] = ACPI_REG_UNSUPPORTED; } From 302b1e508ca1eb3edb551511e24db70bb1624eb4 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 7 Oct 2021 18:27:14 -0500 Subject: [PATCH 090/320] mb/google/poppy: set SMBIOS enclosure type for all poppy variants Some poppy variants did not select a system type, which led to the default desktop type being set. Select the best fit enclosure type for each variant. Alphabetize the variant-specific options for improved readability. Change-Id: I7c23f8fa3ae1de67f7a68b8a4e9ec16c4e8044df Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/58229 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/poppy/Kconfig | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index f4be0c53aee..586180b30eb 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -135,17 +135,19 @@ config VARIANT_SPECIFIC_OPTIONS_ATLAS select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EXCLUDE_NATIVE_SD_INTERFACE + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_SPI_TPM_CR50 + select SYSTEM_TYPE_LAPTOP select VARIANT_HAS_CAMERA_ACPI - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config VARIANT_SPECIFIC_OPTIONS_POPPY def_bool n select DRIVERS_I2C_MAX98927 + select MAINBOARD_HAS_I2C_TPM_CR50 select NO_FADT_8042 + select SYSTEM_TYPE_LAPTOP select VARIANT_HAS_CAMERA_ACPI - select MAINBOARD_HAS_I2C_TPM_CR50 config VARIANT_SPECIFIC_OPTIONS_NAMI def_bool n @@ -155,14 +157,16 @@ config VARIANT_SPECIFIC_OPTIONS_NAMI select DRIVERS_SPI_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select MAINBOARD_HAS_SPI_TPM_CR50 + select SYSTEM_TYPE_LAPTOP config VARIANT_SPECIFIC_OPTIONS_NAUTILUS def_bool n select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 - select VARIANT_HAS_CAMERA_ACPI select MAINBOARD_HAS_I2C_TPM_CR50 + select SYSTEM_TYPE_CONVERTIBLE + select VARIANT_HAS_CAMERA_ACPI config VARIANT_SPECIFIC_OPTIONS_NOCTURNE def_bool n @@ -173,11 +177,11 @@ config VARIANT_SPECIFIC_OPTIONS_NOCTURNE select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EXCLUDE_NATIVE_SD_INTERFACE + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select MAINBOARD_HAS_SPI_TPM_CR50 select NO_FADT_8042 select SYSTEM_TYPE_DETACHABLE select VARIANT_HAS_CAMERA_ACPI - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config VARIANT_SPECIFIC_OPTIONS_RAMMUS def_bool n @@ -188,14 +192,15 @@ config VARIANT_SPECIFIC_OPTIONS_RAMMUS select DRIVERS_USB_ACPI select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_SPI_TPM_CR50 + select SYSTEM_TYPE_LAPTOP config VARIANT_SPECIFIC_OPTIONS_SORAKA def_bool n select DRIVERS_I2C_MAX98927 + select MAINBOARD_HAS_I2C_TPM_CR50 select NO_FADT_8042 select SYSTEM_TYPE_DETACHABLE select VARIANT_HAS_CAMERA_ACPI - select MAINBOARD_HAS_I2C_TPM_CR50 config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES From a31d6cd5d02a21452d92859a682ebbc674080c49 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Thu, 7 Oct 2021 07:15:38 +0200 Subject: [PATCH 091/320] drivers/pc80/tpm: Fix wrong debug message MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is the wrong register offset printed in the debug log when the data register is written: 'lpc_tpm: Write reg 0x18 with 0xnn' should be 'lpc_tpm: Write reg 0x24 with 0xnn' for data FIFO access. This can be confusing when searching for issues with the help of the TPM debug messages since the code itself is correct. Fix this error. Change-Id: Ic28ee5a07146e804574b887ea05c62e7e88e9078 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58155 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki --- src/drivers/pc80/tpm/tis.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 526b574611d..2b29acfaa90 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -172,7 +172,7 @@ static inline u8 tpm_read_data(int locality) static inline void tpm_write_data(u8 data, int locality) { - TPM_DEBUG_IO_WRITE(TIS_REG_STS, data); + TPM_DEBUG_IO_WRITE(TIS_REG_DATA_FIFO, data); write8(TIS_REG(locality, TIS_REG_DATA_FIFO), data); } From dacff81a66676e8816740b98266aa2257137fd81 Mon Sep 17 00:00:00 2001 From: Zhenguo Li Date: Tue, 7 Sep 2021 19:45:37 +0800 Subject: [PATCH 092/320] soc/mediatek/mt8195: add tracker dump Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Signed-off-by: Zhenguo Li Change-Id: If457f4a096cd63038bf6b40552aa3caaba33d5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58243 Reviewed-by: Rex-BC Chen Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- .../common/include/soc/tracker_common.h | 40 ++++++ src/soc/mediatek/common/tracker.c | 125 ++++++++++++++++++ src/soc/mediatek/mt8195/Makefile.inc | 2 +- .../mediatek/mt8195/include/soc/addressmap.h | 12 +- src/soc/mediatek/mt8195/soc.c | 2 + 5 files changed, 176 insertions(+), 5 deletions(-) create mode 100644 src/soc/mediatek/common/include/soc/tracker_common.h create mode 100644 src/soc/mediatek/common/tracker.c diff --git a/src/soc/mediatek/common/include/soc/tracker_common.h b/src/soc/mediatek/common/include/soc/tracker_common.h new file mode 100644 index 00000000000..a68d329a254 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/tracker_common.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_TRACKER_H +#define SOC_MEDIATEK_COMMON_TRACKER_H + +#define BUS_DBG_CON 0x000 +#define BUS_DBG_TIMER_CON0 0x004 +#define BUS_DBG_TIMER_CON1 0x008 +#define BUS_TRACE_CON_1 0x900 +#define BUS_TRACE_CON_AO_1 0x9FC +#define BUS_TRACE_CON_2 0xA00 +#define BUS_TRACE_CON_AO_2 0xAFC +#define BUS_TRACE_EN 16 + +#define SYS_TRACK_ENTRY 64 +#define INFRA_ENTRY_NUM 32 +#define PERI_ENTRY_NUM 16 + +#define AR_TRACK_OFFSET 0x0100 +#define AW_TRACK_OFFSET 0x0300 + +#define BUSTRACKER_TIMEOUT 0x300 + +#define BUS_DBG_CON_IRQ_AR_STA0 0x00000100 +#define BUS_DBG_CON_IRQ_AW_STA0 0x00000200 +#define BUS_DBG_CON_IRQ_AR_STA1 0x00100000 +#define BUS_DBG_CON_IRQ_AW_STA1 0x00200000 +#define BUS_DBG_CON_TIMEOUT (BUS_DBG_CON_IRQ_AR_STA0 | BUS_DBG_CON_IRQ_AW_STA0 | \ + BUS_DBG_CON_IRQ_AR_STA1 | BUS_DBG_CON_IRQ_AW_STA1) + +enum { + TRACKER_SYSTRACKER = 0, + TRACKER_INFRATRACKER, + TRACKER_PERISYSTRACKER, + TRACKER_NUM, +}; + +void bustracker_init(void); + +#endif diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c new file mode 100644 index 00000000000..6d4e6b2f057 --- /dev/null +++ b/src/soc/mediatek/common/tracker.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static struct tracker { + uintptr_t base_addr; + u32 timeout; + u32 entry; + u32 offset[2]; + const char *str; +} tracker_data[TRACKER_NUM] = { + [TRACKER_SYSTRACKER] = { + .base_addr = DBG_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = SYS_TRACK_ENTRY, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "systracker", + }, + [TRACKER_INFRATRACKER] = { + .base_addr = INFRA_TRACKER_BASE, + .timeout = BUSTRACKER_TIMEOUT, + .entry = INFRA_ENTRY_NUM, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "infra_tracker", + }, + [TRACKER_PERISYSTRACKER] = { + .base_addr = PERI_TRACKER_BASE, + .timeout = BUSTRACKER_TIMEOUT, + .entry = PERI_ENTRY_NUM, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "peri_tracker", + }, +}; + +static void setup_init(void) +{ + u32 val; + /* + * Set infra/peri tracker timeout. + * timeout = clock_in_mhz * 1000 / 16 * timeout_in_ms + * + * timeout: 200ms + * infra tracker clock: 156MHz + * peri tracker clock: 78MHz + */ + val = 156 * 1000 / 16 * 200; + write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + + val = 78 * 1000 / 16 * 200; + write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + + /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); + + /* + * Enable infra/peri tracker. + * bit[0] - BUS_DBG_EN + * bit[1] - TIMEOUT_EN + * bit[2] - SLV_ERR_EN + * bit[13] - HALT_ON_TIMEOUT_EN + * bit[14] - BUS_OT_WEN_CTRL + */ + val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); + +} + +static void tracker_dump_data(void) +{ + int i, j, k; + int size; + uintptr_t reg; + struct tracker *tra; + + for (j = 0; j < TRACKER_NUM; j++) { + tra = &tracker_data[j]; + + if (!(read32((void *)(tra->base_addr)) & tra->timeout)) + continue; + + printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); + for (k = 0; k < 2; k++) { + /* + * for systracker: + * offset[0] dump from offset 0x100 ~ 0x2F8. + * offset[1] dump from offset 0x300 ~ 0x4FC + * + * for infra tracker: + * offset[0] dump from offset 0x100 ~ 0x1F8 + * offset[1] dump from offset 0x300 ~ 0x3FC + * + * for perisys tracker: + * offset[0] dump from offset 0x100 ~ 0x2F8 + * offset[1] dump from offset 0x300 ~ 0x4FC + */ + size = 2 * tra->entry; + for (i = 0; i < size; i++) { + reg = tra->base_addr + tra->offset[k] + i * 4; + printk(BIOS_INFO, "%#lx:%#x,", reg, read32((void *)reg)); + + if (i % 4 == 3 || i == size - 1) + printk(BIOS_INFO, "\n"); + } + } + + printk(BIOS_INFO, "**Dump %s debug register end**\n", tra->str); + } +} + +void bustracker_init(void) +{ + tracker_dump_data(); + setup_init(); +} diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 6540ce2288c..5d444c7564f 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -48,7 +48,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c romstage-y += mt6691.c romstage-y += mt6360.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c - +ramstage-y += ../common/tracker.c ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index 3ddaa54d748..88b545a97e9 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -4,10 +4,11 @@ #define __SOC_MEDIATEK_MT8195_INCLUDE_SOC_ADDRESSMAP_H__ enum { - MCUSYS_BASE = 0x0C530000, - MCUPM_SRAM_BASE = 0x0C540000, - MCUPM_CFG_BASE = 0x0C560000, - IO_PHYS = 0x10000000, + MCUSYS_BASE = 0x0C530000, + MCUPM_SRAM_BASE = 0x0C540000, + MCUPM_CFG_BASE = 0x0C560000, + BUS_TRACE_MONITOR_BASE = 0x0D040000, + IO_PHYS = 0x10000000, }; enum { @@ -35,12 +36,15 @@ enum { DEVAPC_PERI2_AO_BASE = IO_PHYS + 0x00038000, DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000, DEVAPC_FMEM_AO_BASE = IO_PHYS + 0x00044000, + DBG_TRACKER_BASE = IO_PHYS + 0x00208000, + PERI_TRACKER_BASE = IO_PHYS + 0x00218000, EMI0_BASE = IO_PHYS + 0x00219000, EMI1_BASE = IO_PHYS + 0x0021D000, I2C_DMA_BASE = IO_PHYS + 0x00220080, EMI1_SUB_BASE = IO_PHYS + 0x00225000, EMI0_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, SCP_CFG_BASE = IO_PHYS + 0x00700000, diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 399196489a9..20bd226cc96 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -35,6 +36,7 @@ static void soc_init(struct device *dev) ufs_disable_refclk(); hdmi_low_power_setting(); + bustracker_init(); } static struct device_operations soc_ops = { From 6b0661d12099a6a582aee8f0f649f4bf2b382dd7 Mon Sep 17 00:00:00 2001 From: Zhenguo Li Date: Fri, 8 Oct 2021 17:08:30 +0800 Subject: [PATCH 093/320] soc/mediatek/mt8192: add tracker dump Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Signed-off-by: Zhenguo Li Change-Id: I82f8e6e5f8ccb7f8246cae45a01a3ddd5f2966f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58244 Reviewed-by: Rex-BC Chen Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8192/Makefile.inc | 1 + src/soc/mediatek/mt8192/include/soc/addressmap.h | 12 ++++++++---- src/soc/mediatek/mt8192/soc.c | 2 ++ 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 934b6888b2c..d713e4d4c2a 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -63,6 +63,7 @@ ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c +ramstage-y += ../common/tracker.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 8dd76d9df37..440f7ca3c9e 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -4,10 +4,11 @@ #define __SOC_MEDIATEK_MT8192_INCLUDE_SOC_ADDRESSMAP_H__ enum { - MCUSYS_BASE = 0x0C530000, - MCUPM_SRAM_BASE = 0x0C540000, - MCUPM_CFG_BASE = 0x0C560000, - IO_PHYS = 0x10000000, + MCUSYS_BASE = 0x0C530000, + MCUPM_SRAM_BASE = 0x0C540000, + MCUPM_CFG_BASE = 0x0C560000, + BUS_TRACE_MONITOR_BASE = 0x0D040000, + IO_PHYS = 0x10000000, }; enum { @@ -35,10 +36,13 @@ enum { DEVAPC_PERI2_AO_BASE = IO_PHYS + 0x00038000, DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000, DEVAPC_FMEM_AO_BASE = IO_PHYS + 0x00044000, + DBG_TRACKER_BASE = IO_PHYS + 0x00208000, + PERI_TRACKER_BASE = IO_PHYS + 0x00218000, I2C_DMA_BASE = IO_PHYS + 0x00217080, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, SCP_CFG_BASE = IO_PHYS + 0x00700000, diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 006a212da9f..355827ac27a 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -33,6 +34,7 @@ static void soc_init(struct device *dev) if (CONFIG(MTK_DFD)) dfd_init(); ufs_disable_refclk(); + bustracker_init(); } static struct device_operations soc_ops = { From ef90f07d065156f911aa29eac98ea394f4d776c4 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Thu, 7 Oct 2021 17:08:30 +0800 Subject: [PATCH 094/320] mb/google/guybrush/var/nipperkin: update fw_config field update fw_config for nipperkin BUG=b:196909635 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kevin Chiu Change-Id: Icd2c5509450e70aed158f146179f3a7fa24b547a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58161 Tested-by: build bot (Jenkins) Reviewed-by: Bhanu Prakash Maiya Reviewed-by: Rob Barnes --- .../variants/nipperkin/overridetree.cb | 26 ++++++++----------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 05ef586c7a6..77e35bc59fe 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -1,32 +1,28 @@ # SPDX-License-Identifier: GPL-2.0-or-later fw_config - field USB_DB 0 1 - option USB_DB_A1_PS8811_C1_PS8818 0 - option USB_DB_A1_ANX7491_C1_ANX7451 1 - end - field FORM_FACTOR 2 - option FORM_FACTOR_CLAMSHELL 0 - option FORM_FACTOR_CONVERTIBLE 1 - end - field KB_BL 3 + field KB_BL 0 option KB_BL_ABSENT 0 option KB_BL_PRESENT 1 end - field FP 4 + field FP 1 option FP_ABSENT 0 option FP_PRESENT 1 end - field WLAN 5 6 + field WLAN 2 3 option WLAN_WCN6856 0 option WLAN_RTL8852 1 end - field WWAN 7 8 + field WWAN 4 5 option WWAN_DIASABLED 0 option WWAN_L850GL 1 end - field BEEP_MODE 9 - option BEEP_MODE_AMP 0 - option BEEP_MODE_BIT_BANG 1 + field STORAGE 6 + option STORAGE_EMMC 0 + option STORAGE_SSD 1 + end + field KB_MAP 7 + option KB_MAP_PRIVACY 0 + option KB_MAP_NO_PRIVACY 1 end end From 425e73d3f545430884ad2020d56300aae88a1714 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 20 Sep 2021 16:31:33 +0200 Subject: [PATCH 095/320] soc/amd/*: Enable ACPIMMIO decode first in fch_pre_init Since the GPIO mux/control MMIO regions are within the ACPIMMIO region, we need to call enable_acpimmio_decode_pm04 here first so that accessing the GPIO registers will work. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473 Signed-off-by: Felix Held Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/early_fch.c | 4 +++- src/soc/amd/picasso/early_fch.c | 4 +++- src/soc/amd/stoneyridge/southbridge.c | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index bddcbee418e..7782d43fdd9 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -44,9 +44,11 @@ void configure_port80_routing_early(void) /* Before console init */ void fch_pre_init(void) { + /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access + the GPIO registers. */ + enable_acpimmio_decode_pm04(); lpc_early_init(); fch_spi_early_init(); - enable_acpimmio_decode_pm04(); fch_smbus_init(); fch_enable_cf9_io(); fch_enable_legacy_io(); diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index ae3aed2d98d..3d1cd1b2e7c 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -42,13 +42,15 @@ static void reset_i2c_peripherals(void) /* Before console init */ void fch_pre_init(void) { + /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access + the GPIO registers. */ + enable_acpimmio_decode_pm04(); lpc_early_init(); if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) lpc_configure_decodes(); fch_spi_early_init(); - enable_acpimmio_decode_pm04(); fch_smbus_init(); fch_enable_cf9_io(); fch_enable_legacy_io(); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7493770fac9..de27ac540a6 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -328,6 +328,9 @@ void bootblock_fch_early_init(void) { int reboot = 0; + /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access + the GPIO registers. */ + enable_acpimmio_decode_pm04(); lpc_enable_rom(); sb_enable_lpc(); lpc_enable_port80(); @@ -335,7 +338,6 @@ void bootblock_fch_early_init(void) lpc_enable_spi_prefetch(); sb_init_spi_base(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ - enable_acpimmio_decode_pm04(); fch_smbus_init(); fch_enable_cf9_io(); setup_spread_spectrum(&reboot); From 2d17ea4d501c8e0f68813cda80dd6412b10ca0d8 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 5 Oct 2021 13:57:30 -0600 Subject: [PATCH 096/320] soc/amd/common/block/espi_util: Refactor eSPI Setup eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/bootblock.c | 6 ------ src/soc/amd/cezanne/early_fch.c | 15 +++------------ src/soc/amd/cezanne/include/soc/southbridge.h | 1 - src/soc/amd/common/block/include/amdblocks/espi.h | 11 +++++++++++ src/soc/amd/picasso/early_fch.c | 6 +++--- 5 files changed, 17 insertions(+), 22 deletions(-) diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c index fc1c5e7c0af..c3cb1384732 100644 --- a/src/soc/amd/cezanne/bootblock.c +++ b/src/soc/amd/cezanne/bootblock.c @@ -92,12 +92,6 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) set_caching(); write_resume_eip(); enable_pci_mmconf(); - /* - * If NO_EARLY_BOOTBLOCK_POSTCODES is selected, we need to initialize port80h - * routing as early as possible - */ - if (CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)) - configure_port80_routing_early(); /* * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 7782d43fdd9..69458b6220d 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -32,22 +32,16 @@ static void reset_i2c_peripherals(void) sb_reset_i2c_peripherals(&reset_info); } -/* Initialize port80h routing early if needed */ -void configure_port80_routing_early(void) -{ - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { - mb_set_up_early_espi(); - espi_setup(); - } -} - /* Before console init */ void fch_pre_init(void) { /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access the GPIO registers. */ enable_acpimmio_decode_pm04(); + /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); + /* Setup eSPI to enable port80 routing. */ + configure_espi(); fch_spi_early_init(); fch_smbus_init(); fch_enable_cf9_io(); @@ -80,7 +74,4 @@ void fch_early_init(void) if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); - - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)) - espi_setup(); } diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 8a1150e0ae8..88137075c76 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -111,7 +111,6 @@ #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) -void configure_port80_routing_early(void); void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 9a563f9e36e..7e49ea0f2e5 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -131,4 +131,15 @@ int espi_setup(void); /* Run mainboard configuration needed to set up eSPI */ void mb_set_up_early_espi(void); +/* Setup eSPI with any mainboard specific initialization. */ +static inline void configure_espi(void) +{ + /* If eSPI is setup in PSP Verstage, continue with that. Else setup eSPI to perform + port80h routing as early as possible. */ + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { + mb_set_up_early_espi(); + espi_setup(); + } +} + #endif /* AMD_BLOCK_ESPI_H */ diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 3d1cd1b2e7c..8771e387bc7 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -45,7 +45,10 @@ void fch_pre_init(void) /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access the GPIO registers. */ enable_acpimmio_decode_pm04(); + /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); + /* Setup eSPI to enable port80 routing. */ + configure_espi(); if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) lpc_configure_decodes(); @@ -81,7 +84,4 @@ void fch_early_init(void) if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); - - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) - espi_setup(); } From 5705b63a08d28ddf8c5a22600e19aa8dd8513614 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 5 Oct 2021 14:11:13 -0600 Subject: [PATCH 097/320] soc/amd/common: Add support to read and set SPI speeds from verstage Currently all SPI speed configurations are done through EFS at build time. There is a need to apply SPI speed overrides at run-time - eg. based on board version after assessing the signal integrity. This override configuration can be carried out by PSP verstage and bootblock. Export the APIs to set and read SPI speeds from both PSP verstage and bootblock. BUG=None TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I281531e506b56173471b918c746f58d1ad97162c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/include/amdblocks/psp_efs.h | 1 - src/soc/amd/common/block/include/amdblocks/spi.h | 1 + src/soc/amd/common/block/psp/Makefile.inc | 1 + src/soc/amd/common/block/psp/psp_efs.c | 9 +++++++-- src/soc/amd/common/block/spi/fch_spi.c | 2 +- src/soc/amd/common/psp_verstage/fch.c | 2 ++ 6 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index 77da70a06f8..0da7ff79aaa 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -7,7 +7,6 @@ #include #define EFS_OFFSET (0xffffff - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000 + 1) -#define EFS_ADDRESS (0xff000000 + EFS_OFFSET) #define EMBEDDED_FW_SIGNATURE 0x55aa55aa diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index c4ad44f8a49..eaea0f79c92 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -116,4 +116,5 @@ void spi_write8(uint8_t reg, uint8_t val); void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); +void fch_spi_config_modes(void); #endif /* AMD_BLOCK_SPI_H */ diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index db9ebda5949..2b407a2b4c4 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -23,5 +23,6 @@ smm-y += psp_gen2.c smm-y += psp_smm_gen2.c bootblock-y += psp_efs.c +verstage-y += psp_efs.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c index b0397f6ae89..5814f48c638 100644 --- a/src/soc/amd/common/block/psp/psp_efs.c +++ b/src/soc/amd/common/block/psp/psp_efs.c @@ -2,13 +2,18 @@ #include #include +#include +#include #include -struct _embedded_firmware *efs = (struct _embedded_firmware *)EFS_ADDRESS; +static struct _embedded_firmware *efs; bool efs_is_valid(void) { - if (efs->signature != EMBEDDED_FW_SIGNATURE) + if (!efs) + efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs)); + + if (!efs || efs->signature != EMBEDDED_FW_SIGNATURE) return false; return true; diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 38be7be8cf3..51787fae926 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -91,7 +91,7 @@ static void fch_spi_set_read_mode(u32 mode) spi_write32(SPI_CNTRL0, val | SPI_READ_MODE(mode)); } -static void fch_spi_config_modes(void) +void fch_spi_config_modes(void) { uint8_t read_mode, fast_speed; uint8_t normal_speed = CONFIG_NORMAL_READ_SPI_SPEED; diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index c74e88fd128..f578bcb3394 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -161,4 +161,6 @@ void verstage_soc_init(void) printk(BIOS_DEBUG, "Setting up i2c\n"); i2c_soc_early_init(); printk(BIOS_DEBUG, "i2c setup\n"); + fch_spi_config_modes(); + show_spi_speeds_and_modes(); } From 2526be8db381addd398afae55370127f3a747cdc Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 5 Oct 2021 13:46:40 -0600 Subject: [PATCH 098/320] soc/amd/common/block/spi: Support fast speed override Add support to override SPI ROM fast speed based on board version. This will allow boards to start at lower speeds during bringup and then switch to higher speeds after assessing the signal integrity. Also implement a default no-op override. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58116 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Raul Rangel --- src/soc/amd/common/block/include/amdblocks/spi.h | 1 + src/soc/amd/common/block/spi/fch_spi.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index eaea0f79c92..35a3782f7a2 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -117,4 +117,5 @@ void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); void fch_spi_config_modes(void); +void mainboard_spi_fast_speed_override(uint8_t *fast_speed); #endif /* AMD_BLOCK_SPI_H */ diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 51787fae926..fad8cd9951d 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -50,6 +50,11 @@ void show_spi_speeds_and_modes(void) printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]); } +void __weak mainboard_spi_fast_speed_override(uint8_t *fast_speed) +{ + /* No overriding SPI speeds. */ +} + static uint8_t lower_speed(uint8_t speed1, uint8_t speed2) { uint8_t speeds[] = {SPI_SPEED_800K, SPI_SPEED_16M, SPI_SPEED_22M, @@ -102,6 +107,7 @@ void fch_spi_config_modes(void) read_mode = CONFIG_EFS_SPI_READ_MODE; fast_speed = CONFIG_EFS_SPI_SPEED; } + mainboard_spi_fast_speed_override(&fast_speed); if (fast_speed != CONFIG_EFS_SPI_SPEED) { normal_speed = lower_speed(normal_speed, fast_speed); From 9eaaf0d309af6fce19132676314932e85b790b65 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 5 Oct 2021 14:20:14 -0600 Subject: [PATCH 099/320] mb/google/guybrush: Override SPI Fast speeds Add support to override SPI fast speeds based on board version from both bootblock and verstage. Overrides apply for Guybrush only and SPI speed is overridden from 66 MHz to 100 MHz starting board version 4. This will help to improve the boot time on board version by ~60 ms and still allow the old boards to boot with 66 MHz. BUG=b:199779306 TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58117 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Raul Rangel --- src/mainboard/google/guybrush/Kconfig | 16 ++++++++++++++++ src/mainboard/google/guybrush/Makefile.inc | 1 + src/mainboard/google/guybrush/chromeos.c | 9 +++++++++ 3 files changed, 26 insertions(+) diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index c259d25fb59..e5f138258ff 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -111,6 +111,22 @@ config NORMAL_READ_SPI_SPEED config ALT_SPI_SPEED default 0 # 66MHz +config OVERRIDE_EFS_SPI_SPEED + int + default 3 if EM100 + default 4 # 100MHz + help + Override EFS SPI Speed Configuration to be applied based on certain + board version. + +config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD + hex + default 0x4 if BOARD_GOOGLE_GUYBRUSH + default 0xffffffff + help + Minimum board version starting which the Override EFS SPI Speed + configuration has to be applied. + endif # !EM100 config VARIANT_DIR diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index f3140ddbdb2..6bc32882767 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin),) $(info APCB sources present.) diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index c1621d917ec..a43b3032bb6 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include @@ -36,3 +37,11 @@ int get_ec_is_trusted(void) /* EC is trusted if not in RW. */ return !gpio_get(GPIO_EC_IN_RW); } + +void mainboard_spi_fast_speed_override(uint8_t *fast_speed) +{ + uint32_t board_ver = board_id(); + + if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) + *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; +} From 680539ce8a65ddcf1170d1c6e84c6b8d0f45897a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 19 Nov 2020 13:59:08 -0600 Subject: [PATCH 100/320] mb/google/wyvern: use SaGv_FixedHigh No need for dynamic config (and the additional RAM training time) on a Chromebox; always use high power/high performance mode. Change-Id: I8ad773d1c616b746235ec67b98b83c5910464140 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/58230 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- src/mainboard/google/hatch/variants/wyvern/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb index 8ca9ce4683c..b9dd489cf2d 100644 --- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb @@ -20,6 +20,10 @@ chip soc/intel/cannonlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # No need for dynamic config (and the additional RAM training time) + # on a Chromebox; always use high power/high performance mode + register "SaGv" = "SaGv_FixedHigh" + # USB configuration register "usb2_ports[0]" = "{ .enable = 1, From 15539f1b50f55e71f5a0b87ef6c13c361aee2026 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 11 Oct 2021 17:19:29 -0500 Subject: [PATCH 101/320] mb/google/fizz: use SaGv_FixedHigh No need for dynamic config (and the additional RAM training time) on a Chromebox; always use high power/high performance mode. Change-Id: I0295bac619af45a0d82da2bf39985c8bdcb77d5e Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/58231 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/fizz/variants/fizz/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/fizz/variants/fizz/overridetree.cb b/src/mainboard/google/fizz/variants/fizz/overridetree.cb index 3394bdf9a4d..b4eea385e09 100644 --- a/src/mainboard/google/fizz/variants/fizz/overridetree.cb +++ b/src/mainboard/google/fizz/variants/fizz/overridetree.cb @@ -3,6 +3,10 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_A7" + # No need for dynamic config (and the additional RAM training time) + # on a Chromebox; always use high power/high performance mode + register "SaGv" = "SaGv_FixedHigh" + device domain 0 on device pci 14.0 on chip drivers/usb/acpi From 51254ee9397a535f5e51d9b12702b1a385e40f0e Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Mon, 18 May 2020 23:41:45 -0500 Subject: [PATCH 102/320] nb/intel/haswell: Add HDAU ACPI device The HDAU stub device enables HDMI audio under MacOS. Change-Id: Ifa2155512dd909a4e4a753f6475541e9410dfe91 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/58272 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/haswell/acpi/hostbridge.asl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 0aa76a5add3..7dfae9fa944 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -203,3 +203,9 @@ Device (PDRC) /* Integrated graphics 0:2.0 */ #include + +/* Intel Mini-HD 0:03.0 */ +Device (HDAU) +{ + Name (_ADR, 0x00030000) +} From 2353cd9936702c6e556a9f810f180eced1e113d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 4 Oct 2021 16:59:49 +0200 Subject: [PATCH 103/320] soc/intel: drop P_BLK support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P_BLK is legacy and superseded by ACPI _CST. Also, the implementation for most platforms in soc/intel is broken. Thus, drop it. For APL the IO redirection is kept since it's used as replacement for the broken MWAIT instructions. Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/apollolake/acpi.c | 4 ---- src/soc/intel/baytrail/acpi.c | 8 +------- src/soc/intel/baytrail/fadt.c | 6 +----- src/soc/intel/braswell/acpi.c | 8 +------- src/soc/intel/braswell/fadt.c | 6 +----- src/soc/intel/broadwell/pch/fadt.c | 5 ----- src/soc/intel/common/block/acpi/acpi.c | 14 +++----------- src/soc/intel/denverton_ns/acpi.c | 3 --- src/soc/intel/denverton_ns/include/soc/msr.h | 1 - src/soc/intel/elkhartlake/acpi.c | 3 --- src/soc/intel/skylake/fadt.c | 6 +----- src/soc/intel/xeon_sp/include/soc/msr.h | 9 --------- src/soc/intel/xeon_sp/skx/cpu.c | 7 +------ src/soc/intel/xeon_sp/skx/soc_acpi.c | 5 ----- 14 files changed, 9 insertions(+), 76 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a28894f044d..b6d61b19d70 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -122,11 +122,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->pm_tmr_len = 4; - fadt->duty_width = 3; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 445441e146a..b91134fe20c 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -272,17 +272,11 @@ static void generate_p_state_entries(int core, int cores_per_package) void generate_cpu_entries(const struct device *device) { int core; - int pcontrol_blk = get_pmbase(), plen = 6; const struct pattrs *pattrs = pattrs_get(); for (core = 0; core < pattrs->num_cpus; core++) { - if (core > 0) { - pcontrol_blk = 0; - plen = 0; - } - /* Generate processor \_SB.CPUx */ - acpigen_write_processor(core, pcontrol_blk, plen); + acpigen_write_processor(core, 0, 0); /* Generate P-state tables */ generate_p_state_entries(core, pattrs->num_cpus); diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index 395bdd37f2e..316df6f2359 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -30,16 +30,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->duty_offset = 1; - fadt->duty_width = 0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index c70b69dc21c..757358d0f58 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -280,17 +280,11 @@ static void generate_p_state_entries(int core, int cores_per_package) void generate_cpu_entries(const struct device *device) { int core; - int pcontrol_blk = get_pmbase(), plen = 6; const struct pattrs *pattrs = pattrs_get(); for (core = 0; core < pattrs->num_cpus; core++) { - if (core > 0) { - pcontrol_blk = 0; - plen = 0; - } - /* Generate processor \_SB.CPUx */ - acpigen_write_processor(core, pcontrol_blk, plen); + acpigen_write_processor(core, 0, 0); /* Generate P-state tables */ generate_p_state_entries(core, pattrs->num_cpus); diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index 395bdd37f2e..316df6f2359 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -30,16 +30,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->duty_offset = 1; - fadt->duty_width = 0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index f13601dff04..bdce9a48829 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -29,11 +29,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 32; - /* P_LVLx not used */ - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; - fadt->duty_offset = 0; - fadt->duty_width = 0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 164631d14dd..cff2e219fd7 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -145,11 +145,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) /* GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->duty_offset = 1; fadt->day_alrm = 0xd; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; @@ -398,8 +397,7 @@ __weak void soc_power_states_generation(int core_id, void generate_cpu_entries(const struct device *device) { - int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; - int plen = 6; + int core_id, cpu_id; int totalcores = dev_count_cpu(); unsigned int num_virt; unsigned int num_phys; @@ -413,14 +411,8 @@ void generate_cpu_entries(const struct device *device) for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { for (core_id = 0; core_id < num_virt; core_id++) { - if (core_id > 0) { - pcontrol_blk = 0; - plen = 0; - } - /* Generate processor \_SB.CPUx */ - acpigen_write_processor((cpu_id) * num_virt + - core_id, pcontrol_blk, plen); + acpigen_write_processor((cpu_id) * num_virt + core_id, 0, 0); /* Generate C-state tables */ generate_c_state_entries(); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 4384cadd9e7..a28da481346 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -102,9 +102,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; /* PM2 Control Registers */ diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 89caf44c17b..21f3e7b41f5 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -7,7 +7,6 @@ #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 22b8767f48c..abbb1ec206b 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -160,9 +160,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->preferred_pm_profile = PM_MOBILE; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_width = 0x3; /* CLK_VAL bits 3:1 */ if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index b8eb9d02e5d..774974a76cc 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -34,10 +34,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->pm_tmr_len = 4; /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->duty_offset = 1; - fadt->duty_width = 0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; @@ -45,7 +41,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->iapc_boot_arch |= ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h index 3d68bf25654..9a8b641b493 100644 --- a/src/soc/intel/xeon_sp/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -28,18 +28,9 @@ /* No package C-state limit. All C-States supported by the processor are available. */ #define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT) #define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT) -#define IO_MWAIT_REDIRECTION_SHIFT 10 -#define IO_MWAIT_REDIRECTION_ENABLE (1 << IO_MWAIT_REDIRECTION_SHIFT) #define CFG_LOCK_SHIFT 15 #define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT) -/* MSR_PMG_IO_CAPTURE_BASE bits */ -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define LVL_2_BASE_ADDRESS_SHIFT 0 /* 15:0 bits */ -#define LVL_2_BASE_ADDRESS (0x0514 << LVL_2_BASE_ADDRESS_SHIFT) -#define CST_RANGE_SHIFT 16 /* 18:16 bits */ -#define CST_RANGE_MAX_C6 (0x1 << CST_RANGE_SHIFT) - /* MSR_POWER_CTL bits */ #define MSR_POWER_CTL 0x1fc #define BIDIR_PROCHOT_ENABLE_SHIFT 0 diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 848c907e58c..df2b9b3a006 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -54,14 +54,9 @@ static void xeon_sp_core_init(struct device *cpu) /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/ msr.hi = 0; - msr.lo = (PKG_CSTATE_NO_LIMIT | IO_MWAIT_REDIRECTION_ENABLE | CFG_LOCK_ENABLE); + msr.lo = (PKG_CSTATE_NO_LIMIT | CFG_LOCK_ENABLE); wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - /* set MSR_PMG_IO_CAPTURE_BASE - scope per core */ - msr.hi = 0; - msr.lo = (LVL_2_BASE_ADDRESS | CST_RANGE_MAX_C6); - wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); - /* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */ msr = rdmsr(MSR_POWER_CTL); msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 41039eabddd..23bb6d6e3c1 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -48,11 +48,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - - fadt->duty_width = 0; - /* RTC Registers */ fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; From 7c6d673c2692e52ba9714f5d3fecd0476e94bd48 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 13 Oct 2021 14:36:13 -0600 Subject: [PATCH 104/320] mb/google/guybrush: Re-arrange override speed config Currently override speed config is applied only for non EM100 cases. For EM100 case, override speed board version defaults to 0 leading to "comparison of unsigned expression >= 0 is always true" error. Fix this error by defining the override speed config for both EM100 and non-EM100 use-cases. BUG=None TEST=Build Guybrush for both EM100 and non-EM100 cases. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: Id8ee7b01c69c4555d6e6a7b0d5f095ea3aaf3405 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58309 Reviewed-by: Felix Held Reviewed-by: Raul Rangel Reviewed-by: Rob Barnes Tested-by: build bot (Jenkins) --- src/mainboard/google/guybrush/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index e5f138258ff..489c045524a 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -111,6 +111,8 @@ config NORMAL_READ_SPI_SPEED config ALT_SPI_SPEED default 0 # 66MHz +endif # !EM100 + config OVERRIDE_EFS_SPI_SPEED int default 3 if EM100 @@ -127,8 +129,6 @@ config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD Minimum board version starting which the Override EFS SPI Speed configuration has to be applied. -endif # !EM100 - config VARIANT_DIR default "guybrush" if BOARD_GOOGLE_GUYBRUSH default "nipperkin" if BOARD_GOOGLE_NIPPERKIN From 7f22bc465912bcb5117b725a0f68e01c81fea267 Mon Sep 17 00:00:00 2001 From: Derek Huang Date: Wed, 25 Aug 2021 17:47:25 +0800 Subject: [PATCH 105/320] soc/intel/common/tcss: Optimize USB-C DP flow and code structure HPD event may not be ready when configuring TCSS mux for DP, check if any DP device is connected and wait for HPD ready before TCSS configuration. Remove unnecessary dependency on mainboard functions, use generic interface which provides USB-C mux operations. BUG=b:192947843 TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name for Brya. Build coreboot and update your Brya. Boot Brya with USB-C display connected, you should find `HPD ready after %lu ms` and `Port C%zd is configured to DP mode!` in coreboot log. Display should show screen in developer mode or recovery mode. Signed-off-by: Derek Huang Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57139 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../common/block/include/intelblocks/tcss.h | 26 +-------- src/soc/intel/common/block/tcss/tcss.c | 56 ++++++++++++++----- 2 files changed, 43 insertions(+), 39 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index c07c96cd825..e5834b08c66 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -4,6 +4,7 @@ #define _TCSS_H_ #include +#include /* PMC IPC related offsets and commands */ #define PMC_IPC_USBC_CMD_ID 0xA7 @@ -126,19 +127,6 @@ enum pmc_ipc_command_type { #define MODE_DP_PIN_E BIT(4) #define MODE_DP_PIN_F BIT(5) -/* struct to hold all tcss_mux related variables */ -struct tcss_mux_info { - bool dp; /* DP connected */ - bool usb; /* USB connected */ - bool cable; /* Active/Passive Cable */ - bool polarity; /* polarity of connected device */ - bool hpd_lvl; /* HPD Level assert */ - bool hpd_irq; /* HPD IRQ assert */ - bool ufp; - bool acc; - uint8_t dp_mode; /* DP Operation Mode */ -}; - struct tcss_port_map { uint8_t usb2_port; /* USB2 Port Number */ uint8_t usb3_port; /* USB3 Port Number */ @@ -156,20 +144,10 @@ struct typec_aux_bias_pads { */ void tcss_configure(const struct typec_aux_bias_pads pads[MAX_TYPE_C_PORTS]); -/* - * Mainboard method to setup any mux config needed for TCSS display operations. - * This function will need to obtain any mux data needed to forward to IOM/PMC - * Since the mux data may be stored differently by different mainboards this - * function must be defined by mainboard with its specific mux data stored in a - * tcss_mux_info struct as defined above. - * Returns completed tcss_mux_info structure for the specified port - */ -const struct tcss_mux_info *mainboard_tcss_get_mux_info(int port); - /* * Method to get only the port information to initialize the muxes to * disconnect mode during boot. - * returns tscc_port_map of all ports on system + * Returns tcss_port_map of all ports on system */ const struct tcss_port_map *tcss_get_port_info(size_t *num_ports); diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index 28564e34cc9..03f630cf525 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -16,6 +16,8 @@ #define BIAS_CTRL_VW_INDEX_SHIFT 16 #define BIAS_CTRL_BIT_POS_SHIFT 8 +#define WAIT_FOR_DISPLAYPORT_TIMEOUT_MS 1000 +#define WAIT_FOR_HPD_TIMEOUT_MS 3000 static uint32_t tcss_make_conn_cmd(int u, int u3, int u2, int ufp, int hsl, int sbu, int acc) @@ -130,7 +132,7 @@ static int send_pmc_disconnect_request(int port, const struct tcss_port_map *por return send_pmc_req(CONNECT_REQ, &req, &rsp, PMC_IPC_DISC_REQ_SIZE); } -static int send_pmc_connect_request(int port, const struct tcss_mux_info *mux_data, +static int send_pmc_connect_request(int port, const struct usbc_mux_info *mux_data, const struct tcss_port_map *port_map) { uint32_t cmd; @@ -144,7 +146,7 @@ static int send_pmc_connect_request(int port, const struct tcss_mux_info *mux_da mux_data->ufp, mux_data->polarity, mux_data->polarity, - mux_data->acc); + mux_data->dbg_acc); req.buf[0] = cmd; @@ -162,7 +164,7 @@ static int send_pmc_connect_request(int port, const struct tcss_mux_info *mux_da return send_pmc_req(CONNECT_REQ, &req, &rsp, PMC_IPC_CONN_REQ_SIZE); } -static int send_pmc_safe_mode_request(int port, const struct tcss_mux_info *mux_data, +static int send_pmc_safe_mode_request(int port, const struct usbc_mux_info *mux_data, const struct tcss_port_map *port_map) { uint32_t cmd; @@ -181,7 +183,7 @@ static int send_pmc_safe_mode_request(int port, const struct tcss_mux_info *mux_ return send_pmc_req(SAFE_REQ, &req, &rsp, PMC_IPC_SAFE_REQ_SIZE); } -static int send_pmc_dp_hpd_request(int port, const struct tcss_mux_info *mux_data, +static int send_pmc_dp_hpd_request(int port, const struct usbc_mux_info *mux_data, const struct tcss_port_map *port_map) { struct pmc_ipc_buffer req = { 0 }; @@ -200,7 +202,7 @@ static int send_pmc_dp_hpd_request(int port, const struct tcss_mux_info *mux_dat } -static int send_pmc_dp_mode_request(int port, const struct tcss_mux_info *mux_data, +static int send_pmc_dp_mode_request(int port, const struct usbc_mux_info *mux_data, const struct tcss_port_map *port_map) { uint32_t cmd; @@ -223,7 +225,7 @@ static int send_pmc_dp_mode_request(int port, const struct tcss_mux_info *mux_da GET_TCSS_ALT_FIELD(USB3, cmd), GET_TCSS_ALT_FIELD(MODE, cmd)); - switch (mux_data->dp_mode) { + switch (mux_data->dp_pin_mode) { case MODE_DP_PIN_A: dp_mode = 1; break; @@ -282,35 +284,59 @@ static void tcss_init_mux(int port, const struct tcss_port_map *port_map) static void tcss_configure_dp_mode(const struct tcss_port_map *port_map, size_t num_ports) { - int ret; + int ret, port_bitmask; size_t i; - const struct tcss_mux_info *mux_info; + const struct usbc_ops *ops; + struct usbc_mux_info mux_info; const struct tcss_port_map *port_info; if (!display_init_required()) return; + ops = usbc_get_ops(); + if (ops == NULL) + return; + + port_bitmask = ops->dp_ops.wait_for_connection(WAIT_FOR_DISPLAYPORT_TIMEOUT_MS); + if (!port_bitmask) /* No DP device is connected */ + return; + for (i = 0; i < num_ports; i++) { - mux_info = mainboard_tcss_get_mux_info(i); - port_info = &port_map[i]; + if (!(port_bitmask & BIT(i))) + continue; + + ret = ops->dp_ops.enter_dp_mode(i); + if (ret < 0) + continue; + + ret = ops->dp_ops.wait_for_hpd(i, WAIT_FOR_HPD_TIMEOUT_MS); + if (ret < 0) + continue; - if (!mux_info->dp) + ret = ops->mux_ops.get_mux_info(i, &mux_info); + if (ret < 0) continue; - ret = send_pmc_connect_request(i, mux_info, port_info); + port_info = &port_map[i]; + + ret = send_pmc_connect_request(i, &mux_info, port_info); if (ret) { printk(BIOS_ERR, "Port %zd connect request failed\n", i); continue; } - ret = send_pmc_safe_mode_request(i, mux_info, port_info); + ret = send_pmc_safe_mode_request(i, &mux_info, port_info); if (ret) { printk(BIOS_ERR, "Port %zd safe mode request failed\n", i); continue; } - ret = send_pmc_dp_mode_request(i, mux_info, port_info); - if (ret) + ret = send_pmc_dp_mode_request(i, &mux_info, port_info); + if (ret) { printk(BIOS_ERR, "Port C%zd mux set failed with error %d\n", i, ret); + } else { + printk(BIOS_INFO, "Port C%zd is configured to DP mode!\n", i); + return; + } } } From 07bf6ff781193081e45e2920682ea2cf08e69cc6 Mon Sep 17 00:00:00 2001 From: Alan Huang Date: Tue, 5 Oct 2021 18:09:53 +0800 Subject: [PATCH 106/320] mb/google/brya/variants/brask: Init overridetree Init overridetree based on the schematics. Refer to brya0/overridetree.cb to update the settings of the devices including DPTF, WIFI, NAU8825 and etc. Refer to kano/overridetree.cb to update the SSD settings (pcie4_0). TODO: DPTF and USB positions will be further updated later. BUG=none TEST=Build Pass Signed-off-by: Alan Huang Change-Id: I30d26a47fe93736c63b578c9180b148ef73e8b9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58165 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar Reviewed-by: Tim Wawrzynczak --- .../brya/variants/brask/overridetree.cb | 288 +++++++++++++++++- 1 file changed, 286 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index e707a9b6b90..3805666cd53 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -1,6 +1,290 @@ chip soc/intel/alderlake - device domain 0 on - end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + }" + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_pull_up" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0C" + register "sar_threshold[1]" = "0x1C" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "6" + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + device generic 2 alias conn2 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 NFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb3_port4 on end + end + end + end + end + end end From 5412a81485b27a04c004acdb623d017ffa9bb587 Mon Sep 17 00:00:00 2001 From: Julian Schroeder Date: Tue, 12 Oct 2021 10:58:49 -0500 Subject: [PATCH 107/320] src/soc/amd/cezanne: enable clock gating Enabling clock gating for CGPLL to lower power consumption in S3 and S0i3 states. See also: Cezanne PPR chapter 7, rev 3.03. BUG=b:185273565 TEST=iotools mmio_read32 0xfed80e2c and 0e30 show clk gating enabled and suspend_stress_test works. Change-Id: I33cbdeec62e49db90b680da37e5028df03a9c015 Signed-off-by: Julian Schroeder Reviewed-on: https://review.coreboot.org/c/coreboot/+/58279 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/fch.c | 23 +++++++++++++++++++ src/soc/amd/cezanne/include/soc/southbridge.h | 11 +++++++++ 2 files changed, 34 insertions(+) diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index ac79cc9e115..dd19c310bc5 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -169,6 +169,28 @@ static void gpp_clk_setup(void) misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); } +static void cgpll_clock_gate_init(void) +{ + uint32_t t; + + t = misc_read32(MISC_CLKGATEDCNTL); + t |= ALINKCLK_GATEOFFEN; + t |= BLINKCLK_GATEOFFEN; + t |= XTAL_PAD_S3_TURNOFF_EN; + t |= XTAL_PAD_S5_TURNOFF_EN; + misc_write32(MISC_CLKGATEDCNTL, t); + + t = misc_read32(MISC_CGPLL_CONFIGURATION0); + t |= USB_PHY_CMCLK_S3_DIS; + t |= USB_PHY_CMCLK_S0I3_DIS; + t |= USB_PHY_CMCLK_S5_DIS; + misc_write32(MISC_CGPLL_CONFIGURATION0, t); + + t = pm_read32(PM_ISACONTROL); + t |= ABCLKGATEEN; + pm_write32(PM_ISACONTROL, t); +} + void fch_init(void *chip_info) { fch_init_resets(); @@ -181,6 +203,7 @@ void fch_init(void *chip_info) gpp_clk_setup(); fch_clk_output_48Mhz(); + cgpll_clock_gate_init(); } void fch_final(void *chip_info) diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 88137075c76..addb850621b 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -6,6 +6,8 @@ #include /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_ISACONTROL 0x04 +#define ABCLKGATEEN BIT(16) #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) #define PWR_RESET_CFG 0x10 @@ -82,6 +84,15 @@ #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) #define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift)) +#define MISC_CLKGATEDCNTL 0x2c +#define ALINKCLK_GATEOFFEN BIT(16) +#define BLINKCLK_GATEOFFEN BIT(17) +#define XTAL_PAD_S3_TURNOFF_EN BIT(20) +#define XTAL_PAD_S5_TURNOFF_EN BIT(21) +#define MISC_CGPLL_CONFIGURATION0 0x30 +#define USB_PHY_CMCLK_S3_DIS BIT(8) +#define USB_PHY_CMCLK_S0I3_DIS BIT(9) +#define USB_PHY_CMCLK_S5_DIS BIT(10) #define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define MISC_I2C0_PAD_CTRL 0xd8 From d4ba2b14caf61a8a9716a6525b8e4313f6121e7b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 12 Oct 2021 21:01:13 +0200 Subject: [PATCH 108/320] sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1 Enable PCIe Clock power management and ASPM L1 substate by default. This matches what Broadwell does. Change-Id: Ic2bbcbc23d6bab0900d3e90ad8e2fbfa4aea3c16 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58281 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 03b3e9a50f5..25ed6efa122 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -68,6 +68,12 @@ config PCIEXP_AER bool default y +config PCIEXP_CLK_PM + default y + +config PCIEXP_L1_SUB_STATE + default y + config SERIALIO_UART_CONSOLE bool "Use SerialIO UART for console" depends on INTEL_LYNXPOINT_LP From f343ed42ebeac7d28fb751635a6771731baae554 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 25 Aug 2021 10:26:17 +0200 Subject: [PATCH 109/320] mb/siemens/mc_ehl2: Set coreboot ready LED This mainboard has its own coreboot ready LED. The LED is switched on via GPIO GPP_F20. Change-Id: I3570d691e90d2cb6e11b856b876f0327da118522 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58293 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- .../siemens/mc_ehl/variants/mc_ehl2/mainboard.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index 4ae857c69ab..b979380d920 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include +#include #include +#include #include void variant_mainboard_final(void) @@ -11,3 +14,11 @@ void variant_mainboard_final(void) INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */ pcr_write16(PID_ITSS, 0x3150, 0x1032); } + +static void finalize_boot(void *unused) +{ + /* Set coreboot ready LED. */ + gpio_output(GPP_F20, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); From 0c3aaba9561ac794c6bab3baa0465a0e1884f7f6 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 25 Aug 2021 10:38:34 +0200 Subject: [PATCH 110/320] mb/siemens/mc_ehl2: Enable PCI devices Correct the remaining PCI devices, differing from the ehl1 mainboard. Change-Id: I8112fa5ea86e879741061798530150701b759156 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58294 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- .../siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 062ac5ff835..06fdf0a1808 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -161,7 +161,7 @@ chip soc/intel/elkhartlake device pci 11.6 off end # Intel PSE IS20 device pci 11.7 off end # Intel PSE IS21 - device pci 12.0 off end # GSPI2 + device pci 12.0 on end # GSPI2 device pci 12.3 on end # Management Engine UMA Access device pci 12.4 on end # Management Engine PTT DMA Controller device pci 12.5 off end # UFS0 @@ -177,7 +177,7 @@ chip soc/intel/elkhartlake device pci 14.0 on end # USB3.1 xHCI device pci 14.1 off end # USB3.1 xDCI (OTG) - device pci 15.0 off end # I2C0 + device pci 15.0 on end # I2C0 device pci 15.1 on end # I2C1 device pci 15.2 on # I2C2 # Enable external RTC chip @@ -195,7 +195,7 @@ chip soc/intel/elkhartlake device i2c 0x32 on end # RTC RX6110 SA end end - device pci 15.3 off end # I2C3 + device pci 15.3 on end # I2C3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 on end # Management Engine Interface 2 @@ -213,7 +213,7 @@ chip soc/intel/elkhartlake device pci 18.6 off end # Intel PSE QEP3 device pci 19.0 on end # I2C4 - device pci 19.1 off end # I2C5 + device pci 19.1 on end # I2C5 device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC From 76b4e414f30e155d86d2d86d91c887b9f15dce27 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 25 Aug 2021 15:29:34 +0200 Subject: [PATCH 111/320] mb/siemens/mc_ehl2: Adjust USB settings Correct the USB settings, suitable for this mainboard. Change-Id: I691d91d2a76e27b8efdc18eeae737a78e9ae38fa Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58295 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- .../mc_ehl/variants/mc_ehl2/devicetree.cb | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 06fdf0a1808..9d037cad6b9 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -27,21 +27,21 @@ chip soc/intel/elkhartlake }" # USB related UPDs - register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB - register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Port is unused - register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Port is unused - register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Port is unused - register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Port is unused - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Port is unused - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Port is unused - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Port is unused + register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # X125/X135 + register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # X125/X135 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # X145/X155 + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # X145/X155 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB Panel + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # USB Panel + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Port is not used - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Port is not used + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # UNUSED + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # UNUSED # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" From 71b227d6ebddd1236473c62c2d7f340ebd9981b5 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Wed, 25 Aug 2021 15:36:31 +0200 Subject: [PATCH 112/320] mb/siemens/mc_ehl2: Adjust PCH serial IO settings Correct the PCH serial IO settings, suitable for this mainboard. Change-Id: I3c9915b2d52fbc6a15ac1e68c77bfb3983f7b1cd Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58296 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- .../mc_ehl/variants/mc_ehl2/devicetree.cb | 23 +++++-------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 9d037cad6b9..451c5dd5f23 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -98,30 +98,19 @@ chip soc/intel/elkhartlake # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexI2C6] = PchSerialIoDisabled, [PchSerialIoIndexI2C7] = PchSerialIoDisabled, }" - register "SerialIoI2cPadsTermination" = "{ - [PchSerialIoIndexI2C0] = 1, - [PchSerialIoIndexI2C1] = 1, - [PchSerialIoIndexI2C2] = 1, - [PchSerialIoIndexI2C3] = 1, - [PchSerialIoIndexI2C4] = 1, - [PchSerialIoIndexI2C5] = 1, - [PchSerialIoIndexI2C6] = 1, - [PchSerialIoIndexI2C7] = 1, - }" - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" From e7f43502b540a42f23a967b6206370050ef75f23 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 11 Oct 2021 23:31:02 -0600 Subject: [PATCH 113/320] soc/amd/common/acpi/upep: Add Low Power State Entry Notifications Add support to handle S0ix entry and exit notifications by adding the corresponding _DSM functions. The function indices are chosen based on the Modern Standby BIOS Implementation Guide 56358 Rev. 1.04. Inside the notification functions perform any mainboard specific S0ix entry and exit actions. BUG=b:195748540 TEST=Build and boot to OS in Guybrush. Ensure that the notification functions are invoked on S0ix entry and exit. Perform suspend/resume cycles for multiple iterations. Change-Id: I3014551f6e281d466628559453a0141a3dd6abad Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/58274 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/common/acpi/upep.asl | 34 ++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/src/soc/amd/common/acpi/upep.asl b/src/soc/amd/common/acpi/upep.asl index ef068452f8f..b44ed43b23c 100644 --- a/src/soc/amd/common/acpi/upep.asl +++ b/src/soc/amd/common/acpi/upep.asl @@ -5,8 +5,13 @@ #define PEPD_DSM_LPI_ADDITIONAL_FUNCTIONS 1 #define PEPD_DSM_LPI_GET_DEVICE_CONSTRAINTS 1 -#define PEPD_DSM_NOTIFICATIONS_UUID "11e00d56-ce64-47ce-837b-1f898f9aa461" -#define PEPD_DSM_NOTIFICATION_ENUM_FUNCTIONS 0 +#define PEPD_DSM_NOTIFICATIONS_UUID "11e00d56-ce64-47ce-837b-1f898f9aa461" +#define PEPD_DSM_NOTIFICATION_ENUM_FUNCTIONS 0 +#define PEPD_DSM_NOTIFICATION_ADDITIONAL_FUNCTIONS 1 +#define PEPD_DSM_NOTIFICATION_LOW_POWER_ENTRY 5 +#define PEPD_DSM_NOTIFICATION_LOW_POWER_EXIT 6 + +External(\_SB.MS0X, MethodObj) /* * Power Engine Plug-in Device @@ -89,10 +94,27 @@ Scope (\_SB) { * this UUID. */ Case (PEPD_DSM_NOTIFICATION_ENUM_FUNCTIONS) { - /* - * TODO(b/185586290): Add additional functions when - * linux kernel driver is fixed. - */ + Local0 = Buffer { 0x00 } + CreateByteField(Local0, 0x00, SUPP) + + SUPP = PEPD_DSM_NOTIFICATION_ADDITIONAL_FUNCTIONS + SUPP |= 1 << PEPD_DSM_NOTIFICATION_LOW_POWER_ENTRY + SUPP |= 1 << PEPD_DSM_NOTIFICATION_LOW_POWER_EXIT + + Return (Local0) + } + Case (PEPD_DSM_NOTIFICATION_LOW_POWER_ENTRY) { + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } + Return (Buffer() { 0x00 }) + } + Case (PEPD_DSM_NOTIFICATION_LOW_POWER_EXIT) { + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } Return (Buffer() { 0x00 }) } Default { From d086e3d6e42036b1ec0fc2173db5386279ac838b Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 8 Oct 2021 17:04:10 -0600 Subject: [PATCH 114/320] mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entry Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on S0i3 entry. Based on the schematics, the pull-down on that signal leads to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to achieve some power savings and de-assert it on S0i3 exit. BUG=b:195748540 TEST=Build and boot to OS in Guybrush. Ensure that the signal gets asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger suspend/resume cycles and ensure that the WWAN module is enumerated after each cycle. Change-Id: I43c8655ee5209779748e4365db973e094cb08aca Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/mainboard/google/guybrush/mainboard.c | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 3626157338b..39ef2a0795b 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -13,11 +13,13 @@ #include #define BACKLIGHT_GPIO GPIO_129 +#define WWAN_AUX_RST_GPIO GPIO_18 #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" #define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" #define METHOD_MAINBOARD_INI "\\_SB.MINI" #define METHOD_MAINBOARD_WAK "\\_SB.MWAK" #define METHOD_MAINBOARD_PTS "\\_SB.MPTS" +#define METHOD_MAINBOARD_S0X "\\_SB.MS0X" /* * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -151,6 +153,31 @@ static void mainboard_write_mpts(void) acpigen_pop_len(); } +static void mainboard_assert_wwan_aux_reset(void) +{ + if (variant_has_pcie_wwan()) + acpigen_soc_clear_tx_gpio(WWAN_AUX_RST_GPIO); +} + +static void mainboard_deassert_wwan_aux_reset(void) +{ + if (variant_has_pcie_wwan()) + acpigen_soc_set_tx_gpio(WWAN_AUX_RST_GPIO); +} + +static void mainboard_write_ms0x(void) +{ + acpigen_write_method_serialized(METHOD_MAINBOARD_S0X, 1); + /* S0ix Entry */ + acpigen_write_if_lequal_op_int(ARG0_OP, 1); + mainboard_assert_wwan_aux_reset(); + /* S0ix Exit */ + acpigen_write_else(); + mainboard_deassert_wwan_aux_reset(); + acpigen_pop_len(); + acpigen_pop_len(); +} + static void mainboard_fill_ssdt(const struct device *dev) { mainboard_write_blken(); @@ -158,6 +185,7 @@ static void mainboard_fill_ssdt(const struct device *dev) mainboard_write_mini(); mainboard_write_mpts(); mainboard_write_mwak(); + mainboard_write_ms0x(); } static void mainboard_enable(struct device *dev) From c45e0bedb26002b32cf6ecaca26a56214c28a8b5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 6 Oct 2021 23:28:03 -0700 Subject: [PATCH 115/320] soc/intel/common/cse: Reorganize firmware update checks for CSE Lite `cse_fw_update()` is currently checking whether an update is required by comparing versions once and then again comparing versions later in `cse_is_downgrade_instance()` to determine if the update is an upgrade or downgrade. Additionally, if CSE RW partition is corrupt (determined based on `cse_is_rw_bp_sign_valid()`), `cse_is_downgrade_instance()` ends up using the corrupted version information to determine if it is a downgrade instance. This change reorganizes the firmware update checks to return different status values: 1. CSE_UPDATE_NOT_REQUIRED: No update required. Versions match. 2. CSE_UPDATE_UPGRADE: Update required and it is an upgrade. 3. CSE_UPDATE_DOWNGRADE: Update required and it is a downgrade (requires data clear). 4. CSE_UPDATE_CORRUPTED: `cse_is_rw_bp_sign_valid()` failed and hence requires data clear. 5. CSE_UPDATE_METADATA_ERROR: Unable to read CSE metadata from CBFS. This change also prepares the file for follow up changes which completely drop cse_rw_metadata structure. BUG=b:184892226 Change-Id: Iabecab8e373e65a11ba7fe1bfc125467571a0588 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58157 Reviewed-by: Sridhar Siricilla Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cse/cse_lite.c | 118 +++++++++++----------- 1 file changed, 61 insertions(+), 57 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 762de2a10d1..b381c481031 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -502,27 +502,16 @@ static bool cse_get_source_rdev(struct region_device *rdev) * If ver_cmp_status < 0, coreboot downgrades CSE RW region * If ver_cmp_status > 0, coreboot upgrades CSE RW region */ -static int cse_check_version_mismatch(const struct cse_bp_info *cse_bp_info, - const struct cse_rw_metadata *source_metadata) -{ - const struct fw_version *cse_rw_ver; - - printk(BIOS_DEBUG, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", - source_metadata->version.major, - source_metadata->version.minor, - source_metadata->version.hotfix, - source_metadata->version.build); - - cse_rw_ver = cse_get_rw_version(cse_bp_info); - - if (source_metadata->version.major != cse_rw_ver->major) - return source_metadata->version.major - cse_rw_ver->major; - else if (source_metadata->version.minor != cse_rw_ver->minor) - return source_metadata->version.minor - cse_rw_ver->minor; - else if (source_metadata->version.hotfix != cse_rw_ver->hotfix) - return source_metadata->version.hotfix - cse_rw_ver->hotfix; +static int compare_cse_version(const struct fw_version *a, const struct fw_version *b) +{ + if (a->major != b->major) + return a->major - b->major; + else if (a->minor != b->minor) + return a->minor - b->minor; + else if (a->hotfix != b->hotfix) + return a->hotfix - b->hotfix; else - return source_metadata->version.build - cse_rw_ver->build; + return a->build - b->build; } /* The function calculates SHA-256 of CSE RW blob and compares it with the provided SHA value */ @@ -568,24 +557,43 @@ static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf return true; } -static bool cse_is_rw_version_latest(const struct cse_bp_info *cse_bp_info, - const struct cse_rw_metadata *source_metadata) -{ - return !cse_check_version_mismatch(cse_bp_info, source_metadata); -} +enum cse_update_status { + CSE_UPDATE_NOT_REQUIRED, + CSE_UPDATE_UPGRADE, + CSE_UPDATE_DOWNGRADE, + CSE_UPDATE_CORRUPTED, + CSE_UPDATE_METADATA_ERROR, +}; -static bool cse_is_downgrade_instance(const struct cse_bp_info *cse_bp_info, - const struct cse_rw_metadata *source_metadata) -{ - return cse_check_version_mismatch(cse_bp_info, source_metadata) < 0; -} +static struct cse_rw_metadata source_metadata; -static bool cse_is_update_required(const struct cse_bp_info *cse_bp_info, - const struct cse_rw_metadata *source_metadata, - struct region_device *target_rdev) +static enum cse_update_status cse_check_update_status(const struct cse_bp_info *cse_bp_info, + struct region_device *target_rdev) { - return (!cse_is_rw_bp_sign_valid(target_rdev) || - !cse_is_rw_version_latest(cse_bp_info, source_metadata)); + int ret; + + if (!cse_is_rw_bp_sign_valid(target_rdev)) + return CSE_UPDATE_CORRUPTED; + + if (cbfs_load(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, &source_metadata, + sizeof(source_metadata)) != sizeof(source_metadata)) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE CBFS RW metadata\n"); + return CSE_UPDATE_METADATA_ERROR; + } + + printk(BIOS_DEBUG, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", + source_metadata.version.major, + source_metadata.version.minor, + source_metadata.version.hotfix, + source_metadata.version.build); + + ret = compare_cse_version(&source_metadata.version, cse_get_rw_version(cse_bp_info)); + if (ret == 0) + return CSE_UPDATE_NOT_REQUIRED; + else if (ret < 0) + return CSE_UPDATE_DOWNGRADE; + else + return CSE_UPDATE_UPGRADE; } static bool cse_write_rw_region(const struct region_device *target_rdev, @@ -630,7 +638,7 @@ static enum csme_failure_reason cse_update_rw(const struct cse_bp_info *cse_bp_i } static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, - const struct cse_rw_metadata *source_metadata) + enum cse_update_status status) { /* * To set CSE's operation mode to HMRFPO mode: @@ -640,18 +648,19 @@ static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, if (!cse_boot_to_ro(cse_bp_info)) return false; - if (cse_is_downgrade_instance(cse_bp_info, source_metadata) && - !cse_data_clear_request(cse_bp_info)) { - printk(BIOS_ERR, "cse_lite: CSE FW downgrade is aborted\n"); - return false; + if ((status == CSE_UPDATE_DOWNGRADE) || (status == CSE_UPDATE_CORRUPTED)) { + if (!cse_data_clear_request(cse_bp_info)) { + printk(BIOS_ERR, "cse_lite: CSE data clear failed!\n"); + return false; + } } return cse_hmrfpo_enable(); } static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, - const struct cse_rw_metadata *source_metadata, - struct region_device *target_rdev) + enum cse_update_status status, + struct region_device *target_rdev) { struct region_device source_rdev; enum csme_failure_reason rv; @@ -666,13 +675,13 @@ static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info * return CSE_LITE_SKU_RW_BLOB_NOT_FOUND; } - if (!cse_verify_cbfs_rw_sha256(source_metadata->sha256, cse_cbfs_rw, + if (!cse_verify_cbfs_rw_sha256(source_metadata.sha256, cse_cbfs_rw, region_device_sz(&source_rdev))) { rv = CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH; goto error_exit; } - if (!cse_prep_for_rw_update(cse_bp_info, source_metadata)) { + if (!cse_prep_for_rw_update(cse_bp_info, status)) { rv = CSE_COMMUNICATION_ERROR; goto error_exit; } @@ -688,26 +697,21 @@ static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info * static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info) { struct region_device target_rdev; - struct cse_rw_metadata source_metadata; - - /* Read CSE CBFS RW metadata */ - if (cbfs_load(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, &source_metadata, - sizeof(source_metadata)) != sizeof(source_metadata)) { - printk(BIOS_ERR, "cse_lite: Failed to get CSE CBFS RW metadata\n"); - return CSE_LITE_SKU_RW_METADATA_NOT_FOUND; - } + enum cse_update_status status; if (!cse_get_target_rdev(cse_bp_info, &target_rdev)) { printk(BIOS_ERR, "cse_lite: Failed to get CSE RW Partition\n"); return CSE_LITE_SKU_RW_ACCESS_ERROR; } - if (cse_is_update_required(cse_bp_info, &source_metadata, &target_rdev)) { - printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); - return cse_trigger_fw_update(cse_bp_info, &source_metadata, &target_rdev); - } + status = cse_check_update_status(cse_bp_info, &target_rdev); + if (status == CSE_UPDATE_NOT_REQUIRED) + return CSE_NO_ERROR; + if (status == CSE_UPDATE_METADATA_ERROR) + return CSE_LITE_SKU_RW_METADATA_NOT_FOUND; - return 0; + printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); + return cse_trigger_fw_update(cse_bp_info, status, &target_rdev); } void cse_fw_sync(void) From c1e4c5aaa5cbe9b1fa8d16be9b23038bc5fbc9b8 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Fri, 23 Jul 2021 13:35:14 +0200 Subject: [PATCH 116/320] tests: Add lib/lzma-test test case Files used by this test are in: tests/data/lib/lzma-test/ file.bin - files with uncompressed data file.lzma.bin - files with LZMA-compressed data from file.bin How to prepare compressed file: util/cbfs-compression-tool compress file.bin /tmp/file.lzma.bin lzma dd if=/tmp/file.lzma.bin of=file.lzma.bin skip=8 ibs=1 Signed-off-by: Jakub Czapiga Change-Id: Id75e0b41991382d4c391b031862106de58eacdf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57555 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Julius Werner --- tests/Makefile.inc | 3 +- tests/data/lib/lzma-test/data.1.bin | Bin 0 -> 124784 bytes tests/data/lib/lzma-test/data.1.lzma.bin | Bin 0 -> 52133 bytes tests/data/lib/lzma-test/data.2.bin | 104 +++ tests/data/lib/lzma-test/data.2.lzma.bin | Bin 0 -> 1537 bytes tests/data/lib/lzma-test/data.3.bin | 764 +++++++++++++++++++++++ tests/data/lib/lzma-test/data.3.lzma.bin | Bin 0 -> 3865 bytes tests/data/lib/lzma-test/data.4.bin | Bin 0 -> 60912 bytes tests/data/lib/lzma-test/data.4.lzma.bin | Bin 0 -> 17064 bytes tests/lib/Makefile.inc | 6 + tests/lib/lzma-test.c | 190 ++++++ 11 files changed, 1066 insertions(+), 1 deletion(-) create mode 100644 tests/data/lib/lzma-test/data.1.bin create mode 100644 tests/data/lib/lzma-test/data.1.lzma.bin create mode 100644 tests/data/lib/lzma-test/data.2.bin create mode 100644 tests/data/lib/lzma-test/data.2.lzma.bin create mode 100644 tests/data/lib/lzma-test/data.3.bin create mode 100644 tests/data/lib/lzma-test/data.3.lzma.bin create mode 100644 tests/data/lib/lzma-test/data.4.bin create mode 100644 tests/data/lib/lzma-test/data.4.lzma.bin create mode 100644 tests/lib/lzma-test.c diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 982f42baf7a..6397e9b6701 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -141,7 +141,8 @@ $$($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER) $($(1)-objs): TEST_CFLAGS += -I$$(dir $$($(1)-config-file)) \ -D__$$(shell echo $$($(1)-stage) | tr '[:lower:]' '[:upper:]')__ \ - -D__TEST_NAME__=\"$(subst /,_,$(1))\" + -D__TEST_NAME__=\"$(subst /,_,$(1))\" \ + -D__TEST_DATA_DIR__=\"$(testsrc)/data\" # Give us a way to distinguish between coreboot source files and test files in code. $($(1)-srcobjs): TEST_CFLAGS += -D__TEST_SRCOBJ__ diff --git a/tests/data/lib/lzma-test/data.1.bin b/tests/data/lib/lzma-test/data.1.bin new file mode 100644 index 0000000000000000000000000000000000000000..2ac7245fd05365e530c92da95affec1b9c2970bb GIT binary patch literal 124784 zcmeFadwdnux$wUyiI6HfK~bYpiFWsuU9<(Y%C6dG!w$^Y*@_i}Dk?UDP;V3h(W;na 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+bootloaders, or implement firmware standards, like PC BIOS services or +UEFI. This allows for systems to only include the features necessary +in the target application, reducing the amount of code and flash space +required. + +coreboot was formerly known as LinuxBIOS. + + +Payloads +-------- + +After the basic initialization of the hardware has been performed, any +desired "payload" can be started by coreboot. + +See for a list of supported payloads. + + +Supported Hardware +------------------ + +coreboot supports a wide range of chipsets, devices, and mainboards. + +For details please consult: + + * + + +Build Requirements +------------------ + + * make + * gcc / g++ + Because Linux distribution compilers tend to use lots of patches. coreboot + does lots of "unusual" things in its build system, some of which break due + to those patches, sometimes by gcc aborting, sometimes - and that's worse - + by generating broken object code. + Two options: use our toolchain (eg. make crosstools-i386) or enable the + `ANY_TOOLCHAIN` Kconfig option if you're feeling lucky (no support in this + case). + * iasl (for targets with ACPI support) + * pkg-config + * libssl-dev (openssl) + +Optional: + + * doxygen (for generating/viewing documentation) + * gdb (for better debugging facilities on some targets) + * ncurses (for `make menuconfig` and `make nconfig`) + * flex and bison (for regenerating parsers) + + +Building coreboot +----------------- + +Please consult for details. + + +Testing coreboot Without Modifying Your Hardware +------------------------------------------------ + +If you want to test coreboot without any risks before you really decide +to use it on your hardware, you can use the QEMU system emulator to run +coreboot virtually in QEMU. + +Please see for details. + + +Website and Mailing List +------------------------ + +Further details on the project, a FAQ, many HOWTOs, news, development +guidelines and more can be found on the coreboot website: + + + +You can contact us directly on the coreboot mailing list: + + + + +Copyright and License +--------------------- + +The copyright on coreboot is owned by quite a large number of individual +developers and companies. Please check the individual source files for details. + +coreboot is licensed under the terms of the GNU General Public License (GPL). +Some files are licensed under the "GPL (version 2, or any later version)", +and some files are licensed under the "GPL, version 2". For some parts, which +were derived from other projects, other (GPL-compatible) licenses may apply. +Please check the individual source files for details. + +This makes the resulting coreboot images licensed under the GPL, version 2. diff --git a/tests/data/lib/lzma-test/data.2.lzma.bin b/tests/data/lib/lzma-test/data.2.lzma.bin new file mode 100644 index 0000000000000000000000000000000000000000..e1dd3f7b047cf28270d5b756fe2a54a3a8fa484c GIT binary patch literal 1537 zcmV+c2LAa001yBG=?nk>0000005P3w%!Jt@4x&w;-;+UUUR4Ryyt%uz2PWHy;0?9N z;D#lG-DaX>je_IBIQ`00~Qjn2FR$sd=`;sC#QO94oGn(}bmE-zN6o^bmWDuO{yXq5C z;O^W2mOQ2}ZTG-`@kCN)`vy}e8(a4587V+KOsWJggV=;I;86-M<=y$ zJziV|``&Osq8UhBdhRSwmoA6eXWxmhxXV5*Bu%*N#X7j{H5+v4YZB zyX;u^)_39HY*u{rou#q??`uT%hZZIN_{t}Zeq2-wj%;ntW8XZzQ7!O@or z4}omS`psRI0CgM_3)wrI9*B#|(Re#T0HID0^H6?v5x>H_cc`!CLL_l?TG#5>zCQQD znU?4?kHzYBtxWx(0Bg4sx8iD+C}Or`Xoh2ynTy0IYbSdgWM}{aashvC1DPeUwAoOR zT{v(b9dROCh4g1&?Ha)_ZH;IREtTFovl!elWwT;yu9L56+OV{MKyc%jI;&R*e`&`2 zU(CB>koS@^#TP&MnPQwibuY2F!fABvS^VK4Kt)l}?6KDZbef?m3+Kh1HH9xApBHqB zQ@7DPU*PJIKPNu2?4^pI1tK*sCU!=O;!Lb*q|?$9i`LFElKpoM`{re^q=@JeYHWdB zHqpBYQy!&_P_o~4ckw{V(0^vt5;05gP7@)wCBQ|e-KcG5B#igR^#{7*p5ql&%0;qZ z7}bjNiGmyXsZHj-aj6!i$-yIMpG3VLo0Fn(ESL4C!cTbdr z^*e>(jl4)d0wWWjylZu+WgGvnbejT2EP=GIpdh*k?&YdN`_4{$Ra`8gSm-K}oOF~R z`~B#{p3e{XQo>%!eKT6&b}x#oeKxBa(<2}LbP z5HI^5nmbYTqx!a;xO$YXg}?%$c1hMKWxJQ}l(`Eg8S|}iD}v!LD>t*~lcPohnUSL) z2H*U8|LuWRIb!UL5(u#JB*+5@^ec~hwEQQmUKx3!2tKft<1GcMD9nPZ7FFAOwg*4( z_3Bf`2O1@Ik&9lihc}!c9#5~1^g8Eq`fZL@)3-sf3?@{ki%Y!&IXCK9+4`*v3*G00 z8ox=NzgrbNMNTEcGGOP^Dc}K0G2bXydUD)3ueMVr(=xgV3#d1JrggbgUlzey6Vgj+ zIsM);v(aHA*vt-L8b*A2h(1td9)v9C-ZPzp*zprb;c8a>36{r7RgK&P;@Vs7mcXt7 nt*))X=wV^j+S_cz_1iC8laU0D@d|J()ga6G*T63laf=ljt4sxm literal 0 HcmV?d00001 diff --git a/tests/data/lib/lzma-test/data.3.bin b/tests/data/lib/lzma-test/data.3.bin new file mode 100644 index 00000000000..6da1ac926c6 --- /dev/null +++ b/tests/data/lib/lzma-test/data.3.bin @@ -0,0 +1,764 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Auxiliary functions and definitions. */ + +#define LG_ROOT_SIZE align_up_pow2(sizeof(struct imd_root_pointer) +\ + sizeof(struct imd_root) + 3 * sizeof(struct imd_entry)) +#define LG_ENTRY_ALIGN (2 * sizeof(int32_t)) +#define LG_ENTRY_SIZE (2 * sizeof(int32_t)) +#define LG_ENTRY_ID 0xA001 + +#define SM_ROOT_SIZE LG_ROOT_SIZE +#define SM_ENTRY_ALIGN sizeof(uint32_t) +#define SM_ENTRY_SIZE sizeof(uint32_t) +#define SM_ENTRY_ID 0xB001 + +#define INVALID_REGION_ID 0xC001 + +static uint32_t align_up_pow2(uint32_t x) +{ + return (1 << log2_ceil(x)); +} + +static size_t max_entries(size_t root_size) +{ + return (root_size - sizeof(struct imd_root_pointer) - sizeof(struct imd_root)) + / sizeof(struct imd_entry); +} + +/* + * Mainly, we should check that imd_handle_init() aligns upper_limit properly + * for various inputs. Upper limit is the _exclusive_ address, so we expect + * ALIGN_DOWN. + */ +static void test_imd_handle_init(void **state) +{ + int i; + void *base; + struct imd imd; + uintptr_t test_inputs[] = { + 0, /* Lowest possible address */ + 0xA000, /* Fits in 16 bits, should not get rounded down*/ + 0xDEAA, /* Fits in 16 bits */ + 0xB0B0B000, /* Fits in 32 bits, should not get rounded down */ + 0xF0F0F0F0, /* Fits in 32 bits */ + ((1ULL << 32) + 4), /* Just above 32-bit limit */ + 0x6666777788889000, /* Fits in 64 bits, should not get rounded down */ + ((1ULL << 60) - 100) /* Very large address, fitting in 64 bits */ + }; + + for (i = 0; i < ARRAY_SIZE(test_inputs); i++) { + base = (void *)test_inputs[i]; + + imd_handle_init(&imd, (void *)base); + + assert_int_equal(imd.lg.limit % LIMIT_ALIGN, 0); + assert_int_equal(imd.lg.limit, ALIGN_DOWN(test_inputs[i], LIMIT_ALIGN)); + assert_ptr_equal(imd.lg.r, NULL); + + /* Small allocations not initialized */ + assert_ptr_equal(imd.sm.limit, NULL); + assert_ptr_equal(imd.sm.r, NULL); + } +} + +static void test_imd_handle_init_partial_recovery(void **state) +{ + void *base; + struct imd imd = {0}; + const struct imd_entry *entry; + + imd_handle_init_partial_recovery(&imd); + assert_null(imd.lg.limit); + assert_null(imd.sm.limit); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + imd_handle_init_partial_recovery(&imd); + + assert_non_null(imd.lg.r); + assert_null(imd.sm.limit); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + entry = imd_entry_add(&imd, SMALL_REGION_ID, LG_ENTRY_SIZE); + assert_non_null(entry); + + imd_handle_init_partial_recovery(&imd); + + assert_non_null(imd.lg.r); + assert_non_null(imd.sm.limit); + assert_ptr_equal(imd.lg.r + entry->start_offset + LG_ENTRY_SIZE, imd.sm.limit); + assert_non_null(imd.sm.r); + + free(base); +} + +static void test_imd_create_empty(void **state) +{ + struct imd imd = {0}; + void *base; + struct imd_root *r; + struct imd_entry *e; + + /* Expect imd_create_empty to fail, since imd handle is not initialized */ + assert_int_equal(-1, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + base = malloc(sizeof(struct imd_root_pointer) + sizeof(struct imd_root)); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + /* Try incorrect sizes */ + assert_int_equal(-1, imd_create_empty(&imd, + sizeof(struct imd_root_pointer), + LG_ENTRY_ALIGN)); + assert_int_equal(-1, imd_create_empty(&imd, LG_ROOT_SIZE, 2 * LG_ROOT_SIZE)); + + /* Working case */ + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + + /* Only large allocation initialized with one entry for the root region */ + r = (struct imd_root *) (imd.lg.r); + assert_non_null(r); + + e = &r->entries[r->num_entries - 1]; + + assert_int_equal(max_entries(LG_ROOT_SIZE), r->max_entries); + assert_int_equal(1, r->num_entries); + assert_int_equal(0, r->flags); + assert_int_equal(LG_ENTRY_ALIGN, r->entry_align); + assert_int_equal(0, r->max_offset); + assert_ptr_equal(e, &r->entries); + + assert_int_equal(IMD_ENTRY_MAGIC, e->magic); + assert_int_equal(0, e->start_offset); + assert_int_equal(LG_ROOT_SIZE, e->size); + assert_int_equal(CBMEM_ID_IMD_ROOT, e->id); + + free(base); +} + +static void test_imd_create_tiered_empty(void **state) +{ + void *base; + size_t sm_region_size, lg_region_wrong_size; + struct imd imd = {0}; + struct imd_root *r; + struct imd_entry *fst_lg_entry, *snd_lg_entry, *sm_entry; + + /* Uninitialized imd handle */ + assert_int_equal(-1, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + LG_ROOT_SIZE, SM_ENTRY_ALIGN)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + /* Too small root_size for small region */ + assert_int_equal(-1, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + sizeof(int32_t), 2 * sizeof(int32_t))); + + /* Fail when large region doesn't have capacity for more than 1 entry */ + lg_region_wrong_size = sizeof(struct imd_root_pointer) + sizeof(struct imd_root) + + sizeof(struct imd_entry); + expect_assert_failure( + imd_create_tiered_empty(&imd, lg_region_wrong_size, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN) + ); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + r = imd.lg.r; + + /* One entry for root_region and one for small allocations */ + assert_int_equal(2, r->num_entries); + + fst_lg_entry = &r->entries[0]; + assert_int_equal(IMD_ENTRY_MAGIC, fst_lg_entry->magic); + assert_int_equal(0, fst_lg_entry->start_offset); + assert_int_equal(LG_ROOT_SIZE, fst_lg_entry->size); + assert_int_equal(CBMEM_ID_IMD_ROOT, fst_lg_entry->id); + + /* Calculated like in imd_create_tiered_empty */ + sm_region_size = max_entries(SM_ROOT_SIZE) * SM_ENTRY_ALIGN; + sm_region_size += SM_ROOT_SIZE; + sm_region_size = ALIGN_UP(sm_region_size, LG_ENTRY_ALIGN); + + snd_lg_entry = &r->entries[1]; + assert_int_equal(IMD_ENTRY_MAGIC, snd_lg_entry->magic); + assert_int_equal(-sm_region_size, snd_lg_entry->start_offset); + assert_int_equal(CBMEM_ID_IMD_SMALL, snd_lg_entry->id); + + assert_int_equal(sm_region_size, snd_lg_entry->size); + + r = imd.sm.r; + assert_int_equal(1, r->num_entries); + + sm_entry = &r->entries[0]; + assert_int_equal(IMD_ENTRY_MAGIC, sm_entry->magic); + assert_int_equal(0, sm_entry->start_offset); + assert_int_equal(SM_ROOT_SIZE, sm_entry->size); + assert_int_equal(CBMEM_ID_IMD_ROOT, sm_entry->id); + + free(base); +} + +/* Tests for imdr_recover. */ +static void test_imd_recover(void **state) +{ + int32_t offset_copy, max_offset_copy; + uint32_t rp_magic_copy, num_entries_copy; + uint32_t e_align_copy, e_magic_copy, e_id_copy; + uint32_t size_copy, diff; + void *base; + struct imd imd = {0}; + struct imd_root_pointer *rp; + struct imd_root *r; + struct imd_entry *lg_root_entry, *sm_root_entry, *ptr; + const struct imd_entry *lg_entry; + + /* Fail when the limit for lg was not set. */ + imd.lg.limit = (uintptr_t) NULL; + assert_int_equal(-1, imd_recover(&imd)); + + /* Set the limit for lg. */ + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + /* Fail when the root pointer is not valid. */ + rp = (void *)imd.lg.limit - sizeof(struct imd_root_pointer); + assert_non_null(rp); + assert_int_equal(IMD_ROOT_PTR_MAGIC, rp->magic); + + rp_magic_copy = rp->magic; + rp->magic = 0; + assert_int_equal(-1, imd_recover(&imd)); + rp->magic = rp_magic_copy; + + /* Set the root pointer. */ + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + assert_int_equal(2, ((struct imd_root *)imd.lg.r)->num_entries); + assert_int_equal(1, ((struct imd_root *)imd.sm.r)->num_entries); + + /* Fail if the number of entries exceeds the maximum number of entries. */ + r = imd.lg.r; + num_entries_copy = r->num_entries; + r->num_entries = r->max_entries + 1; + assert_int_equal(-1, imd_recover(&imd)); + r->num_entries = num_entries_copy; + + /* Fail if entry align is not a power of 2. */ + e_align_copy = r->entry_align; + r->entry_align++; + assert_int_equal(-1, imd_recover(&imd)); + r->entry_align = e_align_copy; + + /* Fail when an entry is not valid. */ + lg_root_entry = &r->entries[0]; + e_magic_copy = lg_root_entry->magic; + lg_root_entry->magic = 0; + assert_int_equal(-1, imd_recover(&imd)); + lg_root_entry->magic = e_magic_copy; + + /* Add new entries: large and small. */ + lg_entry = imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE); + assert_non_null(lg_entry); + assert_int_equal(3, r->num_entries); + + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); + assert_int_equal(2, ((struct imd_root *)imd.sm.r)->num_entries); + + /* Fail when start_addr is lower than low_limit. */ + r = imd.lg.r; + max_offset_copy = r->max_offset; + r->max_offset = lg_entry->start_offset + sizeof(int32_t); + assert_int_equal(-1, imd_recover(&imd)); + r->max_offset = max_offset_copy; + + /* Fail when start_addr is at least imdr->limit. */ + offset_copy = lg_entry->start_offset; + ptr = (struct imd_entry *)lg_entry; + ptr->start_offset = (void *)imd.lg.limit - (void *)r; + assert_int_equal(-1, imd_recover(&imd)); + ptr->start_offset = offset_copy; + + /* Fail when (start_addr + e->size) is higher than imdr->limit. */ + size_copy = lg_entry->size; + diff = (void *)imd.lg.limit - ((void *)r + lg_entry->start_offset); + ptr->size = diff + 1; + assert_int_equal(-1, imd_recover(&imd)); + ptr->size = size_copy; + + /* Succeed if small region is not present. */ + sm_root_entry = &r->entries[1]; + e_id_copy = sm_root_entry->id; + sm_root_entry->id = 0; + assert_int_equal(0, imd_recover(&imd)); + sm_root_entry->id = e_id_copy; + + assert_int_equal(0, imd_recover(&imd)); + + free(base); +} + +static void test_imd_limit_size(void **state) +{ + void *base; + struct imd imd = {0}; + size_t root_size, max_size; + + max_size = align_up_pow2(sizeof(struct imd_root_pointer) + + sizeof(struct imd_root) + 3 * sizeof(struct imd_entry)); + + assert_int_equal(-1, imd_limit_size(&imd, max_size)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + root_size = align_up_pow2(sizeof(struct imd_root_pointer) + + sizeof(struct imd_root) + 2 * sizeof(struct imd_entry)); + imd.lg.r = (void *)imd.lg.limit - root_size; + + imd_create_empty(&imd, root_size, LG_ENTRY_ALIGN); + assert_int_equal(-1, imd_limit_size(&imd, root_size - 1)); + assert_int_equal(0, imd_limit_size(&imd, max_size)); + + /* Cannot create such a big entry */ + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, max_size - root_size + 1)); + + free(base); +} + +static void test_imd_lockdown(void **state) +{ + struct imd imd = {0}; + struct imd_root *r_lg, *r_sm; + + assert_int_equal(-1, imd_lockdown(&imd)); + + imd.lg.r = malloc(sizeof(struct imd_root)); + if (imd.lg.r == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + r_lg = (struct imd_root *) (imd.lg.r); + + assert_int_equal(0, imd_lockdown(&imd)); + assert_true(r_lg->flags & IMD_FLAG_LOCKED); + + imd.sm.r = malloc(sizeof(struct imd_root)); + if (imd.sm.r == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + r_sm = (struct imd_root *) (imd.sm.r); + + assert_int_equal(0, imd_lockdown(&imd)); + assert_true(r_sm->flags & IMD_FLAG_LOCKED); + + free(imd.lg.r); + free(imd.sm.r); +} + +static void test_imd_region_used(void **state) +{ + struct imd imd = {0}; + struct imd_entry *first_entry, *new_entry; + struct imd_root *r; + size_t size; + void *imd_base; + void *base; + + assert_int_equal(-1, imd_region_used(&imd, &base, &size)); + + imd_base = malloc(LIMIT_ALIGN); + if (imd_base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)imd_base)); + + assert_int_equal(-1, imd_region_used(&imd, &base, &size)); + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + assert_int_equal(0, imd_region_used(&imd, &base, &size)); + + r = (struct imd_root *)imd.lg.r; + first_entry = &r->entries[r->num_entries - 1]; + + assert_int_equal(r + first_entry->start_offset, (uintptr_t)base); + assert_int_equal(first_entry->size, size); + + assert_non_null(imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + assert_int_equal(2, r->num_entries); + + assert_int_equal(0, imd_region_used(&imd, &base, &size)); + + new_entry = &r->entries[r->num_entries - 1]; + + assert_true((void *)r + new_entry->start_offset == base); + assert_int_equal(first_entry->size + new_entry->size, size); + + free(imd_base); +} + +static void test_imd_entry_add(void **state) +{ + int i; + struct imd imd = {0}; + size_t entry_size = 0; + size_t used_size; + ssize_t entry_offset; + void *base; + struct imd_root *r, *sm_r, *lg_r; + struct imd_entry *first_entry, *new_entry; + uint32_t num_entries_copy; + int32_t max_offset_copy; + + /* No small region case. */ + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + + r = (struct imd_root *)imd.lg.r; + first_entry = &r->entries[r->num_entries - 1]; + + /* Cannot add an entry when root is locked. */ + r->flags = IMD_FLAG_LOCKED; + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + r->flags = 0; + + /* Fail when the maximum number of entries has been reached. */ + num_entries_copy = r->num_entries; + r->num_entries = r->max_entries; + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + r->num_entries = num_entries_copy; + + /* Fail when entry size is 0 */ + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, 0)); + + /* Fail when entry size (after alignment) overflows imd total size. */ + entry_size = 2049; + max_offset_copy = r->max_offset; + r->max_offset = -entry_size; + assert_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + r->max_offset = max_offset_copy; + + /* Finally succeed. */ + entry_size = 2 * sizeof(int32_t); + assert_non_null(imd_entry_add(&imd, LG_ENTRY_ID, entry_size)); + assert_int_equal(2, r->num_entries); + + new_entry = &r->entries[r->num_entries - 1]; + assert_int_equal(sizeof(struct imd_entry), (void *)new_entry - (void *)first_entry); + + assert_int_equal(IMD_ENTRY_MAGIC, new_entry->magic); + assert_int_equal(LG_ENTRY_ID, new_entry->id); + assert_int_equal(entry_size, new_entry->size); + + used_size = ALIGN_UP(entry_size, r->entry_align); + entry_offset = first_entry->start_offset - used_size; + assert_int_equal(entry_offset, new_entry->start_offset); + + /* Use small region case. */ + imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, SM_ROOT_SIZE, + SM_ENTRY_ALIGN); + + lg_r = imd.lg.r; + sm_r = imd.sm.r; + + /* All five new entries should be added to small allocations */ + for (i = 0; i < 5; i++) { + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); + assert_int_equal(i+2, sm_r->num_entries); + assert_int_equal(2, lg_r->num_entries); + } + + /* But next should fall back on large region */ + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); + assert_int_equal(6, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + /* + * Small allocation is created when occupies less than 1/4 of available + * small region. Verify this. + */ + imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, SM_ROOT_SIZE, + SM_ENTRY_ALIGN); + + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, -sm_r->max_offset / 4 + 1)); + assert_int_equal(1, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + /* Next two should go into small region */ + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, -sm_r->max_offset / 4)); + assert_int_equal(2, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + /* (1/4 * 3/4) */ + assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, -sm_r->max_offset / 16 * 3)); + assert_int_equal(3, sm_r->num_entries); + assert_int_equal(3, lg_r->num_entries); + + free(base); +} + +static void test_imd_entry_find(void **state) +{ + struct imd imd = {0}; + void *base; + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + assert_non_null(imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + + assert_non_null(imd_entry_find(&imd, LG_ENTRY_ID)); + assert_non_null(imd_entry_find(&imd, SMALL_REGION_ID)); + + /* Try invalid id, should fail */ + assert_null(imd_entry_find(&imd, INVALID_REGION_ID)); + + free(base); +} + +static void test_imd_entry_find_or_add(void **state) +{ + struct imd imd = {0}; + const struct imd_entry *entry; + struct imd_root *r; + void *base; + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_null(imd_entry_find_or_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + entry = imd_entry_find_or_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE); + assert_non_null(entry); + + r = (struct imd_root *)imd.lg.r; + + assert_int_equal(entry->id, LG_ENTRY_ID); + assert_int_equal(2, r->num_entries); + assert_non_null(imd_entry_find_or_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE)); + assert_int_equal(2, r->num_entries); + + free(base); +} + +static void test_imd_entry_size(void **state) +{ + struct imd_entry entry = { .size = LG_ENTRY_SIZE }; + + assert_int_equal(LG_ENTRY_SIZE, imd_entry_size(&entry)); + + entry.size = 0; + assert_int_equal(0, imd_entry_size(&entry)); +} + +static void test_imd_entry_at(void **state) +{ + struct imd imd = {0}; + struct imd_root *r; + struct imd_entry *e = NULL; + const struct imd_entry *entry; + void *base; + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); + + /* Fail when entry is NULL */ + assert_null(imd_entry_at(&imd, e)); + + entry = imd_entry_add(&imd, LG_ENTRY_ID, LG_ENTRY_SIZE); + assert_non_null(entry); + + r = (struct imd_root *)imd.lg.r; + assert_ptr_equal((void *)r + entry->start_offset, imd_entry_at(&imd, entry)); + + free(base); +} + +static void test_imd_entry_id(void **state) +{ + struct imd_entry entry = { .id = LG_ENTRY_ID }; + + assert_int_equal(LG_ENTRY_ID, imd_entry_id(&entry)); +} + +static void test_imd_entry_remove(void **state) +{ + void *base; + struct imd imd = {0}; + struct imd_root *r; + const struct imd_entry *fst_lg_entry, *snd_lg_entry, *fst_sm_entry; + const struct imd_entry *e = NULL; + + /* Uninitialized handle */ + assert_int_equal(-1, imd_entry_remove(&imd, e)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + r = imd.lg.r; + assert_int_equal(2, r->num_entries); + fst_lg_entry = &r->entries[0]; + snd_lg_entry = &r->entries[1]; + + /* Only last entry can be removed */ + assert_int_equal(-1, imd_entry_remove(&imd, fst_lg_entry)); + r->flags = IMD_FLAG_LOCKED; + assert_int_equal(-1, imd_entry_remove(&imd, snd_lg_entry)); + r->flags = 0; + + r = imd.sm.r; + assert_int_equal(1, r->num_entries); + fst_sm_entry = &r->entries[0]; + + /* Fail trying to remove root entry */ + assert_int_equal(-1, imd_entry_remove(&imd, fst_sm_entry)); + assert_int_equal(1, r->num_entries); + + r = imd.lg.r; + assert_int_equal(0, imd_entry_remove(&imd, snd_lg_entry)); + assert_int_equal(1, r->num_entries); + + /* Fail trying to remove root entry */ + assert_int_equal(-1, imd_entry_remove(&imd, fst_lg_entry)); + assert_int_equal(1, r->num_entries); + + free(base); +} + +static void test_imd_cursor_init(void **state) +{ + struct imd imd = {0}; + struct imd_cursor cursor; + + assert_int_equal(-1, imd_cursor_init(NULL, NULL)); + assert_int_equal(-1, imd_cursor_init(NULL, &cursor)); + assert_int_equal(-1, imd_cursor_init(&imd, NULL)); + assert_int_equal(0, imd_cursor_init(&imd, &cursor)); + + assert_ptr_equal(cursor.imdr[0], &imd.lg); + assert_ptr_equal(cursor.imdr[1], &imd.sm); +} + +static void test_imd_cursor_next(void **state) +{ + void *base; + struct imd imd = {0}; + struct imd_cursor cursor; + struct imd_root *r; + const struct imd_entry *entry; + struct imd_entry *fst_lg_entry, *snd_lg_entry, *fst_sm_entry; + assert_int_equal(0, imd_cursor_init(&imd, &cursor)); + + cursor.current_imdr = 3; + cursor.current_entry = 0; + assert_null(imd_cursor_next(&cursor)); + + cursor.current_imdr = 0; + assert_null(imd_cursor_next(&cursor)); + + base = malloc(LIMIT_ALIGN); + if (base == NULL) + fail_msg("Cannot allocate enough memory - fail test"); + imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); + + assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN)); + + r = imd.lg.r; + entry = imd_cursor_next(&cursor); + assert_non_null(entry); + + fst_lg_entry = &r->entries[0]; + assert_int_equal(fst_lg_entry->id, entry->id); + assert_ptr_equal(fst_lg_entry, entry); + + entry = imd_cursor_next(&cursor); + assert_non_null(entry); + + snd_lg_entry = &r->entries[1]; + assert_int_equal(snd_lg_entry->id, entry->id); + assert_ptr_equal(snd_lg_entry, entry); + + entry = imd_cursor_next(&cursor); + assert_non_null(entry); + + r = imd.sm.r; + fst_sm_entry = &r->entries[0]; + assert_int_equal(fst_sm_entry->id, entry->id); + assert_ptr_equal(fst_sm_entry, entry); + + entry = imd_cursor_next(&cursor); + assert_null(entry); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_imd_handle_init), + cmocka_unit_test(test_imd_handle_init_partial_recovery), + cmocka_unit_test(test_imd_create_empty), + cmocka_unit_test(test_imd_create_tiered_empty), + cmocka_unit_test(test_imd_recover), + cmocka_unit_test(test_imd_limit_size), + cmocka_unit_test(test_imd_lockdown), + cmocka_unit_test(test_imd_region_used), + cmocka_unit_test(test_imd_entry_add), + cmocka_unit_test(test_imd_entry_find), + cmocka_unit_test(test_imd_entry_find_or_add), + cmocka_unit_test(test_imd_entry_size), + cmocka_unit_test(test_imd_entry_at), + cmocka_unit_test(test_imd_entry_id), + cmocka_unit_test(test_imd_entry_remove), + cmocka_unit_test(test_imd_cursor_init), + cmocka_unit_test(test_imd_cursor_next), + }; + + return cb_run_group_tests(tests, NULL, NULL); +} + diff --git a/tests/data/lib/lzma-test/data.3.lzma.bin b/tests/data/lib/lzma-test/data.3.lzma.bin new file mode 100644 index 0000000000000000000000000000000000000000..ca20babe82602ccaeccd37c37cd36e40e9b08ddc GIT binary patch literal 3865 zcmV+!59aUz0AK(BLs}X}#@ELm zS$b(dvk>`2qzUx1SAlJ-lr7h z1ogfe-mZ)IyqR0Rlj2oUKc-4I)dge?DtZV zqselvTkN8ndZ#L|<*R*fG&S@I+*s0iyxc6>|bk^vZX#b(uHb6@kS&X{Ok_V1}h zbo3s!c#8w~Y5Jq_99W}TJ{NvvH(QK*Si7BOX#+MDq~=C;?ZM_8&+;bRi|c#ZEnCxs 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z$*Pi$yO6$6G_vQ5kY)`OGzfFfX{aHFzWA|`Qo}1UOu0S&=94rE8?IC~oekChADs49 zADl8vdTLMMFu_MJr&=6x#(dl)H{h#C38*NT+l+evxbT82PWdVY|2cWl)i|EaZqA;3 zp?-8T-A^Ce{^D0>ZW)DzpZ0(%4U9ZKDC1e)#l$IGUnry;QpJvf`7uPrC_eVElLH8+ zI-x;9R1;E889O(76Uzo&<(owDWy9X}<*XoVcuKxcYb04Yb#7&ALrc>49|l-Qtxx4* z0FWuPCBB+=l&EVOPr~A8k6RYgqMg1wYet8Sn%aN??xS)s$LHvtBZby*3e05@IsWIu zTSQuC0{^f^VKxTvDkyk}F-bnat?}RftBrciR{ZeNVOfK>=BpIBilgSN+sosk?zsMua@@{;{Wn*a zSAX^>jqT9_%ZhENR17t@E3V}DUay<_Tj_I7BmRR(9U#%q@b1sweY14?*^A$;WReZ68jwJe(8?fxOVcadAdujm zP9H<}urJ4Xu>~bcZSBn=4(80GbSrDEzOMUW`ZgdA=pkdLh=vj9hD%_cLDT;s44)?a z6>YQtHo;!C6EoUS4E^9tVPCqEj|hVC54`Tj<|C0me~~_L?@le#RdvKDB0{WwEsC8Y z?QwBAgit`uep}c?ytFzuIgwNF)OWeJ+%IbIB-9L$eEiFLvS|juc}#c6(Pc=MJi>!= zda|J$ROsqT++ELa{! +#include +#include +#include +#include +#include +#include +#include +#include + + +struct lzma_test_state { + char *raw_filename; + size_t raw_file_sz; + char *comp_filename; + size_t comp_file_sz; +}; + +static int get_file_size(const char *fname) +{ + struct stat st; + if (stat(fname, &st) == -1) + return -1; + return st.st_size; +} + +static int teardown_ulzman_file(void **state) +{ + struct lzma_test_state *s = *state; + + test_free(s->raw_filename); + test_free(s->comp_filename); + test_free(s); + + return 0; +} + +/* Set data file with prestate */ +static int setup_ulzman_file(void **state) +{ + int ret = 0; + const char *fname_base = *state; + const char path_prefix[] = __TEST_DATA_DIR__ "/lib/lzma-test/%s%s"; + const char raw_file_suffix[] = ".bin"; + const char comp_file_suffix[] = ".lzma.bin"; + struct lzma_test_state *s = test_malloc(sizeof(*s)); + memset(s, 0, sizeof(*s)); + + if (!s) + return 1; + + const size_t raw_filename_size = strlen(path_prefix) + strlen(fname_base) + + ARRAY_SIZE(raw_file_suffix); + s->raw_filename = test_malloc(raw_filename_size); + + const size_t comp_filename_size = strlen(path_prefix) + strlen(fname_base) + + ARRAY_SIZE(comp_file_suffix); + s->comp_filename = test_malloc(comp_filename_size); + + if (!s->raw_filename || !s->comp_filename) { + print_error("File path allocation error\n"); + ret = 2; + goto error; + } + + snprintf(s->raw_filename, raw_filename_size, path_prefix, fname_base, raw_file_suffix); + snprintf(s->comp_filename, comp_filename_size, path_prefix, fname_base, + comp_file_suffix); + + s->raw_file_sz = get_file_size(s->raw_filename); + s->comp_file_sz = get_file_size(s->comp_filename); + + if (s->raw_file_sz == -1) { + print_error("Unable to open file: %s\n", s->raw_filename); + ret = 3; + goto error; + } + + if (s->comp_file_sz == -1) { + print_error("Unable to open file: %s\n", s->comp_filename); + ret = 3; + goto error; + } + + *state = s; + return 0; +error: + teardown_ulzman_file((void **)&s); + return ret; +} + +static int read_file(const char *fname, uint8_t *buf, size_t sz) +{ + int f = open(fname, O_RDONLY); + int read_sz = 0; + + if (f == -1) + return -1; + + read_sz = read(f, buf, sz); + + close(f); + return read_sz; +} + +static void test_ulzman_correct_file(void **state) +{ + struct lzma_test_state *s = *state; + uint8_t *raw_buf = test_malloc(s->raw_file_sz); + uint8_t *decomp_buf = test_malloc(s->raw_file_sz); + uint8_t *comp_buf = test_malloc(s->comp_file_sz); + + assert_non_null(raw_buf); + assert_non_null(decomp_buf); + assert_non_null(comp_buf); + assert_int_equal(s->raw_file_sz, read_file(s->raw_filename, raw_buf, s->raw_file_sz)); + assert_int_equal(s->comp_file_sz, + read_file(s->comp_filename, comp_buf, s->comp_file_sz)); + + assert_int_equal(s->raw_file_sz, + ulzman(comp_buf, s->comp_file_sz, decomp_buf, s->raw_file_sz)); + assert_memory_equal(raw_buf, decomp_buf, s->raw_file_sz); + + test_free(raw_buf); + test_free(decomp_buf); + test_free(comp_buf); +} + +static void test_ulzman_input_too_small(void **state) +{ + uint8_t in_buf[32]; + uint8_t out_buf[32]; + + assert_int_equal(0, ulzman(in_buf, LZMA_PROPERTIES_SIZE, out_buf, sizeof(out_buf))); +} + +static void test_ulzman_zero_buffer(void **state) +{ + uint8_t in_buf[LZMA_PROPERTIES_SIZE + 1 * KiB]; + uint8_t out_buf[2 * KiB]; + + memset(in_buf, 0, sizeof(in_buf)); + memset(out_buf, 0, sizeof(out_buf)); + + assert_int_equal(0, ulzman(in_buf, sizeof(in_buf), out_buf, sizeof(out_buf))); +} + +#define ULZMAN_CORRECT_FILE_TEST(_file_prefix) \ +{ \ + .name = "test_ulzman_correct_file(" _file_prefix ")", \ + .test_func = test_ulzman_correct_file, \ + .setup_func = setup_ulzman_file, \ + .teardown_func = teardown_ulzman_file, \ + .initial_state = (_file_prefix) \ +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + /* "data.N" in macros below refers to files: + - __TEST_DATA_DIR__ /lib/lzma-test/data.N.bin + - __TEST_DATA_DIR__ /lib/lzma-test/data.N.bin.lzma + Files data.N.bin suffix are raw data, and data.N.lzma.bin are its + LZMA-compressed form. Both are required to exist. + */ + + /* util/cbfs-compression-tool compressed by itself. + To test compression of executable files like payloads. */ + ULZMAN_CORRECT_FILE_TEST("data.1"), + + /* README.md compressed by util/cbfs-compression-tool. */ + ULZMAN_CORRECT_FILE_TEST("data.2"), + + /* tests/lib/imd-test.c compressed by util/cbfs-compression-tool + Structured text file. */ + ULZMAN_CORRECT_FILE_TEST("data.3"), + + /* libcmocka.so.0.7.0 compressed by util/cbfs-compression-tool + Another binary file, shared object. */ + ULZMAN_CORRECT_FILE_TEST("data.4"), + + cmocka_unit_test(test_ulzman_input_too_small), + + cmocka_unit_test(test_ulzman_zero_buffer), + }; + + return cb_run_group_tests(tests, NULL, NULL); +} From fe74240adb9c195a199b33e4e1fcd6bfa790fdaa Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Tue, 12 Oct 2021 15:03:13 -0600 Subject: [PATCH 117/320] mb/google/guybrush: Disable HAVE_ACPI_RESUME / S3 S3 is not currently functional on Guybrush. Remove support from ACPI. BUG=b:202401767 b:181766974 TEST=Boot Guybrush Confirm 'deep' is not in /sys/power/mem_sleep Confirm S0ix suspend/resume still works BRANCH=None Change-Id: I9ed3e051f7f2e411670649ac2528a6f40229bdc6 Signed-off-by: Rob Barnes Reviewed-on: https://review.coreboot.org/c/coreboot/+/58282 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/guybrush/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 489c045524a..c97c06d9635 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION - select HAVE_ACPI_RESUME select HAVE_EM100_SUPPORT select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS From ba358a70d7d4cb2737f6bfc7df46b49010269b54 Mon Sep 17 00:00:00 2001 From: Matt Ziegelbaum Date: Mon, 11 Oct 2021 23:44:44 -0400 Subject: [PATCH 118/320] mb/google/hatch/var/scout: set correct i2c configuration Scout only uses I2C 1, 2, and 3 in DVT units. This removes extraneous I2C configuration copied from Puff. BUG=b:202195805 TEST=Boot scout, verify no more errors due to missing I2C devices Change-Id: Ide70a53e83b3e14540873062e3bef24d1134d2e1 Signed-off-by: Matt Ziegelbaum Reviewed-on: https://review.coreboot.org/c/coreboot/+/58236 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel --- .../google/hatch/variants/scout/gpio.c | 26 ++++++----- .../hatch/variants/scout/overridetree.cb | 45 ++++++------------- 2 files changed, 29 insertions(+), 42 deletions(-) diff --git a/src/mainboard/google/hatch/variants/scout/gpio.c b/src/mainboard/google/hatch/variants/scout/gpio.c index c916d556cdd..5491efef9dc 100644 --- a/src/mainboard/google/hatch/variants/scout/gpio.c +++ b/src/mainboard/google/hatch/variants/scout/gpio.c @@ -51,16 +51,14 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* C15 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C15, 1, DEEP), - - /* - * TODO(b/187094460): Re-enable touch screen I2C after resolving USB - * conflict - */ - + /* C16 : PCH_I2C_RFU_SDA (NC) */ + PAD_NC(GPP_C16, NONE), + /* C17 : PCH_I2C_RFU_SCL (NC) */ + PAD_NC(GPP_C17, NONE), /* C18 : PCH_I2C_USI_SDA */ - PAD_NC(GPP_C18, NONE), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : PCH_I2C_USI_SDL */ - PAD_NC(GPP_C19, NONE), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* D13 : SMBUS_ISP_SCALAR */ PAD_CFG_GPO(GPP_D13, 0, DEEP), @@ -112,14 +110,22 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - /* H4: PCH_I2C_PCON_SDA */ + /* H4: PCH_I2C_SCALER_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ + /* H5: PCH_I2C_SCALER_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* H6 : PCH_I2C_TPU_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : PCH_I2C_TPU_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : NC */ + PAD_NC(GPP_H9, NONE), + /* H10 : NC */ + PAD_NC(GPP_H10, NONE), + /* H11 : NC */ + PAD_NC(GPP_H11, NONE), /* H22 : PWM_PP3300_BIOZZER */ PAD_CFG_GPO(GPP_H22, 0, DEEP), }; diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb index 8b7d558b471..9b336211774 100644 --- a/src/mainboard/google/hatch/variants/scout/overridetree.cb +++ b/src/mainboard/google/hatch/variants/scout/overridetree.cb @@ -4,11 +4,11 @@ chip soc/intel/cannonlake register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, @@ -150,32 +150,26 @@ chip soc/intel/cannonlake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | + #| I2C1 | USI (Touch screen) | + #| I2C2 | SCALER | + #| I2C3 | TPU | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, .early_init = 1, }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, - }, - .i2c[2] = { + .i2c[1] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 60, .fall_time_ns = 60, }, - .i2c[3] = { + .i2c[2] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 60, .fall_time_ns = 60, }, - .i2c[4] = { + .i2c[3] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 60, .fall_time_ns = 60, @@ -380,24 +374,11 @@ chip soc/intel/cannonlake device pci 15.0 off # RFU - Reserved for Future Use. end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2, PCON PS175. - device pci 15.3 off end # I2C #3, Realtek RTD2142. + device pci 15.1 on end # I2C #1, USI (Touch screen) + device pci 15.2 on end # I2C #2, SCALER + device pci 15.3 on end # I2C #3, TPU device pci 16.0 on end # Management Engine Interface 1 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 + device pci 19.0 off end # I2C #4 device pci 1a.0 on end # eMMC device pci 1c.6 on # PCI Root Port 7 (LAN) chip drivers/net # RTL8111H Ethernet NIC From 7af90247be608ddb79b689e0bfded3caf1c11d07 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 13 Oct 2021 17:14:51 -0600 Subject: [PATCH 119/320] mb/google/guybrush: Fix variant_has_pcie_wwan helper variant_has_pcie_wwan helper returns true if gpp_bridge_2 PCIe engine is enabled. On some variants, this engine is used by storage controllers. Fix it by adding a weak override that returns no PCIe WWAN by default. BUG=None TEST=Build and boot to OS in Guybrush. Ensure that PCIe WWAN is enumerated on boards where it is stuffed. Change-Id: I07b9dd8fc5c8c3e1557f9268c1176d4a3cade1af Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/58311 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- .../google/guybrush/variants/baseboard/helpers.c | 7 ++----- .../google/guybrush/variants/guybrush/Makefile.inc | 5 +++++ .../google/guybrush/variants/guybrush/variant.c | 9 +++++++++ 3 files changed, 16 insertions(+), 5 deletions(-) create mode 100644 src/mainboard/google/guybrush/variants/guybrush/variant.c diff --git a/src/mainboard/google/guybrush/variants/baseboard/helpers.c b/src/mainboard/google/guybrush/variants/baseboard/helpers.c index 881c556f70f..248e7a98ab8 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/helpers.c +++ b/src/mainboard/google/guybrush/variants/baseboard/helpers.c @@ -2,9 +2,6 @@ #include #include -#include -#include -#include WEAK_DEV_PTR(fpmcu); @@ -13,7 +10,7 @@ bool variant_has_fpmcu(void) return is_dev_enabled(DEV_PTR(fpmcu)); } -bool variant_has_pcie_wwan(void) +bool __weak variant_has_pcie_wwan(void) { - return is_dev_enabled(DEV_PTR(gpp_bridge_2)); + return false; } diff --git a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc index f7c97bafbf4..d8a1beaf8f8 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc @@ -1,7 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-or-later bootblock-y += gpio.c +bootblock-y += variant.c + romstage-y += gpio.c +romstage-y += variant.c + ramstage-y += gpio.c +ramstage-y += variant.c subdirs-y += ./memory diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c new file mode 100644 index 00000000000..cde24cb9c06 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +bool variant_has_pcie_wwan(void) +{ + return is_dev_enabled(DEV_PTR(gpp_bridge_2)); +} From c7ca0f2e33f06c3683cc1db41f83e3e5f31d566d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 8 Sep 2021 14:22:12 +0200 Subject: [PATCH 120/320] soc/intel/broadwell/pcie.c: Simplify AND-mask There's no need to mask out bit 11, as it is unconditionally set. For some reason, this changes the resulting coreboot image. Also simplify another PCI operation with a redundant AND-mask. Change-Id: I5492acd5f9c61db83a07ce7c1f6b887768c3eadf Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57499 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Felix Held --- src/soc/intel/broadwell/pch/pcie.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 28d858f2b09..29915d6e135 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -516,8 +516,8 @@ static void pch_pcie_early(struct device *dev) } /* Enable LTR in Root Port. Disable OBFF. */ - pci_update_config32(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); - pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); + pci_update_config32(dev, 0x64, ~(3 << 18), (1 << 11)); + pci_or_config32(dev, 0x68, 1 << 10); pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); From 291294d137393bb1f4d59b388f287134943f2a95 Mon Sep 17 00:00:00 2001 From: Selma Bensaid Date: Mon, 11 Oct 2021 16:37:36 -0700 Subject: [PATCH 121/320] soc/intel/alderlake: fix NULL pointer dereference microcode_file could be NULL and passed to get_microcode_size, this was detected by klocwork scan. Signed-off-by: Selma Bensaid Change-Id: Ibb3d49ab18d8c26bbf5d6bf6bdf1bf91137f5736 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58233 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/fsp_params.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 333957f2eaa..f9569f9e417 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -346,12 +346,14 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, /* Locate microcode and pass to FSP-S for 2nd microcode loading */ microcode_file = intel_microcode_find(); - microcode_len = get_microcode_size(microcode_file); - if ((microcode_file != NULL) && (microcode_len != 0)) { - /* Update CPU Microcode patch base address/size */ - s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; - s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; + if (microcode_file != NULL) { + microcode_len = get_microcode_size(microcode_file); + if (microcode_len != 0) { + /* Update CPU Microcode patch base address/size */ + s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; + s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; + } } /* Use coreboot MP PPI services if Kconfig is enabled */ From d1c1afdf574931eb15c7dec1094c6a9bc3ee60a7 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 2 Sep 2016 21:41:26 -0500 Subject: [PATCH 122/320] arch/x86/smbios: Add generation of type 20 table If available, use data from MEMINFO CBMEM table and saved handles from type 17/19 tables to generate type 20 (Memory Device Mapped Address) SMBIOS table. Windows 10/11 and some other OSes use this table to report the total memory available on a given device. Change-Id: I2574d6209d973a8e7f112eb3ef61f5d26986e47b Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/58271 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/arch/x86/smbios.c | 48 +++++++++++++++++++++++++++++++++++++++++++ src/include/smbios.h | 15 ++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index e9c8f47a446..04f8717e724 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1031,6 +1031,50 @@ static int smbios_write_type19(unsigned long *current, int *handle, int type16) return len; } +static int smbios_write_type20_table(unsigned long *current, int *handle, u32 addr_start, + u32 addr_end, int type17_handle, int type19_handle) +{ + struct smbios_type20 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS, + sizeof(*t), *handle); + + t->memory_device_handle = type17_handle; + t->memory_array_mapped_address_handle = type19_handle; + t->addr_start = addr_start; + t->addr_end = addr_end; + t->partition_row_pos = 0xff; + t->interleave_pos = 0xff; + t->interleave_depth = 0xff; + + const int len = smbios_full_table_len(&t->header, t->eos); + *current += len; + *handle += 1; + return len; +} + +static int smbios_write_type20(unsigned long *current, int *handle, + int type17_handle, int type19_handle) +{ + u32 start_addr = 0; + int totallen = 0; + int i; + + struct memory_info *meminfo; + meminfo = cbmem_find(CBMEM_ID_MEMINFO); + if (meminfo == NULL) + return 0; /* can't find mem info in cbmem */ + + printk(BIOS_INFO, "Create SMBIOS type 20\n"); + for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) { + struct dimm_info *dimm; + dimm = &meminfo->dimm[i]; + u32 end_addr = start_addr + (dimm->dimm_size << 10) - 1; + totallen += smbios_write_type20_table(current, handle, start_addr, end_addr, + type17_handle, type19_handle); + start_addr = end_addr + 1; + } + return totallen; +} + static int smbios_write_type32(unsigned long *current, int handle) { struct smbios_type32 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_BOOT_INFORMATION, @@ -1281,8 +1325,12 @@ unsigned long smbios_write_tables(unsigned long current) const int type16 = handle; update_max(len, max_struct_size, smbios_write_type16(¤t, &handle)); + const int type17 = handle; update_max(len, max_struct_size, smbios_write_type17(¤t, &handle, type16)); + const int type19 = handle; update_max(len, max_struct_size, smbios_write_type19(¤t, &handle, type16)); + update_max(len, max_struct_size, + smbios_write_type20(¤t, &handle, type17, type19)); update_max(len, max_struct_size, smbios_write_type32(¤t, handle++)); update_max(len, max_struct_size, smbios_walk_device_tree(all_devices, diff --git a/src/include/smbios.h b/src/include/smbios.h index 0b24c154137..fd9fbd40c9a 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -247,6 +247,7 @@ typedef enum { SMBIOS_PHYS_MEMORY_ARRAY = 16, SMBIOS_MEMORY_DEVICE = 17, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19, + SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS = 20, SMBIOS_SYSTEM_BOOT_INFORMATION = 32, SMBIOS_IPMI_DEVICE_INFORMATION = 38, SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION = 41, @@ -880,6 +881,20 @@ struct smbios_type19 { u8 eos[2]; } __packed; +struct smbios_type20 { + struct smbios_header header; + u32 addr_start; + u32 addr_end; + u16 memory_device_handle; + u16 memory_array_mapped_address_handle; + u8 partition_row_pos; + u8 interleave_pos; + u8 interleave_depth; + u64 ext_addr_start; + u64 ext_addr_end; + u8 eos[2]; +} __packed; + struct smbios_type32 { struct smbios_header header; u8 reserved[6]; From dcc0cc27f4a728e96dd85b88f7321edfcfd7add9 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 23 Sep 2021 11:49:41 +0200 Subject: [PATCH 123/320] MAINTAINERS: Add Reka for SPD utilities Change-Id: Ifd4837e11a0ac22e1c8855553a0c51b0f25ab96c Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/57871 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Maxim Polyakov Reviewed-by: Stefan Reinauer --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 309d37af702..e638ad24546 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -857,6 +857,12 @@ S: Maintained F: src/superio/ F: util/superiotool/ +SPD UTILITIES +M: Reka Norman +S: Maintained +F: util/spd_tools/ +F: util/spdtool/ + MEMLAYOUT M: Julius Werner S: Supported From 05ae8f2ff31ba1d02aba15c99025df91588712e1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 8 Mar 2021 10:35:49 +0100 Subject: [PATCH 124/320] mainboard: Drop invalid `VGA_BIOS_FILE` defaults MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig does not exist in the coreboot tree (including submodules), drop it. These files should be stored in the `site-local` subdirectory and the paths specified for each board in `site-local/Kconfig`. For example: config VGA_BIOS_FILE default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200 Note that this is just an example. There are better ways to structure one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option would be one of them, though variants may still need special handling. Also, update autoport to not generate `VGA_BIOS_FILE` defaults. Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner Reviewed-by: Felix Singer --- src/mainboard/amd/inagua/Kconfig | 5 ----- src/mainboard/amd/persimmon/Kconfig | 5 ----- src/mainboard/amd/south_station/Kconfig | 4 ---- src/mainboard/amd/union_station/Kconfig | 4 ---- src/mainboard/apple/macbookair4_2/Kconfig | 4 ---- src/mainboard/asus/f2a85-m/Kconfig | 4 ---- src/mainboard/getac/p470/Kconfig | 4 ---- src/mainboard/google/auron/Kconfig | 4 ---- src/mainboard/google/beltino/Kconfig | 4 ---- src/mainboard/google/butterfly/Kconfig | 4 ---- src/mainboard/google/jecht/Kconfig | 4 ---- src/mainboard/google/link/Kconfig | 4 ---- src/mainboard/google/parrot/Kconfig | 4 ---- src/mainboard/google/slippy/Kconfig | 4 ---- src/mainboard/google/stout/Kconfig | 4 ---- src/mainboard/hp/folio_9480m/Kconfig | 4 ---- src/mainboard/hp/snb_ivb_laptops/Kconfig | 5 ----- src/mainboard/ibase/mb899/Kconfig | 4 ---- src/mainboard/intel/baskingridge/Kconfig | 4 ---- src/mainboard/intel/dcp847ske/Kconfig | 4 ---- src/mainboard/intel/emeraldlake2/Kconfig | 4 ---- src/mainboard/intel/strago/Kconfig | 9 --------- src/mainboard/intel/wtm2/Kconfig | 4 ---- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 5 ----- src/mainboard/kontron/986lcd-m/Kconfig | 4 ---- src/mainboard/kontron/ktqm77/Kconfig | 4 ---- src/mainboard/lenovo/l520/Kconfig | 4 ---- src/mainboard/lenovo/s230u/Kconfig | 4 ---- src/mainboard/lenovo/t420/Kconfig | 4 ---- src/mainboard/lenovo/t420s/Kconfig | 4 ---- src/mainboard/lenovo/t430s/Kconfig | 4 ---- src/mainboard/lenovo/t440p/Kconfig | 4 ---- src/mainboard/lenovo/t520/Kconfig | 4 ---- src/mainboard/lenovo/t530/Kconfig | 4 ---- src/mainboard/lenovo/x1_carbon_gen1/Kconfig | 4 ---- src/mainboard/lenovo/x220/Kconfig | 7 +------ src/mainboard/lenovo/x230/Kconfig | 4 ---- src/mainboard/pcengines/apu1/Kconfig | 5 ----- src/mainboard/protectli/vault_bsw/Kconfig | 7 ------- src/mainboard/samsung/lumpy/Kconfig | 4 ---- src/mainboard/samsung/stumpy/Kconfig | 4 ---- src/mainboard/supermicro/x9scl/Kconfig | 4 ---- src/mainboard/system76/lemp9/Kconfig | 4 ---- util/autoport/main.go | 3 --- 44 files changed, 1 insertion(+), 190 deletions(-) diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 8346f528430..3706b3335d7 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -36,11 +36,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVBios.bin" - config VGA_BIOS_ID string "VGA device PCI IDs" depends on VGA_BIOS diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index b8345709048..66a05ee3c4d 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -37,11 +37,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string default "1002,9802" diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 883be39644e..32eddb48c94 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -36,10 +36,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config VGA_BIOS_FILE - string - default "site-local/vgabios.bin" - config VGA_BIOS_ID string default "1002,9806" diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index ab920134723..0c20e5fecb1 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -35,10 +35,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config VGA_BIOS_FILE - string - default "site-local/vgabios.bin" - config VGA_BIOS_ID string default "1002,9802" diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 56194e0010d..5e8b1e02abc 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -22,10 +22,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "MacBookAir4,2" -config VGA_BIOS_FILE - string - default "pci8086,0116.rom" - config VGA_BIOS_ID string default "8086,0116" diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 23c611dbc2b..a2e4f60341c 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -95,10 +95,6 @@ config VGA_BIOS_ID string default "1002,9901" -config VGA_BIOS_FILE - string - default "pci1002,9901.rom" - endif config DEVICETREE diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 4523a75bb07..6af53d85e09 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -32,8 +32,4 @@ config IRQ_SLOT_COUNT int default 18 -config VGA_BIOS_FILE - string - default "getac-pci8086,27a2.rom" - endif # BOARD_GETAC_P470 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 0d37a10826a..61447fdacbd 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -51,10 +51,6 @@ config EC_GOOGLE_CHROMEEC_BOARDNAME default "samus" if BOARD_GOOGLE_SAMUS default "" -config VGA_BIOS_FILE - string - default "pci8086,0406.rom" - config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 8ecba7ad034..00b33ad4abb 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -40,10 +40,6 @@ config MAINBOARD_FAMILY string default "Google_Beltino" -config VGA_BIOS_FILE - string - default "pci8086,0406.rom" - # Override the default variant behavior, since the data.vbt is the same # for all variants except monroe config INTEL_GMA_VBT_FILE diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 55d731b2894..4eb151efc1f 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -31,10 +31,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Butterfly" -config VGA_BIOS_FILE - string - default "pci8086,0106.rom" - config MAINBOARD_VENDOR string default "Hewlett-Packard" diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 42be86ab28b..2f54be9b3bb 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -33,10 +33,6 @@ config MAINBOARD_PART_NUMBER default "Rikku" if BOARD_GOOGLE_RIKKU default "Tidus" if BOARD_GOOGLE_TIDUS -config VGA_BIOS_FILE - string - default "pci8086,0406.rom" - # Override the default variant behavior, since the data.vbt is the same # for all variants except tidus config INTEL_GMA_VBT_FILE diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 6926ca18c87..ee68e46df99 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -31,10 +31,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Link" -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index e596951bcd2..5fffcc14de7 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -32,10 +32,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Parrot" -config VGA_BIOS_FILE - string - default "pci8086,0106.rom" - config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 7bb717be29a..e8963f793a4 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -48,10 +48,6 @@ config MAINBOARD_FAMILY config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config VGA_BIOS_FILE - string - default "pci8086,0406.rom" - # Override the default variant behavior, since the data.vbt is the same # for all variants. config INTEL_GMA_VBT_FILE diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index cdba84ac8ad..69cfdcccdd4 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -30,10 +30,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Stout" -config VGA_BIOS_FILE - string - default "pci8086,0156.rom" - config VGA_BIOS_ID string default "8086,0156" diff --git a/src/mainboard/hp/folio_9480m/Kconfig b/src/mainboard/hp/folio_9480m/Kconfig index 967743a62aa..1e0f116e7b1 100644 --- a/src/mainboard/hp/folio_9480m/Kconfig +++ b/src/mainboard/hp/folio_9480m/Kconfig @@ -25,10 +25,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "HP EliteBook Folio 9480m" -config VGA_BIOS_FILE - string - default "pci8086,0a16.rom" - config VGA_BIOS_ID string default "8086,0a16" diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index 7a49bfdb264..d7e2a97ae9b 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -44,11 +44,6 @@ config MAINBOARD_PART_NUMBER config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config VGA_BIOS_FILE - string - default "pci8086,0116.rom" if SOUTHBRIDGE_INTEL_BD82X6X - default "pci8086,0166.rom" if SOUTHBRIDGE_INTEL_C216 - config VGA_BIOS_ID string default "8086,0116" if SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index d073f2bad9a..05b0a09a0ce 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -26,8 +26,4 @@ config IRQ_SLOT_COUNT int default 18 -config VGA_BIOS_FILE - string - default "amipci_01.20" - endif # BOARD_IBASE_MB899 diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 29f83f735af..6d7bc8cf933 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -25,8 +25,4 @@ config MAX_CPUS int default 16 -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - endif # BOARD_INTEL_BASKING_RIDGE diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig index 94d75d92ec0..ebc172b6b09 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -31,10 +31,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Intel NUC DCP847SKE" -config VGA_BIOS_FILE - string - default "pci8086,0106.rom" - config VGA_BIOS_ID string default "8086,0106" diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index f8a2e2e232a..86fe98a803a 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -27,8 +27,4 @@ config MAX_CPUS int default 16 -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - endif # BOARD_INTEL_EMERALDLAKE2 diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index c4a98426afd..64d5dfc8424 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -28,15 +28,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Strago" -config VGA_BIOS_FILE - string - depends on VGA_BIOS - default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin" - help - The C0 version of the video BIOS gets computed from this name - so that they can both be added. Only the correct one for the - system will be run. - config VGA_BIOS_ID string depends on VGA_BIOS diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 44a0cd4097d..cf16b8a7b8f 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -20,8 +20,4 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "WHITETIP MOUNTAIN 2" -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - endif # BOARD_INTEL_WTM2 diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 9b097005526..e1eec04fe5e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -37,11 +37,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string default "1002,9806" # FUSION_G_T56N diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 32357109e4c..e8407de732d 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -28,8 +28,4 @@ config IRQ_SLOT_COUNT int default 18 -config VGA_BIOS_FILE - string - default "amipci_01.20" - endif # BOARD_KONTRON_986LCD_M diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 99b74fa9bc5..47459803ff9 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -21,8 +21,4 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "KTQM77/mITX" -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - endif # BOARD_KONTRON_KTQM77 diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index d212dadf3c9..971dd84b14d 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -24,10 +24,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "ThinkPad L520" -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - config VGA_BIOS_ID string default "8086,0126" diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index c7795043233..08f82aa37cb 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -38,10 +38,6 @@ config DRAM_RESET_GATE_GPIO int default 60 -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - config VGA_BIOS_ID string default "8086,0166" diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index d1cd0ec117f..6f4988c03b7 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -60,10 +60,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - config VGA_BIOS_ID string default "8086,0126" diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index db6e2711e0a..c46d4fc43cf 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -59,10 +59,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - config VGA_BIOS_ID string default "8086,0126" diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 710dda2f713..dce078e91a2 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -69,10 +69,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig index 991c1bd0d97..a26b9b7964f 100644 --- a/src/mainboard/lenovo/t440p/Kconfig +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -47,10 +47,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "ThinkPad T440p" -config VGA_BIOS_FILE - string - default "pci8086,0416.rom" - config VGA_BIOS_ID string default "8086,0416" diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 5e120566ff3..039baa69e1a 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -71,10 +71,6 @@ config VGA_BIOS_ID string default "8086,0126" -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - config PS2K_EISAID default "PNP0303" diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index c2d649c3a06..87be416622d 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -68,10 +68,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - config VGA_BIOS_ID string default "8086,0166" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index d360c56bd8b..ec5092fd399 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -59,10 +59,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - config VGA_BIOS_ID string default "8086,0166" diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 8530e49dc5d..61b3c1489ed 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -67,15 +67,10 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0116.rom" if BOARD_LENOVO_X220I - # FIXME: x1 with i3 cpu may also use "pci8086,0116.rom" - default "pci8086,0126.rom" - config VGA_BIOS_ID string default "8086,0116" if BOARD_LENOVO_X220I + # FIXME: x1 with i3 cpu may also use "8086,0116" default "8086,0126" config PS2K_EISAID diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 61144b89c69..cafdead858f 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -70,10 +70,6 @@ config DRAM_RESET_GATE_GPIO int default 10 -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - config VGA_BIOS_ID string default "8086,0166" diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index c617f984b35..d13c0ecd004 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -40,11 +40,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVbios.bin" - config VGA_BIOS_ID string default "1002,9802" diff --git a/src/mainboard/protectli/vault_bsw/Kconfig b/src/mainboard/protectli/vault_bsw/Kconfig index 1f9fa20159d..e169392d6a0 100644 --- a/src/mainboard/protectli/vault_bsw/Kconfig +++ b/src/mainboard/protectli/vault_bsw/Kconfig @@ -51,13 +51,6 @@ config PXE_ROM_ID default "8086,157b" if BOARD_PROTECTLI_FW4B if !RUN_FSP_GOP -config VGA_BIOS_FILE - string - default "3rdparty/blobs/mainboard/protectli/vault_bsw/vgabios.bin" - help - The C0 version of the video bios gets computed from this name - so that they can both be added. Only the correct one for the - system will be run. config VGA_BIOS_ID string diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index a2c08a07a83..d0574bbbed8 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -35,10 +35,6 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Lumpy" -config VGA_BIOS_FILE - string - default "pci8086,0106.rom" - if EARLY_PCI_BRIDGE config EARLY_PCI_BRIDGE_DEVICE diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 58b581075e8..2a706b992ba 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -30,8 +30,4 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Stumpy" -config VGA_BIOS_FILE - string - default "pci8086,0106.rom" - endif # BOARD_SAMSUNG_STUMPY diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig index 4f46ca8c418..40b42137b2a 100644 --- a/src/mainboard/supermicro/x9scl/Kconfig +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -25,10 +25,6 @@ config USBDEBUG_HCD_INDEX int default 1 -config VGA_BIOS_FILE - string - default "pci102b,0532.rom" - config VGA_BIOS_ID string depends on VGA_BIOS diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig index 81e9d3da4b7..9b6cc7688fd 100644 --- a/src/mainboard/system76/lemp9/Kconfig +++ b/src/mainboard/system76/lemp9/Kconfig @@ -55,10 +55,6 @@ config MAX_CPUS config DIMM_MAX default 2 -config VGA_BIOS_FILE - string - default "pci8086,9b41.rom" - config VGA_BIOS_ID string default "8086,9b41" diff --git a/util/autoport/main.go b/util/autoport/main.go index b889a95681b..9b0b43666a6 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -510,9 +510,6 @@ func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x,%04x", addr.PCIVenID, addr.PCIDevID) - KconfigString["VGA_BIOS_FILE"] = fmt.Sprintf("pci%04x,%04x.rom", - addr.PCIVenID, - addr.PCIDevID) PutPCIDevParent(addr, g.Comment, g.MissingParent) IGDEnabled = true } From ff556ca9956689640503f33098f7fe3c03b475f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 22:56:41 +0300 Subject: [PATCH 125/320] cpu/x86/lapic: Split virtual_wire_mode_init() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only the enable_lapic() part is required while doing SMP init. Also disable_lapic() must not be called if we rely on LAPIC for timer source. Change-Id: Ib5e37c1a0a91fa4e9542141aa74f1c1876fee94e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55261 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/cpu/x86/lapic/lapic.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 9aac163d157..bd2fa67afd3 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -10,12 +10,15 @@ void enable_lapic(void) { msr_t msr; + msr = rdmsr(LAPIC_BASE_MSR); msr.hi &= 0xffffff00; msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; msr.lo |= LAPIC_DEFAULT_BASE; msr.lo |= LAPIC_BASE_MSR_ENABLE; wrmsr(LAPIC_BASE_MSR, msr); + + printk(BIOS_INFO, "Setting up local APIC 0x%x\n", lapicid()); } void disable_lapic(void) @@ -39,19 +42,6 @@ static int need_lapic_init(void) static void lapic_virtual_wire_mode_init(void) { - /* this is so interrupts work. This is very limited scope -- - * linux will do better later, we hope ... - */ - /* this is the first way we learned to do it. It fails on real SMP - * stuff. So we have to do things differently ... - * see the Intel mp1.4 spec, page A-3 - */ - - printk(BIOS_INFO, "Setting up local APIC...\n"); - - /* Enable the local APIC */ - enable_lapic(); - /* * Set Task Priority to 'accept all'. */ @@ -70,14 +60,18 @@ static void lapic_virtual_wire_mode_init(void) lapic_update32(LAPIC_LVT1, ~mask, LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | LAPIC_DELIVERY_MODE_NMI); - printk(BIOS_DEBUG, " apic_id: 0x%x ", lapicid()); - printk(BIOS_INFO, "done.\n"); } void setup_lapic(void) { + /* Enable the local APIC */ if (need_lapic_init()) - lapic_virtual_wire_mode_init(); - else + enable_lapic(); + else if (!CONFIG(UDELAY_LAPIC)) disable_lapic(); + + /* This programming is for PIC mode i8259 interrupts to be delivered to CPU + while LAPIC is enabled. */ + if (need_lapic_init()) + lapic_virtual_wire_mode_init(); } From 90f54c9b8f2ae6d1b222bdcdda9c69f29fab2229 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 20 Jun 2021 19:43:37 +0300 Subject: [PATCH 126/320] cpu/x86/lapic: Add comment on spurious interrupt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The bit LAPIC_SPIV_ENABLE returns 0 after reset even though LAPIC has not been temporarily disabled. Change-Id: Id261bc68fe9d1b1b0e5a3ef599a8f33a686d283b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55699 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/cpu/x86/lapic/lapic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index bd2fa67afd3..a346bc1b149 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -47,9 +47,11 @@ static void lapic_virtual_wire_mode_init(void) */ lapic_update32(LAPIC_TASKPRI, ~LAPIC_TPRI_MASK, 0); - /* Put the local APIC in virtual wire mode */ + /* Set spurious interrupt vector to 0 and keep LAPIC enabled to + be able to clear LVT register mask bits. */ lapic_update32(LAPIC_SPIV, ~LAPIC_VECTOR_MASK, LAPIC_SPIV_ENABLE); + /* Put the local APIC in virtual wire mode */ uint32_t mask = LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | LAPIC_DELIVERY_MODE_MASK; From 7da871ef497e66cd62d4d8bea142cd438bef204b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 20 Jun 2021 14:58:36 +0300 Subject: [PATCH 127/320] cpu/x86/lapic: Do not set read-only bits in LVTx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The bits REMOTE_IRR and SEND_PENDING are documented as read-only, and reserved bits should not be modified either. Change-Id: I6bcb9eb990debe169340a0bfe662158b62a8f4dc Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55700 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/cpu/x86/lapic/lapic.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index a346bc1b149..58e45248aba 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -52,16 +52,12 @@ static void lapic_virtual_wire_mode_init(void) lapic_update32(LAPIC_SPIV, ~LAPIC_VECTOR_MASK, LAPIC_SPIV_ENABLE); /* Put the local APIC in virtual wire mode */ - uint32_t mask = LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_LVT_REMOTE_IRR | - LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | + uint32_t mask = LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_INPUT_POLARITY | LAPIC_DELIVERY_MODE_MASK; - lapic_update32(LAPIC_LVT0, ~mask, LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | - LAPIC_DELIVERY_MODE_EXTINT); - - lapic_update32(LAPIC_LVT1, ~mask, LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | - LAPIC_DELIVERY_MODE_NMI); + lapic_update32(LAPIC_LVT0, ~mask, LAPIC_DELIVERY_MODE_EXTINT); + lapic_update32(LAPIC_LVT1, ~mask, LAPIC_DELIVERY_MODE_NMI); } void setup_lapic(void) From 4cf6605066a54bb74c3f68db7730115a23eef6e5 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 13 Oct 2021 22:14:23 +0200 Subject: [PATCH 128/320] soc/amd/common/block/lpc: simplify eSPI part of Makefile Since espi_util.c is also built in the case of verstage on PSP, we can just add it to all stages. Signed-off-by: Felix Held Change-Id: I65e07c356aac73c5de2d9ce5582434872a223c19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58312 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/lpc/Makefile.inc | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc index 7900b10d138..b1fed7eb01d 100644 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -21,11 +21,4 @@ ramstage-y += spi_dma.c smm-y += spi_dma.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI),y) - -bootblock-y += espi_util.c -romstage-y += espi_util.c -ramstage-y += espi_util.c -verstage-y += espi_util.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c From 595eaccb23994aa2d8b081c78978e3f8181099eb Mon Sep 17 00:00:00 2001 From: Zhi Li Date: Tue, 12 Oct 2021 14:33:21 +0800 Subject: [PATCH 129/320] mb/google/dedede/var/sasukette: Add PIXA2635 touchpad Add PIXA touchpad into devicetree for sasukette. BUG=b:202796169 BRANCH=dedede TEST=built sasukette firmware and verified touchpad function Signed-off-by: Zhi Li Change-Id: I5bc8353692a753ec9254ab02b4ff0481386624b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58239 Tested-by: build bot (Jenkins) Reviewed-by: Weimin Wu Reviewed-by: Henry Sun Reviewed-by: Karthik Ramasubramanian --- .../google/dedede/variants/sasukette/overridetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 8a874620790..4d50783fa27 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -181,6 +181,15 @@ chip soc/intel/jasperlake register "hid_desc_reg_offset" = "0x20" device i2c 2a on end end + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2635"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2d on end + end chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" From 82130369a1c8b06b0aa5e804096d93b98ffce7cc Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Tue, 12 Oct 2021 14:17:37 +0800 Subject: [PATCH 130/320] mb/google/dedede/var/corori: Configure I2C times for Touchpad Configure I2C high / low time in the device tree to ensure Touchpad I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: Touch Pad CLK: 389.2 KHz BUG=b:202787528 TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Change-Id: I0f9d062fc611de0062a39849aee1174268391682 Signed-off-by: Ian Feng Reviewed-on: https://review.coreboot.org/c/coreboot/+/58238 Tested-by: build bot (Jenkins) Reviewed-by: Henry Sun Reviewed-by: Karthik Ramasubramanian Reviewed-by: Paul Menzel --- src/mainboard/google/dedede/variants/corori/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/dedede/variants/corori/overridetree.cb b/src/mainboard/google/dedede/variants/corori/overridetree.cb index d322000cbd2..f7899a61405 100644 --- a/src/mainboard/google/dedede/variants/corori/overridetree.cb +++ b/src/mainboard/google/dedede/variants/corori/overridetree.cb @@ -39,6 +39,8 @@ chip soc/intel/jasperlake register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 255, + .fall_time_ns = 14, }, .i2c[4] = { .speed = I2C_SPEED_FAST, From adb393bdd6cd6734fa2672bd174aca4588a68016 Mon Sep 17 00:00:00 2001 From: Hsuan-ting Chen Date: Thu, 7 Oct 2021 06:21:28 +0000 Subject: [PATCH 131/320] Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/include/bootmode.h | 1 - src/mainboard/google/asurada/chromeos.c | 6 ------ src/mainboard/google/auron/chromeos.c | 13 ------------- src/mainboard/google/beltino/chromeos.c | 7 ------- src/mainboard/google/brya/chromeos.c | 6 ------ src/mainboard/google/butterfly/chromeos.c | 7 ------- src/mainboard/google/cherry/chromeos.c | 6 ------ src/mainboard/google/cyan/chromeos.c | 8 -------- src/mainboard/google/daisy/chromeos.c | 6 ------ src/mainboard/google/dedede/chromeos.c | 6 ------ src/mainboard/google/deltaur/chromeos.c | 7 ------- src/mainboard/google/drallion/chromeos.c | 7 ------- src/mainboard/google/eve/chromeos.c | 6 ------ src/mainboard/google/fizz/chromeos.c | 6 ------ src/mainboard/google/foster/chromeos.c | 7 ------- src/mainboard/google/gale/chromeos.c | 7 ------- src/mainboard/google/glados/chromeos.c | 6 ------ src/mainboard/google/gru/chromeos.c | 6 ------ src/mainboard/google/guybrush/chromeos.c | 11 ----------- src/mainboard/google/hatch/chromeos.c | 6 ------ src/mainboard/google/herobrine/chromeos.c | 6 ------ src/mainboard/google/jecht/chromeos.c | 7 ------- src/mainboard/google/kahlee/chromeos.c | 6 ------ src/mainboard/google/kukui/chromeos.c | 6 ------ src/mainboard/google/link/chromeos.c | 8 -------- src/mainboard/google/mistral/chromeos.c | 8 -------- src/mainboard/google/nyan/chromeos.c | 6 ------ src/mainboard/google/nyan_big/chromeos.c | 6 ------ src/mainboard/google/nyan_blaze/chromeos.c | 6 ------ src/mainboard/google/oak/chromeos.c | 6 ------ src/mainboard/google/octopus/chromeos.c | 6 ------ src/mainboard/google/parrot/chromeos.c | 7 ------- src/mainboard/google/peach_pit/chromeos.c | 6 ------ src/mainboard/google/poppy/chromeos.c | 6 ------ src/mainboard/google/rambi/chromeos.c | 9 --------- src/mainboard/google/reef/chromeos.c | 6 ------ src/mainboard/google/sarien/chromeos.c | 7 ------- src/mainboard/google/slippy/chromeos.c | 6 ------ src/mainboard/google/smaug/chromeos.c | 6 ------ src/mainboard/google/storm/chromeos.c | 7 ------- src/mainboard/google/trogdor/chromeos.c | 6 ------ src/mainboard/google/veyron/chromeos.c | 6 ------ src/mainboard/google/veyron_mickey/chromeos.c | 7 ------- src/mainboard/google/veyron_rialto/chromeos.c | 7 ------- src/mainboard/google/volteer/chromeos.c | 6 ------ src/mainboard/google/zork/chromeos.c | 6 ------ src/security/vboot/bootmode.c | 10 ---------- src/security/vboot/vboot_logic.c | 3 --- src/soc/intel/alderlake/Makefile.inc | 2 -- src/soc/intel/apollolake/Makefile.inc | 2 -- src/soc/intel/skylake/Makefile.inc | 1 - 51 files changed, 322 deletions(-) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index da2dbf65657..aadecba3340 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -11,7 +11,6 @@ int get_recovery_mode_retrain_switch(void); int clear_recovery_mode_switch(void); int get_wipeout_mode_switch(void); int get_lid_switch(void); -int get_ec_is_trusted(void); /* Return 1 if display initialization is required. 0 if not. */ int display_init_required(void); diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 1aa8876ca45..6f8f24281a3 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -40,9 +40,3 @@ int tis_plat_irq_status(void) { return gpio_eint_poll(GPIO_H1_AP_INT); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. This is active low. */ - return !!gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index f449c9cf7ff..50eeddce0a4 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -8,13 +8,6 @@ /* SPI Write protect is GPIO 16 */ #define CROS_WP_GPIO 58 -/* EC_IN_RW is GPIO 25 in samus and 14 otherwise */ -#if CONFIG(BOARD_GOOGLE_SAMUS) -#define EC_IN_RW_GPIO 25 -#else -#define EC_IN_RW_GPIO 14 -#endif - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -39,9 +32,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !get_gpio(EC_IN_RW_GPIO); -} diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 5c49649ef4e..a33caca37af 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -65,10 +65,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index 184cd521049..add73464da6 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -29,9 +29,3 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 960dd879906..356e97b7b5e 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -77,10 +77,3 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 13b673cf07c..748e06e28d4 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -59,9 +59,3 @@ int tis_plat_irq_status(void) { return gpio_eint_poll(GPIO_GSC_AP_INT); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. This is active low. */ - return !!gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 4a48aeb78b3..b88862ca592 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -12,8 +12,6 @@ #define WP_GPIO GP_E_22 -#define EC_IN_RW_GPIO GP_SW_77 - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 @@ -64,9 +62,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(EC_IN_RW_GPIO); -} diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 9cb57f869e8..7599295f1f8 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -37,9 +37,3 @@ int get_write_protect_state(void) { return !gpio_get_value(GPIO_D16); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get_value(GPIO_D17); -} diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index 6be765244d1..fb904cca83b 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -30,9 +30,3 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index b2c34a21614..9d3929e1df5 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -111,10 +111,3 @@ void mainboard_prepare_cr50_reset(void) if (ENV_RAMSTAGE) pmc_soc_set_afterg3_en(true); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index 607f7c3d998..d92ebb133dd 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -110,10 +110,3 @@ void mainboard_prepare_cr50_reset(void) pmc_soc_set_afterg3_en(true); #endif } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 10a837d58ef..11931c676de 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -34,9 +34,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 593982beed1..a74c2f7091c 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -34,9 +34,3 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 8ed41cd2a5f..38d12cb696e 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -26,10 +26,3 @@ int get_write_protect_state(void) { return 0; } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index ac464b4c891..4674581da89 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -157,10 +157,3 @@ int get_write_protect_state(void) { return !read_gpio(get_wp_status_gpio_pin()); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 70b4f641cd9..6a1f0b43585 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -33,9 +33,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 479ca3d85d4..688c0dd27aa 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -49,9 +49,3 @@ int tis_plat_irq_status(void) return gpio_irq_status(GPIO_TPM_IRQ); } #endif - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index a43b3032bb6..df99e6434bf 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -27,17 +27,6 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } -int get_ec_is_trusted(void) -{ - /* Board versions 1 & 2 support H1 DB, but the EC_IN_RW signal is not - routed. So emulate EC is trusted. */ - if (CONFIG(BOARD_GOOGLE_GUYBRUSH) && - (board_id() == UNDEFINED_STRAPPING_ID || board_id() < 3)) - return 1; - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} - void mainboard_spi_fast_speed_override(uint8_t *fast_speed) { uint32_t board_ver = board_id(); diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 400a3fa044f..ee54ade3349 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -34,9 +34,3 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c index 9faf4baf5f9..a11667586bb 100644 --- a/src/mainboard/google/herobrine/chromeos.c +++ b/src/mainboard/google/herobrine/chromeos.c @@ -24,9 +24,3 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Stub GPIO. */ - return 0; -} diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index bc00994a445..cf596360734 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -67,10 +67,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 1f81f222a70..b85f976890a 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -32,9 +32,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 4c4a8bec03f..3f15a3fb913 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -37,9 +37,3 @@ int tis_plat_irq_status(void) { return gpio_eint_poll(CR50_IRQ); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(EC_IN_RW); -} diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index ce9a33dd0cd..540803ca1a2 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -6,8 +6,6 @@ #include #include -#define GPIO_EC_IN_RW 21 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -39,9 +37,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !get_gpio(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 171a8ee6bd3..c827c7d13db 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -1,16 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include void fill_lb_gpios(struct lb_gpios *gpios) { } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 9aaad2f191f..7fe877bff04 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -19,9 +19,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO(R1)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO(U4)); -} diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 9aaad2f191f..7fe877bff04 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -19,9 +19,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO(R1)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO(U4)); -} diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 9aaad2f191f..7fe877bff04 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -19,9 +19,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO(R1)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO(U4)); -} diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 739df2e25bc..9e7af273821 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -34,9 +34,3 @@ int get_write_protect_state(void) { return !gpio_get(WRITE_PROTECT); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(EC_IN_RW); -} diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 4a7f040c47c..03d3b4f0fa2 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -33,9 +33,3 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 346fe76aa91..03b0d476f33 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -68,10 +68,3 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index 3d4f51cb21d..ebbfdd3cb4f 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -37,9 +37,3 @@ int get_write_protect_state(void) { return !gpio_get_value(GPIO_X30); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get_value(GPIO_X23); -} diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 35a9323e165..5dd1e9877e0 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -38,9 +38,3 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index edc714eff58..f9a171820d8 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -8,9 +8,6 @@ /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ #define WP_STATUS_PAD 36 -/* The EC_IN_RW lives on SCGPIO59 */ -#define EC_IN_RW_PAD 59 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -46,9 +43,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !score_get_gpio(EC_IN_RW_PAD); -} diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index f87d9358e32..94d76b99e47 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -33,9 +33,3 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 36825b5dd75..f49b63964f7 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -107,10 +107,3 @@ void mainboard_prepare_cr50_reset(void) if (ENV_RAMSTAGE) pmc_soc_set_afterg3_en(true); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 11d41cd4413..4fffd45b35e 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -30,9 +30,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !get_gpio(14); -} diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index d74df8267e9..13a69bc0ed2 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -19,9 +19,3 @@ int get_write_protect_state(void) { return !gpio_get(WRITE_PROTECT_L); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(EC_IN_RW); -} diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 51a0c5c09e1..21cf94f978e 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -128,10 +128,3 @@ int get_write_protect_state(void) { return !read_gpio(WP_SW); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 718df331f43..90060001917 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -55,9 +55,3 @@ int tis_plat_irq_status(void) { return gpio_irq_status(GPIO_H1_AP_INT); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. This is active low. */ - return !!gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index 411b14e1f7e..b99df04c141 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -56,9 +56,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_ECINRW); -} diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index f3587a3eed7..a3ba7529ba0 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -34,10 +34,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 33f0ee45fc6..95158bf9ee1 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -43,10 +43,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - -int get_ec_is_trusted(void) -{ - /* Do not have a Chrome EC involved in entering recovery mode; - Always return trusted. */ - return 1; -} diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index cdf418d3945..abd50c57bac 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -32,9 +32,3 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index 3c60f9816e2..b581b90d1ac 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -31,9 +31,3 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } - -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 3c50e4ef83d..6c051093ea9 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -57,16 +57,6 @@ int __weak get_recovery_mode_retrain_switch(void) return 0; } -int __weak get_ec_is_trusted(void) -{ - /* - * If board doesn't override this, by default we always assume EC is in - * RW and untrusted. However, newer platforms are supposed to use cr50 - * BOOT_MODE to report this and won't need to override this anymore. - */ - return 0; -} - #if CONFIG(VBOOT_NO_BOARD_SUPPORT) /** * TODO: Create flash protection interface which implements get_write_protect_state. diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 91d42b2c7f8..2973934b990 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -306,9 +306,6 @@ void verstage_main(void) if (CONFIG(TPM_CR50)) check_boot_mode(ctx); - if (get_ec_is_trusted()) - ctx->flags |= VB2_CONTEXT_EC_TRUSTED; - /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(ctx); diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 1c578f215cf..c7e0abc492f 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -46,8 +46,6 @@ ramstage-y += vr_config.c ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c -verstage-y += gpio.c - smm-y += elog.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3b17607a181..49707da1a6e 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -92,13 +92,11 @@ bootblock-y += gpio_glk.c romstage-y += gpio_glk.c smm-y += gpio_glk.c ramstage-y += gpio_glk.c -verstage-y += gpio_glk.c else bootblock-y += gpio_apl.c romstage-y += gpio_apl.c smm-y += gpio_apl.c ramstage-y += gpio_apl.c -verstage-y += gpio_apl.c endif CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 51700b37060..c191aac607f 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -20,7 +20,6 @@ bootblock-y += spi.c bootblock-y += lpc.c bootblock-y += uart.c -verstage-y += gpio.c verstage-y += gspi.c verstage-y += pmutil.c verstage-y += i2c.c From cb70d836ed048b81ad8047e97c9758680cc2da2d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 11 Oct 2021 14:26:42 +0200 Subject: [PATCH 132/320] cpu/intel/haswell: Lock PKG_CST_CONFIG_CONTROL MSR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only. Change-Id: Ieb740aa94255cb3c23a56495c4b645d847637b7f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58222 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak --- src/cpu/intel/haswell/haswell_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2c6384c4e31..90db95b8df5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -395,6 +395,7 @@ static void configure_c_states(void) msr.lo |= (1 << 27); // C3 Auto Undemotion Enable msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable + msr.lo |= (1 << 15); // Lock bits 15:0 msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection if (timed_mwait_capable) From ad6f87d61202984e7604a35b6ce5babee614e676 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 12 Oct 2021 23:35:48 +0200 Subject: [PATCH 133/320] soc/amd/cezanne,picasso/uart: implement read_resource Implement the read_resources function for the UART devices so that the resource allocator knows about their fixed MMIO resources when enabled. TEST=UART still works on Mandolin. Signed-off-by: Felix Held Change-Id: I4ffddee3f5f4281aca98ddfcefa639dfb7a38dae Reviewed-on: https://review.coreboot.org/c/coreboot/+/58306 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/uart.c | 7 ++++++- src/soc/amd/picasso/uart.c | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c index e5f2e4edbb5..cf535d7aece 100644 --- a/src/soc/amd/cezanne/uart.c +++ b/src/soc/amd/cezanne/uart.c @@ -85,8 +85,13 @@ static void uart_enable(struct device *dev) } } +static void uart_read_resources(struct device *dev) +{ + mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4); +} + struct device_operations cezanne_uart_mmio_ops = { - .read_resources = noop_read_resources, + .read_resources = uart_read_resources, .set_resources = noop_set_resources, .scan_bus = scan_static_bus, .enable = uart_enable, diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index b8532aaddf4..1ffb2fdf70d 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -103,8 +103,13 @@ static void uart_enable(struct device *dev) } } +static void uart_read_resources(struct device *dev) +{ + mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4); +} + struct device_operations picasso_uart_mmio_ops = { - .read_resources = noop_read_resources, + .read_resources = uart_read_resources, .set_resources = noop_set_resources, .scan_bus = scan_static_bus, .acpi_name = uart_acpi_name, From 9573c0ed3adbca869cf1b88312a10cc72b756547 Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Thu, 7 Oct 2021 23:09:36 -0700 Subject: [PATCH 134/320] soc/qualcomm/sc7280: Enable compression of SHRM The SHRM region needs to be 4 byte aligned, which make enabling compression slightly more complicated. We need to map it to cached memory before loading it and flushing to memory (in aligned chunks) then remapping the address space back to device memory before beginning execution of the SHRM region. Also, did some cleanup in this file based on comments in CB:49392. BUG=b:182963902 BRANCH=None TEST=Make sure we can still boot to kernel on herobrine Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7280/Makefile.inc | 2 +- src/soc/qualcomm/sc7280/shrm_load_reset.c | 18 ++++++++++++++---- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 364c987dc60..442b2a3858c 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -107,7 +107,7 @@ SHRM_FILE := $(SC7280_BLOB)/shrm/shrm.elf SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm $(SHRM_CBFS)-file := $(SHRM_FILE) $(SHRM_CBFS)-type := payload -$(SHRM_CBFS)-compression := none +$(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) cbfs-files-y += $(SHRM_CBFS) endif diff --git a/src/soc/qualcomm/sc7280/shrm_load_reset.c b/src/soc/qualcomm/sc7280/shrm_load_reset.c index 78830a2df1c..e25d95230ee 100644 --- a/src/soc/qualcomm/sc7280/shrm_load_reset.c +++ b/src/soc/qualcomm/sc7280/shrm_load_reset.c @@ -1,22 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include +#include #include #include +#include void shrm_fw_load_reset(void) { - bool shrm_fw_entry; struct prog shrm_fw_prog = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/shrm"); - shrm_fw_entry = selfload(&shrm_fw_prog); - if (!shrm_fw_entry) + /* map to cached region to force address to be 4 byte aligned */ + mmu_config_range((void *)_shrm, REGION_SIZE(shrm), CACHED_RAM); + + if (!selfload(&shrm_fw_prog)) die("SOC image: SHRM load failed"); + /* flush cached region */ + dcache_clean_by_mva(_shrm, REGION_SIZE(shrm)); + /* remap back to device memory */ + mmu_config_range((void *)_shrm, REGION_SIZE(shrm), DEV_MEM); + clock_reset_shrm(); - printk(BIOS_DEBUG, "\nSOC:SHRM brought out of reset.\n"); + printk(BIOS_DEBUG, "SOC:SHRM brought out of reset.\n"); } From a0f8dc3bd55d4706606e14173bb9afaa97049287 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 11 Oct 2021 14:01:55 +0200 Subject: [PATCH 135/320] soc/intel/cannonlake: Enable Energy/Performance Bias control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set POWER_CTL MSR bit 18 to enable Energy/Performance Bias control. TEST=Boot and verify EPB is enabled in coreboot log: cpu: energy policy set to 6 Change-Id: Ibd1db77b5b63cb6e2b0ad9d2f79caa2f3b576ead Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58221 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Patrick Rudolph Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 99fcadd5818..8c8cad098e5 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -51,6 +51,7 @@ static void configure_misc(void) /* Enable PROCHOT */ msr = rdmsr(MSR_POWER_CTL); msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ + msr.lo |= (1 << 18); /* Enable Energy/Performance Bias control */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); } From d2da8704992a9db90f430e69635e7f10e57cb15c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 7 Oct 2021 00:08:59 -0700 Subject: [PATCH 136/320] soc/intel/common/cse: Split CSE metadata into two CBFS files This change splits CSE metadata structure (added to CBFS) into two separate CBFS files (me_rw.hash and me_rw.version). Since `struct cse_rw_metadata` is now used, it is dropped completely. This change is being made in order to prepare for the upcoming changes to stitch CSE binary at build time. Since the binary might not be available pre-built, it complicates the order of operations for the addition of CSE metadata structure and declaring hash and version as CPPFLAGS_common. Instead rules can be enabled for individual CBFS file targets for hash and version that ensure proper ordering as well. BUG=b:184892226 TEST=Ensured that update works correctly on brya by forcing version mismatch. In case of version match, no update is triggered. Signed-off-by: Furquan Shaikh Change-Id: I7c9bb165e6a64415affcd0b3331628092195fa0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58158 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/Kconfig | 14 +++-- src/soc/intel/common/block/cse/Makefile.inc | 59 ++++++++++--------- src/soc/intel/common/block/cse/cse_lite.c | 56 ++++++++++++++---- .../common/block/include/intelblocks/cse.h | 10 ---- 4 files changed, 86 insertions(+), 53 deletions(-) diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 94f8cd5ebcd..e06895080e9 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -51,11 +51,17 @@ config SOC_INTEL_CSE_RW_CBFS_NAME help CBFS entry name for Intel CSE CBFS RW blob -config SOC_INTEL_CSE_RW_METADATA_CBFS_NAME - string "CBFS name for CSE RW metadata file" if SOC_INTEL_CSE_RW_UPDATE - default "me_rw.metadata" +config SOC_INTEL_CSE_RW_HASH_CBFS_NAME + string "CBFS name for CSE RW hash file" if SOC_INTEL_CSE_RW_UPDATE + default "me_rw.hash" help - CBFS name for Intel CSE CBFS RW metadata file + CBFS name for Intel CSE CBFS RW hash file + +config SOC_INTEL_CSE_RW_VERSION_CBFS_NAME + string "CBFS name for CSE RW version file" if SOC_INTEL_CSE_RW_UPDATE + default "me_rw.version" + help + CBFS name for Intel CSE CBFS RW version file config SOC_INTEL_CSE_RW_FILE string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index e21efc61442..9b50704a57c 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -7,40 +7,43 @@ smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y) -ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") + +ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") +$(error "CSE RW file path is missing and need to be set by mainboard config") +endif + +ifeq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"") +$(error "CSE RW version is missing and need to be set by mainboard config") +endif + +CSE_RW_FILE=$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) + CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) regions-for-file-$(CSE_LITE_ME_RW) = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME)), \ $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME)) cbfs-files-y += $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +$(CSE_LITE_ME_RW)-file := $(CSE_RW_FILE) $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-type := raw -else -$(error "CSE RW file path is missing and need to be set by mainboard config") -endif -# Extract the CSE RW firmware version and update the cse_rw_metadata structure -ifneq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"") -CSE_RW_VERSION:=$(subst ., ,$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))) -MAJOR := $(word 1, $(CSE_RW_VERSION)) -MINOR := $(word 2, $(CSE_RW_VERSION)) -HOTFIX := $(word 3, $(CSE_RW_VERSION)) -BUILD := $(word 4, $(CSE_RW_VERSION)) -CPPFLAGS_common += -DCSE_RW_MAJOR=$(MAJOR) -DCSE_RW_MINOR=$(MINOR) -DCSE_RW_HOTFIX=$(HOTFIX) -DCSE_RW_BUILD=$(BUILD) -else -$(error "CSE RW version is missing and need to be set by mainboard config") -endif +$(obj)/cse_rw.version: + @echo '$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))' > $@ + +CSE_RW_VERSION = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME)) +regions-for-file-$(CSE_RW_VERSION) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_RW_VERSION) +$(CSE_RW_VERSION)-file := $(obj)/cse_rw.version +$(CSE_RW_VERSION)-name := $(CSE_RW_VERSION) +$(CSE_RW_VERSION)-type := raw + +$(obj)/cse_rw.hash: $(CSE_RW_FILE) + openssl dgst -sha256 -binary $< > $@ + +CSE_RW_HASH = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_HASH_CBFS_NAME)) +regions-for-file-$(CSE_RW_HASH) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_RW_HASH) +$(CSE_RW_HASH)-file := $(obj)/cse_rw.hash +$(CSE_RW_HASH)-name := $(CSE_RW_HASH) +$(CSE_RW_HASH)-type := raw -# Compute the hash of the CSE RW binary and update the cse_rw_metadata structure -CSE_RW_PATH := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) -HASH := $(shell openssl dgst -sha256 -hex $(CSE_RW_PATH) | cut -d " " -f2 | fold -w2 | paste -sd',' -) -CPPFLAGS_common += -DCSE_RW_SHA256=$(HASH) - -# Add the CSE RW metadata file to FW_MAIN_A/B -CSE_RW_METADATA = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME)) -regions-for-file-$(CSE_RW_METADATA) = FW_MAIN_A,FW_MAIN_B -cbfs-files-y += $(CSE_RW_METADATA) -$(CSE_RW_METADATA)-file := cse_rw_metadata.c:struct -$(CSE_RW_METADATA)-name := $(CSE_RW_METADATA) -$(CSE_RW_METADATA)-type := raw endif diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index b381c481031..281d3817366 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -565,29 +565,53 @@ enum cse_update_status { CSE_UPDATE_METADATA_ERROR, }; -static struct cse_rw_metadata source_metadata; +static bool read_ver_field(const char *start, char **curr, size_t size, uint16_t *ver_field) +{ + if ((*curr - start) >= size) { + printk(BIOS_ERR, "cse_lite: Version string read overflow!\n"); + return false; + } + + *ver_field = skip_atoi(curr); + (*curr)++; + return true; +} static enum cse_update_status cse_check_update_status(const struct cse_bp_info *cse_bp_info, struct region_device *target_rdev) { int ret; + struct fw_version cbfs_rw_version; + char *version_str, *ptr; + size_t size; if (!cse_is_rw_bp_sign_valid(target_rdev)) return CSE_UPDATE_CORRUPTED; - if (cbfs_load(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, &source_metadata, - sizeof(source_metadata)) != sizeof(source_metadata)) { - printk(BIOS_ERR, "cse_lite: Failed to get CSE CBFS RW metadata\n"); + ptr = version_str = cbfs_map(CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME, &size); + if (!version_str) { + printk(BIOS_ERR, "cse_lite: Failed to get %s\n", + CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME); + return CSE_UPDATE_METADATA_ERROR; + } + + if (!read_ver_field(version_str, &ptr, size, &cbfs_rw_version.major) || + !read_ver_field(version_str, &ptr, size, &cbfs_rw_version.minor) || + !read_ver_field(version_str, &ptr, size, &cbfs_rw_version.hotfix) || + !read_ver_field(version_str, &ptr, size, &cbfs_rw_version.build)) { + cbfs_unmap(version_str); return CSE_UPDATE_METADATA_ERROR; } printk(BIOS_DEBUG, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", - source_metadata.version.major, - source_metadata.version.minor, - source_metadata.version.hotfix, - source_metadata.version.build); + cbfs_rw_version.major, + cbfs_rw_version.minor, + cbfs_rw_version.hotfix, + cbfs_rw_version.build); + + cbfs_unmap(version_str); - ret = compare_cse_version(&source_metadata.version, cse_get_rw_version(cse_bp_info)); + ret = compare_cse_version(&cbfs_rw_version, cse_get_rw_version(cse_bp_info)); if (ret == 0) return CSE_UPDATE_NOT_REQUIRED; else if (ret < 0) @@ -664,6 +688,7 @@ static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info * { struct region_device source_rdev; enum csme_failure_reason rv; + uint8_t *cbfs_rw_hash; if (!cse_get_source_rdev(&source_rdev)) return CSE_LITE_SKU_RW_BLOB_NOT_FOUND; @@ -675,8 +700,16 @@ static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info * return CSE_LITE_SKU_RW_BLOB_NOT_FOUND; } - if (!cse_verify_cbfs_rw_sha256(source_metadata.sha256, cse_cbfs_rw, - region_device_sz(&source_rdev))) { + cbfs_rw_hash = cbfs_map(CONFIG_SOC_INTEL_CSE_RW_HASH_CBFS_NAME, NULL); + if (!cbfs_rw_hash) { + printk(BIOS_ERR, "cse_lite: Failed to get %s\n", + CONFIG_SOC_INTEL_CSE_RW_HASH_CBFS_NAME); + rv = CSE_LITE_SKU_RW_METADATA_NOT_FOUND; + goto error_exit; + } + + if (!cse_verify_cbfs_rw_sha256(cbfs_rw_hash, cse_cbfs_rw, + region_device_sz(&source_rdev))) { rv = CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH; goto error_exit; } @@ -690,6 +723,7 @@ static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info * target_rdev); error_exit: + cbfs_unmap(cbfs_rw_hash); rdev_munmap(&source_rdev, cse_cbfs_rw); return rv; } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f162d485fde..80e28d5e753 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -76,16 +76,6 @@ struct fw_version { uint16_t build; } __packed; -/* - * CSE RW metadata structure - * fw_version - CSE RW firmware version - * sha256 - Hash of the CSE RW binary. - */ -struct cse_rw_metadata { - struct fw_version version; - uint8_t sha256[VB2_SHA256_DIGEST_SIZE]; -}; - /* CSE recovery sub-error codes */ enum csme_failure_reason { /* No error */ From 6c08b1ff8180181ff50150a17ae94abde9ffc2f2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 14 Oct 2021 11:23:49 +0200 Subject: [PATCH 137/320] Doc/mainboard_io_trap_handler_sample.c: Drop file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Looks like nothing references this example. Remove it. If one needs an example, there's several mainboards which contain an I/O trap handler. Change-Id: I4a238fbf354926cb6568e1709bfb79cc546dfd73 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58322 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner --- .../mainboard_io_trap_handler_sample.c | 37 ------------------- 1 file changed, 37 deletions(-) delete mode 100644 Documentation/mainboard_io_trap_handler_sample.c diff --git a/Documentation/mainboard_io_trap_handler_sample.c b/Documentation/mainboard_io_trap_handler_sample.c deleted file mode 100644 index a949009c200..00000000000 --- a/Documentation/mainboard_io_trap_handler_sample.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ec.h" -#include "gpio.h" - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - gnvs->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - //gnvs->smif = 0; - return 1; -} From c2cee06b4efb8992e625ca4554df17c7ef457930 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 12 Oct 2021 23:35:11 +0200 Subject: [PATCH 138/320] soc/amd/common/block/i2c: implement proper read_resource Before this patch the reservation of the MMIO region of the I2C controllers was done in the LPC controller PCI device despite the I2C controllers already being devices in the devicetree. This patch implements this functionality as read_resources function of the I2C device instead. This will only reserve the memory when the I2C devices are enabled in devicetree which is a change from the previous behavior. Signed-off-by: Felix Held Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307 Reviewed-by: Raul Rangel Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/include/soc/iomap.h | 5 ----- src/soc/amd/common/block/i2c/i2c.c | 8 ++++++-- src/soc/amd/common/block/lpc/lpc.c | 8 -------- src/soc/amd/picasso/include/soc/iomap.h | 5 ----- src/soc/amd/stoneyridge/include/soc/iomap.h | 2 -- 5 files changed, 6 insertions(+), 22 deletions(-) diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 236578b9454..a4f0f30d804 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -28,11 +28,6 @@ #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 -/* I2C parameters for lpc_read_resources */ -#define I2C_BASE_ADDRESS APU_I2C2_BASE -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT (I2C_MASTER_DEV_COUNT - I2C_MASTER_START_INDEX) - #define APU_DMAC0_BASE 0xfedc7000 #define APU_DMAC1_BASE 0xfedc8000 #define APU_UART0_BASE 0xfedc9000 diff --git a/src/soc/amd/common/block/i2c/i2c.c b/src/soc/amd/common/block/i2c/i2c.c index 892c83e91f7..ff9ec90fd54 100644 --- a/src/soc/amd/common/block/i2c/i2c.c +++ b/src/soc/amd/common/block/i2c/i2c.c @@ -121,9 +121,13 @@ void i2c_soc_init(void) dw_i2c_soc_init(false); } +static void i2c_read_resources(struct device *dev) +{ + mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4); +} + struct device_operations soc_amd_i2c_mmio_ops = { - /* TODO(kramasub): Move I2C resource info here. */ - .read_resources = noop_read_resources, + .read_resources = i2c_read_resources, .set_resources = noop_set_resources, .scan_bus = scan_smbus, .acpi_name = i2c_acpi_name, diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 3027aae125a..365c14dbf32 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -119,14 +119,6 @@ static void lpc_read_resources(struct device *dev) res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -#ifdef I2C_BASE_ADDRESS - /* I2C devices */ - res = new_resource(dev, 4); - res->base = I2C_BASE_ADDRESS; - res->size = I2C_DEVICE_SIZE * I2C_DEVICE_COUNT; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -#endif - compact_resources(dev); } diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index c56e7af7368..1577568c905 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -48,11 +48,6 @@ #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 -/* I2C parameters for lpc_read_resources */ -#define I2C_BASE_ADDRESS APU_I2C2_BASE -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT (I2C_MASTER_DEV_COUNT - I2C_MASTER_START_INDEX) - #define APU_DMAC0_BASE 0xfedc7000 #define APU_DMAC1_BASE 0xfedc8000 #define APU_UART0_BASE 0xfedc9000 diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index b3c78e80557..c8cee23fa1a 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -13,8 +13,6 @@ /* I2C fixed address */ #define I2C_BASE_ADDRESS 0xfedc2000 #define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 4 - #define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) #define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) #define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) From 297862561e478f1702e56762bcdfdb7d0d7509e2 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 14 Oct 2021 20:59:30 +0200 Subject: [PATCH 139/320] mb/google/kahlee/treeya/audio: use proper I2C base address define I2C_BASE_ADDRESS is the beginning of the MMIO space that contains the I2C controllers MMIO. I2C[ABCD]_BASE_ADDRESS are the base addresses of the 4 I2C controllers, so use I2CA_BASE_ADDRESS instead here. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held Change-Id: Ie8d6a438f76cd33929f5070f9ec6b2f280f471a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58335 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/google/kahlee/variants/treeya/audio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/kahlee/variants/treeya/audio.c b/src/mainboard/google/kahlee/variants/treeya/audio.c index 8265298faba..1c7a4c483bb 100644 --- a/src/mainboard/google/kahlee/variants/treeya/audio.c +++ b/src/mainboard/google/kahlee/variants/treeya/audio.c @@ -23,7 +23,7 @@ void variant_devtree_update(void) printk(BIOS_INFO, "Checking audio codec\n"); return; } - } while (mmio_dev->path.mmio.addr != I2C_BASE_ADDRESS); + } while (mmio_dev->path.mmio.addr != I2CA_BASE_ADDRESS); while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { if (child->path.type != DEVICE_PATH_I2C) From 9836b37793937d710a66a9f9e49fdb5b8f7a55de Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 14 Oct 2021 21:12:30 +0200 Subject: [PATCH 140/320] soc/amd/stoneyridge/include/iomap: drop I2C_BUS_ADDRESS(x) macro The I2C_BUS_ADDRESS(x) macro isn't used to iterate over the I2C controller base addresses, so drop this and use the fixed MMIO address for the I2C[ABCD]_BASE_ADDRESS defines instead which also allows using those defines in the ACPI code. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held Change-Id: Idd7484a0322dc5167cbb7fdcd9a2583f0dbed50e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58336 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/stoneyridge/include/soc/iomap.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index c8cee23fa1a..3d01938144e 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -11,13 +11,10 @@ #define ALINK_AHB_ADDRESS 0xfedc0000 /* I2C fixed address */ -#define I2C_BASE_ADDRESS 0xfedc2000 -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) -#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) -#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) -#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) -#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) +#define I2CA_BASE_ADDRESS 0xfedc2000 +#define I2CB_BASE_ADDRESS 0xfedc3000 +#define I2CC_BASE_ADDRESS 0xfedc4000 +#define I2CD_BASE_ADDRESS 0xfedc5000 #if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 From 640ec2581b1cdbb9dca385b49a32d2bdb1d4d9c5 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 14 Oct 2021 21:15:51 +0200 Subject: [PATCH 141/320] soc/amd/stoneyridge/acpi/sb_fch: use I2C[ABCD]_BASE_ADDRESS defines Now that the I2C[ABCD]_BASE_ADDRESS defines aren't macros that calculate the MMIO addresses any more, those defines can also be used in the ACPI code. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held Change-Id: I7de2f83dc2f8061d8f1735caf10314bcddb2d3fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/58337 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/stoneyridge/acpi/sb_fch.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index bbb5235233f..b389c66aeb6 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -74,7 +74,7 @@ Device (I2CA) { Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 3 } - Memory32Fixed (ReadWrite, 0xFEDC2000, 0x1000) + Memory32Fixed (ReadWrite, I2CA_BASE_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) @@ -90,7 +90,7 @@ Device (I2CB) Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, 0xFEDC3000, 0x1000) + Memory32Fixed (ReadWrite, I2CB_BASE_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { @@ -104,7 +104,7 @@ Device (I2CC) { Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed (ReadWrite, 0xFEDC4000, 0x1000) + Memory32Fixed (ReadWrite, I2CC_BASE_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) @@ -119,7 +119,7 @@ Device (I2CD) Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + Memory32Fixed(ReadWrite, I2CD_BASE_ADDRESS, 0x1000) }) Method (_STA, 0x0, NotSerialized) { From f38fbbec2c0061d122466cec346c2634aa26e236 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 14 Oct 2021 21:35:55 +0200 Subject: [PATCH 142/320] soc/amd/common/include/espi: rename configure_espi Rename configure_espi to configure_espi_with_mb_hook to clarify that this function will call into the mb_set_up_early_espi function in the mainboard-specific code if it exists. Signed-off-by: Felix Held Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58338 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/early_fch.c | 2 +- src/soc/amd/common/block/include/amdblocks/espi.h | 2 +- src/soc/amd/picasso/early_fch.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 69458b6220d..f97f57c8462 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -41,7 +41,7 @@ void fch_pre_init(void) /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); /* Setup eSPI to enable port80 routing. */ - configure_espi(); + configure_espi_with_mb_hook(); fch_spi_early_init(); fch_smbus_init(); fch_enable_cf9_io(); diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 7e49ea0f2e5..0f8066b2a67 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -132,7 +132,7 @@ int espi_setup(void); void mb_set_up_early_espi(void); /* Setup eSPI with any mainboard specific initialization. */ -static inline void configure_espi(void) +static inline void configure_espi_with_mb_hook(void) { /* If eSPI is setup in PSP Verstage, continue with that. Else setup eSPI to perform port80h routing as early as possible. */ diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 8771e387bc7..83b4ae4579a 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -48,7 +48,7 @@ void fch_pre_init(void) /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); /* Setup eSPI to enable port80 routing. */ - configure_espi(); + configure_espi_with_mb_hook(); if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) lpc_configure_decodes(); From 4e379a237466f4c96546a758ae86f17c7d26eed6 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 14 Oct 2021 21:43:11 +0200 Subject: [PATCH 143/320] soc/amd: make configure_espi_with_mb_hook call conditional If a system doesn't use eSPI or has the eSPI interface already configured in verstage on PSP, not calling configure_espi_with_mb_hook from fch_pre_init makes it a bit more obvious that the eSPI interface initialization will be skipped. Signed-off-by: Felix Held Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58339 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/early_fch.c | 8 ++++++-- src/soc/amd/common/block/include/amdblocks/espi.h | 8 ++------ src/soc/amd/picasso/early_fch.c | 7 +++++-- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index f97f57c8462..f06d5767e96 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -40,8 +40,12 @@ void fch_pre_init(void) enable_acpimmio_decode_pm04(); /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); - /* Setup eSPI to enable port80 routing. */ - configure_espi_with_mb_hook(); + + /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI + interface hasn't already been set up in verstage on PSP */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + configure_espi_with_mb_hook(); + fch_spi_early_init(); fch_smbus_init(); fch_enable_cf9_io(); diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 0f8066b2a67..e12b1b84865 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -134,12 +134,8 @@ void mb_set_up_early_espi(void); /* Setup eSPI with any mainboard specific initialization. */ static inline void configure_espi_with_mb_hook(void) { - /* If eSPI is setup in PSP Verstage, continue with that. Else setup eSPI to perform - port80h routing as early as possible. */ - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { - mb_set_up_early_espi(); - espi_setup(); - } + mb_set_up_early_espi(); + espi_setup(); } #endif /* AMD_BLOCK_ESPI_H */ diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 83b4ae4579a..2a1b5c971ac 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -47,8 +47,11 @@ void fch_pre_init(void) enable_acpimmio_decode_pm04(); /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ lpc_early_init(); - /* Setup eSPI to enable port80 routing. */ - configure_espi_with_mb_hook(); + + /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI + interface hasn't already been set up in verstage on PSP */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + configure_espi_with_mb_hook(); if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) lpc_configure_decodes(); From 1c03da5f5af11c4ba1e8e1280be32ceb06af045a Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 14 Oct 2021 21:48:13 +0200 Subject: [PATCH 144/320] soc/amd/common: move configure_espi_with_mb_hook implementation Move the actual implementation of configure_espi_with_mb_hook out of the header file and into the espi_util.c file. Signed-off-by: Felix Held Change-Id: I1106e69a52bf329a41e8e12fd09db846310b102a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58340 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/include/amdblocks/espi.h | 6 +----- src/soc/amd/common/block/lpc/espi_util.c | 7 +++++++ 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index e12b1b84865..f9e25707d09 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -132,10 +132,6 @@ int espi_setup(void); void mb_set_up_early_espi(void); /* Setup eSPI with any mainboard specific initialization. */ -static inline void configure_espi_with_mb_hook(void) -{ - mb_set_up_early_espi(); - espi_setup(); -} +void configure_espi_with_mb_hook(void); #endif /* AMD_BLOCK_ESPI_H */ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index ebc8f459798..4eb700be198 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -1053,3 +1053,10 @@ int espi_setup(void) return 0; } + +/* Setup eSPI with any mainboard specific initialization. */ +void configure_espi_with_mb_hook(void) +{ + mb_set_up_early_espi(); + espi_setup(); +} From 718a3cba252b39068d8bccd988d602065ad4ca65 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 12 Oct 2021 21:39:47 +0200 Subject: [PATCH 145/320] mb/google/guybrush/bootblock: drop redundant clearing of LPC decodes The writes were originally added due to being part of the initialization sequence in the reference code, but coreboot already has those registers cleared by the time we reach this part of the code, so we can drop these redundant writes. Signed-off-by: Felix Held Change-Id: I43344460e5355664841d77daf1df3fd386e047e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58341 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/google/guybrush/bootblock.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 040bc52441e..4a0d3846606 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -39,8 +39,11 @@ void bootblock_mainboard_early_init(void) dword |= LPC_LDRQ0_PD_EN; pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); - pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); - pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0); + /* + * All LPC decodes need to be cleared before we can configure the LPC pads as secondary + * eSPI interface that gets used for the EC communication. This is already done by + * lpc_disable_decodes that gets called before this function. + */ if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) return; From a30ad9faf9ea15fa84eaf4f72d38a1952828ef85 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 14 Oct 2021 21:58:03 +0200 Subject: [PATCH 146/320] mb/google/guybrush/bootblock: add comment about LPC_LDRQ0_PU,PD_EN The definition of those bits changed between Picasso and Renoir/Cezanne so add a comment where those bit definitions are used as well. Signed-off-by: Felix Held Change-Id: If1cf4b06fc35f94cbd482f2869fcc64739e7d272 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58345 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/google/guybrush/bootblock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 4a0d3846606..83ac43ac417 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -34,6 +34,8 @@ void bootblock_mainboard_early_init(void) size_t base_num_gpios, override_num_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios; + /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped + on Picasso and older compared to Renoir/Cezanne and newer */ dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); dword |= LPC_LDRQ0_PD_EN; From 4afdd693fa0ea2bf49ce37eccca74796499004e6 Mon Sep 17 00:00:00 2001 From: "Kevin.Chang" Date: Wed, 13 Oct 2021 17:36:39 +0800 Subject: [PATCH 147/320] mb/google/brya/var/taeko: Include driver for GL9763E for eMMC boot disk Support GL9763E as a eMMC boot disk BRANCH=none BUG=b:202192686 TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taeko. Cq-Depend: chromium:3153210 Signed-off-by: Kevin.Chang Change-Id: I5db2b229ce1bbea54efe15f5288f13f8d4656899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58297 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: YH Lin --- src/mainboard/google/brya/Kconfig.name | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 7d9500221ba..b7f73e1f8f1 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -52,6 +52,7 @@ config BOARD_GOOGLE_KANO config BOARD_GOOGLE_TAEKO bool "-> Taeko" select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9763E config BOARD_GOOGLE_FELWINTER bool "-> Felwinter" From e9fcc976971fc5805dd27e4b0568b8ec9fc057a1 Mon Sep 17 00:00:00 2001 From: Ariel Fang Date: Thu, 14 Oct 2021 14:25:42 +0800 Subject: [PATCH 148/320] mb/google/brya/variants/primus: To fine tune WWAN power sequencing Follow the spec to correct the WWAN poweron and powerdown sequences. BUG=b:195625346 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel Fang Change-Id: I232d283a9d6093f5da64fcdce44e5cb640e3df0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58319 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/Kconfig.name | 1 + .../google/brya/variants/primus/Makefile.inc | 2 +- .../google/brya/variants/primus/gpio.c | 21 +++++++++++++++++-- .../variants/primus/include/variant/gpio.h | 5 +++++ 4 files changed, 26 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index b7f73e1f8f1..7f24adb83f7 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -20,6 +20,7 @@ config BOARD_GOOGLE_PRIMUS select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9755 select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_GIMBLE bool "-> Gimble" diff --git a/src/mainboard/google/brya/variants/primus/Makefile.inc b/src/mainboard/google/brya/variants/primus/Makefile.inc index 716c7ad5df6..129a2938e3e 100644 --- a/src/mainboard/google/brya/variants/primus/Makefile.inc +++ b/src/mainboard/google/brya/variants/primus/Makefile.inc @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c - +romstage-y += gpio.c ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index 714494923fa..ba423fc73cd 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -77,6 +77,8 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ @@ -98,14 +100,16 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D11, 1, DEEP), /* D18 : UART1_TXD ==> SD_PE_RST_L */ PAD_CFG_GPO(GPP_D18, 0, PLTRST), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage)*/ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L */ + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage)*/ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ @@ -121,6 +125,13 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_B4, 1, DEEP), }; +static const struct pad_config romstage_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -132,3 +143,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/primus/include/variant/gpio.h b/src/mainboard/google/brya/variants/primus/include/variant/gpio.h index c4fe342621e..cbf60402653 100644 --- a/src/mainboard/google/brya/variants/primus/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/primus/include/variant/gpio.h @@ -4,5 +4,10 @@ #define VARIANT_GPIO_H #include +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 #endif From ef6a65f02ace77e944ef0405d9fb8a312a78e376 Mon Sep 17 00:00:00 2001 From: Joey Peng Date: Thu, 14 Oct 2021 11:10:02 +0800 Subject: [PATCH 149/320] mb/google/brya/var/taeko: Add fw_config probe for GL9750 and RTS5232S Add support for SD card reader GL9750 and RTS5232S BUG=b:203014989 TEST=FW_NAME=taeko emerge-brya coreboot Signed-off-by: Joey Peng Change-Id: I4353a094e2035ce94b5dd1a737e7e7009ad0614e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/taeko/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 70db169746d..9c5a19c4cf5 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -6,6 +6,8 @@ fw_config field DB_SD 2 3 option DB_SD_ABSENT 0 option DB_SD_OZ711LV2LN 1 + option DB_SD_GL9750 2 + option DB_SD_RTS5232S 3 end field KB_BL 4 option KB_BL_ABSENT 0 @@ -193,6 +195,8 @@ chip soc/intel/alderlake register "srcclk_pin" = "3" device generic 0 on probe DB_SD DB_SD_OZ711LV2LN + probe DB_SD DB_SD_GL9750 + probe DB_SD DB_SD_RTS5232S end end end From d4d4f08f54350bec12a6ff7680709e9c50d4cb19 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 14 Oct 2021 11:19:10 +0200 Subject: [PATCH 150/320] Doc/releases/coreboot-4.11-relnotes.md: Fix typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace `bee` with `been`. Change-Id: I206f9b33d79386fc4f204db3e21a92fa20b703bd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58321 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Georgi Reviewed-by: Felix Held --- Documentation/releases/coreboot-4.11-relnotes.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index f26de27104f..789c19d507c 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -136,7 +136,7 @@ removed soon after release. ### `TSEG` and `cbmem_top()` mapping -Significant refactoring has bee done to achieve some consistency across platforms +Significant refactoring has been done to achieve some consistency across platforms and to reduce code duplication. ### Build system amenities ### From 5c259642c2d59c551fb0e54a14d9eeeb878d1177 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 25 Sep 2021 00:40:52 +0200 Subject: [PATCH 151/320] soc/intel/{common,skl}: set ACPI_FADT_PLATFORM_CLOCK based on Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FADT contains a flag `ACPI_FADT_PLATFORM_CLOCK` telling the OSPM if a specification-compliant PM Timer is present. Currently, this flag is set regardless of the timer being enabled or disabled. To be specification-compliant, only set that flag, when the hardware PM Timer is enabled. This changes behaviour of all mainboards defaulting to USE_PM_ACPI_TIMER=n. Note: On platforms supporting uCode PM ACPI Timer emulation, this is required, too, because emulation does not support `TMR_STS`. Any OS or software checking this flag and thus relying on the overflow flag would not work (properly). Change-Id: Id2e5d69b5515c21e6ce922dab2cb88b494c65ebe Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57934 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/common/block/acpi/acpi.c | 6 ++++-- src/soc/intel/skylake/fadt.c | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index cff2e219fd7..c21a8613903 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -149,8 +149,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; + ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE; + + if (CONFIG(USE_PM_ACPI_TIMER) || !CONFIG(PM_ACPI_TIMER_OPTIONAL)) + fadt->flags |= ACPI_FADT_PLATFORM_CLOCK; fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index 774974a76cc..61e9417abd1 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -42,8 +42,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; + ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE; + + if (CONFIG(USE_PM_ACPI_TIMER)) + fadt->flags |= ACPI_FADT_PLATFORM_CLOCK; if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; From c47fc4002261e241890c098335eaaf4cb51c844a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 25 Sep 2021 00:10:30 +0200 Subject: [PATCH 152/320] soc/intel/pmc: add a note about legacy OSes/payloads to PM Timer Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since ACPI 5.0A it is allowed to disable the ACPI Timer, when the according FADT flag `ACPI_FADT_PLATFORM_CLOCK` is unset. Starting with Skylake, most platforms (except Xeon-SP) support PM Timer emulation, so even legacy OSes and payloads should work fine with the hardware PM Timer disabled. However, when the `TMR_STS` functionality is required, some legacy OSes might still not work (properly). Add a note about this to the Kconfig help. Change-Id: I53f1814113902124779ed85da030374439570688 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58018 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Lance Zhao --- src/soc/intel/common/block/pmc/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index e3978e29dd5..5e5e8d61841 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -76,4 +76,11 @@ config USE_PM_ACPI_TIMER Disabling this option also stops the hardware TCO timer and makes the TCO watchdog unavailable. + Note: On platforms without uCode PM Timer emulation, legacy OSes + or payloads with ACPI version < 5.0A might not work without + PM ACPI timer. + + (Legacy) software requiring `TMR_STS` (for timer overflow + interrupts) will not work with this option disabled. + endif # PM_ACPI_TIMER_OPTIONAL From 9c19bf090e8a1bd69c7fd52188adaa956d65c9a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 26 Sep 2021 14:23:12 +0200 Subject: [PATCH 153/320] soc/intel/dnv_ns: enable uCode PM Timer emulation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Denverton-NS supports uCode PM Timer emulation, according to Intel doc#558579 rev2.2. Thus, enable it. Change-Id: I21f55816da9f5e240fdf01a0e92b67b09ef38599 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57944 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/denverton_ns/Kconfig | 1 + src/soc/intel/denverton_ns/cpu.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index c657285a252..a578a71fd0b 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES + select CPU_SUPPORTS_PM_TIMER_EMULATION select DEBUG_GPIO select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 95f164d1c54..60635483d49 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -94,6 +94,8 @@ static void denverton_core_init(struct device *cpu) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); + + enable_pm_timer_emulation(); } static struct device_operations cpu_dev_ops = { From d1da9570da7a725611dd4227e4297d0bb2ef2d21 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 15 Oct 2021 16:29:22 +0200 Subject: [PATCH 154/320] soc/amd/stoneyridge/include/iomap: rename I2C[ABCD]_BASE_ADDRESS defines Picasso and Cezanne define and use APU_I2C[01234]_BASE for the base addresses of the I2C controllers, so align Stoneyridge with this. The ACPI device names aren't changed from I2C[ABCD] to I2C[0123] for now since this might change behavior in the OS and would also change the resulting binary of a timeless build. TEST=Timeless build results in identical image for Google/Treeya. Signed-off-by: Felix Held Change-Id: I9c400c073eba5c14bd35703b717f75df89a8719d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58370 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/variants/treeya/audio.c | 2 +- src/soc/amd/stoneyridge/acpi/sb_fch.asl | 8 ++++---- src/soc/amd/stoneyridge/chip.c | 8 ++++---- src/soc/amd/stoneyridge/i2c.c | 8 ++++---- src/soc/amd/stoneyridge/include/soc/iomap.h | 8 ++++---- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/kahlee/variants/treeya/audio.c b/src/mainboard/google/kahlee/variants/treeya/audio.c index 1c7a4c483bb..ac7f7a27294 100644 --- a/src/mainboard/google/kahlee/variants/treeya/audio.c +++ b/src/mainboard/google/kahlee/variants/treeya/audio.c @@ -23,7 +23,7 @@ void variant_devtree_update(void) printk(BIOS_INFO, "Checking audio codec\n"); return; } - } while (mmio_dev->path.mmio.addr != I2CA_BASE_ADDRESS); + } while (mmio_dev->path.mmio.addr != APU_I2C0_BASE); while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { if (child->path.type != DEVICE_PATH_I2C) diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index b389c66aeb6..212a111f410 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -74,7 +74,7 @@ Device (I2CA) { Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 3 } - Memory32Fixed (ReadWrite, I2CA_BASE_ADDRESS, 0x1000) + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) @@ -90,7 +90,7 @@ Device (I2CB) Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, I2CB_BASE_ADDRESS, 0x1000) + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { @@ -104,7 +104,7 @@ Device (I2CC) { Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed (ReadWrite, I2CC_BASE_ADDRESS, 0x1000) + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) @@ -119,7 +119,7 @@ Device (I2CD) Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, I2CD_BASE_ADDRESS, 0x1000) + Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index fbf205ece08..5cc52b69269 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -101,10 +101,10 @@ static struct device_operations pci_domain_ops = { static void set_mmio_dev_ops(struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - case I2CB_BASE_ADDRESS: - case I2CC_BASE_ADDRESS: - case I2CD_BASE_ADDRESS: + case APU_I2C0_BASE: + case APU_I2C1_BASE: + case APU_I2C2_BASE: + case APU_I2C3_BASE: dev->ops = &soc_amd_i2c_mmio_ops; break; } diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index a0987755370..6a6d7760fcc 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -7,10 +7,10 @@ #include "chip.h" static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = { - { I2C_MASTER_MODE, I2CA_BASE_ADDRESS, "I2CA" }, - { I2C_MASTER_MODE, I2CB_BASE_ADDRESS, "I2CB" }, - { I2C_MASTER_MODE, I2CC_BASE_ADDRESS, "I2CC" }, - { I2C_MASTER_MODE, I2CD_BASE_ADDRESS, "I2CD" }, + { I2C_MASTER_MODE, APU_I2C0_BASE, "I2CA" }, + { I2C_MASTER_MODE, APU_I2C1_BASE, "I2CB" }, + { I2C_MASTER_MODE, APU_I2C2_BASE, "I2CC" }, + { I2C_MASTER_MODE, APU_I2C3_BASE, "I2CD" }, }; const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 3d01938144e..93e218df978 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -11,10 +11,10 @@ #define ALINK_AHB_ADDRESS 0xfedc0000 /* I2C fixed address */ -#define I2CA_BASE_ADDRESS 0xfedc2000 -#define I2CB_BASE_ADDRESS 0xfedc3000 -#define I2CC_BASE_ADDRESS 0xfedc4000 -#define I2CD_BASE_ADDRESS 0xfedc5000 +#define APU_I2C0_BASE 0xfedc2000 +#define APU_I2C1_BASE 0xfedc3000 +#define APU_I2C2_BASE 0xfedc4000 +#define APU_I2C3_BASE 0xfedc5000 #if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 From c78c46d433eb6103c943dc8f7db9fa970643acce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 20 Jun 2021 15:44:32 +0300 Subject: [PATCH 155/320] cpu/x86/lapic: Only deliver ExtINT to BSP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ExtINT is related to external PIC mode i8259 interrupts, they should be delivered to one CPU (BSP) only. Change-Id: I78490d2cbe3d9f52e10ef2471508263fd6c146ba Signed-off-by: Felix Held Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/42434 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/cpu/x86/lapic/lapic.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 58e45248aba..b4d3c4de429 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -5,6 +5,7 @@ #include #include #include +#include #include void enable_lapic(void) @@ -55,7 +56,11 @@ static void lapic_virtual_wire_mode_init(void) uint32_t mask = LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_INPUT_POLARITY | LAPIC_DELIVERY_MODE_MASK; - lapic_update32(LAPIC_LVT0, ~mask, LAPIC_DELIVERY_MODE_EXTINT); + if (boot_cpu()) + lapic_update32(LAPIC_LVT0, ~mask, LAPIC_DELIVERY_MODE_EXTINT); + else + lapic_update32(LAPIC_LVT0, ~mask, LAPIC_LVT_MASKED | + LAPIC_DELIVERY_MODE_EXTINT); lapic_update32(LAPIC_LVT1, ~mask, LAPIC_DELIVERY_MODE_NMI); } From 37a977dde945de15464925d4501d4b85e01c3a16 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 15 Oct 2021 11:46:11 +0200 Subject: [PATCH 156/320] Skylake boards: Drop setting useless `IRQ_SLOT_COUNT` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The `IRQ_SLOT_COUNT` value is only meaningful when generating a PIRQ table. None of these boards do it, so specifying this value achieves absolutely nothing. Drop it to prevent further useless copy-pasting. Change-Id: I2d63b850c03fc1471c0eef180e8b621311b2c336 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58362 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner --- src/mainboard/asrock/h110m/Kconfig | 4 ---- src/mainboard/facebook/monolith/Kconfig | 4 ---- src/mainboard/google/eve/Kconfig | 4 ---- src/mainboard/google/glados/Kconfig | 4 ---- src/mainboard/intel/kblrvp/Kconfig | 4 ---- src/mainboard/intel/kunimitsu/Kconfig | 4 ---- src/mainboard/intel/saddlebrook/Kconfig | 4 ---- src/mainboard/libretrend/lt1000/Kconfig | 4 ---- src/mainboard/protectli/vault_kbl/Kconfig | 4 ---- src/mainboard/purism/librem_skl/Kconfig | 4 ---- src/mainboard/razer/blade_stealth_kbl/Kconfig | 4 ---- src/mainboard/supermicro/x11-lga1151-series/Kconfig | 4 ---- 12 files changed, 48 deletions(-) diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index aeb89298af9..3a55f9e1f3b 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -17,10 +17,6 @@ config BOARD_SPECIFIC_OPTIONS select RT8168_SET_LED_MODE select MAINBOARD_HAS_LPC_TPM -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_DIR default "asrock/h110m" diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 212ca828c83..50738f49d90 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -16,10 +16,6 @@ config BOARD_SPECIFIC_OPTIONS config CBFS_SIZE default 0x00900000 -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_DIR default "facebook/monolith" diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index ce9b4a4df2e..007cbc7287b 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -46,10 +46,6 @@ config TPM_TIS_ACPI_INTERRUPT int default 64 # GPE0_DW2_00 (GPP_E0) -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_DIR default "google/eve" diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index cd553fffd66..4b0275f641e 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -29,10 +29,6 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_DIR default "google/glados" diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index e7ecfdfcb27..51f46ba1dfe 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -20,10 +20,6 @@ config BOARD_SPECIFIC_OPTIONS config VBOOT select VBOOT_LID_SWITCH -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_DIR default "intel/kblrvp" diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 29c821e715f..85f9e54d82f 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -25,10 +25,6 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_DIR default "intel/kunimitsu" diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index de651f8774c..decbb9688a8 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -16,10 +16,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_DIR default "intel/saddlebrook" diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig index fd6e5203ff6..2726a2ca935 100644 --- a/src/mainboard/libretrend/lt1000/Kconfig +++ b/src/mainboard/libretrend/lt1000/Kconfig @@ -12,10 +12,6 @@ config BOARD_SPECIFIC_OPTIONS select SPD_READ_BY_WORD select SUPERIO_ITE_IT8786E -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_PART_NUMBER default "LT1000" diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 5f76b8d0ba7..3ad5ce65f70 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -15,10 +15,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_INTEL_PTT select MAINBOARD_HAS_TPM2 -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_DIR default "protectli/vault_kbl" diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 9d2688f92e8..4c6f6a8ade2 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -18,10 +18,6 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL if BOARD_PURISM_BASEBOARD_LIBREM_SKL -config IRQ_SLOT_COUNT - int - default 18 - config VARIANT_DIR default "librem13" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 default "librem15" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig index 40671c098e9..b9ca09323e5 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -25,10 +25,6 @@ config VGA_BIOS_ID string default "8086,5916" -config IRQ_SLOT_COUNT - int - default 18 - config MAINBOARD_FAMILY string default "BLADE_STEALTH" diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 519b6ee3f63..eb4a65e7507 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -66,10 +66,6 @@ config DRIVERS_IPMI_SUPERMICRO_OEM config CBFS_SIZE default 0xb00000 -config IRQ_SLOT_COUNT - int - default 18 - config CONSOLE_POST bool default y From 0c12bdc9f886c17a7b9560a9287344a68b1ccb24 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 16 Oct 2021 10:52:05 +0200 Subject: [PATCH 157/320] Documentation: Improve preamble of coding style The coding style doc isn't short, so scrap that, and it's specific to the C parts of our tree, so add that. Change-Id: Ib1ef7c1a96ff40f0cfbae7d22a47a95128981eb8 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/58381 Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- Documentation/contributing/coding_style.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md index 4980659cc0c..e3c92af842d 100644 --- a/Documentation/contributing/coding_style.md +++ b/Documentation/contributing/coding_style.md @@ -1,6 +1,6 @@ # Coding Style -This is a short document describing the preferred coding style for the +This document describes the preferred C coding style for the coreboot project. It is in many ways exactly the same as the Linux kernel coding style. In fact, most of this document has been copied from the [Linux kernel coding style](http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/plain/Documentation/CodingStyle?id=HEAD) From 5bb6f9b7946abb81f495d1f1ead8429553b7c73b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 14 Oct 2021 22:05:45 +0200 Subject: [PATCH 158/320] drivers/emulation/qemu: Add missing include for MMIO Change-Id: Ie3c820e2e20f8f71908319e89e49e5d66f58adc9 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/58347 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/emulation/qemu/bochs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 73fa19e2ca5..d3b9007abe0 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include From 7b34e319f2a796446eba6c84fbe970507cc3a1c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 26 Sep 2021 22:04:11 +0200 Subject: [PATCH 159/320] soc/intel/common: add SGX fields to GNVS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the SGX fields to the GNVS. This is required for Skylake to use the common GNVS. Change-Id: I0077260b7eb1bc2b2fe2af69ac039b38ca0e7423 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57947 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/soc/intel/common/block/acpi/acpi/globalnvs.asl | 3 +++ src/soc/intel/common/block/include/intelblocks/nvs.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index ab63a5c407d..003a5ce3df9 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -25,4 +25,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource , 64, // 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code) + EPCS, 8, // 0x48 - SGX enabled status + EMNA, 64, // 0x49 - 0x50 EPC base address + ELNG, 64, // 0x51 - 0x58 EPC length } diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 5adbdb85500..3ebb08b519f 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -27,6 +27,10 @@ struct __packed global_nvs { u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */ u64 hest_log_addr; /* 0x40 - 47 err log addr (used in SMM, not ASL code) */ + /* SGX */ + u8 epcs; /* 0x48 - SGX enabled status */ + u64 emna; /* 0x49 - 0x50 EPC base address */ + u64 elng; /* 0x51 - 0x58 EPC length */ }; #endif From fbcfb63b06ad5cafc97ce76f8640e5c39b41736d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 26 Sep 2021 18:41:24 +0200 Subject: [PATCH 160/320] soc/intel/skylake: switch to common GNVS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch to common GNVS. No additional fields to those being present in common GNVS are used by any SKL/KBL device. Thus, they're dropped completely. Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Frans Hendriks --- src/mainboard/51nb/x210/dsdt.asl | 2 +- src/mainboard/asrock/h110m/dsdt.asl | 2 +- src/mainboard/clevo/kbl-u/dsdt.asl | 2 +- src/mainboard/facebook/monolith/dsdt.asl | 2 +- src/mainboard/google/eve/dsdt.asl | 2 +- src/mainboard/google/fizz/dsdt.asl | 2 +- src/mainboard/google/glados/dsdt.asl | 2 +- src/mainboard/google/poppy/dsdt.asl | 2 +- src/mainboard/hp/280_g2/dsdt.asl | 2 +- src/mainboard/intel/kblrvp/dsdt.asl | 2 +- src/mainboard/intel/kunimitsu/dsdt.asl | 2 +- src/mainboard/intel/saddlebrook/dsdt.asl | 2 +- src/mainboard/kontron/bsl6/dsdt.asl | 2 +- src/mainboard/libretrend/lt1000/dsdt.asl | 2 +- src/mainboard/protectli/vault_kbl/dsdt.asl | 2 +- src/mainboard/purism/librem_skl/dsdt.asl | 2 +- .../razer/blade_stealth_kbl/dsdt.asl | 2 +- .../supermicro/x11-lga1151-series/dsdt.asl | 2 +- src/soc/intel/skylake/acpi/globalnvs.asl | 47 ------------------- src/soc/intel/skylake/include/soc/nvs.h | 45 +----------------- 20 files changed, 19 insertions(+), 109 deletions(-) delete mode 100644 src/soc/intel/skylake/acpi/globalnvs.asl diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl index 398611f6a45..b4d7741431c 100644 --- a/src/mainboard/51nb/x210/dsdt.asl +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( { #include #include - #include + #include #include Device (\_SB.PCI0) diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl index 22571573f85..517f759b524 100644 --- a/src/mainboard/asrock/h110m/dsdt.asl +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -14,7 +14,7 @@ DefinitionBlock( #include // global NVS and variables - #include + #include // CPU #include diff --git a/src/mainboard/clevo/kbl-u/dsdt.asl b/src/mainboard/clevo/kbl-u/dsdt.asl index 1440ebe71cc..21d18c6363e 100644 --- a/src/mainboard/clevo/kbl-u/dsdt.asl +++ b/src/mainboard/clevo/kbl-u/dsdt.asl @@ -11,7 +11,7 @@ DefinitionBlock( ) { #include - #include + #include #include Device (\_SB.PCI0) { diff --git a/src/mainboard/facebook/monolith/dsdt.asl b/src/mainboard/facebook/monolith/dsdt.asl index 79de6224008..225acfaee1c 100644 --- a/src/mainboard/facebook/monolith/dsdt.asl +++ b/src/mainboard/facebook/monolith/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( #include #include #include - #include + #include #include Scope (\_SB) { diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 2b0dd85a889..357f3bfe6f7 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include /* global NVS and variables */ - #include + #include /* CPU */ #include diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 9800126ed1c..01e94f2f779 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include /* global NVS and variables */ - #include + #include /* CPU */ #include diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 039c406cc74..e25c4319a12 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( #include #include #include - #include + #include #include Scope (\_SB) { diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index cf4692e416e..dbba8064e07 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include /* global NVS and variables */ - #include + #include /* CPU */ #include diff --git a/src/mainboard/hp/280_g2/dsdt.asl b/src/mainboard/hp/280_g2/dsdt.asl index 26ebbe071f1..184fee0d3ae 100644 --- a/src/mainboard/hp/280_g2/dsdt.asl +++ b/src/mainboard/hp/280_g2/dsdt.asl @@ -15,7 +15,7 @@ DefinitionBlock( #include #include - #include + #include Device (\_SB.PCI0) { #include diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 3afa5836bd5..5af8829ff39 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( #include #include #include - #include + #include #include Scope (\_SB) { diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index 490b50ae77f..2ae3dca2d2c 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( #include #include #include - #include + #include #include Scope (\_SB) { diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index e2291da3f9c..1ec9ab022da 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( #include #include #include - #include + #include #include Device (\_SB.PCI0) diff --git a/src/mainboard/kontron/bsl6/dsdt.asl b/src/mainboard/kontron/bsl6/dsdt.asl index ee425e874d6..916e3713f0f 100644 --- a/src/mainboard/kontron/bsl6/dsdt.asl +++ b/src/mainboard/kontron/bsl6/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( #include #include #include - #include + #include Device (\_SB.PCI0) { #include diff --git a/src/mainboard/libretrend/lt1000/dsdt.asl b/src/mainboard/libretrend/lt1000/dsdt.asl index 890b969a907..9f02d56fc62 100644 --- a/src/mainboard/libretrend/lt1000/dsdt.asl +++ b/src/mainboard/libretrend/lt1000/dsdt.asl @@ -12,7 +12,7 @@ DefinitionBlock( { #include #include - #include + #include #include Device (\_SB.PCI0) diff --git a/src/mainboard/protectli/vault_kbl/dsdt.asl b/src/mainboard/protectli/vault_kbl/dsdt.asl index 890b969a907..9f02d56fc62 100644 --- a/src/mainboard/protectli/vault_kbl/dsdt.asl +++ b/src/mainboard/protectli/vault_kbl/dsdt.asl @@ -12,7 +12,7 @@ DefinitionBlock( { #include #include - #include + #include #include Device (\_SB.PCI0) diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index 43c8e7f26b0..ee71d1ab410 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -13,7 +13,7 @@ DefinitionBlock( #include #include #include - #include + #include #include Device (\_SB.PCI0) diff --git a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl index 5fd35695461..e3045776564 100644 --- a/src/mainboard/razer/blade_stealth_kbl/dsdt.asl +++ b/src/mainboard/razer/blade_stealth_kbl/dsdt.asl @@ -14,7 +14,7 @@ DefinitionBlock( #include #include #include - #include + #include #include Device (\_SB.PCI0) diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl index ad20f909c5e..20b4aefc96a 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl +++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl @@ -14,7 +14,7 @@ DefinitionBlock( #include // global NVS and variables - #include + #include // CPU #include diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl deleted file mode 100644 index 3623656ea50..00000000000 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Global Variables */ - -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - , 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - , 8, // 0x03 - SMI function parameter - , 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - , 8, // 0x06 - SCI function parameter - , 8, // 0x07 - SCI function parameter - , 8, // 0x08 - Global Lock function for EC - , 8, // 0x09 - Lock function parameter - , 8, // 0x0a - Lock function parameter - , 8, // 0x0b - Processor Count - PPCM, 8, // 0x0c - Max PPC State - TMPS, 8, // 0x0d - Temperature Sensor ID - TLVL, 8, // 0x0e - Throttle Level Limit - FLVL, 8, // 0x0f - Current FAN Level - TCRT, 8, // 0x10 - Critical Threshold - TPSV, 8, // 0x11 - Passive Threshold - TMAX, 8, // 0x12 - CPU Tj_max - S5U0, 8, // 0x13 - Enable USB in S5 - S3U0, 8, // 0x14 - Enable USB in S3 - S33G, 8, // 0x15 - Enable 3G in S3 - LIDS, 8, // 0x16 - LID State - , 8, // 0x17 - AC Power State - , 32, // 0x18 - 0x1b - CBMEM TOC - CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console - PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit - GPEI, 64, // 0x28 - 0x2f - GPE wake status bit - DPTE, 8, // 0x30 - Enable DPTF - NHLA, 64, // 0x31 - NHLT Address - NHLL, 32, // 0x39 - NHLT Length - , 16, // 0x3d - Wifi Country Identifier - U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap - U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap - UIOR, 8, // 0x42 - UART debug controller init on S3 resume - EPCS, 8, // 0x43 - SGX Enabled status - EMNA, 64, // 0x44 - 0x4B EPC base address - ELNG, 64, // 0x4C - 0x53 EPC Length - A4GB, 64, // 0x54 - 0x5B Base of above 4GB MMIO Resource - A4GS, 64, // 0x5C - 0x63 Length of above 4GB MMIO Resource -} diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 6d5e17256c8..512945898e2 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -3,49 +3,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include - -struct __packed global_nvs { - /* Miscellaneous */ - u16 unused_was_osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 unused_was_prm0; /* 0x03 - SMI function call parameter */ - u8 unused_was_prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 unused_was_prm2; /* 0x06 - SCI function call parameter */ - u8 unused_was_prm3; /* 0x07 - SCI function call parameter */ - u8 unused_was_lckf; /* 0x08 - Global Lock function for EC */ - u8 unused_was_prm4; /* 0x09 - Lock function parameter */ - u8 unused_was_prm5; /* 0x0a - Lock function parameter */ - u8 unused_was_pcnt; /* 0x0b - Processor Count */ - u8 ppcm; /* 0x0c - Max PPC State */ - u8 tmps; /* 0x0d - Temperature Sensor ID */ - u8 tlvl; /* 0x0e - Throttle Level Limit */ - u8 flvl; /* 0x0f - Current FAN Level */ - u8 tcrt; /* 0x10 - Critical Threshold */ - u8 tpsv; /* 0x11 - Passive Threshold */ - u8 tmax; /* 0x12 - CPU Tj_max */ - u8 s5u0; /* 0x13 - Enable USB in S5 */ - u8 s3u0; /* 0x14 - Enable USB in S3 */ - u8 s33g; /* 0x15 - Enable 3G in S3 */ - u8 lids; /* 0x16 - LID State */ - u8 unused_was_pwrs; /* 0x17 - AC Power State */ - u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ - u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ - u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ - u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ - u8 dpte; /* 0x30 - Enable DPTF */ - u64 nhla; /* 0x31 - NHLT Address */ - u32 nhll; /* 0x39 - NHLT Length */ - u16 unused_was_cid1; /* 0x3d - Wifi Country Identifier */ - u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */ - u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */ - u8 uior; /* 0x42 - UART debug controller init on S3 resume */ - u8 epcs; /* 0x43 - SGX Enabled status */ - u64 emna; /* 0x44 - 0x4B EPC base address */ - u64 elng; /* 0x4C - 0x53 EPC Length */ - u64 a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */ - u64 a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */ -}; +#include #endif From 9034689ee7b8e73cb524006de9538e7daf077c49 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 29 Sep 2021 21:12:27 +0200 Subject: [PATCH 161/320] soc/intel: deduplicate acpi_fill_soc_wake MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in common code. Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/alderlake/acpi.c | 15 --------------- src/soc/intel/apollolake/acpi.c | 15 --------------- src/soc/intel/cannonlake/acpi.c | 15 --------------- src/soc/intel/common/block/acpi/acpi.c | 1 + src/soc/intel/elkhartlake/acpi.c | 15 --------------- src/soc/intel/icelake/acpi.c | 15 --------------- src/soc/intel/jasperlake/acpi.c | 15 --------------- src/soc/intel/tigerlake/acpi.c | 15 --------------- 8 files changed, 1 insertion(+), 105 deletions(-) diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index b28ec124838..9f4fa880a05 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -280,21 +280,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index b6d61b19d70..8f5dd12459f 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -95,21 +95,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_LOW; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 70951205e12..d0f38747cbc 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -185,21 +185,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c21a8613903..9bfb91ad3f6 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -218,6 +218,7 @@ int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint * powerbtn or any other wake source like lidopen, key board press etc. */ pm1_en = ps->pm1_en; + pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; pm1_en = acpi_fill_soc_wake(pm1_en, ps); diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index abbb1ec206b..7531331d25f 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -249,21 +249,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index cac21382005..fa6d038a515 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -180,21 +180,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index b4efddba0c5..cc7b8ae62fd 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -260,21 +260,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 1a8ccb9e93c..e560f11f696 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -275,21 +275,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) sa_fill_gnvs(gnvs); } -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; From f855b8bfee8e365987043d904277514f69493cb0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 10 Oct 2021 16:56:31 +0200 Subject: [PATCH 162/320] soc/intel/common/acpi: drop `RTC_EN` from static wake bits mask MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit `RTC_EN` is in the RTC well* so we can rely on the actual register content instead of statically overriding it. Drop it from the static wake bits mask. * Tested on clevo/l140cu Change-Id: Ia0ae71f0a472513233bc0fd5625faf15bf86beaf Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58211 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- src/soc/intel/common/block/acpi/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 9bfb91ad3f6..4d3cb739b34 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -218,7 +218,7 @@ int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint * powerbtn or any other wake source like lidopen, key board press etc. */ pm1_en = ps->pm1_en; - pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; + pm1_en |= WAK_STS | PWRBTN_EN; pm1_en = acpi_fill_soc_wake(pm1_en, ps); From 820b9c4676ba56da56ed04164335c5dba9d3dcbe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 30 Sep 2021 21:03:07 +0200 Subject: [PATCH 163/320] soc/intel/common: add possiblity to override GPE0 to acpi_fill_soc_wake MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, only the PM1_STS mask gets passed to `acpi_fill_soc_wake`. To be able to override the GPE0_STS mask as well, also pass that one. To accomplish that, pointers to the variables are passed now. Change-Id: If9f28cf054ae8b602c0587e4dd4a13a4aba810c7 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58071 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/common/block/acpi/acpi.c | 12 +++++++----- .../intel/common/block/include/intelblocks/acpi.h | 6 +++--- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 4d3cb739b34..6f7412740a7 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -192,10 +192,9 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, } __weak -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) +void acpi_fill_soc_wake(uint32_t *pm1_en, uint32_t *gpe0_en, + const struct chipset_power_state *ps) { - return generic_pm1_en; } /* @@ -210,6 +209,7 @@ uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0) { static uint32_t gpe0_sts[GPE0_REG_MAX]; + uint32_t gpe0_en[GPE0_REG_MAX]; uint32_t pm1_en; int i; @@ -220,14 +220,16 @@ int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint pm1_en = ps->pm1_en; pm1_en |= WAK_STS | PWRBTN_EN; - pm1_en = acpi_fill_soc_wake(pm1_en, ps); + memcpy(gpe0_en, ps->gpe0_en, sizeof(gpe0_en)); + + acpi_fill_soc_wake(&pm1_en, gpe0_en, ps); *pm1 = ps->pm1_sts & pm1_en; /* Mask off GPE0 status bits that are not enabled */ *gpe0 = &gpe0_sts[0]; for (i = 0; i < GPE0_REG_MAX; i++) - gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; + gpe0_sts[i] = ps->gpe0_sts[i] & gpe0_en[i]; return GPE0_REG_MAX; } diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 59fd24436c3..5497275d233 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -6,6 +6,7 @@ #include #include #include +#include #include /* Forward declare the power state struct here */ @@ -47,10 +48,9 @@ acpi_tstate_t *soc_get_tss_table(int *entries); /* * Chipset specific quirks for the wake enable bits. - * Returns wake events for the soc. */ -uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps); +void acpi_fill_soc_wake(uint32_t *pm1_en, uint32_t *gpe0_en, + const struct chipset_power_state *ps); /* Chipset specific settings for filling up dmar table */ unsigned long sa_write_acpi_tables(const struct device *dev, From 01b3c40bfef5f5789a8521da766be8792eeb06c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 27 Sep 2021 18:39:41 +0200 Subject: [PATCH 164/320] soc/intel: move disabling of PM Timer to SoC PMC code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move disabling of PM Timer to SoC PMC code. The original reason for placing that in `finalize` [1] was FSP hanging due to use of the PM timer without enabling timer emulation first in coreboot, which was added later [2]. [1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown) [2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs) Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/alderlake/finalize.c | 9 --------- src/soc/intel/alderlake/pmc.c | 9 +++++++++ src/soc/intel/elkhartlake/finalize.c | 9 --------- src/soc/intel/elkhartlake/pmc.c | 9 +++++++++ src/soc/intel/icelake/finalize.c | 9 --------- src/soc/intel/icelake/pmc.c | 9 +++++++++ src/soc/intel/jasperlake/finalize.c | 9 --------- src/soc/intel/jasperlake/pmc.c | 9 +++++++++ src/soc/intel/tigerlake/finalize.c | 9 --------- src/soc/intel/tigerlake/pmc.c | 9 +++++++++ 10 files changed, 45 insertions(+), 45 deletions(-) diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 4ef572b5f69..aa136d4e09d 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -57,15 +57,6 @@ static void pch_finalize(void) /* TODO: Add Thermal Configuration */ - /* - * Disable ACPI PM timer based on Kconfig - * - * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. - * Disabling ACPI PM timer also switches off TCO - */ - if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); - pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index 6f9b03b16fc..4251cd66bd4 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -152,6 +152,15 @@ static void soc_pmc_init(struct device *dev) * done from the "ops->init" callback. */ pmc_set_acpi_mode(); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + pmc_disable_acpi_timer(); } static void pm1_enable_pwrbtn_smi(void *unused) diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index ad3b4ef8673..d415a1d2b83 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -29,15 +29,6 @@ static void pch_finalize(void) /* TODO: Add Thermal Configuration */ - /* - * Disable ACPI PM timer based on Kconfig - * - * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. - * Disabling ACPI PM timer also switches off TCO - */ - if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); - pmc_clear_pmcon_sts(); } diff --git a/src/soc/intel/elkhartlake/pmc.c b/src/soc/intel/elkhartlake/pmc.c index bcc8c8b04fa..dd6e6160ec5 100644 --- a/src/soc/intel/elkhartlake/pmc.c +++ b/src/soc/intel/elkhartlake/pmc.c @@ -92,6 +92,15 @@ static void soc_pmc_init(struct device *dev) * done from the "ops->init" callback. */ pmc_set_acpi_mode(); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + pmc_disable_acpi_timer(); } static void pmc_fill_ssdt(const struct device *dev) diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index f828cc461dd..eb7ac10f2eb 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -54,15 +54,6 @@ static void pch_finalize(void) */ pch_thermal_configuration(); - /* - * Disable ACPI PM timer based on Kconfig - * - * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. - * Disabling ACPI PM timer also switches off TCO - */ - if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); - pch_handle_sideband(config); pmc_clear_pmcon_sts(); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index ee40fee5f25..7886c1b28fc 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -66,6 +66,15 @@ static void pmc_init(void *unused) config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); config_deep_sx(config->deep_sx_config); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + pmc_disable_acpi_timer(); } /* diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 9aef9eb5d90..40b52946e6a 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -51,15 +51,6 @@ static void pch_finalize(void) /* TODO: Add Thermal Configuration */ - /* - * Disable ACPI PM timer based on Kconfig - * - * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. - * Disabling ACPI PM timer also switches off TCO - */ - if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); - pmcbase = pmc_mmio_regs(); if (config->s0ix_enable) { /* diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index a9fc5257795..d3607dcb57a 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -92,6 +92,15 @@ static void soc_pmc_init(struct device *dev) * done from the "ops->init" callback. */ pmc_set_acpi_mode(); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + pmc_disable_acpi_timer(); } static void pm1_enable_pwrbtn_smi(void *unused) diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 26cba964918..3bbd00266b1 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -35,15 +35,6 @@ static void pch_finalize(void) /* TODO: Add Thermal Configuration */ - /* - * Disable ACPI PM timer based on dt policy - * - * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. - * Disabling ACPI PM timer also switches off TCO - */ - if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); - pmc_clear_pmcon_sts(); } diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index ce37007116d..01891e1be9f 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -151,6 +151,15 @@ static void soc_pmc_init(struct device *dev) * done from the "ops->init" callback. */ pmc_set_acpi_mode(); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + pmc_disable_acpi_timer(); } static void pm1_enable_pwrbtn_smi(void *unused) From 6eaffcdbb13b13aad20a4ea0f06f361432daf713 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 27 Sep 2021 18:45:10 +0200 Subject: [PATCH 165/320] soc/intel: implement ACPI timer disabling per SoC and drop common code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since it's just a one-liner, implement disabling of the ACPI timer in soc code. This reduces complexity. Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/alderlake/Kconfig | 1 - src/soc/intel/alderlake/pmc.c | 2 +- src/soc/intel/common/block/include/intelblocks/pmclib.h | 3 --- src/soc/intel/common/block/pmc/Kconfig | 6 ------ src/soc/intel/common/block/pmc/pmclib.c | 9 --------- src/soc/intel/elkhartlake/Kconfig | 1 - src/soc/intel/elkhartlake/pmc.c | 2 +- src/soc/intel/icelake/Kconfig | 1 - src/soc/intel/icelake/pmc.c | 2 +- src/soc/intel/jasperlake/Kconfig | 1 - src/soc/intel/jasperlake/pmc.c | 2 +- src/soc/intel/tigerlake/Kconfig | 1 - src/soc/intel/tigerlake/pmc.c | 2 +- 13 files changed, 5 insertions(+), 28 deletions(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index e98878f14ee..a57d05e660a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -43,7 +43,6 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_2 select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK - select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index 4251cd66bd4..0d523686d8e 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -160,7 +160,7 @@ static void soc_pmc_init(struct device *dev) * Disabling ACPI PM timer also switches off TCO */ if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } static void pm1_enable_pwrbtn_smi(void *unused) diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 4972a09f8b9..bb38204718c 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -251,9 +251,6 @@ void pmc_set_power_failure_state(bool target_on); uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, uint8_t slp_a_min_assert, uint8_t pm_pwr_cyc_dur); -/* Disabling ACPI PM timer to ensure switches off TCO and necessary of XTAL OSC shutdown */ -void pmc_disable_acpi_timer(void); - /* API to set ACPI mode */ void pmc_set_acpi_mode(void); diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 5e5e8d61841..f60dc696927 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -50,12 +50,6 @@ config PMC_GLOBAL_RESET_ENABLE_LOCK Note that the reset register is still at 0xCF9 this only controls the enable and lock feature. -config PMC_LOW_POWER_MODE_PROGRAM - bool - help - Enable this for PMC devices to perform registers programming - to ensure low power in active idle scenario. - config PM_ACPI_TIMER_OPTIONAL bool default n diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 6c756b1590f..f7efeb78dab 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -711,15 +711,6 @@ uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, return PCH_PM_PWR_CYC_DUR; } -#if CONFIG(PMC_LOW_POWER_MODE_PROGRAM) -void pmc_disable_acpi_timer(void) -{ - uint8_t *pmcbase = pmc_mmio_regs(); - - setbits8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); -} -#endif /* PMC_LOW_POWER_MODE_PROGRAM */ - void pmc_set_acpi_mode(void) { if (!CONFIG(NO_SMM) && !acpi_is_wakeup_s3()) { diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 07af2faf663..e3fbfddb241 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -33,7 +33,6 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_1 select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK - select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/elkhartlake/pmc.c b/src/soc/intel/elkhartlake/pmc.c index dd6e6160ec5..53193ea11e4 100644 --- a/src/soc/intel/elkhartlake/pmc.c +++ b/src/soc/intel/elkhartlake/pmc.c @@ -100,7 +100,7 @@ static void soc_pmc_init(struct device *dev) * Disabling ACPI PM timer also switches off TCO */ if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } static void pmc_fill_ssdt(const struct device *dev) diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 74bae9c433c..fd05f2ec48c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -33,7 +33,6 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_1 select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK - select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 7886c1b28fc..fd91cde57db 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -74,7 +74,7 @@ static void pmc_init(void *unused) * Disabling ACPI PM timer also switches off TCO */ if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } /* diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 690df0cf2dd..43697602a2d 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_2 select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK - select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index d3607dcb57a..47c3bb104bb 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -100,7 +100,7 @@ static void soc_pmc_init(struct device *dev) * Disabling ACPI PM timer also switches off TCO */ if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } static void pm1_enable_pwrbtn_smi(void *unused) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index fe7805ae708..1e9a85179ff 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -42,7 +42,6 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_2 select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK - select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 01891e1be9f..87881703683 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -159,7 +159,7 @@ static void soc_pmc_init(struct device *dev) * Disabling ACPI PM timer also switches off TCO */ if (!CONFIG(USE_PM_ACPI_TIMER)) - pmc_disable_acpi_timer(); + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } static void pm1_enable_pwrbtn_smi(void *unused) From 68bacc210945ef7d65dd542765c3be997caf7b4d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 24 Sep 2021 23:57:37 +0200 Subject: [PATCH 166/320] soc/intel/{skl,cnl,dnv}: disable PM ACPI timer if chosen MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is disabled. This is done to bring SKL, CNL, DNV in line with the other platforms, in order to transition handling of the PM timer from FSP to coreboot in the follow-up changes. For SKL and CNL, this temporarly redundantly disables the PM Timer, since FSP does that, too. This redundancy is resolved in the follow-up. Change-Id: I47280cd670a96c8fa5af107986496234f04e1f77 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57932 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/cannonlake/pmc.c | 9 +++++++++ src/soc/intel/denverton_ns/Kconfig | 1 + src/soc/intel/denverton_ns/include/soc/pmc.h | 2 ++ src/soc/intel/denverton_ns/pmc.c | 11 +++++++++++ src/soc/intel/skylake/pmc.c | 9 +++++++++ 5 files changed, 32 insertions(+) diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index d502e0675a1..4c88685d045 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -118,6 +118,15 @@ static void soc_pmc_init(struct device *dev) * found. */ pmc_set_acpi_mode(); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO. + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } static void pmc_fill_ssdt(const struct device *dev) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index a578a71fd0b..a8ed92be289 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS select PCR_COMMON_IOSF_1_0 + select PM_ACPI_TIMER_OPTIONAL select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index fdb1028f1f8..0ba24fcb2fe 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -240,6 +240,8 @@ #define GPIO_GPE_CFG 0x120 #define GPE0_DWX_MASK 0x7 #define GPE0_DW_SHIFT(x) (4 + 4*(x)) +#define PCH_PWRM_ACPI_TMR_CTL 0xfc +#define ACPI_TIM_DIS (1 << 1) /* I/O ports */ #define RST_CNT 0xcf9 diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index d75f7f05a69..2c208d2aa5b 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -46,6 +47,16 @@ static void pmc_init(struct device *dev) /* Configure ACPI mode. */ pch_set_acpi_mode(); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO. + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8((volatile void *)(uintptr_t)(pwrm_base + PCH_PWRM_ACPI_TMR_CTL), + ACPI_TIM_DIS); } static void pci_pmc_read_resources(struct device *dev) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index c2e724f3539..b9b85c2e8fd 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -101,6 +101,15 @@ void pmc_soc_init(struct device *dev) pci_or_config32(dev, GEN_PMCON_B, 0); setbits32(pwrmbase + GBLRST_CAUSE0, 0); setbits32(pwrmbase + GBLRST_CAUSE1, 0); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO. + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } static void pm1_enable_pwrbtn_smi(void *unused) From 0e905801f8ff6c10b20625e31d851920b3f4c4f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 25 Sep 2021 00:10:30 +0200 Subject: [PATCH 167/320] soc/intel: transition full control over PM Timer from FSP to coreboot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Lance Zhao --- src/soc/intel/alderlake/fsp_params.c | 14 ++++++++++++++ src/soc/intel/cannonlake/fsp_params.c | 9 ++++++++- src/soc/intel/elkhartlake/fsp_params.c | 9 +++++++++ src/soc/intel/icelake/fsp_params.c | 9 +++++++++ src/soc/intel/jasperlake/fsp_params.c | 9 +++++++++ src/soc/intel/skylake/chip.c | 9 ++++++++- src/soc/intel/tigerlake/fsp_params.c | 9 +++++++++ 7 files changed, 66 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index f9569f9e417..6e90cf17f8d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -574,6 +574,19 @@ static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, s_cfg->Enable8254ClockGatingOnS3 = !use_8254; } +static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + s_cfg->EnableTcoTimer = 1; +} + static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { @@ -742,6 +755,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, fill_fsps_thc_params, fill_fsps_tbt_params, fill_fsps_8254_params, + fill_fsps_pm_timer_params, fill_fsps_storage_params, fill_fsps_pcie_params, fill_fsps_misc_power_params, diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 1ae27aefeed..f22e39d442a 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -437,7 +437,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !use_8254; params->Enable8254ClockGatingOnS3 = !use_8254; - params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER); + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + params->EnableTcoTimer = 1; /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 2bf4a511310..f30bb1e19c3 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -167,6 +167,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !use_8254; params->Enable8254ClockGatingOnS3 = 1; + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + params->EnableTcoTimer = 1; + /* PCH Master Gating Control */ params->PchPostMasterClockGating = 1; params->PchPostMasterPowerGating = 1; diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index ba40f3f01d4..fa63a3dfcd4 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -98,6 +98,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !use_8254; params->Enable8254ClockGatingOnS3 = !use_8254; + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + params->EnableTcoTimer = 1; + /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 18db9359ced..085148f7b37 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -85,6 +85,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !use_8254; params->Enable8254ClockGatingOnS3 = 1; + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + params->EnableTcoTimer = 1; + /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index c99067db3d0..d706e1298d1 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -345,7 +345,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); params->Early8254ClockGatingEnable = !use_8254; - params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER); + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + params->EnableTcoTimer = 1; memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 892363b75c0..34ee9d8d17e 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -502,6 +502,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !use_8254; params->Enable8254ClockGatingOnS3 = !use_8254; + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + params->EnableTcoTimer = 1; + /* Enable Hybrid storage auto detection */ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite() && vboot_recovery_mode_enabled() && !cse_is_hfs1_com_normal()) { From 413810e55ff307d998ace4e16145ab71e939e85a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 24 Sep 2021 23:42:14 +0200 Subject: [PATCH 168/320] soc/intel/*: only enable PM Timer emulation if the PM Timer is disabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit uCode PM Timer emulation is only needed when the hardware PM ACPI timer is disabled. Also, since it redirects any register accesses to uCode, it overrides the hardware PM Timer. Thus, only enable emulation when required. Change-Id: I60a775bd6eb4206750f606ce8a8777d2e2dfb579 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57930 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/common/block/cpu/pm_timer_emulation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/cpu/pm_timer_emulation.c b/src/soc/intel/common/block/cpu/pm_timer_emulation.c index 0436e04634f..3c619985156 100644 --- a/src/soc/intel/common/block/cpu/pm_timer_emulation.c +++ b/src/soc/intel/common/block/cpu/pm_timer_emulation.c @@ -11,7 +11,7 @@ void enable_pm_timer_emulation(void) { msr_t msr; - if (!CONFIG_CPU_XTAL_HZ) + if (CONFIG(USE_PM_ACPI_TIMER) || !CONFIG_CPU_XTAL_HZ) return; /* From c9a12f2402bb9151f8a0643d98bb6915bf06531e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Fri, 24 Sep 2021 23:22:51 +0200 Subject: [PATCH 169/320] soc/intel/{common,apl,glk}: guard PM Timer option on SoCs w/o PM Timer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apollo Lake and Gemini Lake do not have a hardware PM ACPI timer but only uCode PM Timer emulation. Add a Kconfig `NO_PM_ACPI_TIMER` denoting SoCs without PM Timer and make it mutually exclusive with the Kconfig `USE_PM_ACPI_TIMER`. This is partly redundant to `PM_ACPI_TIMER_OPTIONAL`, which will be dropped in the follow-up change, though. Change-Id: Ic323bbfb7089c53a6f22724910a0ff3df8904ebd Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57931 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/common/block/pmc/Kconfig | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 6395f16f7c0..0302546335e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_XIP_EARLY_STAGES + select NO_PM_ACPI_TIMER select PARALLEL_MP_AP_WORK select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index f60dc696927..6ec93398065 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -50,6 +50,11 @@ config PMC_GLOBAL_RESET_ENABLE_LOCK Note that the reset register is still at 0xCF9 this only controls the enable and lock feature. +config NO_PM_ACPI_TIMER + bool + help + Selected by SoCs that do not have a PM ACPI timer. + config PM_ACPI_TIMER_OPTIONAL bool default n @@ -62,6 +67,7 @@ if PM_ACPI_TIMER_OPTIONAL config USE_PM_ACPI_TIMER bool "Enable ACPI PM timer" default y + depends on !NO_PM_ACPI_TIMER help This should be disabled for devices running on battery since it can draw much power. Further, it must be disabled, if S0ix From f6611a2ea8d9288e57ce08b9190b3e401c18edd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 3 Aug 2020 16:53:41 +0200 Subject: [PATCH 170/320] soc/intel/skylake: switch to common ACPI code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the common ACPI code to reduce code duplication. After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state table generation (as of commit c2540a9) and the number reduces from 10 to 7 entries. Also, remnants of P_BLK support missed in CB:58096 will vanish. Tested on google/fizz: no errors in dmesg, ACPI tables remain the same (except PSS, as mentioned above). Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40 Tested-by: Matt DeVillier Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- .../supermicro/x11-lga1151-series/fadt.c | 2 +- src/soc/intel/skylake/Kconfig | 2 + src/soc/intel/skylake/acpi.c | 397 +++--------------- src/soc/intel/skylake/chip.c | 3 +- src/soc/intel/skylake/fadt.c | 57 +-- src/soc/intel/skylake/include/soc/acpi.h | 20 - src/soc/intel/skylake/include/soc/pm.h | 6 + src/soc/intel/skylake/include/soc/pmc.h | 2 + src/soc/intel/skylake/include/soc/ramstage.h | 1 - 9 files changed, 64 insertions(+), 426 deletions(-) delete mode 100644 src/soc/intel/skylake/include/soc/acpi.h diff --git a/src/mainboard/supermicro/x11-lga1151-series/fadt.c b/src/mainboard/supermicro/x11-lga1151-series/fadt.c index 6306e03e307..0686f7ad20a 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/fadt.c +++ b/src/mainboard/supermicro/x11-lga1151-series/fadt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include void mainboard_fill_fadt(acpi_fadt_t *fadt) { diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d66c331064d..bd3353d50e9 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -51,6 +51,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 72c5e472de0..cac72532ea9 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -8,33 +8,22 @@ #include #include #include -#include -#include #include -#include +#include #include #include -#include +#include #include -#include -#include -#include #include -#include #include -#include -#include #include #include #include #include #include -#include #include "chip.h" -#define CPUID_6_EAX_ISST (1 << 7) - /* * List of supported C-states in this processor. */ @@ -139,271 +128,65 @@ static int cstate_set_non_s0ix[] = { C_STATE_C7S_LONG_LAT, }; -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - const struct soc_intel_skylake_config *config = config_of_soc(); - - /* Enable DPTF based on mainboard configuration */ - gnvs->dpte = config->dptf_enable; - - /* Set USB2/USB3 wake enable bitmaps. */ - gnvs->u2we = config->usb2_wake_enable_bitmap; - gnvs->u3we = config->usb3_wake_enable_bitmap; - - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) - sgx_fill_gnvs(gnvs); - - /* Fill in Above 4GB MMIO resource */ - sa_fill_gnvs(gnvs); -} - -unsigned long acpi_fill_mcfg(unsigned long current) +acpi_cstate_t *soc_get_cstate_map(size_t *entries) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER - 1); - return current; -} + static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), + ARRAY_SIZE(cstate_set_non_s0ix))]; + int *set; + int i; -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); + config_t *config = config_of_soc(); - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + int is_s0ix_enable = config->s0ix_enable; - return acpi_madt_irq_overrides(current); -} + if (is_s0ix_enable) { + *entries = ARRAY_SIZE(cstate_set_s0ix); + set = cstate_set_s0ix; + } else { + *entries = ARRAY_SIZE(cstate_set_non_s0ix); + set = cstate_set_non_s0ix; + } -static void write_c_state_entries(acpi_cstate_t *map, const int *set, size_t max_c_state) -{ - for (size_t i = 0; i < max_c_state; i++) { + for (i = 0; i < *entries; i++) { memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); map[i].ctype = i + 1; } - - /* Generate C-state tables */ - acpigen_write_CST_package(map, max_c_state); + return map; } -static void generate_c_state_entries(int s0ix_enable) +void soc_power_states_generation(int core_id, int cores_per_package) { - if (s0ix_enable) { - acpi_cstate_t map[ARRAY_SIZE(cstate_set_s0ix)]; - write_c_state_entries(map, cstate_set_s0ix, ARRAY_SIZE(map)); - } else { - acpi_cstate_t map[ARRAY_SIZE(cstate_set_non_s0ix)]; - write_c_state_entries(map, cstate_set_non_s0ix, ARRAY_SIZE(map)); - } -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; + config_t *config = config_of_soc(); - return (int)power; + /* Generate P-state tables */ + if (config->eist_enable) + generate_p_state_entries(core_id, cores_per_package); } -static void generate_p_state_entries(int core, int cores_per_package) +uint32_t soc_read_sci_irq_select(void) { - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; - if (num_entries > PSS_MAX_ENTRIES) { - ratio_step += 1; - num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /* MHz */ - power_max, /* mW */ - PSS_LATENCY_TRANSITION, /* lat1 */ - PSS_LATENCY_BUSMASTER, /* lat2 */ - ratio_turbo << 8, /* control */ - ratio_turbo << 8); /* status */ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /* MHz */ - power_max, /* mW */ - PSS_LATENCY_TRANSITION, /* lat1 */ - PSS_LATENCY_BUSMASTER, /* lat2 */ - ratio_max << 8, /* control */ - ratio_max << 8); /* status */ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CONFIG_CPU_BCLK_MHZ; - - acpigen_write_PSS_package( - clock, /* MHz */ - power, /* mW */ - PSS_LATENCY_TRANSITION, /* lat1 */ - PSS_LATENCY_BUSMASTER, /* lat2 */ - ratio << 8, /* control */ - ratio << 8); /* status */ - } - - /* Fix package length */ - acpigen_pop_len(); + return read32p(soc_read_pmc_base() + IRQ_REG); } -static void generate_cppc_entries(int core_id) +void soc_fill_gnvs(struct global_nvs *gnvs) { - /* Generate GCPC table in first logical core */ - if (core_id == 0) { - struct cppc_config cppc_config; - cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); - acpigen_write_CPPC_package(&cppc_config); - } + const struct soc_intel_skylake_config *config = config_of_soc(); - /* Write _CST entry for each logical core */ - acpigen_write_CPPC_method(); -} + /* Enable DPTF based on mainboard configuration */ + gnvs->dpte = config->dptf_enable; -void generate_cpu_entries(const struct device *device) -{ - int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - config_t *config = config_of_soc(); - int is_s0ix_enable = config->s0ix_enable; - const bool isst_supported = cpuid_eax(6) & CPUID_6_EAX_ISST; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { - for (core_id = 0; core_id < cores_per_package; core_id++) { - if (core_id > 0) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx */ - acpigen_write_processor( - cpu_id*cores_per_package+core_id, - pcontrol_blk, plen); - /* Generate C-state tables */ - generate_c_state_entries(is_s0ix_enable); - - if (config->eist_enable) { - /* Generate P-state tables */ - generate_p_state_entries(core_id, - cores_per_package); - } - - if (isst_supported) - generate_cppc_entries(core_id); - - acpigen_pop_len(); - } - } + /* Set USB2/USB3 wake enable bitmaps. */ + gnvs->u2we = config->usb2_wake_enable_bitmap; + gnvs->u3we = config->usb3_wake_enable_bitmap; - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) + sgx_fill_gnvs(gnvs); - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); } -static unsigned long acpi_fill_dmar(unsigned long current) +static unsigned long soc_fill_dmar(unsigned long current) { const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; @@ -455,9 +238,9 @@ static unsigned long acpi_fill_dmar(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(const struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) +unsigned long sa_write_acpi_tables(const struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) { acpi_dmar_t *const dmar = (acpi_dmar_t *)current; @@ -466,7 +249,7 @@ unsigned long northbridge_write_acpi_tables(const struct device *const dev, return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); current += dmar->header.length; current = acpi_align_current(current); acpi_add_table(rsdp, dmar); @@ -474,103 +257,23 @@ unsigned long northbridge_write_acpi_tables(const struct device *const dev, return current; } -int acpi_sci_irq(void) -{ - int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL; - int sci_irq = 9; - - /* Determine how SCI is routed. */ - switch (scis) { - case SCIS_IRQ9: - case SCIS_IRQ10: - case SCIS_IRQ11: - sci_irq = scis - SCIS_IRQ9 + 9; - break; - case SCIS_IRQ20: - case SCIS_IRQ21: - case SCIS_IRQ22: - case SCIS_IRQ23: - sci_irq = scis - SCIS_IRQ20 + 20; - break; - default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; - break; - } - - printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; -} - -unsigned long acpi_madt_irq_overrides(unsigned long current) +int soc_madt_sci_irq_polarity(int sci) { - int sci = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; - - /* INT_SRC_OVR */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - if (sci >= 20) - flags |= MP_IRQ_POLARITY_LOW; + return MP_IRQ_POLARITY_LOW; else - flags |= MP_IRQ_POLARITY_HIGH; - - /* SCI */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); - - /* NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - - return current; -} - -unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - current = acpi_write_dbg2_pci_uart(rsdp, current, - uart_get_device(), - ACPI_ACCESS_SIZE_DWORD_ACCESS); - current = acpi_write_hpet(device, current, rsdp); - return acpi_align_current(current); + return MP_IRQ_POLARITY_HIGH; } -/* Save wake source information for calculating ACPI _SWS values */ -int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0) +void acpi_fill_soc_wake(uint32_t *pm1_en, uint32_t *gpe0_en, + const struct chipset_power_state *ps) { const struct soc_intel_skylake_config *config = config_of_soc(); - static uint32_t gpe0_sts[GPE0_REG_MAX]; - uint32_t pm1_en; - uint32_t gpe0_std; - int i; - const int last_index = GPE0_REG_MAX - 1; - - pm1_en = ps->pm1_en; - gpe0_std = ps->gpe0_en[3]; - - /* - * Chipset state in the suspend well (but not RTC) is lost in Deep S3 - * so enable Deep S3 wake events that are configured by the mainboard - */ - if (ps->prev_sleep_state == ACPI_S3 && - (config->deep_s3_enable_ac || config->deep_s3_enable_dc)) { - pm1_en |= PWRBTN_STS; /* Always enabled as wake source */ + + if (ps->prev_sleep_state == ACPI_S3 && deep_s3_enabled()) { if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN) - gpe0_std |= LAN_WAK_EN; + gpe0_en[GPE_STD] |= LAN_WAK_EN; if (config->deep_sx_config & DSX_EN_WAKE_PIN) - pm1_en |= PCIEXPWAK_STS; + *pm1_en |= PCIEXPWAK_STS; } - - *pm1 = ps->pm1_sts & pm1_en; - - /* Mask off GPE0 status bits that are not enabled */ - *gpe0 = &gpe0_sts[0]; - for (i = 0; i < last_index; i++) - gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; - gpe0_sts[last_index] = ps->gpe0_sts[last_index] & gpe0_std; - - return GPE0_REG_MAX; } diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d706e1298d1..dd42f31961d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -18,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -191,7 +191,6 @@ static struct device_operations pci_domain_ops = { .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = &northbridge_write_acpi_tables, .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index 61e9417abd1..774dd5e1f57 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -2,68 +2,28 @@ #include #include -#include #include #include #include "chip.h" -void acpi_fill_fadt(acpi_fadt_t *fadt) +void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; config_t *config = config_of_soc(); - fadt->header.revision = get_acpi_table_revision(FADT); - - fadt->sci_int = acpi_sci_irq(); - - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; if (!CONFIG(NO_FADT_8042)) fadt->iapc_boot_arch |= ACPI_FADT_8042; - fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE; - - if (CONFIG(USE_PM_ACPI_TIMER)) - fadt->flags |= ACPI_FADT_PLATFORM_CLOCK; - if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; @@ -77,17 +37,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; } diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h deleted file mode 100644 index 683a50490ae..00000000000 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ACPI_H_ -#define _SOC_ACPI_H_ - -#include - -/* P-state configuration */ -#define PSS_MAX_ENTRIES 8 -#define PSS_RATIO_STEP 2 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 - -/* Return the selected ACPI SCI IRQ */ -int acpi_sci_irq(void); -unsigned long acpi_madt_irq_overrides(unsigned long current); -unsigned long northbridge_write_acpi_tables(const struct device *, - unsigned long current, struct acpi_rsdp *); - -#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index a57772446ea..f0ce1465623 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -141,6 +141,12 @@ #define PRSTS 0x10 +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + struct chipset_power_state { uint16_t pm1_sts; uint16_t pm1_en; diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 8fe3f83cadf..165d57170ee 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -59,6 +59,8 @@ #define ETR3 0xac #define ETR3_CF9LOCK (1 << 31) #define ETR3_CF9GR (1 << 20) +#define SCI_IRQ_ADJUST 0 +#define IRQ_REG ACTL /* Memory mapped IO registers in PMC */ #define S3_PWRGATE_POL 0x28 diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h index 02d53a1e17d..a5e6930bec9 100644 --- a/src/soc/intel/skylake/include/soc/ramstage.h +++ b/src/soc/intel/skylake/include/soc/ramstage.h @@ -15,6 +15,5 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params); void soc_init_pre_device(void *chip_info); void soc_irq_settings(FSP_SIL_UPD *params); -const char *soc_acpi_name(const struct device *dev); #endif From 6644d7c508a1a15d5a0c79f47cdf09585c99192f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 08:10:05 +0300 Subject: [PATCH 171/320] drivers/generic/ioapic: Drop enable_virtual_wire MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards with DRIVERS_GENERIC_IOAPIC select it. Presumably the related configuration of routing IRQ0 when IOAPIC is enabled should be always done to provide i8259 legacy compatibility for payloads. Change-Id: Ie87816271fa63bba892c8615aa5e72ee68f6ba93 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55287 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/arch/x86/include/arch/ioapic.h | 1 - src/arch/x86/ioapic.c | 12 ++---------- src/drivers/generic/ioapic/chip.h | 1 - src/drivers/generic/ioapic/ioapic.c | 2 +- src/mainboard/lenovo/t400/devicetree.cb | 1 - src/mainboard/lenovo/x200/devicetree.cb | 1 - src/mainboard/roda/rk9/devicetree.cb | 1 - src/mainboard/samsung/lumpy/devicetree.cb | 1 - 8 files changed, 3 insertions(+), 17 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 372cb79e9fa..99536d4dfd2 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -35,7 +35,6 @@ void setup_ioapic(void *ioapic_base, u8 ioapic_id); void clear_ioapic(void *ioapic_base); void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); -void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire); #endif #endif diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index a11e5dd9b32..61fed890d1f 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -136,17 +136,9 @@ void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb) } } -void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire) +void setup_ioapic(void *ioapic_base, u8 ioapic_id) { set_ioapic_id(ioapic_base, ioapic_id); clear_ioapic(ioapic_base); - - if (enable_virtual_wire) - route_i8259_irq0(ioapic_base); -} - - -void setup_ioapic(void *ioapic_base, u8 ioapic_id) -{ - setup_ioapic_helper(ioapic_base, ioapic_id, true); + route_i8259_irq0(ioapic_base); } diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h index 9a9395f7142..a5fbeab5d46 100644 --- a/src/drivers/generic/ioapic/chip.h +++ b/src/drivers/generic/ioapic/chip.h @@ -6,7 +6,6 @@ typedef struct drivers_generic_ioapic_config { u32 version; u8 apicid; - u8 enable_virtual_wire; u8 have_isa_interrupts; void *base; } ioapic_config_t; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 4a8bcf81770..b286af3c149 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -13,7 +13,7 @@ static void ioapic_init(struct device *dev) if (!dev->enabled || !config) return; - setup_ioapic_helper(config->base, config->apicid, config->enable_virtual_wire); + setup_ioapic(config->base, config->apicid); } static void ioapic_read_resources(struct device *dev) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index ae389de5dd5..670b4883f33 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -143,7 +143,6 @@ chip northbridge/intel/gm45 chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 2 on end end diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 4db554b50b3..dd631a70341 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -133,7 +133,6 @@ chip northbridge/intel/gm45 chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 2 on end end diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 0af98373cac..cc5d76390fd 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -121,7 +121,6 @@ chip northbridge/intel/gm45 device pci 1f.0 on # LPC bridge chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 2 on end end diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 13a2299086b..1aab76de9ce 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -107,7 +107,6 @@ chip northbridge/intel/sandybridge chip drivers/generic/ioapic register "have_isa_interrupts" = "1" - register "enable_virtual_wire" = "1" register "base" = "(void *)0xfec00000" device ioapic 4 on end end From 253c356c2bca2a9552a42ea4dd38c71a639877a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 14:34:57 +0300 Subject: [PATCH 172/320] sb/amd/cimx/sb800: Clear IOAPIC vectors only once MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I640d17cdee2bdaa4fe7049ce66a327b58924bc6f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55288 Tested-by: build bot (Jenkins) Reviewed-by: MichaÅ‚ Å»ygowski --- src/arch/x86/include/arch/ioapic.h | 1 - src/arch/x86/ioapic.c | 7 +------ src/southbridge/amd/cimx/sb800/late.c | 1 - 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 99536d4dfd2..d8df39b4556 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -32,7 +32,6 @@ void set_ioapic_id(void *ioapic_base, u8 ioapic_id); u8 get_ioapic_id(void *ioapic_base); u8 get_ioapic_version(void *ioapic_base); void setup_ioapic(void *ioapic_base, u8 ioapic_id); -void clear_ioapic(void *ioapic_base); void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); #endif diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 61fed890d1f..1d30baad488 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -60,11 +60,6 @@ static void clear_vectors(void *ioapic_base, u8 first, u8 last) } } -void clear_ioapic(void *ioapic_base) -{ - clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1); -} - static void route_i8259_irq0(void *ioapic_base) { u32 bsp_lapicid = lapicid(); @@ -139,6 +134,6 @@ void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb) void setup_ioapic(void *ioapic_base, u8 ioapic_id) { set_ioapic_id(ioapic_base, ioapic_id); - clear_ioapic(ioapic_base); + clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1); route_i8259_irq0(ioapic_base); } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 9fdf596cbd6..b6cc3c777b5 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -340,7 +340,6 @@ static void sb800_enable(struct device *dev) break; case PCI_DEVFN(0x14, 0): /* 0:14:0 SMBUS */ - clear_ioapic(VIO_APIC_VADDR); /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); break; From b31b033ccc50a2f5c609f5fd2cbfda588994b518 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 31 May 2021 14:41:15 +0300 Subject: [PATCH 173/320] cpu/x86/lapic: Drop xapic_write_atomic() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove code, which was only needed for B and C2 stepping of P54C. The linux kernel source has commentary on X86_BUG_11AP: * See if we have a good local APIC by checking for buggy Pentia, * i.e. all B steppings and the C2 stepping of P54C when using their * integrated APIC (see 11AP erratum in "Pentium Processor * Specification Update") Change-Id: Iec10335f603674bcef2e7494831cf11200795d38 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55199 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/x86/lapic/lapic_cpu_init.c | 2 +- src/include/cpu/x86/lapic.h | 17 +++-------------- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e141ad8ec9b..bc0f44fd90c 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -128,7 +128,7 @@ static int lapic_start_cpu(unsigned long apicid) printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { printk(BIOS_ERR, "Try to reset ESR\n"); - xapic_write_atomic(LAPIC_ESR, 0); + lapic_write(LAPIC_ESR, 0); printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); } diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 4fbae88ca58..05d096e318a 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -18,21 +18,10 @@ static __always_inline void xapic_write(unsigned int reg, uint32_t v) write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v); } -static inline void xapic_write_atomic(unsigned long reg, uint32_t v) -{ - volatile uint32_t *ptr; - - ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE + reg); - - asm volatile ("xchgl %0, %1\n" - : "+r" (v), "+m" (*(ptr)) - : : "memory", "cc"); -} - static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t apicid) { - xapic_write_atomic(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - xapic_write_atomic(LAPIC_ICR, icrlow); + xapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + xapic_write(LAPIC_ICR, icrlow); } static __always_inline int xapic_busy(void) @@ -114,7 +103,7 @@ static __always_inline void lapic_update32(unsigned int reg, uint32_t mask, uint value = xapic_read(reg); value &= mask; value |= or; - xapic_write_atomic(reg, value); + xapic_write(reg, value); } } From 5f4ae427edaef5e6c7dd2f22b574041d9d5dcb36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 16 Oct 2021 13:35:04 +0300 Subject: [PATCH 174/320] cpu/intel/hyperthreading: Use CPUID leaf 0xb without X2APIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is not a requirement to have X2APIC mode enabled to use CPUID leaf 0xb EDX to detect logical CPU is a hyperthreading sibling. Change-Id: I288f2df5a392c396f92bb6d18908df35de55915d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/58383 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/cpu/intel/common/hyperthreading.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index b9c17b6fa1e..2936770cc34 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -23,12 +23,10 @@ bool intel_ht_sibling(void) if (!intel_ht_supported()) return false; - if (is_x2apic_mode()) { - if (cpuid_eax(0) >= 0xb) { - result = cpuid_ext(0xb, 0); - const uint32_t div = 1 << (result.eax & 0x1f); - return result.edx % div > 0; - } + if (cpuid_eax(0) >= 0xb) { + result = cpuid_ext(0xb, 0); + const uint32_t div = 1 << (result.eax & 0x1f); + return result.edx % div > 0; } apic_ids = 1; From a000922e077ec906c39c5e07ba2e38feefd5b8c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 16 Oct 2021 13:35:04 +0300 Subject: [PATCH 175/320] cpu/intel/hyperthreading: Use cpuid_get_max_func() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4b69b1d20b5a768c269d85f0ea23f79e02391a71 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/58384 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/cpu/intel/common/hyperthreading.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index 2936770cc34..3297b381b37 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -19,24 +19,26 @@ bool intel_ht_sibling(void) { struct cpuid_result result; unsigned int core_ids, apic_ids, threads; + unsigned int max_leaf; if (!intel_ht_supported()) return false; - if (cpuid_eax(0) >= 0xb) { + max_leaf = cpuid_get_max_func(); + if (max_leaf >= 0xb) { result = cpuid_ext(0xb, 0); const uint32_t div = 1 << (result.eax & 0x1f); return result.edx % div > 0; } apic_ids = 1; - if (cpuid_eax(0) >= 1) + if (max_leaf >= 1) apic_ids = (cpuid_ebx(1) >> 16) & 0xff; if (apic_ids == 0) apic_ids = 1; core_ids = 1; - if (cpuid_eax(0) >= 4) { + if (max_leaf >= 4) { result = cpuid_ext(4, 0); core_ids += (result.eax >> 26) & 0x3f; } From 5791123356c7edd2942f87f5ba2786143776fe54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 16 Oct 2021 13:35:04 +0300 Subject: [PATCH 176/320] cpu/intel/hyperthreading: Use initial LAPIC IDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For older CPU models where CPUID leaf 0xb is not supported, use initial LAPIC ID from CPUID instead of LAPIC register space to to detect if logical CPU is a hyperthreading sibling. The one in LAPIC space is more complex to read, and might not reflect CPU topology as it can be modified in XAPIC mode. Change-Id: I8c458824db1ea66948126622a3e0d0604e391e4b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/58385 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/cpu/intel/common/hyperthreading.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index 3297b381b37..f9170b383ab 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -18,22 +17,27 @@ bool intel_ht_supported(void) bool intel_ht_sibling(void) { struct cpuid_result result; - unsigned int core_ids, apic_ids, threads; + unsigned int core_ids, apic_ids; unsigned int max_leaf; + uint32_t initial_lapicid, threads; if (!intel_ht_supported()) return false; max_leaf = cpuid_get_max_func(); + + /* Detect from 32-bit X2APIC ID. */ if (max_leaf >= 0xb) { result = cpuid_ext(0xb, 0); - const uint32_t div = 1 << (result.eax & 0x1f); - return result.edx % div > 0; + threads = 1 << (result.eax & 0x1f); + initial_lapicid = result.edx; + return initial_lapicid % threads > 0; } - apic_ids = 1; - if (max_leaf >= 1) - apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + /* Detect from 8-bit XAPIC ID. */ + result = cpuid_ext(0x1, 0); + initial_lapicid = result.ebx >> 24; + apic_ids = (result.ebx >> 16) & 0xff; if (apic_ids == 0) apic_ids = 1; @@ -44,5 +48,5 @@ bool intel_ht_sibling(void) } threads = (apic_ids / core_ids); - return !!(lapicid() & (threads - 1)); + return initial_lapicid % threads > 0; } From bc89bc6680c186c3a7969e93f48b90bc6d6e9eb6 Mon Sep 17 00:00:00 2001 From: Bernardo Perez Priego Date: Tue, 5 Oct 2021 11:30:39 -0700 Subject: [PATCH 177/320] mb/intel/adlrvp_m: Enable retimer force power gpio Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain to toggle during a switch from DP Alt to TBT Alt modes. Contrary to DS specifying it may be left unconfigured, hence floating, there are instances seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp). Hence configure it to LOW. Branch=none Bug=none Test=Boot to OS, connect TBT dock which enumerates in DP Alt, Login, TBT dock enumerates in TBT Alt Signed-off-by: Bernardo Perez Priego Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58113 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik --- src/mainboard/intel/adlrvp/gpio_m.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 6f0568dbdab..915b549e034 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -169,7 +169,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE), /* E3 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT) + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + + /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_E4, 0, DEEP) }; void variant_configure_gpio_pads(void) From 66c8062a0072e9b162bf132fc5f279db158ab708 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Tue, 13 Jul 2021 07:23:22 +0100 Subject: [PATCH 178/320] soc/skylake: Make VT-d controllable from CMOS option Make VT-d enable or disable based on CMOS value "vtd" 1 = Enable 0 = Disable Signed-off-by: Sean Rhodes Change-Id: I1aea14968e08ee6af822bd259ca1d462f8926994 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56252 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/soc/intel/skylake/acpi.c | 2 +- src/soc/intel/skylake/chip.c | 2 +- src/soc/intel/skylake/include/soc/systemagent.h | 2 +- src/soc/intel/skylake/systemagent.c | 9 +++++++-- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index cac72532ea9..9bbfec3cd5c 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -245,7 +245,7 @@ unsigned long sa_write_acpi_tables(const struct device *const dev, acpi_dmar_t *const dmar = (acpi_dmar_t *)current; /* Create DMAR table only if we have VT-d capability. */ - if (!soc_is_vtd_capable()) + if (!soc_vtd_enabled()) return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index dd42f31961d..a04869990db 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -509,7 +509,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchIoApicBdfValid = 0; /* Enable VT-d and X2APIC */ - if (soc_is_vtd_capable()) { + if (soc_vtd_enabled()) { params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; params->X2ApicOptOut = 0; diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index da9ba553fe1..9d917769ead 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -31,7 +31,7 @@ #define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_HI 0x58e4 -bool soc_is_vtd_capable(void); +bool soc_vtd_enabled(void); static const struct sa_mmio_descriptor soc_gfxvt_mmio_descriptor = { GFXVTBAR, diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 2b297670b1c..f11208720d0 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -6,15 +6,20 @@ #include #include #include +#include #include #include #include #include #include +#include #include "chip.h" -bool soc_is_vtd_capable(void) +bool soc_vtd_enabled(void) { + const unsigned int vtd = get_uint_option("vtd", 1); + if (!vtd) + return false; struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); return root_dev && !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); @@ -41,7 +46,7 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); - if (soc_is_vtd_capable()) { + if (soc_vtd_enabled()) { if (is_devfn_enabled(SA_DEVFN_IGD)) sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1); From e8b6b07bfc4cca2e7554ac8fecb6ddf88f89bc0e Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 14 Oct 2021 20:55:41 +0100 Subject: [PATCH 179/320] intel/tigerlake: Add missing IRQ for CNVi Add CNVi (14.3) to IRQ Table to stop dmesg error: iwlwifi 0000:00:14.3: can't derive routing for PCI INT F iwlwifi 0000:00:14.3: PCI INT F: not connected Signed-off-by: Sean Rhodes Change-Id: I5b793997f9ea954217871eb4656dacf6abe77e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58342 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/fsp_params.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 34ee9d8d17e..89c8126af04 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -164,6 +164,7 @@ static const struct slot_irq_constraints irq_constraints[] = { .slot = PCH_DEV_SLOT_XHCI, .fns = { ANY_PIRQ(PCH_DEVFN_XHCI), + FIXED_INT_ANY_PIRQ(PCH_DEVFN_CNVI_WIFI, PCI_INT_A), }, }, { From 12ae850dfc10709f8c3bcf92ab7ba1397eb4ae43 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Fri, 8 Oct 2021 09:57:14 +0000 Subject: [PATCH 180/320] libpayload: Add unit-tests framework and first test case This commit adds a unit-tests framework ported from coreboot, and test for drivers/speaker. Usage of the unit-tests framework is same as for the coreboot one. Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f Signed-off-by: Jakub Czapiga Reviewed-on: https://review.coreboot.org/c/coreboot/+/58242 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg Reviewed-by: Yu-Ping Wu --- payloads/libpayload/Makefile | 33 ++- payloads/libpayload/Makefile.inc | 4 +- payloads/libpayload/configs/config.unit-tests | 2 + payloads/libpayload/tests/Makefile.inc | 277 ++++++++++++++++++ .../libpayload/tests/drivers/Makefile.inc | 9 + .../libpayload/tests/drivers/speaker-test.c | 148 ++++++++++ .../libpayload/tests/include/mocks/x86_io.h | 30 ++ .../libpayload/tests/include/tests/test.h | 52 ++++ util/testing/Makefile.inc | 1 + 9 files changed, 549 insertions(+), 7 deletions(-) create mode 100644 payloads/libpayload/configs/config.unit-tests create mode 100644 payloads/libpayload/tests/Makefile.inc create mode 100644 payloads/libpayload/tests/drivers/Makefile.inc create mode 100644 payloads/libpayload/tests/drivers/speaker-test.c create mode 100644 payloads/libpayload/tests/include/mocks/x86_io.h create mode 100644 payloads/libpayload/tests/include/tests/test.h diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 923106248cd..ee83a0aeca9 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -114,17 +114,35 @@ ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 ARCH-$(CONFIG_LP_ARCH_MOCK) := mock -# Three cases where we don't need fully populated $(obj) lists: +# Five cases where we don't need fully populated $(obj) lists: # 1. when no .config exists # 2. when make config (in any flavour) is run # 3. when make distclean is run +# 4. when make help% or make clean% is run +# 5. when make %-test or make %-tests or make %coverage-report is run # Don't waste time on reading all Makefile.incs in these cases ifeq ($(strip $(HAVE_DOTCONFIG)),) -NOCOMPILE:=1 +NOCOMPILE := 1 endif ifneq ($(MAKECMDGOALS),) -ifneq ($(filter %config %clean,$(MAKECMDGOALS)),) -NOCOMPILE:=1 +ifneq ($(filter %config %clean clean-% help%,$(MAKECMDGOALS)),) +NOCOMPILE := 1 +endif +ifneq ($(filter %clean help% clean%, $(MAKECMDGOALS)),) +UNIT_TEST := 1 +endif +endif + +ifneq ($(filter help%, $(MAKECMDGOALS)),) +NOCOMPILE := 1 +UNIT_TEST := 1 +else +ifneq ($(filter %-test %-tests %coverage-report, $(MAKECMDGOALS)),) +ifneq ($(filter-out %-test %-tests %coverage-report, $(MAKECMDGOALS)),) +$(error Cannot mix unit-tests targets with other targets) +endif +NOCOMPILE := +UNIT_TEST := 1 endif endif @@ -135,6 +153,7 @@ $(xcompile): $(top)/../../util/xcompile/xcompile ifeq ($(NOCOMPILE),1) include $(TOPLEVEL)/Makefile.inc +include $(TOPLEVEL)/tests/Makefile.inc real-all: config else @@ -283,9 +302,13 @@ evaluate_subdirs= \ $(eval $(call includemakefiles,$(dir)/Makefile.inc))) \ $(if $(subdirs),$(eval $(call evaluate_subdirs))) -# collect all object files eligible for building +# collect all object files eligible for building or run unit-tests +ifneq ($(UNIT_TEST),1) subdirs:=$(TOPLEVEL) $(eval $(call evaluate_subdirs)) +else +include $(TOPLEVEL)/tests/Makefile.inc +endif src-to-obj=$(addsuffix .$(1).o, $(basename $(addprefix $(obj)/, $($(1)-srcs)))) $(foreach class,$(classes),$(eval $(class)-objs:=$(call src-to-obj,$(class)))) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index df0f14298f6..8e0a3d6f775 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -135,7 +135,7 @@ prepare: junit.xml: echo '' > $@.tmp - for i in $(filter-out %.old,$(wildcard configs/*)); do \ + for i in $(filter-out %.old %.unit-tests,$(wildcard configs/*)); do \ $(MAKE) clean; \ echo "Building libpayload for $$i"; \ cp "$$i" junit_config; \ @@ -158,7 +158,7 @@ junit.xml: mv $@.tmp $@ test-configs: - for config in $(filter-out %.old,$(wildcard configs/*)); do \ + for config in $(filter-out %.old %.unit-tests,$(wildcard configs/*)); do \ $(MAKE) clean; \ cp "$$config" test_config; \ echo "*** Making libpayload config $$config ***"; \ diff --git a/payloads/libpayload/configs/config.unit-tests b/payloads/libpayload/configs/config.unit-tests new file mode 100644 index 00000000000..dc1a49a2e57 --- /dev/null +++ b/payloads/libpayload/configs/config.unit-tests @@ -0,0 +1,2 @@ +CONFIG_LP_ARCH_MOCK=y +CONFIG_LP_ARCH_BIG_ENDIAN=n diff --git a/payloads/libpayload/tests/Makefile.inc b/payloads/libpayload/tests/Makefile.inc new file mode 100644 index 00000000000..9ae84426b80 --- /dev/null +++ b/payloads/libpayload/tests/Makefile.inc @@ -0,0 +1,277 @@ +# SPDX-License-Identifier: GPL-2.0-only + +testsrc := $(top)/tests + +# Place the build output in one of two places depending on COV, so that code +# built with code coverage never mixes with code built without code coverage. +ifeq ($(COV),1) +testobj := $(obj)/coverage +else +testobj := $(obj)/tests +endif +coverage-dir := $(testobj)/coverage_reports + +coreboottop := ../../ + +cmockasrc := $(coreboottop)/3rdparty/cmocka +cmockaobj := $(objutil)/cmocka +CMOCKA_LIB := $(cmockaobj)/src/libcmocka.so + +CMAKE := cmake + +TEST_DEFAULT_CONFIG := $(top)/configs/config.unit-tests +TEST_DOTCONFIG := $(testobj)/.config +TEST_KCONFIG_AUTOHEADER := $(testobj)/libpayload-config.src.h +TEST_KCONFIG_AUTOCONFIG := $(testobj)/auto.conf +TEST_KCONFIG_DEPENDENCIES := $(testobj)/auto.conf.cmd +TEST_KCONFIG_SPLITCONFIG := $(testobj)/config/ +TEST_KCONFIG_TRISTATE := $(testobj)/tristate.conf +TEST_KCONFIG_NEGATIVES := 1 +TEST_KBUILD_KCONFIG := $(top)/Kconfig +TEST_CONFIG_ := CONFIG_LP_ + + +# Default includes +TEST_CFLAGS := -include include/kconfig.h -include include/compiler.h +TEST_CFLAGS += -Iinclude -Iinclude/mock +TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) + +# Test specific includes +TEST_CFLAGS += -I$(testsrc)/include -I$(testsrc)/include/mocks +TEST_CFLAGS += -I$(cmockasrc)/include + +# Minimal subset of warnings and errors. Tests can be less strict than actual build. +TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla +TEST_CFLAGS += -Wwrite-strings -Wno-trigraphs -Wimplicit-fallthrough +TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror + +TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin + +# Make unit-tests detectable by the code +TEST_CFLAGS += -D__TEST__ + +# Link against CMocka +TEST_LDFLAGS := -L$(dir $(CMOCKA_LIB)) -lcmocka -Wl,-rpath=$(dir $(CMOCKA_LIB)) + +TEST_LDFLAGS += -Wl,--gc-sections + +# Disable userspace relocations +TEST_CFLAGS += -fno-pie -fno-pic +TEST_LDFLAGS += -no-pie + +ifeq ($(COV),1) +TEST_CFLAGS += --coverage +TEST_LDFLAGS += --coverage +endif + + +# Extra attributes for unit tests. Declated per each test. Only `srcs` is required. +attributes := cflags config mocks srcs + +alltests := +subdirs := tests/crypto tests/curses tests/drivers tests/gdb tests/libc tests/libcbfs +subdirs += tests/liblz4 tests/liblzma tests/libpci + +define tests-handler +alltests += $(1)$(2) +$(foreach attribute,$(attributes), \ + $(eval $(1)$(2)-$(attribute) += $($(2)-$(attribute)))) +$(foreach attribute,$(attributes), \ + $(eval $(2)-$(attribute) := )) +endef + +# Copy attributes of one test to another +# $1 - input test name +# $2 - output test name +copy-test = $(foreach attribute,$(attributes), \ + $(eval $(strip $(2))-$(attribute) := $($(strip $(1))-$(attribute)))) + +$(call add-special-class,tests) +$(call evaluate_subdirs) + +# Create actual targets for unit test binaries +# $1 - test name +define TEST_CC_template + +# Generate custom config.h redefining given config symbols, and declaring mocked +# functions weak. It is important that the compiler already sees that they are +# weak (and they aren't just turned weak at a later stage) to prevent certain +# optimizations that would break if the function gets replaced. (For clang this +# file needs to be marked `system_header` to prevent it from warning about +# `#pragma weak` entries without a matching function declaration, since there is +# no -Wno-xxx commandline for that.) +$(1)-config-file := $(testobj)/$(1)/libpayload-config.h +$$($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER) + mkdir -p $$(dir $$@); + printf '// File generated by tests/Makefile.inc\n// Do not change\n' > $$@; + printf '#ifndef TEST_LIBPAYLOAD_CONFIG_H_\n' >> $$@; + printf '#define TEST_LIBPAYLOAD_CONFIG_H_\n' >> $$@; + printf '#include <%s>\n\n' "$(notdir $(TEST_KCONFIG_AUTOHEADER))" >> $$@; + for kv in $$($(1)-config); do \ + key="`echo $$$$kv | cut -d '=' -f -1`"; \ + value="`echo $$$$kv | cut -d '=' -f 2-`"; \ + printf '#undef %s\n' "$$$$key" >> $$@; \ + printf '#define %s %s\n\n' "$$$$key" "$$$$value" >> $$@; \ + done + printf '#ifdef __clang__\n' >> $$@; + printf '#pragma clang system_header\n' >> $$@; + printf '#endif\n\n' >> $$@; + printf '#ifdef __TEST_SRCOBJ__\n' >> $$@; + for m in $$($(1)-mocks); do \ + printf '#pragma weak %s\n' "$$$$m" >> $$@; \ + done + printf '#endif\n\n' >> $$@; + printf '#endif\n' >> $$@; + +$($(1)-objs): TEST_CFLAGS += -I$$(dir $$($(1)-config-file)) \ + -D__TEST_NAME__=\"$(subst /,_,$(1))\" + +# Give us a way to distinguish between libpayload source files and test files in the code. +$($(1)-srcobjs): TEST_CFLAGS += -D__TEST_SRCOBJ__ + +# Compile sources and apply mocking/wrapping for selected symbols. +# For each listed mock add new symbol with prefix `__real_`, +# pointing to the same section:address. This will keep original +# function accessible if required. +$($(1)-objs): $(testobj)/$(1)/%.o: $$$$*.c $$($(1)-config-file) + mkdir -p $$(dir $$@) + $(HOSTCC) $$(TEST_CFLAGS) $($(1)-cflags) -MMD \ + -MF $$(basename $$@).d -MT $$@ -c $$< -o $$@.orig + objcopy_wrap_flags=''; \ + for sym in $$($(1)-mocks); do \ + sym_line="$$$$($(HOSTOBJDUMP) -t $$@.orig \ + | grep -E \"[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s$$$$sym$$$$\")"; \ + if [ ! -z "$$$$sym_line" ] ; then \ + addr="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$1 }')"; \ + section="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$(NF - 2) }')"; \ + objcopy_wrap_flags="$$$$objcopy_wrap_flags --add-symbol __real_$$$${sym}=$$$${section}:0x$$$${addr},function,global"; \ + fi \ + done ; \ + $(HOSTOBJCOPY) $$@.orig $$$$objcopy_wrap_flags $$@ + +$($(1)-bin): $($(1)-objs) $(CMOCKA_LIB) + $(HOSTCC) $$^ $($(1)-cflags) $$(TEST_LDFLAGS) -o $$@ + +endef + +$(foreach test,$(alltests), \ + $(eval $(test)-srcobjs := $(addprefix $(testobj)/$(test)/, \ + $(patsubst %.c,%.o,$(filter-out tests/%,$($(test)-srcs))))) \ + $(eval $(test)-objs := $(addprefix $(testobj)/$(test)/, \ + $(patsubst %.c,%.o,$($(test)-srcs)))) \ + $(eval $(test)-bin := $(testobj)/$(test)/run)) +$(foreach test,$(alltests), \ + $(eval $(call TEST_CC_template,$(test)))) +$(foreach test,$(alltests), \ + $(eval all-test-objs += $($(test)-objs)) \ + $(eval test-bins += $($(test)-bin))) + +DEPENDENCIES += $(addsuffix .d,$(basename $(all-test-objs))) +-include $(DEPENDENCIES) + +# Build CMocka +$(CMOCKA_LIB): + echo "*** Building CMOCKA ***" + mkdir -p $(cmockaobj) + cd $(cmockaobj) && $(CMAKE) $(abspath $(cmockasrc)) + $(MAKE) -C $(cmockaobj) + +# Kconfig targets +$(TEST_DOTCONFIG): + mkdir -p $(dir $@) + cp $(TEST_DEFAULT_CONFIG) $(TEST_DOTCONFIG) + +$(TEST_KCONFIG_AUTOHEADER): TEST_KCONFIG_FLAGS := DOTCONFIG=$(TEST_DOTCONFIG) \ + KCONFIG_AUTOHEADER=$(TEST_KCONFIG_AUTOHEADER) \ + KCONFIG_AUTOCONFIG=$(TEST_KCONFIG_AUTOCONFIG) \ + KCONFIG_DEPENDENCIES=$(TEST_KCONFIG_DEPENDENCIES) \ + KCONFIG_SPLITCONFIG=$(TEST_KCONFIG_SPLITCONFIG) \ + KCONFIG_TRISTATE=$(TEST_KCONFIG_TRISTATE) \ + KCONFIG_NEGATIVES=$(TEST_KCONFIG_NEGATIVES) \ + KBUILD_KCONFIG=$(TEST_KBUILD_KCONFIG) \ + KBUILD_DEFCONFIG=$(TEST_DEFAULT_CONFIG) \ + CONFIG_=$(TEST_CONFIG_) + +$(TEST_KCONFIG_AUTOHEADER): $(TEST_DOTCONFIG) $(objk)/conf + mkdir -p $(dir $@) + $(MAKE) $(TEST_KCONFIG_FLAGS) olddefconfig V=$(V) + $(MAKE) $(TEST_KCONFIG_FLAGS) syncconfig V=$(V) + +$(TEST_KCONFIG_AUTOCONFIG): $(TEST_KCONFIG_AUTOHEADER) + true + +.PHONY: $(alltests) $(addprefix clean-,$(alltests)) +.PHONY: unit-tests build-unit-tests run-unit-tests clean-unit-tests + +ifeq ($(JUNIT_OUTPUT),y) +$(alltests): export CMOCKA_MESSAGE_OUTPUT=xml +$(alltests): export CMOCKA_XML_FILE=$(testobj)/junit-%g.xml +endif + +$(alltests): $$($$(@)-bin) + rm -f $(testobj)/junit-libpayload-$(subst /,_,$(patsubst $(testobj)/%/,%,$(dir $^)))\(*\).xml + rm -f $(testobj)/$(subst /,_,$^).failed + -$^ || echo failed > $(testobj)/$(subst /,_,$^).failed + +# Build a code coverage report by collecting all the gcov files into a single +# report. If COV is not set, this might be a user error, and they're trying +# to generate a coverage report without first having built and run the code +# with code coverage. absence of COV=1 will be corrected. + +.PHONY: coverage-report clean-coverage-report + +ifeq ($(COV),1) +coverage-report: + lcov -o $(testobj)/tests.info -c -d $(testobj) --exclude '$(testsrc)/*' + genhtml -q -o $(coverage-dir) -t "coreboot unit tests" -s $(testobj)/tests.info + +clean-coverage-report: + rm -Rf $(coverage-dir) +else +coverage-report: + COV=1 V=$(V) $(MAKE) coverage-report + +clean-coverage-report: + COV=1 V=$(V) $(MAKE) clean-coverage-report +endif + +unit-tests: build-unit-tests run-unit-tests + +build-unit-tests: $(test-bins) + +run-unit-tests: $(alltests) + if [ `find $(testobj) -name '*.failed' | wc -l` -gt 0 ]; then \ + echo "**********************"; \ + echo " TESTS FAILED"; \ + echo "**********************"; \ + exit 1; \ + else \ + echo "**********************"; \ + echo " ALL TESTS PASSED"; \ + echo "**********************"; \ + exit 0; \ + fi + +$(addprefix clean-,$(alltests)): clean-% + rm -rf $(testobj)/$* + +clean-unit-tests: + rm -rf $(testobj) + +list-unit-tests: + @echo "unit-tests:" + for t in $(sort $(alltests)); do \ + echo " $$t"; \ + done + +help-unit-tests help:: + @echo '*** libpayload unit-tests targets ***' + @echo ' Use "COV=1 make [target]" to enable code coverage for unit tests' + @echo ' unit-tests - Run all unit-tests from tests/' + @echo ' clean-unit-tests - Remove unit-tests build artifacts' + @echo ' list-unit-tests - List all unit-tests' + @echo ' - Build and run single unit-test' + @echo ' clean- - Remove single unit-test build artifacts' + @echo ' coverage-report - Generate a code coverage report' + @echo ' clean-coverage-report - Remove the code coverage report' + @echo diff --git a/payloads/libpayload/tests/drivers/Makefile.inc b/payloads/libpayload/tests/drivers/Makefile.inc new file mode 100644 index 00000000000..e39921a33f9 --- /dev/null +++ b/payloads/libpayload/tests/drivers/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +tests-y += speaker-test + +speaker-test-srcs += tests/drivers/speaker-test.c +speaker-test-mocks += inb +speaker-test-mocks += outb +speaker-test-mocks += arch_ndelay +speaker-test-cflags += -include $(testsrc)/include/mocks/x86_io.h diff --git a/payloads/libpayload/tests/drivers/speaker-test.c b/payloads/libpayload/tests/drivers/speaker-test.c new file mode 100644 index 00000000000..199fa588649 --- /dev/null +++ b/payloads/libpayload/tests/drivers/speaker-test.c @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Include source to gain access to private defines */ +#include "../drivers/speaker.c" + +#include + +void outb(unsigned char val, int port) +{ + check_expected(val); + check_expected(port); +} + +unsigned char inb(int port) +{ + check_expected(port); + return mock_type(unsigned char); +} + +static void setup_speaker_enable_calls(u16 freq, u8 port_val) +{ + /* Minimal correct value should be at leaset 256. For values lowe than that, + counter will have an incorrect value. Regardless, there is */ + u16 reg16 = 1193180 / freq; + + /* Select counter 2 */ + expect_value(outb, val, 0xb6); + expect_value(outb, port, I82C54_CONTROL_WORD_REGISTER); + + /* Write freq. [LSB, MSB] */ + expect_value(outb, val, (u8)(reg16 & 0xff)); + expect_value(outb, port, I82C54_COUNTER2); + expect_value(outb, val, (u8)(reg16 >> 8)); + expect_value(outb, port, I82C54_COUNTER2); + + /* Enable PC speaker */ + expect_value(inb, port, PC_SPEAKER_PORT); + will_return(inb, port_val); + expect_value(outb, val, port_val | 0x3); + expect_value(outb, port, PC_SPEAKER_PORT); +} + +static void test_speaker_enable(void **state) +{ + setup_speaker_enable_calls(1, 0); + speaker_enable(1); + + setup_speaker_enable_calls(1, 0xff); + speaker_enable(1); + + setup_speaker_enable_calls(1, 123); + speaker_enable(1); + + setup_speaker_enable_calls(1, -1); + speaker_enable(1); + + setup_speaker_enable_calls(-1, 0); + speaker_enable(-1); + + setup_speaker_enable_calls(-1, 0xff); + speaker_enable(-1); + + setup_speaker_enable_calls(-1, 222); + speaker_enable(-1); + + setup_speaker_enable_calls(-1, -1); + speaker_enable(-1); + + setup_speaker_enable_calls(10000, 0); + speaker_enable(10000); + + setup_speaker_enable_calls(10000, 0xff); + speaker_enable(10000); + + setup_speaker_enable_calls(10000, 91); + speaker_enable(10000); + + setup_speaker_enable_calls(10000, -1); + speaker_enable(10000); +} + +static void setup_speaker_disable_calls(u8 value) +{ + expect_value(inb, port, PC_SPEAKER_PORT); + will_return(inb, value); + expect_value(outb, val, value & 0xfc); + expect_value(outb, port, PC_SPEAKER_PORT); +} + +static void test_speaker_disable(void **state) +{ + setup_speaker_disable_calls(0); + speaker_disable(); + + setup_speaker_disable_calls(0xfc); + speaker_disable(); + + setup_speaker_disable_calls(0xff); + speaker_disable(); + + setup_speaker_disable_calls(0xff - 0xfc); + speaker_disable(); +} + +void arch_ndelay(uint64_t ns) +{ + check_expected(ns); +} + +static void setup_speaker_tone_calls(u16 freq, unsigned int duration) +{ + setup_speaker_enable_calls(freq, ~freq & 0xff); + expect_value(arch_ndelay, ns, (uint64_t)duration * NSECS_PER_MSEC); + setup_speaker_disable_calls(0xff); + expect_any(arch_ndelay, ns); +} + +static void test_speaker_tone(void **state) +{ + setup_speaker_tone_calls(500, 100); + speaker_tone(500, 100); + + setup_speaker_tone_calls(4321, 0); + speaker_tone(4321, 0); + + setup_speaker_tone_calls(-1, -1); + speaker_tone(-1, -1); + + setup_speaker_tone_calls(10000, 1000); + speaker_tone(10000, 1000); + + setup_speaker_tone_calls(433, 890); + speaker_tone(433, 890); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_speaker_enable), + cmocka_unit_test(test_speaker_disable), + cmocka_unit_test(test_speaker_tone), + }; + + return lp_run_group_tests(tests, NULL, NULL); +} diff --git a/payloads/libpayload/tests/include/mocks/x86_io.h b/payloads/libpayload/tests/include/mocks/x86_io.h new file mode 100644 index 00000000000..c35a57263c2 --- /dev/null +++ b/payloads/libpayload/tests/include/mocks/x86_io.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef TESTS_MOCKS_X86_IO_H_ +#define TESTS_MOCKS_X86_IO_H_ + +unsigned int inl(int port); + +unsigned short inw(int port); + +unsigned char inb(int port); + +void outl(unsigned int val, int port); + +void outw(unsigned short val, int port); + +void outb(unsigned char val, int port); + +void outsl(int port, const void *addr, unsigned long count); + +void outsw(int port, const void *addr, unsigned long count); + +void outsb(int port, const void *addr, unsigned long count); + +void insl(int port, void *addr, unsigned long count); + +void insw(int port, void *addr, unsigned long count); + +void insb(int port, void *addr, unsigned long count); + +#endif diff --git a/payloads/libpayload/tests/include/tests/test.h b/payloads/libpayload/tests/include/tests/test.h new file mode 100644 index 00000000000..47f0fdc5f39 --- /dev/null +++ b/payloads/libpayload/tests/include/tests/test.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _TESTS_TEST_H +#define _TESTS_TEST_H + +/* + * Standard test header that should be included in all tests. For now it just encapsulates the + * include dependencies for Cmocka. Test-specific APIs that are so generic we would want them + * available everywhere could also be added here. + */ + +#include +#include +#include +#include +#include + +/* Helper macro to aviud checkpatch errors for some macros */ +#define EMPTY_WRAP(...) __VA_ARGS__ + +/* + * Set symbol value and make it global. + */ +#define TEST_SYMBOL(symbol, value) asm(".set " #symbol ", " #value "\n\t.globl " #symbol) + +/* + * Define memory region for testing purpose. + * + * Create buffer with specified name and size. + * Create end symbol for it. + */ +#define TEST_REGION(region, size) uint8_t _##region[size]; \ + TEST_SYMBOL(_e##region, _##region + size); \ + TEST_SYMBOL(_##region##_size, size) + +/* + * Set start, end and size symbols describing region without allocating memory for it. + */ +#define TEST_REGION_UNALLOCATED(region, start, size) EMPTY_WRAP( \ + TEST_SYMBOL(_##region, start); \ + TEST_SYMBOL(_e##region, _##region + size); \ + TEST_SYMBOL(_##region##_size, size) \ +) + +/* Wrapper for running cmocka test groups using name provided by build system in __TEST_NAME__ + This should be used instead of cmocka_run_group_tests(). If there is a need to use custom + group name, then please use cmocka_run_group_tests_name(). */ +#define lp_run_group_tests(group_tests, group_setup, group_teardown) \ + cmocka_run_group_tests_name((__TEST_NAME__ "(" #group_tests ")"), group_tests, \ + group_setup, group_teardown) + +#endif /* _TESTS_TEST_H */ diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index a390654045d..a9fd6488cc1 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -97,6 +97,7 @@ endif $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra124/lp0 BLD=tegra124_lp0 MFLAGS= MAKEFLAGS=xcompile=$(COREBOOT_BUILD_DIR)/xcompile MAKETARGET=all junit.xml $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra210/lp0 BLD=tegra120_lp0 MFLAGS= MAKEFLAGS=xcompile=$(COREBOOT_BUILD_DIR)/xcompile MAKETARGET=all junit.xml $(MAKE) unit-tests JUNIT_OUTPUT=y + (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) unit-tests JUNIT_OUTPUT=y) test-basic: test-lint test-tools test-abuild test-payloads test-cleanup From c2c38f5fdea0579d1a64ce63c00737bbe3ca5759 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 8 Oct 2021 13:10:38 -0600 Subject: [PATCH 181/320] arch/x86,cpu/x86,lib/thread: Remove usage of cpu_info from lib/thread We only ever start and execute threads on the BSP. By explicitly checking to see if the CPU is the BSP we can remove the dependency on cpu_info. With this change we can in theory enable threads in all stages. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify coop multithreading still works Suggested-by: Julius Werner Signed-off-by: Raul E Rangel Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58199 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/cpu.h | 3 --- src/cpu/x86/cpu_info.S.inc | 3 --- src/cpu/x86/lapic/lapic_cpu_init.c | 1 - src/cpu/x86/mp_init.c | 1 - src/include/thread.h | 7 ------- src/lib/thread.c | 23 +++++++++++++++-------- 6 files changed, 15 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 8e96fae2c2b..9a3b63d6b3b 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -231,9 +231,6 @@ struct thread; struct cpu_info { struct device *cpu; size_t index; -#if CONFIG(COOP_MULTITASKING) - struct thread *thread; -#endif }; /* diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc index dffd1bc3467..fc3e26d178f 100644 --- a/src/cpu/x86/cpu_info.S.inc +++ b/src/cpu/x86/cpu_info.S.inc @@ -2,9 +2,6 @@ /* Push struct cpu_info */ .macro push_cpu_info index=$0 -#if CONFIG(COOP_MULTITASKING) - push $0 /* *thread */ -#endif push \index /* index */ push $0 /* *cpu */ .endm diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index bc0f44fd90c..c35888a7fdb 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -253,7 +253,6 @@ static int start_cpu(struct device *cpu) info->index = index; info->cpu = cpu; cpu_add_map_entry(info->index); - thread_init_cpu_info_non_bsp(info); /* Advertise the new stack and index to start_cpu */ secondary_stack = stack_top; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 123b2b5eb5c..497ed3cfc56 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -193,7 +193,6 @@ static void asmlinkage ap_init(unsigned int cpu) info->cpu = cpus_dev[cpu]; cpu_add_map_entry(info->index); - thread_init_cpu_info_non_bsp(info); /* Fix up APIC id with reality. */ info->cpu->path.apic.apic_id = lapicid(); diff --git a/src/include/thread.h b/src/include/thread.h index cb085b55099..62c6283acf7 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -73,11 +73,6 @@ void thread_coop_disable(void); void thread_mutex_lock(struct thread_mutex *mutex); void thread_mutex_unlock(struct thread_mutex *mutex); -static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) -{ - ci->thread = NULL; -} - /* Architecture specific thread functions. */ asmlinkage void switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack); /* Set up the stack frame for a new thread so that a switch_to_thread() call @@ -96,8 +91,6 @@ static inline int thread_yield_microseconds(unsigned int microsecs) } static inline void thread_coop_enable(void) {} static inline void thread_coop_disable(void) {} -struct cpu_info; -static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { } static inline void thread_mutex_lock(struct thread_mutex *mutex) {} diff --git a/src/lib/thread.c b/src/lib/thread.c index 9008147eaeb..da6189d6f18 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -4,10 +4,10 @@ #include #include #include -#include #include #include #include +#include #include #include @@ -27,17 +27,25 @@ static struct thread all_threads[TOTAL_NUM_THREADS]; static struct thread *runnable_threads; static struct thread *free_threads; +static struct thread *active_thread; + static inline int thread_can_yield(const struct thread *t) { return (t != NULL && t->can_yield > 0); } +static inline void set_current_thread(struct thread *t) +{ + assert(boot_cpu()); + active_thread = t; +} + static inline struct thread *current_thread(void) { - if (!initialized) + if (!initialized || !boot_cpu()) return NULL; - return cpu_info()->thread; + return active_thread; } static inline int thread_list_empty(struct thread **list) @@ -108,7 +116,6 @@ __noreturn static enum cb_err idle_thread(void *unused) static void schedule(struct thread *t) { struct thread *current = current_thread(); - struct cpu_info *ci = cpu_info(); /* If t is NULL need to find new runnable thread. */ if (t == NULL) { @@ -123,7 +130,7 @@ static void schedule(struct thread *t) if (t->handle) t->handle->state = THREAD_STARTED; - ci->thread = t; + set_current_thread(t); switch_to_thread(t->stack_current, ¤t->stack_current); } @@ -239,14 +246,14 @@ static void threads_initialize(void) int i; struct thread *t; u8 *stack_top; - struct cpu_info *ci; if (initialized) return; t = &all_threads[0]; - ci = cpu_info(); - ci->thread = t; + + set_current_thread(t); + t->stack_orig = (uintptr_t)NULL; /* We never free the main thread */ t->id = 0; t->can_yield = 1; From 8e9db4eed5989cb2bffda11c2e10df5536e41ee3 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 8 Oct 2021 13:10:38 -0600 Subject: [PATCH 182/320] arch/x86/assembly_entry: Remove cpu_info Since cpu_info() is no longer required to use threads, we no longer need to initialize it in romstage or earlier. This code was also incomplete since it didn't initialize the %gs segment. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel Change-Id: I615b718e9f035ca68ecca9f57d7f4121db0c83b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58203 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/arch/x86/assembly_entry.S | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 4e7baf4427c..6e730273f84 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include /* @@ -36,8 +35,6 @@ _start: /* reset stack pointer to CAR/EARLYRAM stack */ mov $_STACK_TOP, %esp - push_cpu_info - /* clear .bss section as it is not shared */ cld xor %eax, %eax From db3e4b943a826eacbc2e38e0866b52cbaea1f19b Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 8 Oct 2021 13:10:38 -0600 Subject: [PATCH 183/320] cpu/x86/smm/smm_stub: Remove cpu_info Now that cpu_info() is no longer used by COOP_MULTITASKING, we no longer need to set up cpu_info in SMM. When using CPU_INFO_V2, if something does manage to call cpu_info() while executing in SMM mode, the %gs segment is disabled, so it will generate an exception. BUG=b:179699789 TEST=Boot guybrush to OS with threads enabled Signed-off-by: Raul E Rangel Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58204 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Paul Menzel --- src/cpu/x86/smm/smm_stub.S | 32 +------------------------------- 1 file changed, 1 insertion(+), 31 deletions(-) diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index e409983eaee..c83839cc013 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -9,7 +9,6 @@ * found in smm.h. */ -#include #include #include #include @@ -83,21 +82,8 @@ smm_relocate_gdt: /* gdt selector 0x20 tss segment */ .word 0xffff, 0x0000 .byte 0x00, 0x8b, 0x80, 0x00 - -#if CONFIG(CPU_INFO_V2) -per_cpu_segment_descriptors: - .rept CONFIG_MAX_CPUS - /* selgdt 0x28, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - .endr -#endif /* CPU_INFO_V2 */ smm_relocate_gdt_end: -#if CONFIG(CPU_INFO_V2) -.set per_cpu_segment_selector, per_cpu_segment_descriptors - smm_relocate_gdt -#endif /* CPU_INFO_V2 */ - .align 4 .code32 .global smm_trampoline32 @@ -109,7 +95,7 @@ smm_trampoline32: movw %ax, %ss xor %ax, %ax /* zero out the gs and fs segment index */ movw %ax, %fs - movw %ax, %gs /* Will be used for cpu_info */ + movw %ax, %gs /* Used by cpu_info in ramstage */ /* The CPU number is calculated by reading the initial APIC id. Since * the OS can manipulate the APIC id use the non-changing cpuid result @@ -167,22 +153,6 @@ apicid_end: movl $0, 4(%ebx) #endif -#if CONFIG(CPU_INFO_V2) - push_cpu_info index=%ecx - push_per_cpu_segment_data - - /* - * Update the AP's per_cpu_segment_descriptor to point to the - * per_cpu_segment_data that was allocated on the stack. - */ - set_segment_descriptor_base $per_cpu_segment_descriptors, %esp, %ecx - - mov %ecx, %eax - shl $3, %eax /* The index is << 3 in the segment selector */ - add $per_cpu_segment_selector, %eax - mov %eax, %gs -#endif - /* Create stack frame by pushing a NULL stack base pointer */ pushl $0x0 mov %esp, %ebp From 9ae922abf728814e10781a71f35803bd53d57524 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 8 Oct 2021 13:10:38 -0600 Subject: [PATCH 184/320] cpu/x86/cpu_info.S: Remove ebx save/restore The push/pop of %ebx was only added because smm_stub saves the canary value in it. Now that we no longer use cpu_info in smm, we no longer need to save the register. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58205 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/cpu/x86/cpu_info.S.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc index fc3e26d178f..9ffdd844444 100644 --- a/src/cpu/x86/cpu_info.S.inc +++ b/src/cpu/x86/cpu_info.S.inc @@ -28,12 +28,11 @@ * @desc_index: Index of the descriptor in the table. Defaults to 0. Must be a * register if specified. * - * Clobbers %eax. + * Clobbers %eax, %ebx. */ .macro set_segment_descriptor_base desc_array:req, base:req, desc_index mov \base, %eax - push %ebx /* preserve ebx */ mov \desc_array, %ebx .ifb \desc_index @@ -50,5 +49,4 @@ movb %al, 7(%ebx, \desc_index, 8) .endif - pop %ebx .endm From b54388df63f1a42b623e01ec03476712b4a08710 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 14 Feb 2021 15:09:45 +0200 Subject: [PATCH 185/320] ACPI: Have common acpi_fill_mcfg() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As long as there is only one PCI segment we do not need more complicated MCFG generation. Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/acpi/acpi.c | 10 +++++++++- src/include/acpi/acpi.h | 1 - src/mainboard/emulation/qemu-q35/acpi_tables.c | 8 -------- src/northbridge/intel/e7505/northbridge.c | 6 ------ src/northbridge/intel/gm45/acpi.c | 8 -------- src/northbridge/intel/haswell/acpi.c | 8 -------- src/northbridge/intel/i945/Makefile.inc | 1 - src/northbridge/intel/i945/acpi.c | 14 -------------- src/northbridge/intel/ironlake/Makefile.inc | 2 -- src/northbridge/intel/ironlake/acpi.c | 12 ------------ src/northbridge/intel/pineview/Makefile.inc | 1 - src/northbridge/intel/pineview/acpi.c | 13 ------------- src/northbridge/intel/sandybridge/acpi.c | 8 -------- src/northbridge/intel/x4x/acpi.c | 8 -------- src/soc/amd/common/block/acpi/tables.c | 12 ------------ src/soc/intel/baytrail/acpi.c | 7 ------- src/soc/intel/braswell/acpi.c | 7 ------- src/soc/intel/broadwell/acpi.c | 8 -------- src/soc/intel/common/block/acpi/acpi.c | 9 --------- src/soc/intel/denverton_ns/acpi.c | 9 --------- src/soc/intel/quark/acpi.c | 5 ----- src/southbridge/amd/agesa/hudson/lpc.c | 8 -------- src/southbridge/amd/cimx/sb800/late.c | 8 -------- src/southbridge/amd/pi/hudson/lpc.c | 10 ---------- src/southbridge/intel/i82371eb/acpi_tables.c | 6 ------ 25 files changed, 9 insertions(+), 180 deletions(-) delete mode 100644 src/northbridge/intel/i945/acpi.c delete mode 100644 src/northbridge/intel/ironlake/acpi.c delete mode 100644 src/northbridge/intel/pineview/acpi.c diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 6417ef891e1..282d734bd7b 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -263,6 +263,13 @@ void acpi_create_madt(acpi_madt_t *madt) header->checksum = acpi_checksum((void *)madt, header->length); } +static unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); + return current; +} + /* MCFG is defined in the PCI Firmware Specification 3.0. */ void acpi_create_mcfg(acpi_mcfg_t *mcfg) { @@ -284,7 +291,8 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) header->length = sizeof(acpi_mcfg_t); header->revision = get_acpi_table_revision(MCFG); - current = acpi_fill_mcfg(current); + if (CONFIG(MMCONF_SUPPORT)) + current = acpi_fill_mcfg(current); /* (Re)calculate length and checksum. */ header->length = current - (unsigned long)mcfg; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index bc0b30c720a..4f059bb947c 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1217,7 +1217,6 @@ unsigned long fw_cfg_acpi_tables(unsigned long start); /* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); -unsigned long acpi_fill_mcfg(unsigned long current); unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length); diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index ccf49c245b2..e85ce659f6f 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -12,11 +12,3 @@ void mainboard_fill_fadt(acpi_fadt_t *fadt) fadt->acpi_enable = 0; fadt->acpi_disable = 0; } - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER - 1); - return current; -} diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 4908ecd7a46..c03adbffc67 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -9,12 +9,6 @@ #include "e7505.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void mch_domain_read_resources(struct device *dev) { int idx; diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index d88fdb70130..30d3fedb157 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -11,14 +11,6 @@ #include "gm45.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} - static unsigned long acpi_fill_dmar(unsigned long current) { const struct device *dev; diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 15f2c5383a7..290dc1e9287 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -9,14 +9,6 @@ #include "haswell.h" #include -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} - static unsigned long acpi_fill_dmar(unsigned long current) { struct device *const igfx_dev = pcidev_on_root(2, 0); diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 8023d476148..e9702087e80 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -7,7 +7,6 @@ bootblock-y += bootblock.c ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c -ramstage-y += acpi.c romstage-y += romstage.c romstage-y += memmap.c diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c deleted file mode 100644 index 03c85de7d36..00000000000 --- a/src/northbridge/intel/i945/acpi.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include "i945.h" - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} diff --git a/src/northbridge/intel/ironlake/Makefile.inc b/src/northbridge/intel/ironlake/Makefile.inc index 89c9e16106e..afca10c5898 100644 --- a/src/northbridge/intel/ironlake/Makefile.inc +++ b/src/northbridge/intel/ironlake/Makefile.inc @@ -9,8 +9,6 @@ ramstage-y += northbridge.c ramstage-y += smi.c ramstage-y += gma.c -ramstage-y += acpi.c - romstage-y += memmap.c romstage-y += raminit.c romstage-y += raminit_tables.c diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c deleted file mode 100644 index 97676e7cbb2..00000000000 --- a/src/northbridge/intel/ironlake/acpi.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include "ironlake.h" - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 08e04f20e2c..b231a3e171a 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -8,7 +8,6 @@ bootblock-y += bootblock.c ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c -ramstage-y += acpi.c romstage-y += romstage.c romstage-y += memmap.c diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c deleted file mode 100644 index a04cb0b45ab..00000000000 --- a/src/northbridge/intel/pineview/acpi.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 608aa3c68cd..c2f6eae0e7d 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -9,14 +9,6 @@ #include "sandybridge.h" #include -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} - static unsigned long acpi_create_igfx_rmrr(const unsigned long current) { const u32 base_mask = ~(u32)(MiB - 1); diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 8f94b3454ba..44635c702d7 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -6,14 +6,6 @@ #include #include "x4x.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} - unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp) diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c index 8bad755de1a..ec484a97810 100644 --- a/src/soc/amd/common/block/acpi/tables.c +++ b/src/soc/amd/common/block/acpi/tables.c @@ -17,18 +17,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, return acpi_write_hpet(device, current, rsdp); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, - 0, - 0, - CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} - unsigned long acpi_fill_madt_irqoverride(unsigned long current) { const struct soc_amd_common_config *cfg = soc_get_common_config(); diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index b91134fe20c..e6c5abfcd3b 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -86,13 +86,6 @@ int acpi_sci_irq(void) return sci_irq; } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - return current; -} - unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 757358d0f58..d37799c92ca 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -108,13 +108,6 @@ int acpi_sci_irq(void) return sci_irq; } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - return current; -} - static acpi_tstate_t soc_tss_table[] = { { 100, 1000, 0, 0x00, 0 }, { 88, 875, 0, 0x1e, 0 }, diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 512f9f3d461..00e6807bd5c 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -21,14 +21,6 @@ #include #include -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER - 1); - return current; -} - static unsigned long acpi_fill_dmar(unsigned long current) { struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 6f7412740a7..f144a6d5fad 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -23,15 +23,6 @@ #define CPUID_6_EAX_ISST (1 << 7) -__attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ - current += acpi_create_mcfg_mmconfig((void *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER - 1); - return current; -} - static int acpi_sci_irq(void) { int sci_irq = 9; diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index a28da481346..b8b793e4df0 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -81,15 +81,6 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) return cstate_map; } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ - current += acpi_create_mcfg_mmconfig((void *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_MMCONF_BUS_NUMBER - 1); - return current; -} - void soc_fill_fadt(acpi_fadt_t *fadt) { u16 pmbase = get_pmbase(); diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index fc96fb6c3b8..9ea62bbcdb5 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -10,11 +10,6 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - return current; -} - void acpi_fill_fadt(acpi_fadt_t *fadt) { struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index b80bb6ad35d..9bf928ec565 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -318,14 +318,6 @@ static const char *lpc_acpi_name(const struct device *dev) return NULL; } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} - static void lpc_final(struct device *dev) { if (!acpi_is_wakeup_s3()) { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b6cc3c777b5..4a5895b09ba 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -121,14 +121,6 @@ static void lpc_init(struct device *dev) printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); - - return current; -} - static const char *lpc_acpi_name(const struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index b77548ecbb8..77d39c5e915 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -318,16 +318,6 @@ static void hudson_lpc_enable_resources(struct device *dev) hudson_lpc_enable_childrens_resources(dev); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, - 0, - 0, - CONFIG_MMCONF_BUS_NUMBER - 1); - return current; -} - static const char *lpc_acpi_name(const struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 41fc4eeaa10..5d4ca699a92 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -38,9 +38,3 @@ void generate_cpu_entries(const struct device *device) } acpigen_pop_len(); } - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* chipset doesn't have mmconfig */ - return current; -} From 1e1078d6999f8a94ff35bd43a948721649b84f91 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 8 Sep 2021 23:03:56 +0200 Subject: [PATCH 186/320] build system: immediately report what users are supposed to look into Instead of just logging "Check out that file over there for this type of values", why not emit them directly? Change-Id: I54630afce4011ab9ee3eda415e95d5b7d5812e6b Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/57508 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- toolchain.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/toolchain.inc b/toolchain.inc index 80dab78d633..893f7d1a11a 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -108,7 +108,8 @@ standard-archs = $(sort $(foreach stagearch, \ # e.g.: smm special class uses i386 as compiler set define create_class_compiler $(if $(2),,$(warning *** The toolchain architecture for $(1) is unknown.) \ - $(error Check your .config file for CONFIG_ARCH_$(1)_* settings)) + $(warning CONFIG_ARCH_$(1)_* settings in $(DOTCONFIG):) \ + $(error $(shell grep CONFIG_ARCH_$(1)_ $(DOTCONFIG)))) CC_$(1) := $(CC_$(2)) GCC_$(1) := $(GCC_CC_$(2)) LD_$(1) := $(LD_$(2)) From dcb26139cad89f078403c375b5cb8ca38456caaf Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Sat, 24 Jul 2021 21:17:29 +0530 Subject: [PATCH 187/320] sc7280: Add GSI FW download support Add GSI Firmware download support for QUP wrappers. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil Change-Id: I68c106c942acadc752351f03843d93612cf9c19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56590 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/soc/qualcomm/sc7280/Makefile.inc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 442b2a3858c..9c02826ae0e 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -110,4 +110,12 @@ $(SHRM_CBFS)-type := payload $(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) cbfs-files-y += $(SHRM_CBFS) +################################################################################ +GSI_FW_FILE := $(SC7280_BLOB)/qup_fw/gsi_fw.bin +GSI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/gsi_fw +$(GSI_FW_CBFS)-file := $(GSI_FW_FILE) +$(GSI_FW_CBFS)-type := raw +$(GSI_FW_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(GSI_FW_CBFS) + endif From 967730f5656e433094d97e65ce6927734d7112c7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 17 Jul 2021 11:43:44 +0200 Subject: [PATCH 188/320] kconfig_lint: Drop overly restrictive rule about choice configs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This rule was creating trouble: * A symbol may only be declared inside or outside a choice. The linter treats every occurence of a `config` entry as a symbol declaration, even when it's just setting a default or adding selects. This is not easy to fix as the symbol objects are not created first and then added to the $symbols array when we know what kind of decla- ration we have, but are created incrementally inside this global list. Change-Id: I48a17f6403470251be6b6d44bb82a8bdcbefe9f6 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/56410 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- util/lint/kconfig_lint | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 7f26ef298f4..76dd78764c4 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -814,16 +814,7 @@ sub add_symbol { } else { $symbols{$symbol}{count}++; - - if ( $inside_choice && !$symbols{$symbol}{choice} ) { - show_error( "$symbol entry at $filename:$line_no has already been created inside a choice block " - . "at $symbols{$symbol}{0}{file}:$symbols{$symbol}{0}{line_no}." ); - } - elsif ( !$inside_choice && $symbols{$symbol}{choice} ) { - show_error( "$symbol entry at $filename:$line_no has already been created outside a choice block " - . "at $symbols{$symbol}{0}{file}:$symbols{$symbol}{0}{line_no}." ); - } - elsif ( $inside_choice && $symbols{$symbol}{choice} ) { + if ( $inside_choice && $symbols{$symbol}{choice} ) { show_error( "$symbol entry at $filename:$line_no has already been created inside another choice block " . "at $symbols{$symbol}{0}{file}:$symbols{$symbol}{0}{line_no}." ); } From 2bfef8d856f9f5cc0fcadefd1fd92c249ac6bfd8 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 25 Jun 2021 23:55:51 -0700 Subject: [PATCH 189/320] cbfstool: Add helper function `buffer_from_file_aligned_size` This change adds a helper function `buffer_from_file_aligned_size` that loads a file into memory buffer by creating a memory buffer of size rounded up to the provided `size_granularity` parameter. BUG=b:189177186,b:189167923 Change-Id: Iad3430d476abcdad850505ac50e36cd5d5deecb4 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/55989 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Tim Wawrzynczak --- util/cbfstool/common.c | 16 +++++++++++++--- util/cbfstool/common.h | 5 +++++ 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 539d0baccf5..5889e2a937f 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -49,7 +49,8 @@ int buffer_create(struct buffer *buffer, size_t size, const char *name) return (buffer->data == NULL); } -int buffer_from_file(struct buffer *buffer, const char *filename) +int buffer_from_file_aligned_size(struct buffer *buffer, const char *filename, + size_t size_granularity) { FILE *fp = fopen(filename, "rb"); if (!fp) { @@ -63,20 +64,29 @@ int buffer_from_file(struct buffer *buffer, const char *filename) fclose(fp); return -1; } - buffer->size = file_size; + buffer->size = ALIGN_UP(file_size, size_granularity); buffer->name = strdup(filename); buffer->data = (char *)malloc(buffer->size); assert(buffer->data); - if (fread(buffer->data, 1, buffer->size, fp) != buffer->size) { + if (fread(buffer->data, 1, file_size, fp) != (size_t)file_size) { fprintf(stderr, "incomplete read: %s\n", filename); fclose(fp); buffer_delete(buffer); return -1; } fclose(fp); + + if (buffer->size > (size_t)file_size) + memset(buffer->data + file_size, 0xff, buffer->size - file_size); + return 0; } +int buffer_from_file(struct buffer *buffer, const char *filename) +{ + return buffer_from_file_aligned_size(buffer, filename, 1); +} + int buffer_write_file(struct buffer *buffer, const char *filename) { FILE *fp = fopen(filename, "wb"); diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 07ffdf82317..b23c8d21b0a 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -132,6 +132,11 @@ int buffer_create(struct buffer *buffer, size_t size, const char *name); /* Loads a file into memory buffer. Returns 0 on success, otherwise non-zero. */ int buffer_from_file(struct buffer *buffer, const char *filename); +/* Loads a file into memory buffer (with buffer size rounded up to a multiple of + size_granularity). Returns 0 on success, otherwise non-zero. */ +int buffer_from_file_aligned_size(struct buffer *buffer, const char *filename, + size_t size_granularity); + /* Writes memory buffer content into file. * Returns 0 on success, otherwise non-zero. */ int buffer_write_file(struct buffer *buffer, const char *filename); From 768cb760e1bab4c398923146a5ee9c8468897649 Mon Sep 17 00:00:00 2001 From: Kenneth Chan Date: Thu, 14 Oct 2021 11:41:02 +0800 Subject: [PATCH 190/320] mb/google/guybrush/dewatt: update DRAM table Samsung LPDDR4X 4266 2G K4U6E3S4AB-MGCL Hynix LPDDR4X 4266 2G H54G46CYRBX267 Micron LPDDR4X 4266 2G MT53E512M32D1NP-046 WT:B Micron LPDDR4X 4266 4G MT53E1G32D2NP-046 WT:B BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan Change-Id: I31ec5b84b5ad2e8d0aedf41ceb56f9e5f7fa538a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58313 Reviewed-by: Rob Barnes Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../guybrush/variants/dewatt/memory/Makefile.inc | 11 +++++++---- .../variants/dewatt/memory/dram_id.generated.txt | 9 +++++++++ .../variants/dewatt/memory/mem_parts_used.txt | 15 ++++----------- 3 files changed, 20 insertions(+), 15 deletions(-) diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc index 6751a4283f6..069b2eb0bfa 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc @@ -1,5 +1,8 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt index fa247902eee..5ce9e79cdc3 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt @@ -1 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K4U6E3S4AB-MGCL 0 (0000) +H54G46CYRBX267 0 (0000) +MT53E1G32D2NP-046 WT:B 1 (0001) +MT53E512M32D1NP-046 WT:B 0 (0000) diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt index 416b512673a..4b6ba225ac5 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt @@ -1,11 +1,4 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name, Fixed ID (optional) +K4U6E3S4AB-MGCL +H54G46CYRBX267 +MT53E1G32D2NP-046 WT:B +MT53E512M32D1NP-046 WT:B From 35360a9e66156042f2d9e4a8aec0ab2b9672ba89 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 18 Oct 2021 13:57:50 +0200 Subject: [PATCH 191/320] soc/amd/common/block/include/psp_efs: rename embedded_firmware elements The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held Change-Id: Ia70e97f10f4fa0ac63cc65a33ecdc956538482b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58418 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Kangheui Won --- src/soc/amd/common/block/include/amdblocks/psp_efs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index 0da7ff79aaa..c5c13a28373 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -35,8 +35,8 @@ typedef struct _embedded_firmware { uint32_t imc_entry; uint32_t gec_entry; uint32_t xhci_entry; - uint32_t psp_entry; - uint32_t comboable; + uint32_t psp_directory; + uint32_t combo_psp_directory; uint32_t bios0_entry; uint32_t bios1_entry; uint32_t bios2_entry; From ad68b07d45fdc2489ec008d77466d116352db1b2 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 18 Oct 2021 14:00:35 +0200 Subject: [PATCH 192/320] util/amdfwtool: rename PSP related embedded_firmware struct elements The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Kangheui Won --- util/amdfwtool/amdfwtool.c | 6 +++--- util/amdfwtool/amdfwtool.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index d051582498f..9ad913e6f1b 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1587,13 +1587,13 @@ int main(int argc, char **argv) } if (comboable) - amd_romsig->comboable = BUFF_TO_RUN(ctx, pspdir); + amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, pspdir); else - amd_romsig->psp_entry = BUFF_TO_RUN(ctx, pspdir); + amd_romsig->psp_directory = BUFF_TO_RUN(ctx, pspdir); #if PSP_COMBO psp_combo_directory *combo_dir = new_combo_dir(&ctx); - amd_romsig->comboable = BUFF_TO_RUN(ctx, combo_dir); + amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, combo_dir); /* 0 -Compare PSP ID, 1 -Compare chip family ID */ combo_dir->entries[0].id_sel = 0; /* TODO: PSP ID. Documentation is needed. */ diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index d246af79322..d7f0f5db968 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -86,8 +86,8 @@ typedef struct _embedded_firmware { uint32_t imc_entry; uint32_t gec_entry; uint32_t xhci_entry; - uint32_t psp_entry; - uint32_t comboable; + uint32_t psp_directory; + uint32_t combo_psp_directory; uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; From 3c1c90bf6107f34cf35e66dc92762ba02799e9ff Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 18 Oct 2021 14:04:01 +0200 Subject: [PATCH 193/320] soc/amd/common/block/include/psp_efs: don't typedef struct Don't use a typedef for the embedded_firmware struct so that it's clearer that this is a struct. TEST=Timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held Change-Id: I97a02c350af57c8f58014aaf7dda8b4796905ff3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58420 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Kangheui Won --- src/soc/amd/common/block/include/amdblocks/psp_efs.h | 4 ++-- src/soc/amd/common/block/psp/psp_efs.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index c5c13a28373..1a6059a1be7 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -30,7 +30,7 @@ struct second_gen_efs { /* todo: expand for Server products */ } __attribute__((packed)); /* Copied from coreboot/util/amdfwtool.h */ -typedef struct _embedded_firmware { +struct embedded_firmware { uint32_t signature; /* 0x55aa55aa */ uint32_t imc_entry; uint32_t gec_entry; @@ -60,7 +60,7 @@ typedef struct _embedded_firmware { uint8_t reserved_4Ah; uint8_t reserved_4Bh; uint32_t reserved_4Ch; -} __attribute__((packed, aligned(16))) embedded_firmware; +} __attribute__((packed, aligned(16))); bool efs_is_valid(void); bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed); diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c index 5814f48c638..feb0276463b 100644 --- a/src/soc/amd/common/block/psp/psp_efs.c +++ b/src/soc/amd/common/block/psp/psp_efs.c @@ -6,7 +6,7 @@ #include #include -static struct _embedded_firmware *efs; +static struct embedded_firmware *efs; bool efs_is_valid(void) { From 3b9be63bd32daff1083f38b409beab71f2655b4f Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Mon, 18 Oct 2021 16:14:24 -0600 Subject: [PATCH 194/320] arch/x86: Increase MAX_SMBIOS_SIZE With the recent addition of SMBIOS table 20, the cbmem area on google/brya0 overflows and ERROR: Increase SMBIOS size SMBIOS tables: 2128 bytes. is seen in the logs. Therefore, double the size of the SMBIOS area from 2 KiB to 4 KiB to accomodate more tables as needed. This happens during ramstage so 2k is not a big deal at this point. Change-Id: I43aa6a88d176e783cc9a4441b35b8d608c4101cd Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/58432 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Angel Pons --- src/arch/x86/tables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 492674c5a97..09ec0eaaa36 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -143,7 +143,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) { unsigned long high_table_pointer; -#define MAX_SMBIOS_SIZE 2048 +#define MAX_SMBIOS_SIZE (4 * KiB) high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE); From 14643b33b0f7ea9cde6ce8230793562d4a1b475c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 17 Oct 2021 13:21:05 +0200 Subject: [PATCH 195/320] soc/intel/*/acpi.c: Don't copy structs with `memcpy()` A regular assignment works just as well and also allows type-checking. Change-Id: Id772771f000ba3bad5d4af05f5651c0f0ee43d6d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58390 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/intel/alderlake/acpi.c | 2 +- src/soc/intel/cannonlake/acpi.c | 2 +- src/soc/intel/elkhartlake/acpi.c | 2 +- src/soc/intel/icelake/acpi.c | 2 +- src/soc/intel/jasperlake/acpi.c | 2 +- src/soc/intel/tigerlake/acpi.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 9f4fa880a05..075b4d66238 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -131,7 +131,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) } for (i = 0; i < *entries; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i] = cstate_map[set[i]]; map[i].ctype = i + 1; } return map; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index d0f38747cbc..5e2d1425d32 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -131,7 +131,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) } for (i = 0; i < *entries; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i] = cstate_map[set[i]]; map[i].ctype = i + 1; } return map; diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 7531331d25f..e44a5d4ebaa 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -130,7 +130,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) } for (i = 0; i < *entries; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i] = cstate_map[set[i]]; map[i].ctype = i + 1; } return map; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index fa6d038a515..f822e8323b2 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -127,7 +127,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) } for (i = 0; i < *entries; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i] = cstate_map[set[i]]; map[i].ctype = i + 1; } return map; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index cc7b8ae62fd..28ed1f19704 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -130,7 +130,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) } for (i = 0; i < *entries; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i] = cstate_map[set[i]]; map[i].ctype = i + 1; } return map; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index e560f11f696..bf032693448 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -130,7 +130,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) } for (i = 0; i < *entries; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i] = cstate_map[set[i]]; map[i].ctype = i + 1; } return map; From d2794cea1291f7f6e35b426b8b66cbb08da6d532 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 17 Oct 2021 12:59:43 +0200 Subject: [PATCH 196/320] acpi/acpigen: Constify CST functions' pointers The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry` functions don't modify the provided C-state information. So, make the pointer parameters read-only to enforce this. Also constify arguments where possible. Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Felix Held --- src/acpi/acpigen.c | 4 ++-- src/include/acpi/acpigen.h | 4 ++-- src/soc/amd/cezanne/acpi.c | 2 +- src/soc/amd/picasso/acpi.c | 2 +- src/soc/intel/baytrail/acpi.c | 2 +- src/soc/intel/braswell/acpi.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index c8f14378c91..e0892e654f9 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -994,7 +994,7 @@ void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) acpigen_pop_len(); } -void acpigen_write_CST_package_entry(acpi_cstate_t *cstate) +void acpigen_write_CST_package_entry(const acpi_cstate_t *cstate) { acpigen_write_package(4); acpigen_write_register_resource(&cstate->resource); @@ -1004,7 +1004,7 @@ void acpigen_write_CST_package_entry(acpi_cstate_t *cstate) acpigen_pop_len(); } -void acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) +void acpigen_write_CST_package(const acpi_cstate_t *cstate, int nentries) { int i; acpigen_write_name("_CST"); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index c019130e288..cf14c7f39d0 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -357,8 +357,8 @@ void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries); typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord; void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); -void acpigen_write_CST_package_entry(acpi_cstate_t *cstate); -void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); +void acpigen_write_CST_package_entry(const acpi_cstate_t *cstate); +void acpigen_write_CST_package(const acpi_cstate_t *entry, int nentries); typedef enum { CSD_HW_ALL = 0xfe } CSD_coord; void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index); diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 3b3a88befe8..d390ca4f220 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -279,7 +279,7 @@ void generate_cpu_entries(const struct device *device) .addrl = PS_STS_REG, }; - acpi_cstate_t cstate_info[] = { + const acpi_cstate_t cstate_info[] = { [0] = { .ctype = 1, .latency = 1, diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 99c1648f8a7..c0808d9f2e4 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -289,7 +289,7 @@ void generate_cpu_entries(const struct device *device) .addrl = PS_STS_REG, }; - acpi_cstate_t cstate_info[] = { + const acpi_cstate_t cstate_info[] = { [0] = { .ctype = 1, .latency = 1, diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index e6c5abfcd3b..0f9768793eb 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -28,7 +28,7 @@ } /* C-state map without S0ix */ -static acpi_cstate_t cstate_map[] = { +static const acpi_cstate_t cstate_map[] = { { /* C1 */ .ctype = 1, /* ACPI C1 */ diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index d37799c92ca..85e70276e40 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -36,7 +36,7 @@ } /* C-state map without S0ix */ -static acpi_cstate_t cstate_map[] = { +static const acpi_cstate_t cstate_map[] = { { /* C1 */ .ctype = 1, /* ACPI C1 */ From e9f10ff38bf95000115d7c0a45cb0e6323cc61c8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 17 Oct 2021 13:28:23 +0200 Subject: [PATCH 197/320] soc/intel: Constify `soc_get_cstate_map()` Return a read-only pointer from the `soc_get_cstate_map()` function. Also, constify the actual data where applicable. Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/intel/alderlake/acpi.c | 2 +- src/soc/intel/apollolake/acpi.c | 4 ++-- src/soc/intel/cannonlake/acpi.c | 2 +- src/soc/intel/common/block/acpi/acpi.c | 2 +- src/soc/intel/common/block/include/intelblocks/acpi.h | 2 +- src/soc/intel/denverton_ns/acpi.c | 4 ++-- src/soc/intel/elkhartlake/acpi.c | 2 +- src/soc/intel/icelake/acpi.c | 2 +- src/soc/intel/jasperlake/acpi.c | 2 +- src/soc/intel/tigerlake/acpi.c | 2 +- src/soc/intel/xeon_sp/acpi.c | 2 +- 11 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 075b4d66238..ab25646f87f 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -111,7 +111,7 @@ static int cstate_set_s0ix[] = { C_STATE_C10 }; -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), ARRAY_SIZE(cstate_set_non_s0ix))]; diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 8f5dd12459f..6e3bde4bb99 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -30,7 +30,7 @@ .addrl = address, \ } -static acpi_cstate_t cstate_map[] = { +static const acpi_cstate_t cstate_map[] = { { /* C1 */ .ctype = 1, /* ACPI C1 */ @@ -62,7 +62,7 @@ void soc_write_sci_irq_select(uint32_t scis) write32p(soc_read_pmc_base() + IRQ_REG, scis); } -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { *entries = ARRAY_SIZE(cstate_map); return cstate_map; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 5e2d1425d32..fa84ea8ef42 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -111,7 +111,7 @@ static int cstate_set_s0ix[] = { C_STATE_C10 }; -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), ARRAY_SIZE(cstate_set_non_s0ix))]; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index f144a6d5fad..af7212e70e4 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -248,7 +248,7 @@ int common_calculate_power_ratio(int tdp, int p1_ratio, int ratio) static void generate_c_state_entries(void) { - acpi_cstate_t *c_state_map; + const acpi_cstate_t *c_state_map; size_t entries; c_state_map = soc_get_cstate_map(&entries); diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 5497275d233..02a9da58cf5 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -38,7 +38,7 @@ void soc_write_sci_irq_select(uint32_t scis); * get_cstate_map returns a table of processor specific acpi_cstate_t entries * and number of entries in the table */ -acpi_cstate_t *soc_get_cstate_map(size_t *num_entries); +const acpi_cstate_t *soc_get_cstate_map(size_t *num_entries); /* * get_tstate_map returns a table of processor specific acpi_tstate_t entries diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index b8b793e4df0..82b8cf111fb 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -27,7 +27,7 @@ .addrl = address, \ } -static acpi_cstate_t cstate_map[] = { +static const acpi_cstate_t cstate_map[] = { { /* C1 */ .ctype = 1, /* ACPI C1 */ @@ -75,7 +75,7 @@ uint32_t soc_read_sci_irq_select(void) return pci_read_config32(dev, PMC_ACPI_CNT); } -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { *entries = ARRAY_SIZE(cstate_map); return cstate_map; diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index e44a5d4ebaa..44387ea3f4f 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -110,7 +110,7 @@ static int cstate_set_s0ix[] = { C_STATE_C10 }; -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), ARRAY_SIZE(cstate_set_non_s0ix))]; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index f822e8323b2..d11f3ca8fff 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -107,7 +107,7 @@ static int cstate_set_s0ix[] = { C_STATE_C10 }; -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), ARRAY_SIZE(cstate_set_non_s0ix))]; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 28ed1f19704..ad6a79cba69 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -110,7 +110,7 @@ static int cstate_set_s0ix[] = { C_STATE_C10 }; -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), ARRAY_SIZE(cstate_set_non_s0ix))]; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index bf032693448..36fb6797493 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -110,7 +110,7 @@ static int cstate_set_s0ix[] = { C_STATE_C10 }; -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), ARRAY_SIZE(cstate_set_non_s0ix))]; diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 9da1b145952..de9db88bad9 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -58,7 +58,7 @@ static int cstate_set_c1_c6[] = { C_STATE_C6, }; -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { static acpi_cstate_t map[ARRAY_SIZE(cstate_set_all)]; int *cstate_set; From afd268a0cb440c1ccfaec5593bffbfe49bcfbf24 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 17 Oct 2021 13:35:23 +0200 Subject: [PATCH 198/320] cpu/intel/speedstep: Constify `get_cst_entries()` Make the `get_cst_entries()` function provide a read-only pointer. Also, constify the actual data where applicable. Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/cpu/intel/speedstep/acpi.c | 2 +- src/include/acpi/acpigen.h | 2 +- src/mainboard/acer/g43t-am3/cstates.c | 2 +- src/mainboard/apple/macbook21/cstates.c | 4 ++-- src/mainboard/asrock/g41c-gs/cstates.c | 2 +- src/mainboard/asus/p5gc-mx/cstates.c | 2 +- src/mainboard/asus/p5qc/cstates.c | 2 +- src/mainboard/asus/p5ql-em/cstates.c | 2 +- src/mainboard/asus/p5qpl-am/cstates.c | 2 +- src/mainboard/foxconn/d41s/cstates.c | 2 +- src/mainboard/foxconn/g41s-k/cstates.c | 2 +- src/mainboard/getac/p470/cstates.c | 4 ++-- src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c | 2 +- src/mainboard/gigabyte/ga-d510ud/cstates.c | 2 +- src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 4 ++-- src/mainboard/ibase/mb899/cstates.c | 2 +- src/mainboard/intel/d510mo/cstates.c | 2 +- src/mainboard/intel/d945gclf/cstates.c | 2 +- src/mainboard/intel/dg41wv/cstates.c | 2 +- src/mainboard/intel/dg43gt/cstates.c | 2 +- src/mainboard/kontron/986lcd-m/cstates.c | 2 +- src/mainboard/lenovo/t400/cstates.c | 4 ++-- src/mainboard/lenovo/t60/cstates.c | 4 ++-- src/mainboard/lenovo/thinkcentre_a58/cstates.c | 2 +- src/mainboard/lenovo/x200/cstates.c | 4 ++-- src/mainboard/lenovo/x60/cstates.c | 4 ++-- src/mainboard/roda/rk886ex/cstates.c | 2 +- src/mainboard/roda/rk9/cstates.c | 4 ++-- 28 files changed, 36 insertions(+), 36 deletions(-) diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index f1c5b9966b7..b340b6d511f 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -88,7 +88,7 @@ void generate_cpu_entries(const struct device *device) CPUs share the same layout. */ int num_cstates; - acpi_cstate_t *cstates; + const acpi_cstate_t *cstates; sst_table_t pstates; uint8_t coordination; diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index cf14c7f39d0..3af0959cfd4 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -499,7 +499,7 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou void acpigen_write_indexfield(const char *idx, const char *data, struct fieldlist *l, size_t count, uint8_t flags); -int get_cst_entries(acpi_cstate_t **); +int get_cst_entries(const acpi_cstate_t **); /* * Get element from package into specified destination op: diff --git a/src/mainboard/acer/g43t-am3/cstates.c b/src/mainboard/acer/g43t-am3/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/acer/g43t-am3/cstates.c +++ b/src/mainboard/acer/g43t-am3/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c index 8f295040f77..13d06f0839b 100644 --- a/src/mainboard/apple/macbook21/cstates.c +++ b/src/mainboard/apple/macbook21/cstates.c @@ -2,7 +2,7 @@ #include -static acpi_cstate_t cst_entries[] = { +static const acpi_cstate_t cst_entries[] = { { .ctype = 1, .latency = 1, @@ -31,7 +31,7 @@ static acpi_cstate_t cst_entries[] = { }, }; -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/mainboard/asrock/g41c-gs/cstates.c b/src/mainboard/asrock/g41c-gs/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/asrock/g41c-gs/cstates.c +++ b/src/mainboard/asrock/g41c-gs/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/asus/p5gc-mx/cstates.c b/src/mainboard/asus/p5gc-mx/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/asus/p5gc-mx/cstates.c +++ b/src/mainboard/asus/p5gc-mx/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/asus/p5qc/cstates.c b/src/mainboard/asus/p5qc/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/asus/p5qc/cstates.c +++ b/src/mainboard/asus/p5qc/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/asus/p5ql-em/cstates.c b/src/mainboard/asus/p5ql-em/cstates.c index 791f78e38db..7f17b9f11e0 100644 --- a/src/mainboard/asus/p5ql-em/cstates.c +++ b/src/mainboard/asus/p5ql-em/cstates.c @@ -3,7 +3,7 @@ #include /* TODO: Could work... */ -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/asus/p5qpl-am/cstates.c b/src/mainboard/asus/p5qpl-am/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/asus/p5qpl-am/cstates.c +++ b/src/mainboard/asus/p5qpl-am/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/foxconn/d41s/cstates.c b/src/mainboard/foxconn/d41s/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/foxconn/d41s/cstates.c +++ b/src/mainboard/foxconn/d41s/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/foxconn/g41s-k/cstates.c b/src/mainboard/foxconn/g41s-k/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/foxconn/g41s-k/cstates.c +++ b/src/mainboard/foxconn/g41s-k/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c index 2b9997e3019..6c2d8bfcdb2 100644 --- a/src/mainboard/getac/p470/cstates.c +++ b/src/mainboard/getac/p470/cstates.c @@ -3,7 +3,7 @@ #include #include -static acpi_cstate_t cst_entries[] = { +static const acpi_cstate_t cst_entries[] = { { /* ACPI C1 / CPU C1 */ 1, 0x01, 1000, @@ -21,7 +21,7 @@ static acpi_cstate_t cst_entries[] = { }, }; -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/gigabyte/ga-d510ud/cstates.c b/src/mainboard/gigabyte/ga-d510ud/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/gigabyte/ga-d510ud/cstates.c +++ b/src/mainboard/gigabyte/ga-d510ud/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c index 0a7b9b98f42..f4cf4ce2aa5 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -2,9 +2,9 @@ #include -static acpi_cstate_t cst_entries[] = {}; +static const acpi_cstate_t cst_entries[] = {}; -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/mainboard/ibase/mb899/cstates.c b/src/mainboard/ibase/mb899/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/ibase/mb899/cstates.c +++ b/src/mainboard/ibase/mb899/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/intel/d510mo/cstates.c b/src/mainboard/intel/d510mo/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/intel/d510mo/cstates.c +++ b/src/mainboard/intel/d510mo/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/intel/d945gclf/cstates.c b/src/mainboard/intel/d945gclf/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/intel/d945gclf/cstates.c +++ b/src/mainboard/intel/d945gclf/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/intel/dg41wv/cstates.c b/src/mainboard/intel/dg41wv/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/intel/dg41wv/cstates.c +++ b/src/mainboard/intel/dg41wv/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/intel/dg43gt/cstates.c b/src/mainboard/intel/dg43gt/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/intel/dg43gt/cstates.c +++ b/src/mainboard/intel/dg43gt/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/kontron/986lcd-m/cstates.c b/src/mainboard/kontron/986lcd-m/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/kontron/986lcd-m/cstates.c +++ b/src/mainboard/kontron/986lcd-m/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c index 57d02882861..b435d83c01a 100644 --- a/src/mainboard/lenovo/t400/cstates.c +++ b/src/mainboard/lenovo/t400/cstates.c @@ -2,7 +2,7 @@ #include -static acpi_cstate_t cst_entries[] = { +static const acpi_cstate_t cst_entries[] = { { /* ACPI C1 / CPU C1 */ 1, 0x01, 1000, @@ -20,7 +20,7 @@ static acpi_cstate_t cst_entries[] = { }, }; -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/mainboard/lenovo/t60/cstates.c b/src/mainboard/lenovo/t60/cstates.c index 7a1e4d60016..cc3f566f2fd 100644 --- a/src/mainboard/lenovo/t60/cstates.c +++ b/src/mainboard/lenovo/t60/cstates.c @@ -3,13 +3,13 @@ #include #include -static acpi_cstate_t cst_entries[] = { +static const acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, 0, 1, 0 } }, { 2, 1, 500, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0 } }, { 3, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, }; -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/mainboard/lenovo/thinkcentre_a58/cstates.c b/src/mainboard/lenovo/thinkcentre_a58/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cstates.c +++ b/src/mainboard/lenovo/thinkcentre_a58/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c index 57d02882861..b435d83c01a 100644 --- a/src/mainboard/lenovo/x200/cstates.c +++ b/src/mainboard/lenovo/x200/cstates.c @@ -2,7 +2,7 @@ #include -static acpi_cstate_t cst_entries[] = { +static const acpi_cstate_t cst_entries[] = { { /* ACPI C1 / CPU C1 */ 1, 0x01, 1000, @@ -20,7 +20,7 @@ static acpi_cstate_t cst_entries[] = { }, }; -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/mainboard/lenovo/x60/cstates.c b/src/mainboard/lenovo/x60/cstates.c index c6237bc5924..840c8a0d76a 100644 --- a/src/mainboard/lenovo/x60/cstates.c +++ b/src/mainboard/lenovo/x60/cstates.c @@ -13,7 +13,7 @@ .addrh = 0, \ } -static acpi_cstate_t cst_entries[] = { +static const acpi_cstate_t cst_entries[] = { { .ctype = 1, .latency = 1, @@ -34,7 +34,7 @@ static acpi_cstate_t cst_entries[] = { }, }; -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/mainboard/roda/rk886ex/cstates.c b/src/mainboard/roda/rk886ex/cstates.c index 21b18b9e8d0..4adf0edc637 100644 --- a/src/mainboard/roda/rk886ex/cstates.c +++ b/src/mainboard/roda/rk886ex/cstates.c @@ -2,7 +2,7 @@ #include -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { return 0; } diff --git a/src/mainboard/roda/rk9/cstates.c b/src/mainboard/roda/rk9/cstates.c index 0f85da1d8e7..ed49994b617 100644 --- a/src/mainboard/roda/rk9/cstates.c +++ b/src/mainboard/roda/rk9/cstates.c @@ -2,7 +2,7 @@ #include -static acpi_cstate_t cst_entries[] = { +static const acpi_cstate_t cst_entries[] = { { /* ACPI C1 / CPU C1 */ 1, 0x01, 1000, @@ -15,7 +15,7 @@ static acpi_cstate_t cst_entries[] = { }, }; -int get_cst_entries(acpi_cstate_t **entries) +int get_cst_entries(const acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); From 796aeeba96fce7d6560c4d1994962a7107137666 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 16 Sep 2021 22:02:01 -0700 Subject: [PATCH 199/320] util/cse_fpt: Add a new tool for managing Intel CSE FPT binaries This change adds a new tool `cse_fpt` which can be used to print and dump CSE partitions in Flash Partition Table (FPT) format. BUG=b:189167923 Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/55259 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- Makefile.inc | 8 +- util/cbfstool/Makefile | 9 +- util/cbfstool/Makefile.inc | 14 + util/cbfstool/cse_fpt.c | 434 +++++++++++++++++++++++++ util/cbfstool/cse_fpt.h | 37 +++ util/cbfstool/fpt_formats/Makefile.inc | 3 + util/cbfstool/fpt_formats/fpt_hdr_20.c | 106 ++++++ util/cbfstool/fpt_formats/fpt_hdr_21.c | 114 +++++++ 8 files changed, 721 insertions(+), 4 deletions(-) create mode 100644 util/cbfstool/cse_fpt.c create mode 100644 util/cbfstool/cse_fpt.h create mode 100644 util/cbfstool/fpt_formats/Makefile.inc create mode 100644 util/cbfstool/fpt_formats/fpt_hdr_20.c create mode 100644 util/cbfstool/fpt_formats/fpt_hdr_21.c diff --git a/Makefile.inc b/Makefile.inc index 501fc598079..7be0505971c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -60,7 +60,7 @@ COREBOOT_EXPORTS += CCACHE_EXTRAFILES ####################################################################### # root rule to resolve if in build mode (ie. configuration exists) real-target: $(obj)/config.h coreboot files_added -coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool +coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(obj)/cse_fpt # This target can be used in site local to run scripts or additional # targets after the build completes by creating a Makefile.inc in the @@ -544,6 +544,7 @@ RMODTOOL:=$(objutil)/cbfstool/rmodtool IFWITOOL:=$(objutil)/cbfstool/ifwitool IFITTOOL:=$(objutil)/cbfstool/ifittool AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress +CSE_FPT:=$(objutil)/cbfstool/cse_fpt $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -563,6 +564,9 @@ $(obj)/ifittool: $(IFITTOOL) $(obj)/amdcompress: $(AMDCOMPRESS) cp $< $@ +$(obj)/cse_fpt: $(CSE_FPT) + cp $< $@ + _WINCHECK=$(shell uname -o 2> /dev/null) STACK= ifeq ($(_WINCHECK),Msys) @@ -689,7 +693,7 @@ install-git-commit-clangfmt: include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) ########################################################################### # Common recipes for all stages diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index f5e0c6917e3..dc5177b2f12 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -13,7 +13,7 @@ VBOOT_SOURCE ?= $(top)/3rdparty/vboot VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib) .PHONY: all -all: cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool +all: cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt cbfstool: $(objutil)/cbfstool/cbfstool @@ -29,7 +29,9 @@ cbfs-compression-tool: $(objutil)/cbfstool/cbfs-compression-tool elogtool: $(objutil)/cbfstool/elogtool -.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool +cse_fpt: $(objutil)/cbfstool/cse_fpt + +.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt clean: $(RM) fmd_parser.c fmd_parser.h fmd_scanner.c fmd_scanner.h $(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj) @@ -39,6 +41,7 @@ clean: $(RM) $(objutil)/cbfstool/ifittool $(ifitobj) $(RM) $(objutil)/cbfstool/cbfs-compression-tool $(cbfscompobj) $(RM) $(objutil)/cbfstool/elogtool $(elogobj) + $(RM) $(objutil)/cbfstool/cse_fpt $(cse_fpt_obj) $(RM) -r $(VBOOT_HOST_BUILD) linux_trampoline.c: linux_trampoline.S @@ -61,6 +64,7 @@ install: all $(INSTALL) ifittool $(DESTDIR)$(BINDIR) $(INSTALL) cbfs-compression-tool $(DESTDIR)$(BINDIR) $(INSTALL) elogtool $(DESTDIR)$(BINDIR) + $(INSTALL) cse_fpt $(DESTDIR)$(BINDIR) distclean: clean @@ -74,6 +78,7 @@ help: @echo " ifittool - Manipulate Intel FW Interface Table (FIT)" @echo " cbfs-compression-tool - benchmark compression algorithms" @echo " elogtool - Display ELOG events" + @echo " cse_fpt - Manage Intel CSE Flash Partition Table (FPT)" ifneq ($(V),1) .SILENT: diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 1113c86c515..050bc0d81e2 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -96,6 +96,12 @@ elogobj += valstr.o elogobj += elog.o elogobj += common.o +include $(top)/util/cbfstool/fpt_formats/Makefile.inc +cse_fpt_obj := +cse_fpt_obj += cse_fpt.o +cse_fpt_obj += common.o +cse_fpt_obj += $(foreach var, $(fpt_formats_obj), $(var)) + TOOLCFLAGS ?= -Werror -Wall -Wextra -Wshadow TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings @@ -178,6 +184,10 @@ $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lz4/lib/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< +$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/fpt_formats/%.c + printf " HOSTCC $(subst $(objutil)/,,$(@))\n" + $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + $(objutil)/cbfstool/cbfstool: $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) $(VBOOT_HOSTLIB) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) -v $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) $(VBOOT_HOSTLIB) @@ -210,6 +220,10 @@ $(objutil)/cbfstool/elogtool: $(addprefix $(objutil)/cbfstool/,$(elogobj)) $(VBO printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(elogobj)) $(VBOOT_HOSTLIB) +$(objutil)/cbfstool/cse_fpt: $(addprefix $(objutil)/cbfstool/,$(cse_fpt_obj)) + printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cse_fpt_obj)) + # Yacc source is superset of header $(objutil)/cbfstool/fmd.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_parser.o: TOOLCFLAGS += -Wno-redundant-decls diff --git a/util/cbfstool/cse_fpt.c b/util/cbfstool/cse_fpt.c new file mode 100644 index 00000000000..bde3a8c1655 --- /dev/null +++ b/util/cbfstool/cse_fpt.c @@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* CSE FPT tool */ + +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "cse_fpt.h" + +static struct params { + const char *output_dir; + const char *partition_name; + + struct fpt_hdr_ops *hdr_ops; +} params; + +#define FPT_ENTRY_TYPE_MASK 0x7f +#define FPT_ENTRY_TYPE_SHIFT 0 +#define GET_FPT_ENTRY_TYPE(x) (((x) >> FPT_ENTRY_TYPE_SHIFT) & FPT_ENTRY_TYPE_MASK) +#define FPT_ENTRY_TYPE_CODE 0x0 +#define FPT_ENTRY_TYPE_DATA 0x1 + +#define FPT_ENTRY_VALID_MASK 0xff +#define FPT_ENTRY_VALID_SHIFT 24 +#define GET_FPT_ENTRY_VALID(x) (((x) >> FPT_ENTRY_VALID_SHIFT) & FPT_ENTRY_VALID_MASK) +#define FPT_ENTRY_INVALID 0xff +#define FPT_ENTRY_VALID 0x0 + +struct fpt_entry { + uint8_t name[4]; /* ASCII short name */ + uint8_t rsvd1[4]; + uint32_t offset; /* Offset in bytes from start of FPT binary */ + uint32_t length; /* Size in bytes */ + uint8_t rsvd2[12]; + uint32_t flags; +} __packed; + +static struct fpt { + struct buffer input_buff; + + const struct fpt_hdr_ops *hdr_ops; + + fpt_hdr_ptr hdr; + struct fpt_entry *entries; +} fpt; + +static void usage(const char *name) +{ + printf("%s: Utility for CSE FPT\n\n" + "USAGE:\n" + " %s FILE COMMAND\n\n" + "COMMANDs:\n" + " print\n" + " dump [-o OUTPUT_DIR] [-n NAME]\n" + "\nOPTIONS:\n" + " -o OUTPUT_DIR : Directory to dump the partition files in\n" + " -n NAME : Name of partition to dump\n" + "\n", + name, name); +} + +void read_member(struct buffer *buff, void *dst, size_t size) +{ + uint8_t *src = buffer_get(buff); + + switch (size) { + case 1: + *(uint8_t *)dst = read_le8(src); + break; + case 2: + *(uint16_t *)dst = read_le16(src); + break; + case 4: + *(uint32_t *)dst = read_le32(src); + break; + case 8: + *(uint64_t *)dst = read_le64(src); + break; + default: + memcpy(dst, src, size); + } + + buffer_seek(buff, size); +} + +static int get_fpt_buff(struct buffer *input_buff, struct buffer *fpt_buff) +{ + /* + * FPT marker is typically at offset 0x10 in the released CSE binary. Check at offset + * 0x10 first and if that fails fall back to checking offset 0. + */ + const size_t fpt_offsets[] = { 0x10, 0 }; + size_t i; + + for (i = 0; i < ARRAY_SIZE(fpt_offsets); i++) { + if (buffer_size(input_buff) < (strlen(FPT_MARKER) + fpt_offsets[i])) + continue; + + const uint8_t *data = buffer_get(input_buff); + + if (!memcmp(data + fpt_offsets[i], FPT_MARKER, strlen(FPT_MARKER))) + break; + } + + if (i == ARRAY_SIZE(fpt_offsets)) { + ERROR("Could not locate FPT at known offsets.\n"); + return -1; + } + + buffer_clone(fpt_buff, input_buff); + buffer_seek(fpt_buff, fpt_offsets[i]); + + return 0; +} + +static int read_fpt_entries(struct buffer *buff) +{ + size_t i; + struct fpt_entry *e; + const size_t entries = fpt.hdr_ops->get_entry_count(fpt.hdr); + const size_t fpt_entries_size = sizeof(struct fpt_entry) * entries; + + if (buffer_size(buff) < fpt_entries_size) { + ERROR("Not enough bytes(actual=0x%zx, expected=0x%zx) for FPT entries!\n", + buffer_size(buff), fpt_entries_size); + return -1; + } + + e = fpt.entries = malloc(fpt_entries_size); + + for (i = 0; i < entries; i++, e++) { + READ_MEMBER(buff, e->name); + READ_MEMBER(buff, e->rsvd1); + READ_MEMBER(buff, e->offset); + READ_MEMBER(buff, e->length); + READ_MEMBER(buff, e->rsvd2); + READ_MEMBER(buff, e->flags); + } + + return 0; +} + +static const struct fpt_hdr_ops *get_fpt_hdr_ops(struct buffer *buff) +{ + static const struct fpt_hdr_ops *hdr_ops[] = { + &fpt_hdr_20_ops, + &fpt_hdr_21_ops, + }; + + for (size_t i = 0; i < ARRAY_SIZE(hdr_ops); i++) { + if (hdr_ops[i]->match_version(buff)) + return hdr_ops[i]; + } + + return NULL; +} + +static int fpt_parse(const char *image_name) +{ + struct buffer *input_buff = &fpt.input_buff; + struct buffer fpt_buff; + + if (buffer_from_file(input_buff, image_name)) { + ERROR("Failed to read input file %s\n", image_name); + return -1; + } + + if (get_fpt_buff(input_buff, &fpt_buff)) + return -1; + + fpt.hdr_ops = get_fpt_hdr_ops(&fpt_buff); + if (fpt.hdr_ops == NULL) { + ERROR("FPT header format not supported!\n"); + return -1; + } + + fpt.hdr = fpt.hdr_ops->read(&fpt_buff); + if (!fpt.hdr) { + ERROR("Unable to read FPT header!\n"); + return -1; + } + + return read_fpt_entries(&fpt_buff); +} + +static bool is_partition_valid(const struct fpt_entry *e) +{ + return e->offset != 0 && e->length != 0 && + GET_FPT_ENTRY_VALID(e->flags) != FPT_ENTRY_INVALID; +} + +static bool is_partition_code(const struct fpt_entry *e) +{ + return GET_FPT_ENTRY_TYPE(e->flags) == FPT_ENTRY_TYPE_CODE; +} + +static void print_fpt_entry(const struct fpt_entry *e) +{ + printf("%-25s0x%-23x0x%-23x%c,%c (0x%.8x)\n", + e->name, e->offset, e->length, + is_partition_code(e) ? 'C' : 'D', + is_partition_valid(e) ? 'V' : 'I', + e->flags); +} + +static void print_fpt_entries(const struct fpt_entry *e, size_t count) +{ + printf("\n * FPT entries\n"); + + printf("%-25s%-25s%-25s%-25s\n", "Name", "Offset", "Size", "Flags"); + + printf("==============================================================" + "===============================\n"); + + for (size_t i = 0; i < count; i++) + print_fpt_entry(&e[i]); + + printf("==============================================================" + "================================\n"); + printf("Flags: I=invalid, V=valid, C=code, D=data\n"); +} + +static bool partition_name_match(const struct fpt_entry *e, const char *name) +{ + if (!name) + return false; + + return !memcmp(e->name, name, sizeof(e->name)); +} + +static const struct fpt_entry *get_partition_entry(const char *name) +{ + for (size_t i = 0; i < fpt.hdr_ops->get_entry_count(fpt.hdr); i++) { + if (partition_name_match(&fpt.entries[i], name)) + return &fpt.entries[i]; + } + + return NULL; +} + +static int cmd_print(void) +{ + if (params.partition_name == NULL) { + fpt.hdr_ops->print(fpt.hdr); + print_fpt_entries(fpt.entries, fpt.hdr_ops->get_entry_count(fpt.hdr)); + } else { + const struct fpt_entry *e = get_partition_entry(params.partition_name); + if (e) + print_fpt_entry(e); + else { + ERROR("Partition %s not found!\n", params.partition_name); + return -1; + } + } + return 0; +} + +static bool should_dump_partition(const struct fpt_entry *e) +{ + if (!is_partition_valid(e)) { + if (partition_name_match(e, params.partition_name)) { + ERROR("Invalid partition requested to be dumped!\n"); + exit(-1); + } + return false; + } + + /* Dump all partitions if no name provided. */ + if (params.partition_name == NULL) + return true; + + return partition_name_match(e, params.partition_name); +} + +static char *get_file_path(const struct fpt_entry *e) +{ + size_t filename_len = sizeof(e->name) + 1; + char *filepath; + + /* output_dir name followed by '/' */ + if (params.output_dir) + filename_len += strlen(params.output_dir) + 1; + + filepath = malloc(filename_len); + if (!filepath) + return NULL; + + snprintf(filepath, filename_len, "%s%s%s", + params.output_dir ? : "", + params.output_dir ? "/" : "", + e->name); + + return filepath; +} + +static int write_partition_to_file(const struct fpt_entry *e) +{ + size_t end_offset = e->offset + e->length - 1; + struct buffer part_buffer; + char *filepath; + + if (end_offset > buffer_size(&fpt.input_buff)) { + ERROR("Offset out of bounds for the partition!\n"); + return -1; + } + + filepath = get_file_path(e); + if (!filepath) { + ERROR("Failed to allocate space for filepath!\n"); + return -1; + } + + printf("Dumping %.4s in %s\n", e->name, filepath); + + buffer_splice(&part_buffer, &fpt.input_buff, e->offset, e->length); + buffer_write_file(&part_buffer, filepath); + + free(filepath); + + return 0; +} + +static int cmd_dump(void) +{ + size_t i; + bool found = false; + struct stat sb; + + if (params.output_dir && (stat(params.output_dir, &sb) == -1)) { + ERROR("Failed to stat %s: %s\n", params.output_dir, strerror(errno)); + return -1; + } + + for (i = 0; i < fpt.hdr_ops->get_entry_count(fpt.hdr); i++) { + if (!should_dump_partition(&fpt.entries[i])) + continue; + found = true; + if (write_partition_to_file(&fpt.entries[i])) + return -1; + } + + if (found == false) { + if (params.partition_name) + ERROR("%s not found!\n", params.partition_name); + ERROR("No partitions dumped!\n"); + return -1; + } + + return 0; +} + +static struct command { + const char *name; + const char *optstring; + int (*function)(void); +} commands[] = { + { "print", "n:?", cmd_print }, + { "dump", "n:o:?", cmd_dump }, +}; + +static struct option long_options[] = { + {"help", required_argument, 0, 'h'}, + {"partition_name", required_argument, 0, 'n'}, + {"output_dir", required_argument, 0, 'o'}, + {NULL, 0, 0, 0 } +}; + +int main(int argc, char **argv) +{ + if (argc < 3) { + ERROR("Incorrect number of args(%d)!\n", argc); + usage(argv[0]); + return 1; + } + + const char *prog_name = argv[0]; + const char *image_name = argv[1]; + const char *cmd = argv[2]; + size_t i; + + for (i = 0; i < ARRAY_SIZE(commands); i++) { + if (strcmp(cmd, commands[i].name)) + continue; + + int c; + int option_index; + + while (1) { + c = getopt_long(argc, argv, commands[i].optstring, + long_options, &option_index); + + if (c == -1) + break; + + if (strchr(commands[i].optstring, c) == NULL) { + ERROR("Invalid option '%c'\n", c); + usage(prog_name); + return 1; + } + + switch (c) { + case 'o': + params.output_dir = optarg; + break; + case 'n': + params.partition_name = optarg; + break; + case 'h': + case '?': + default: + usage(prog_name); + return 1; + } + } + + break; + } + + if (i == ARRAY_SIZE(commands)) { + ERROR("No command match %s\n", cmd); + usage(prog_name); + return 1; + } + + if (fpt_parse(image_name)) + return 1; + + return commands[i].function(); +} diff --git a/util/cbfstool/cse_fpt.h b/util/cbfstool/cse_fpt.h new file mode 100644 index 00000000000..eda8a079309 --- /dev/null +++ b/util/cbfstool/cse_fpt.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __CBFSTOOL_CSE_FPT_H__ +#define __CBFSTOOL_CSE_FPT_H__ + +#include +#include + +#include "common.h" + +#define FPT_MARKER "$FPT" +#define FPT_ENTRY_VERSION 0x10 + +#define READ_MEMBER(_buff, _x) read_member(_buff, &(_x), sizeof(_x)) + +enum fpt_hdr_version { + FPT_HDR_VERSION_20 = 0x20, + FPT_HDR_VERSION_21 = 0x21, +}; + +typedef void *fpt_hdr_ptr; + +struct fpt_hdr_ops { + bool (*match_version)(struct buffer *buff); + + fpt_hdr_ptr (*read)(struct buffer *buff); + void (*print)(const fpt_hdr_ptr ptr); + + size_t (*get_entry_count)(const fpt_hdr_ptr ptr); +}; + +extern const struct fpt_hdr_ops fpt_hdr_20_ops; +extern const struct fpt_hdr_ops fpt_hdr_21_ops; + +void read_member(struct buffer *buff, void *dst, size_t size); + +#endif /* __CBFSTOOL_CSE_FPT_H__ */ diff --git a/util/cbfstool/fpt_formats/Makefile.inc b/util/cbfstool/fpt_formats/Makefile.inc new file mode 100644 index 00000000000..865eaed5cdd --- /dev/null +++ b/util/cbfstool/fpt_formats/Makefile.inc @@ -0,0 +1,3 @@ + +fpt_formats_obj += fpt_hdr_20.o +fpt_formats_obj += fpt_hdr_21.o diff --git a/util/cbfstool/fpt_formats/fpt_hdr_20.c b/util/cbfstool/fpt_formats/fpt_hdr_20.c new file mode 100644 index 00000000000..166d24cdf06 --- /dev/null +++ b/util/cbfstool/fpt_formats/fpt_hdr_20.c @@ -0,0 +1,106 @@ +/* CSE FPT header version 0x20 */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "cse_fpt.h" + +struct fpt_hdr { + uint8_t marker[4]; /* FPT_MARKER */ + uint32_t num_entries; + uint8_t hdr_version; /* FPT_HDR_VERSION_20 */ + uint8_t entry_version; /* FPT_ENTRY_VERSION */ + uint8_t hdr_length; + uint8_t hdr_checksum; + uint8_t rsvd[20]; +} __packed; + +static bool match_version(struct buffer *buff) +{ + const uint8_t *data = buffer_get(buff); + uint8_t version = read_at_le8(data, offsetof(struct fpt_hdr, hdr_version)); + + return version == FPT_HDR_VERSION_20; +} + +static bool validate_fpt_hdr(const struct fpt_hdr *h) +{ + if (memcmp(h->marker, FPT_MARKER, sizeof(h->marker))) { + ERROR("Invalid FPT header marker!\n"); + return false; + } + + if (h->hdr_version != FPT_HDR_VERSION_20) { + ERROR("Invalid FPT header version(0x%x)!\n", h->hdr_version); + return false; + } + + if (h->entry_version != FPT_ENTRY_VERSION) { + ERROR("Invalid FPT entry version(0x%x)!\n", h->entry_version); + return false; + } + + const uint8_t *data = (const uint8_t *)h; + uint8_t checksum = 0; + + for (size_t i = 0; i < sizeof(*h); i++) + checksum += data[i]; + + if (checksum != 0) { + ERROR("Invalid checksum (0x%x)!\n", h->hdr_checksum); + return false; + } + + return true; +} + +static fpt_hdr_ptr read_fpt_hdr(struct buffer *buff) +{ + struct fpt_hdr *h = malloc(sizeof(*h)); + if (!h) + return NULL; + + READ_MEMBER(buff, h->marker); + READ_MEMBER(buff, h->num_entries); + READ_MEMBER(buff, h->hdr_version); + READ_MEMBER(buff, h->entry_version); + READ_MEMBER(buff, h->hdr_length); + READ_MEMBER(buff, h->hdr_checksum); + READ_MEMBER(buff, h->rsvd); + + if (!validate_fpt_hdr(h)) { + free(h); + return NULL; + } + + return h; +} + +static void print_fpt_hdr(const fpt_hdr_ptr ptr) +{ + struct fpt_hdr *h = ptr; + + printf(" * FPT header\n"); + printf("%-25s: %.4s\n", "Marker", h->marker); + printf("%-25s: %d\n", "Number of entries", h->num_entries); + printf("%-25s: 0x%x\n", "Header version", h->hdr_version); + printf("%-25s: 0x%x\n", "Entry version", h->entry_version); + printf("%-25s: %d\n", "Header length", h->hdr_length); + printf("%-25s: 0x%x\n", "Header checksum", h->hdr_checksum); +} + +static size_t get_entry_count(const fpt_hdr_ptr ptr) +{ + struct fpt_hdr *h = ptr; + + return h->num_entries; +} + +const struct fpt_hdr_ops fpt_hdr_20_ops = { + .match_version = match_version, + + .read = read_fpt_hdr, + .print = print_fpt_hdr, + + .get_entry_count = get_entry_count, +}; diff --git a/util/cbfstool/fpt_formats/fpt_hdr_21.c b/util/cbfstool/fpt_formats/fpt_hdr_21.c new file mode 100644 index 00000000000..57746ddd742 --- /dev/null +++ b/util/cbfstool/fpt_formats/fpt_hdr_21.c @@ -0,0 +1,114 @@ +/* CSE FPT header version 0x21 */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "cse_fpt.h" + +struct fpt_hdr { + uint8_t marker[4]; /* FPT_MARKER */ + uint32_t num_entries; + uint8_t hdr_version; /* FPT_HDR_VERSION_21 */ + uint8_t entry_version; /* FPT_ENTRY_VERSION */ + uint8_t hdr_length; + uint8_t redundancy; + uint8_t reserved[8]; + uint32_t checksum; + struct { + uint16_t major; + uint16_t minor; + uint16_t build; + uint16_t hotfix; + } fit_tool_version; +} __packed; + +static bool match_version(struct buffer *buff) +{ + const uint8_t *data = buffer_get(buff); + uint8_t version = read_at_le8(data, offsetof(struct fpt_hdr, hdr_version)); + + return version == FPT_HDR_VERSION_21; +} + +static bool validate_fpt_hdr(const struct fpt_hdr *h) +{ + if (memcmp(h->marker, FPT_MARKER, sizeof(h->marker))) { + ERROR("Invalid FPT header marker!\n"); + return false; + } + + if (h->hdr_version != FPT_HDR_VERSION_21) { + ERROR("Invalid FPT header version(0x%x)!\n", h->hdr_version); + return false; + } + + if (h->entry_version != FPT_ENTRY_VERSION) { + ERROR("Invalid FPT entry version(0x%x)!\n", h->entry_version); + return false; + } + + return true; +} + +static fpt_hdr_ptr read_fpt_hdr(struct buffer *buff) +{ + struct fpt_hdr *h = malloc(sizeof(*h)); + if (!h) + return NULL; + + READ_MEMBER(buff, h->marker); + READ_MEMBER(buff, h->num_entries); + READ_MEMBER(buff, h->hdr_version); + READ_MEMBER(buff, h->entry_version); + READ_MEMBER(buff, h->hdr_length); + READ_MEMBER(buff, h->redundancy); + READ_MEMBER(buff, h->reserved); + READ_MEMBER(buff, h->checksum); + READ_MEMBER(buff, h->fit_tool_version); + + if (!validate_fpt_hdr(h)) { + free(h); + return NULL; + } + + return h; +} + +static void print_fpt_hdr(const fpt_hdr_ptr ptr) +{ + struct fpt_hdr *h = ptr; + + printf(" * FPT header\n"); + printf("%-25s: %.4s\n", "Marker", h->marker); + printf("%-25s: %d\n", "Number of entries", h->num_entries); + printf("%-25s: 0x%x\n", "Header version", h->hdr_version); + printf("%-25s: 0x%x\n", "Entry version", h->entry_version); + printf("%-25s: %d\n", "Header length", h->hdr_length); + printf("%-25s: 0x%x\n", "Redundancy", h->redundancy); + printf("%-25s: ", "Reserved"); + for (size_t i = 0; i < ARRAY_SIZE(h->reserved); i++) + printf("0x%x ", h->reserved[i]); + printf("\n"); + printf("%-25s: 0x%x\n", "Checksum", h->checksum); + printf("%-25s: %d.%d.%d.%d(%.2x.%.2x.%.2x.%.2x)\n", "FIT Tool Version", + h->fit_tool_version.major, h->fit_tool_version.minor, + h->fit_tool_version.build, h->fit_tool_version.hotfix, + h->fit_tool_version.major, h->fit_tool_version.minor, + h->fit_tool_version.build, h->fit_tool_version.hotfix); +} + +static size_t get_entry_count(const fpt_hdr_ptr ptr) +{ + struct fpt_hdr *h = ptr; + + return h->num_entries; +} + +const struct fpt_hdr_ops fpt_hdr_21_ops = { + .match_version = match_version, + + .read = read_fpt_hdr, + .print = print_fpt_hdr, + + .get_entry_count = get_entry_count, +}; From d7fb6a90e1d0130db18c84530272f5d35dd914b0 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 16 Sep 2021 22:04:11 -0700 Subject: [PATCH 200/320] util/cse_serger: Add a new tool for stitching CSE components This change adds a new tool `cse_serger` which can be used to print, dump and stitch together different components for the CSE region. BUG=b:189177186 Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/55503 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- Makefile.inc | 8 +- util/cbfstool/Makefile | 9 +- util/cbfstool/Makefile.inc | 14 + util/cbfstool/bpdt_formats/Makefile.inc | 8 + util/cbfstool/bpdt_formats/bpdt_1_6.c | 272 +++++ util/cbfstool/bpdt_formats/bpdt_1_7.c | 367 +++++++ util/cbfstool/bpdt_formats/subpart_entry_1.c | 66 ++ util/cbfstool/bpdt_formats/subpart_hdr_1.c | 69 ++ util/cbfstool/bpdt_formats/subpart_hdr_2.c | 72 ++ util/cbfstool/cse_serger.c | 987 +++++++++++++++++++ util/cbfstool/cse_serger.h | 95 ++ 11 files changed, 1963 insertions(+), 4 deletions(-) create mode 100644 util/cbfstool/bpdt_formats/Makefile.inc create mode 100644 util/cbfstool/bpdt_formats/bpdt_1_6.c create mode 100644 util/cbfstool/bpdt_formats/bpdt_1_7.c create mode 100644 util/cbfstool/bpdt_formats/subpart_entry_1.c create mode 100644 util/cbfstool/bpdt_formats/subpart_hdr_1.c create mode 100644 util/cbfstool/bpdt_formats/subpart_hdr_2.c create mode 100644 util/cbfstool/cse_serger.c create mode 100644 util/cbfstool/cse_serger.h diff --git a/Makefile.inc b/Makefile.inc index 7be0505971c..b784f3eee80 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -60,7 +60,7 @@ COREBOOT_EXPORTS += CCACHE_EXTRAFILES ####################################################################### # root rule to resolve if in build mode (ie. configuration exists) real-target: $(obj)/config.h coreboot files_added -coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(obj)/cse_fpt +coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(obj)/cse_fpt $(obj)/cse_serger # This target can be used in site local to run scripts or additional # targets after the build completes by creating a Makefile.inc in the @@ -545,6 +545,7 @@ IFWITOOL:=$(objutil)/cbfstool/ifwitool IFITTOOL:=$(objutil)/cbfstool/ifittool AMDCOMPRESS:=$(objutil)/cbfstool/amdcompress CSE_FPT:=$(objutil)/cbfstool/cse_fpt +CSE_SERGER:=$(objutil)/cbfstool/cse_serger $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -567,6 +568,9 @@ $(obj)/amdcompress: $(AMDCOMPRESS) $(obj)/cse_fpt: $(CSE_FPT) cp $< $@ +$(obj)/cse_serger: $(CSE_SERGER) + cp $< $@ + _WINCHECK=$(shell uname -o 2> /dev/null) STACK= ifeq ($(_WINCHECK),Msys) @@ -693,7 +697,7 @@ install-git-commit-clangfmt: include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) ########################################################################### # Common recipes for all stages diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index dc5177b2f12..e853ae509c0 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -13,7 +13,7 @@ VBOOT_SOURCE ?= $(top)/3rdparty/vboot VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib) .PHONY: all -all: cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt +all: cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt cse_serger cbfstool: $(objutil)/cbfstool/cbfstool @@ -31,7 +31,9 @@ elogtool: $(objutil)/cbfstool/elogtool cse_fpt: $(objutil)/cbfstool/cse_fpt -.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt +cse_serger: $(objutil)/cbfstool/cse_serger + +.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool elogtool cse_fpt cse_serger clean: $(RM) fmd_parser.c fmd_parser.h fmd_scanner.c fmd_scanner.h $(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj) @@ -42,6 +44,7 @@ clean: $(RM) $(objutil)/cbfstool/cbfs-compression-tool $(cbfscompobj) $(RM) $(objutil)/cbfstool/elogtool $(elogobj) $(RM) $(objutil)/cbfstool/cse_fpt $(cse_fpt_obj) + $(RM) $(objutil)/cbfstool/cse_serger $(cse_serger_obj) $(RM) -r $(VBOOT_HOST_BUILD) linux_trampoline.c: linux_trampoline.S @@ -65,6 +68,7 @@ install: all $(INSTALL) cbfs-compression-tool $(DESTDIR)$(BINDIR) $(INSTALL) elogtool $(DESTDIR)$(BINDIR) $(INSTALL) cse_fpt $(DESTDIR)$(BINDIR) + $(INSTALL) cse_serger $(DESTDIR)$(BINDIR) distclean: clean @@ -79,6 +83,7 @@ help: @echo " cbfs-compression-tool - benchmark compression algorithms" @echo " elogtool - Display ELOG events" @echo " cse_fpt - Manage Intel CSE Flash Partition Table (FPT)" + @echo " cse_serger - Stitch Intel CSE components" ifneq ($(V),1) .SILENT: diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 050bc0d81e2..0a445b5942b 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -102,6 +102,12 @@ cse_fpt_obj += cse_fpt.o cse_fpt_obj += common.o cse_fpt_obj += $(foreach var, $(fpt_formats_obj), $(var)) +include $(top)/util/cbfstool/bpdt_formats/Makefile.inc +cse_serger_obj := +cse_serger_obj += cse_serger.o +cse_serger_obj += common.o +cse_serger_obj += $(foreach var, $(bpdt_formats_obj), $(var)) + TOOLCFLAGS ?= -Werror -Wall -Wextra -Wshadow TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings @@ -188,6 +194,10 @@ $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/fpt_formats/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< +$(objutil)/cbfstool/%.o: $(top)/util/cbfstool/bpdt_formats/%.c + printf " HOSTCC $(subst $(objutil)/,,$(@))\n" + $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + $(objutil)/cbfstool/cbfstool: $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) $(VBOOT_HOSTLIB) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) -v $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) $(VBOOT_HOSTLIB) @@ -224,6 +234,10 @@ $(objutil)/cbfstool/cse_fpt: $(addprefix $(objutil)/cbfstool/,$(cse_fpt_obj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cse_fpt_obj)) +$(objutil)/cbfstool/cse_serger: $(addprefix $(objutil)/cbfstool/,$(cse_serger_obj)) + printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cse_serger_obj)) + # Yacc source is superset of header $(objutil)/cbfstool/fmd.o: TOOLCFLAGS += -Wno-redundant-decls $(objutil)/cbfstool/fmd_parser.o: TOOLCFLAGS += -Wno-redundant-decls diff --git a/util/cbfstool/bpdt_formats/Makefile.inc b/util/cbfstool/bpdt_formats/Makefile.inc new file mode 100644 index 00000000000..c676489e9ff --- /dev/null +++ b/util/cbfstool/bpdt_formats/Makefile.inc @@ -0,0 +1,8 @@ + +bpdt_formats_obj += bpdt_1_6.o +bpdt_formats_obj += bpdt_1_7.o + +bpdt_formats_obj += subpart_hdr_1.o +bpdt_formats_obj += subpart_hdr_2.o + +bpdt_formats_obj += subpart_entry_1.o diff --git a/util/cbfstool/bpdt_formats/bpdt_1_6.c b/util/cbfstool/bpdt_formats/bpdt_1_6.c new file mode 100644 index 00000000000..eaa29026702 --- /dev/null +++ b/util/cbfstool/bpdt_formats/bpdt_1_6.c @@ -0,0 +1,272 @@ +/* BPDT version 1.6 support */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "cse_serger.h" + +struct bpdt_header { + uint32_t signature; /* BPDT_SIGNATURE */ + uint16_t descriptor_count; + uint16_t version; /* Layout 1.6 = 1 */ + uint16_t reserved; + uint8_t whole_checksum; + uint8_t rom_checksum; + uint32_t ifwi_version; + struct { + uint16_t major; + uint16_t minor; + uint16_t build; + uint16_t hotfix; + } fit_tool_version; +} __packed; + +struct cse_layout { + uint8_t rom_bypass[16]; + uint32_t data_offset; + uint32_t data_size; + uint32_t bp1_offset; + uint32_t bp1_size; + uint32_t bp2_offset; + uint32_t bp2_size; + uint32_t bp3_offset; + uint32_t bp3_size; + uint32_t reserved[16]; + uint8_t checksum; +} __packed; + +static bool match_version(const struct buffer *buff) +{ + const uint8_t *data = buffer_get(buff); + const uint32_t sig = read_le32(data); + const uint16_t version = read_at_le16(data, offsetof(struct bpdt_header, version)); + + if (sig != BPDT_SIGNATURE) { + ERROR("Invalid BPDT signature(0x%x)!\n", sig); + return false; + } + + return version == BPDT_VERSION_1_6; +} + +static bpdt_hdr_ptr create_bpdt_hdr(void) +{ + struct bpdt_header *h = malloc(sizeof(*h)); + + if (!h) + return NULL; + + h->signature = BPDT_SIGNATURE; + h->descriptor_count = 0; + h->version = BPDT_VERSION_1_6; + h->reserved = 0; + /* TODO(b/202549343): Need to calculate checksum */ + h->whole_checksum = 0; + h->rom_checksum = 0; + h->ifwi_version = 0; + h->fit_tool_version.major = 0; + h->fit_tool_version.minor = 0; + h->fit_tool_version.build = 0; + h->fit_tool_version.hotfix = 0; + + return 0; +} + +static void print_bpdt_hdr(const bpdt_hdr_ptr ptr) +{ + struct bpdt_header *h = ptr; + + printf(" * BPDT header\n"); + printf("%-25s 0x%-23.8x\n", "Signature", h->signature); + printf("%-25s %-25d\n", "Descriptor count", h->descriptor_count); + printf("%-25s %d (Layout 1.6)\n", "BPDT Version", h->version); + printf("%-25s 0x%-23x\n", "Reserved", h->reserved); + printf("%-25s 0x%-23x\n", "Whole Checksum", h->whole_checksum); + printf("%-25s 0x%-23x\n", "ROM Checksum", h->rom_checksum); + printf("%-25s 0x%-23x\n", "IFWI Version", h->ifwi_version); + printf("%-25s %d.%d.%d.%d(%.2x.%.2x.%.2x.%.2x)\n", "FIT Tool Version", + h->fit_tool_version.major, h->fit_tool_version.minor, + h->fit_tool_version.build, h->fit_tool_version.hotfix, + h->fit_tool_version.major, h->fit_tool_version.minor, + h->fit_tool_version.build, h->fit_tool_version.hotfix); +} + +static bpdt_hdr_ptr read_bpdt_hdr(struct buffer *buff) +{ + struct bpdt_header *h = malloc(sizeof(*h)); + + if (!h) + return NULL; + + READ_MEMBER(buff, h->signature); + READ_MEMBER(buff, h->descriptor_count); + READ_MEMBER(buff, h->version); + READ_MEMBER(buff, h->reserved); + READ_MEMBER(buff, h->whole_checksum); + READ_MEMBER(buff, h->rom_checksum); + READ_MEMBER(buff, h->ifwi_version); + READ_MEMBER(buff, h->fit_tool_version); + + return h; +} + +static int write_bpdt_hdr(struct buffer *buff, const bpdt_hdr_ptr ptr) +{ + struct bpdt_header *h = ptr; + + if (buffer_size(buff) < sizeof(struct bpdt_header)) { + ERROR("Not enough size in buffer for BPDT header!\n"); + return -1; + } + + WRITE_MEMBER(buff, h->signature); + WRITE_MEMBER(buff, h->descriptor_count); + WRITE_MEMBER(buff, h->version); + WRITE_MEMBER(buff, h->reserved); + WRITE_MEMBER(buff, h->whole_checksum); + WRITE_MEMBER(buff, h->rom_checksum); + WRITE_MEMBER(buff, h->ifwi_version); + WRITE_MEMBER(buff, h->fit_tool_version); + + return 0; +} + +static size_t get_bpdt_entry_count(const bpdt_hdr_ptr ptr) +{ + return ((const struct bpdt_header *)ptr)->descriptor_count; +} + +static void inc_bpdt_entry_count(bpdt_hdr_ptr ptr) +{ + struct bpdt_header *h = ptr; + h->descriptor_count++; +} + +static cse_layout_ptr create_cse_layout(const struct cse_layout_regions *r) +{ + struct cse_layout *l = malloc(sizeof(*l)); + + if (!l) + return NULL; + + l->data_offset = r->data_partition.offset; + l->data_size = r->data_partition.size; + l->bp1_offset = r->bp1.offset; + l->bp1_size = r->bp1.size; + l->bp2_offset = r->bp2.offset; + l->bp2_size = r->bp2.size; + l->bp3_offset = r->bp3.offset; + l->bp3_size = r->bp3.size; + l->checksum = 0; /* unused */ + + return 0; +} + +static void print_cse_layout(const cse_layout_ptr ptr) +{ + struct cse_layout *l = ptr; + + printf(" * CSE Layout\n\n"); + printf("ROM Bypass: "); + for (size_t i = 0; i < sizeof(l->rom_bypass); i++) + printf("0x%x ", l->rom_bypass[i]); + printf("\n"); + printf("Data partition offset: 0x%x\n", l->data_offset); + printf("Data partition size: 0x%x\n", l->data_size); + printf("BP1 offset: 0x%x\n", l->bp1_offset); + printf("BP1 size: 0x%x\n", l->bp1_size); + printf("BP2 offset: 0x%x\n", l->bp2_offset); + printf("BP2 size: 0x%x\n", l->bp2_size); + printf("BP3 offset: 0x%x\n", l->bp3_offset); + printf("BP3 size: 0x%x\n", l->bp3_size); + printf("Checksum: 0x%x\n", l->checksum); +} + +static cse_layout_ptr read_cse_layout(struct buffer *buff) +{ + struct cse_layout *l = malloc(sizeof(*l)); + + if (!l) + return NULL; + + READ_MEMBER(buff, l->rom_bypass); + READ_MEMBER(buff, l->data_offset); + READ_MEMBER(buff, l->data_size); + READ_MEMBER(buff, l->bp1_offset); + READ_MEMBER(buff, l->bp1_size); + READ_MEMBER(buff, l->bp2_offset); + READ_MEMBER(buff, l->bp2_size); + READ_MEMBER(buff, l->bp3_offset); + READ_MEMBER(buff, l->bp3_size); + READ_MEMBER(buff, l->reserved); + READ_MEMBER(buff, l->checksum); + + return l; +} + +static int write_cse_layout(struct buffer *buff, const cse_layout_ptr ptr) +{ + struct cse_layout *l = ptr; + + if (buffer_size(buff) < sizeof(struct cse_layout)) { + ERROR("Not enough size in buffer for CSE layout!\n"); + return -1; + } + + WRITE_MEMBER(buff, l->rom_bypass); + WRITE_MEMBER(buff, l->data_offset); + WRITE_MEMBER(buff, l->data_size); + WRITE_MEMBER(buff, l->bp1_offset); + WRITE_MEMBER(buff, l->bp1_size); + WRITE_MEMBER(buff, l->bp2_offset); + WRITE_MEMBER(buff, l->bp2_size); + WRITE_MEMBER(buff, l->bp3_offset); + WRITE_MEMBER(buff, l->bp3_size); + WRITE_MEMBER(buff, l->reserved); + WRITE_MEMBER(buff, l->checksum); + + return 0; +} + +static void update_checksum(bpdt_hdr_ptr ptr, struct bpdt_entry *e) +{ + (void)ptr; + (void)e; + + /* TODO(b/202549343) */ + ERROR("Update checksum is not supported for 1.6!\n"); +} + +static bool validate_checksum(bpdt_hdr_ptr ptr, struct bpdt_entry *e) +{ + (void)e; + (void)ptr; + + /* TODO(b/202549343) */ + ERROR("Validate checksum is not supported for 1.6!\n"); + + return true; +} + +const struct bpdt_ops bpdt_1_6_ops = { + .match_version = match_version, + + .create_hdr = create_bpdt_hdr, + .print_hdr = print_bpdt_hdr, + .read_hdr = read_bpdt_hdr, + .write_hdr = write_bpdt_hdr, + + .get_entry_count = get_bpdt_entry_count, + .inc_entry_count = inc_bpdt_entry_count, + + .create_layout = create_cse_layout, + .print_layout = print_cse_layout, + .read_layout = read_cse_layout, + .write_layout = write_cse_layout, + + .update_checksum = update_checksum, + .validate_checksum = validate_checksum, + + .subpart_hdr_version = SUBPART_HDR_VERSION_1, + .subpart_entry_version = SUBPART_ENTRY_VERSION_1, +}; diff --git a/util/cbfstool/bpdt_formats/bpdt_1_7.c b/util/cbfstool/bpdt_formats/bpdt_1_7.c new file mode 100644 index 00000000000..53294242ca1 --- /dev/null +++ b/util/cbfstool/bpdt_formats/bpdt_1_7.c @@ -0,0 +1,367 @@ +/* BPDT version 1.7 support */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "cse_serger.h" + +enum bpdt_flags { + BPDT_FLAGS_REDUNDANCY_SUPPORTED = 1 << 0, +}; + +struct bpdt_header { + uint32_t signature; /* BPDT_SIGNATURE */ + uint16_t descriptor_count; + uint8_t version; /* Layout 1.7 = 2 */ + uint8_t flags; /* See enum bpdt_flags */ + uint32_t checksum; + uint32_t ifwi_version; + struct { + uint16_t major; + uint16_t minor; + uint16_t build; + uint16_t hotfix; + } fit_tool_version; +} __packed; + +struct cse_layout { + uint8_t rom_bypass[16]; + uint16_t size; + uint16_t redundancy; + uint32_t checksum; + uint32_t data_offset; + uint32_t data_size; + uint32_t bp1_offset; + uint32_t bp1_size; + uint32_t bp2_offset; + uint32_t bp2_size; + uint32_t bp3_offset; + uint32_t bp3_size; + uint32_t bp4_offset; + uint32_t bp4_size; + uint32_t bp5_offset; + uint32_t bp5_size; + uint32_t temp_base_addr; + uint32_t temp_base_size; + uint32_t flog_offset; + uint32_t flog_size; +} __packed; + +static bool match_version(const struct buffer *buff) +{ + const uint8_t *data = buffer_get(buff); + const uint32_t sig = read_le32(data); + const uint8_t version = read_at_le8(data, offsetof(struct bpdt_header, version)); + + if (sig != BPDT_SIGNATURE) { + ERROR("Invalid BPDT signature(0x%x)!\n", sig); + return false; + } + + return version == BPDT_VERSION_1_7; +} + +static bpdt_hdr_ptr create_bpdt_hdr(void) +{ + struct bpdt_header *h = calloc(1, sizeof(*h)); + + if (!h) + return NULL; + + h->signature = BPDT_SIGNATURE; + h->descriptor_count = 0; + h->version = BPDT_VERSION_1_7; + h->flags = 0; + h->checksum = 0; + h->ifwi_version = 0; + h->fit_tool_version.major = 0; + h->fit_tool_version.minor = 0; + h->fit_tool_version.build = 0; + h->fit_tool_version.hotfix = 0; + + return h; +} + +static void print_bpdt_hdr(const bpdt_hdr_ptr ptr) +{ + struct bpdt_header *h = ptr; + + printf(" * BPDT header\n"); + printf("%-25s 0x%-23.8x\n", "Signature", h->signature); + printf("%-25s %-25d\n", "Descriptor count", h->descriptor_count); + printf("%-25s %d (Layout 1.7)\n", "BPDT Version", h->version); + printf("%-25s 0x%-23x\n", "Flags", h->flags); + printf("%-25s 0x%-23x\n", "Checksum", h->checksum); + printf("%-25s 0x%-23x\n", "IFWI Version", h->ifwi_version); + printf("%-25s %d.%d.%d.%d(%.2x.%.2x.%.2x.%.2x)\n", "FIT Tool Version", + h->fit_tool_version.major, h->fit_tool_version.minor, + h->fit_tool_version.build, h->fit_tool_version.hotfix, + h->fit_tool_version.major, h->fit_tool_version.minor, + h->fit_tool_version.build, h->fit_tool_version.hotfix); +} + +static bpdt_hdr_ptr read_bpdt_hdr(struct buffer *buff) +{ + struct bpdt_header *h = calloc(1, sizeof(*h)); + + if (!h) + return NULL; + + READ_MEMBER(buff, h->signature); + READ_MEMBER(buff, h->descriptor_count); + READ_MEMBER(buff, h->version); + READ_MEMBER(buff, h->flags); + READ_MEMBER(buff, h->checksum); + READ_MEMBER(buff, h->ifwi_version); + READ_MEMBER(buff, h->fit_tool_version); + + return h; +} + +static int write_bpdt_hdr(struct buffer *buff, const bpdt_hdr_ptr ptr) +{ + struct bpdt_header *h = ptr; + + if (buffer_size(buff) < sizeof(struct bpdt_header)) { + ERROR("Not enough size in buffer for BPDT header!\n"); + return -1; + } + + WRITE_MEMBER(buff, h->signature); + WRITE_MEMBER(buff, h->descriptor_count); + WRITE_MEMBER(buff, h->version); + WRITE_MEMBER(buff, h->flags); + WRITE_MEMBER(buff, h->checksum); + WRITE_MEMBER(buff, h->ifwi_version); + WRITE_MEMBER(buff, h->fit_tool_version); + + return 0; +} + +static size_t get_bpdt_entry_count(const bpdt_hdr_ptr ptr) +{ + return ((const struct bpdt_header *)ptr)->descriptor_count; +} + +static void inc_bpdt_entry_count(bpdt_hdr_ptr ptr) +{ + struct bpdt_header *h = ptr; + h->descriptor_count++; +} + +static uint32_t crc32(uint32_t seed, const uint8_t *data, size_t len) +{ + uint32_t crc = seed; + + for (size_t i = 0; i < len; i++) { + crc ^= *data++; + + for (size_t b = 0; b < 8; b++) { + if (crc & 1) + crc = (crc >> 1) ^ 0xedb88320; + else + crc = crc >> 1; + } + } + + return crc; +} + +/* + * Calculate checksum by: + * a. stashing l->checksum in curr_checksum and setting l->checksum to 0 + * b. calculating checksum + * c. restoring l->checksum and return calculated checksum value. + */ +static uint32_t calculate_layout_checksum(struct cse_layout *l) +{ + uint32_t curr_checksum = l->checksum; + uint32_t calc_checksum; + + l->checksum = 0; + calc_checksum = ~crc32(0xffffffff, (void *)&l->size, l->size); + l->checksum = curr_checksum; + + return calc_checksum; +} + +static cse_layout_ptr create_cse_layout(const struct cse_layout_regions *r) +{ + struct cse_layout *l = calloc(1, sizeof(*l)); + + if (!l) + return NULL; + + memset(l->rom_bypass, 0xff, sizeof(l->rom_bypass)); + l->size = sizeof(struct cse_layout) - sizeof(l->rom_bypass); + l->redundancy = 0; + l->checksum = 0; + l->data_offset = r->data_partition.offset; + l->data_size = r->data_partition.size; + l->bp1_offset = r->bp1.offset; + l->bp1_size = r->bp1.size; + l->bp2_offset = r->bp2.offset; + l->bp2_size = r->bp2.size; + l->bp3_offset = r->bp3.offset; + l->bp3_size = r->bp3.size; + l->bp4_offset = r->bp4.offset; + l->bp4_size = r->bp4.size; + l->bp5_offset = 0; + l->bp5_size = 0; + l->temp_base_addr = 0; + l->temp_base_size = 0; + l->flog_offset = 0; + l->flog_size = 0; + + l->checksum = calculate_layout_checksum(l); + + return l; +} + +static void print_cse_layout(const cse_layout_ptr ptr) +{ + struct cse_layout *l = ptr; + + printf(" * CSE Layout\n\n"); + printf("ROM Bypass: "); + for (size_t i = 0; i < sizeof(l->rom_bypass); i++) + printf("0x%x ", l->rom_bypass[i]); + printf("\n"); + printf("Size: 0x%x\n", l->size); + printf("Redundancy: 0x%x\n", l->redundancy); + printf("Checksum: 0x%x\n", l->checksum); + printf("Data partition offset: 0x%x\n", l->data_offset); + printf("Data partition size: 0x%x\n", l->data_size); + printf("BP1 offset: 0x%x\n", l->bp1_offset); + printf("BP1 size: 0x%x\n", l->bp1_size); + printf("BP2 offset: 0x%x\n", l->bp2_offset); + printf("BP2 size: 0x%x\n", l->bp2_size); + printf("BP3 offset: 0x%x\n", l->bp3_offset); + printf("BP3 size: 0x%x\n", l->bp3_size); + printf("BP4 offset: 0x%x\n", l->bp4_offset); + printf("BP4 size: 0x%x\n", l->bp4_size); + printf("BP5 offset: 0x%x\n", l->bp5_offset); + printf("BP5 size: 0x%x\n", l->bp5_size); + printf("Temp base addr: 0x%x\n", l->temp_base_addr); + printf("Temp base size: 0x%x\n", l->temp_base_size); + printf("FLOG offset: 0x%x\n", l->flog_offset); + printf("FLOG size: 0x%x\n", l->flog_size); +} + +static cse_layout_ptr read_cse_layout(struct buffer *buff) +{ + struct cse_layout *l = calloc(1, sizeof(*l)); + + if (!l) + return NULL; + + READ_MEMBER(buff, l->rom_bypass); + READ_MEMBER(buff, l->size); + READ_MEMBER(buff, l->redundancy); + READ_MEMBER(buff, l->checksum); + READ_MEMBER(buff, l->data_offset); + READ_MEMBER(buff, l->data_size); + READ_MEMBER(buff, l->bp1_offset); + READ_MEMBER(buff, l->bp1_size); + READ_MEMBER(buff, l->bp2_offset); + READ_MEMBER(buff, l->bp2_size); + READ_MEMBER(buff, l->bp3_offset); + READ_MEMBER(buff, l->bp3_size); + READ_MEMBER(buff, l->bp4_offset); + READ_MEMBER(buff, l->bp4_size); + READ_MEMBER(buff, l->bp5_offset); + READ_MEMBER(buff, l->bp5_size); + READ_MEMBER(buff, l->temp_base_addr); + READ_MEMBER(buff, l->temp_base_size); + READ_MEMBER(buff, l->flog_offset); + READ_MEMBER(buff, l->flog_size); + + return l; +} + +static int write_cse_layout(struct buffer *buff, const cse_layout_ptr ptr) +{ + struct cse_layout *l = ptr; + + if (buffer_size(buff) < sizeof(struct cse_layout)) { + ERROR("Not enough size in buffer for CSE layout!\n"); + return -1; + } + + WRITE_MEMBER(buff, l->rom_bypass); + WRITE_MEMBER(buff, l->size); + WRITE_MEMBER(buff, l->redundancy); + WRITE_MEMBER(buff, l->checksum); + WRITE_MEMBER(buff, l->data_offset); + WRITE_MEMBER(buff, l->data_size); + WRITE_MEMBER(buff, l->bp1_offset); + WRITE_MEMBER(buff, l->bp1_size); + WRITE_MEMBER(buff, l->bp2_offset); + WRITE_MEMBER(buff, l->bp2_size); + WRITE_MEMBER(buff, l->bp3_offset); + WRITE_MEMBER(buff, l->bp3_size); + WRITE_MEMBER(buff, l->bp4_offset); + WRITE_MEMBER(buff, l->bp4_size); + WRITE_MEMBER(buff, l->bp5_offset); + WRITE_MEMBER(buff, l->bp5_size); + WRITE_MEMBER(buff, l->temp_base_addr); + WRITE_MEMBER(buff, l->temp_base_size); + WRITE_MEMBER(buff, l->flog_offset); + WRITE_MEMBER(buff, l->flog_size); + + return 0; +} + +static uint32_t calculate_bpdt_checksum(struct bpdt_header *h, struct bpdt_entry *e) +{ + uint32_t calc_checksum; + uint32_t curr_checksum = h->checksum; + + h->checksum = 0; + + calc_checksum = crc32(0xffffffff, (void *)&h->descriptor_count, + sizeof(*h) - sizeof(h->signature)); + + if (e && h->descriptor_count) + calc_checksum = crc32(calc_checksum, (void *)e, + h->descriptor_count * sizeof(struct bpdt_entry)); + + h->checksum = curr_checksum; + + return ~calc_checksum; +} + +static void update_checksum(bpdt_hdr_ptr ptr, struct bpdt_entry *e) +{ + struct bpdt_header *h = ptr; + h->checksum = calculate_bpdt_checksum(h, e); +} + +static bool validate_checksum(bpdt_hdr_ptr ptr, struct bpdt_entry *e) +{ + struct bpdt_header *h = ptr; + return calculate_bpdt_checksum(h, e) == h->checksum; +} + +const struct bpdt_ops bpdt_1_7_ops = { + .match_version = match_version, + + .create_hdr = create_bpdt_hdr, + .print_hdr = print_bpdt_hdr, + .read_hdr = read_bpdt_hdr, + .write_hdr = write_bpdt_hdr, + + .get_entry_count = get_bpdt_entry_count, + .inc_entry_count = inc_bpdt_entry_count, + + .create_layout = create_cse_layout, + .print_layout = print_cse_layout, + .read_layout = read_cse_layout, + .write_layout = write_cse_layout, + + .update_checksum = update_checksum, + .validate_checksum = validate_checksum, + + .subpart_hdr_version = SUBPART_HDR_VERSION_2, + .subpart_entry_version = SUBPART_ENTRY_VERSION_1, +}; diff --git a/util/cbfstool/bpdt_formats/subpart_entry_1.c b/util/cbfstool/bpdt_formats/subpart_entry_1.c new file mode 100644 index 00000000000..a5982ff1324 --- /dev/null +++ b/util/cbfstool/bpdt_formats/subpart_entry_1.c @@ -0,0 +1,66 @@ +/* Subpart directory entry version 1 support */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "cse_serger.h" + +#define SUBPART_OFFSET_SHIFT 0 +#define SUBPART_OFFSET_MASK 0x1ffffff +#define SUBPART_OFFSET(x) (((x) >> SUBPART_OFFSET_SHIFT) & SUBPART_OFFSET_MASK) +#define SUBPART_COMPRESSED_SHIFT 25 +#define SUBPART_COMPRESSED_MASK 1 +#define SUBPART_COMPRESSED(x) \ + (((x) >> SUBPART_COMPRESSED_SHIFT) & SUBPART_COMPRESSED_MASK) + +struct subpart_entry { + uint8_t name[12]; + uint32_t offset_bytes; + uint32_t length; + uint32_t rsvd2; +} __packed; + +static void subpart_read_entry(struct buffer *buff, struct subpart_entry *e) +{ + READ_MEMBER(buff, e->name); + READ_MEMBER(buff, e->offset_bytes); + READ_MEMBER(buff, e->length); + READ_MEMBER(buff, e->rsvd2); +} + +static void subpart_print_entry(const struct subpart_entry *e, size_t index) +{ + printf("%-25zd%-25.12s0x%-23x%-25c0x%-23x0x%-23x\n", index, + e->name, SUBPART_OFFSET(e->offset_bytes), + SUBPART_COMPRESSED(e->offset_bytes) ? 'Y' : 'N', + e->length, e->rsvd2); +} + +static void subpart_print_entries(struct buffer *buff, size_t count) +{ + struct subpart_entry *e = malloc(count * sizeof(*e)); + + if (!e) + return; + + for (size_t i = 0; i < count; i++) + subpart_read_entry(buff, &e[i]); + + printf("%-25s%-25s%-25s%-25s%-25s%-25s\n", "Entry #", "Name", "Offset", + "Huffman Compressed?", "Length", "Rsvd"); + + printf("=====================================================================" + "=====================================================================\n"); + + for (size_t i = 0; i < count; i++) + subpart_print_entry(&e[i], i + 1); + + printf("=====================================================================" + "=====================================================================\n"); + + free(e); +} + +const struct subpart_entry_ops subpart_entry_1_ops = { + .print = subpart_print_entries, +}; diff --git a/util/cbfstool/bpdt_formats/subpart_hdr_1.c b/util/cbfstool/bpdt_formats/subpart_hdr_1.c new file mode 100644 index 00000000000..5335c7a844e --- /dev/null +++ b/util/cbfstool/bpdt_formats/subpart_hdr_1.c @@ -0,0 +1,69 @@ +/* Subpart directory header version 1 support */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "cse_serger.h" + +struct subpart_hdr { + uint32_t signature; /* SUBPART_SIGNATURE */ + uint32_t count; + uint8_t hdr_version; /* Header version = 1 */ + uint8_t entry_version; /* Entry version = 1 */ + uint8_t length; + uint8_t checksum; + uint8_t name[4]; +} __packed; + +static void subpart_hdr_print(const subpart_hdr_ptr ptr) +{ + const struct subpart_hdr *hdr = ptr; + + printf("%-25s %.4s\n", "Signature", (const char *)&hdr->signature); + printf("%-25s %-25d\n", "Count", hdr->count); + printf("%-25s %-25d\n", "Header Version", hdr->hdr_version); + printf("%-25s %-25d\n", "Entry Version", hdr->entry_version); + printf("%-25s 0x%-23x\n", "Header Length", hdr->length); + printf("%-25s 0x%-23x\n", "Checksum", hdr->checksum); + printf("%-25s ", "Name"); + for (size_t i = 0; i < sizeof(hdr->name); i++) + printf("%c", hdr->name[i]); + printf("\n"); +} + +static subpart_hdr_ptr subpart_hdr_read(struct buffer *buff) +{ + struct subpart_hdr *hdr = malloc(sizeof(*hdr)); + + if (!hdr) + return NULL; + + READ_MEMBER(buff, hdr->signature); + READ_MEMBER(buff, hdr->count); + READ_MEMBER(buff, hdr->hdr_version); + READ_MEMBER(buff, hdr->entry_version); + READ_MEMBER(buff, hdr->length); + READ_MEMBER(buff, hdr->checksum); + READ_MEMBER(buff, hdr->name); + + return hdr; +} + +static size_t subpart_get_count(const subpart_hdr_ptr ptr) +{ + const struct subpart_hdr *hdr = ptr; + + return hdr->count; +} + +static void subpart_hdr_free(subpart_hdr_ptr ptr) +{ + free(ptr); +} + +const struct subpart_hdr_ops subpart_hdr_1_ops = { + .read = subpart_hdr_read, + .print = subpart_hdr_print, + .get_entry_count = subpart_get_count, + .free = subpart_hdr_free, +}; diff --git a/util/cbfstool/bpdt_formats/subpart_hdr_2.c b/util/cbfstool/bpdt_formats/subpart_hdr_2.c new file mode 100644 index 00000000000..17304dc4475 --- /dev/null +++ b/util/cbfstool/bpdt_formats/subpart_hdr_2.c @@ -0,0 +1,72 @@ +/* Subpart directory header version 2 support */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "cse_serger.h" + +struct subpart_hdr { + uint32_t signature; /* SUBPART_SIGNATURE */ + uint32_t count; + uint8_t hdr_version; /* Header version = 2 */ + uint8_t entry_version; /* Entry version = 1 */ + uint8_t length; + uint8_t reserved; + uint8_t name[4]; + uint32_t checksum; +} __packed; + +static subpart_hdr_ptr subpart_hdr_read(struct buffer *buff) +{ + struct subpart_hdr *hdr = malloc(sizeof(*hdr)); + + if (!hdr) + return NULL; + + READ_MEMBER(buff, hdr->signature); + READ_MEMBER(buff, hdr->count); + READ_MEMBER(buff, hdr->hdr_version); + READ_MEMBER(buff, hdr->entry_version); + READ_MEMBER(buff, hdr->length); + READ_MEMBER(buff, hdr->reserved); + READ_MEMBER(buff, hdr->name); + READ_MEMBER(buff, hdr->checksum); + + return hdr; +} + +static void subpart_hdr_print(const subpart_hdr_ptr ptr) +{ + const struct subpart_hdr *hdr = ptr; + + printf("%-25s %.4s\n", "Signature", (const char *)&hdr->signature); + printf("%-25s %-25d\n", "Count", hdr->count); + printf("%-25s %-25d\n", "Header Version", hdr->hdr_version); + printf("%-25s %-25d\n", "Entry Version", hdr->entry_version); + printf("%-25s 0x%-23x\n", "Header Length", hdr->length); + printf("%-25s 0x%-23x\n", "Reserved", hdr->reserved); + printf("%-25s ", "Name"); + for (size_t i = 0; i < sizeof(hdr->name); i++) + printf("%c", hdr->name[i]); + printf("\n"); + printf("%-25s 0x%-23x\n", "Checksum", hdr->checksum); +} + +static size_t subpart_get_count(const subpart_hdr_ptr ptr) +{ + const struct subpart_hdr *hdr = ptr; + + return hdr->count; +} + +static void subpart_hdr_free(subpart_hdr_ptr ptr) +{ + free(ptr); +} + +const struct subpart_hdr_ops subpart_hdr_2_ops = { + .read = subpart_hdr_read, + .print = subpart_hdr_print, + .get_entry_count = subpart_get_count, + .free = subpart_hdr_free, +}; diff --git a/util/cbfstool/cse_serger.c b/util/cbfstool/cse_serger.c new file mode 100644 index 00000000000..cc49671d190 --- /dev/null +++ b/util/cbfstool/cse_serger.c @@ -0,0 +1,987 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* CSE Serger - Tool for stitching Intel CSE components */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cse_serger.h" + +#define NO_PARTITION_TYPE (-1) + +static struct params { + bool print_sub_parts; + const char *partition_name; + int partition_type; + const char *output_dir; + const char *image_name; + const char *version_str; + const char *input_file; + struct cse_layout_regions layout_regions; +} params; + +static const struct { + const char *version_str; + const struct bpdt_ops *ops; +} bpdt_ops_table[] = { + { "1.6", &bpdt_1_6_ops }, + { "1.7", &bpdt_1_7_ops }, +}; + +static const struct { + enum subpart_hdr_version version; + const struct subpart_hdr_ops *ops; +} subpart_hdr_ops_table[] = { + { SUBPART_HDR_VERSION_1, &subpart_hdr_1_ops }, + { SUBPART_HDR_VERSION_2, &subpart_hdr_2_ops }, +}; + +static const struct { + enum subpart_entry_version version; + const struct subpart_entry_ops *ops; +} subpart_entry_ops_table[] = { + { SUBPART_ENTRY_VERSION_1, &subpart_entry_1_ops }, +}; + +enum bpdt_entry_type { + SMIP = 0, + CSE_RBE = 1, + CSE_BUP = 2, + UCODE = 3, + IBB = 4, + S_BPDT = 5, + OBB = 6, + CSE_MAIN = 7, + ISH = 8, + CSE_IDLM = 9, + IFP_OVERRIDE = 10, + UTOK = 11, + UFS_PHY = 12, + UFS_GPP = 13, + PMC = 14, + IUNIT = 15, + NVM_CFG = 16, + UEP = 17, + OEM_KM = 20, + PAVP = 22, + IOM_FW = 23, + NPHY_FW = 24, + TBT_FW = 25, + ICC = 32, + + MAX_SUBPARTS, +}; + +static struct { + struct buffer input_buff; + + const struct bpdt_ops *bpdt_ops; + const struct subpart_hdr_ops *subpart_hdr_ops; + const struct subpart_entry_ops *subpart_entry_ops; + + bpdt_hdr_ptr bpdt_hdr; + cse_layout_ptr cse_layout; + struct bpdt_entry bpdt_entries[MAX_SUBPARTS]; + struct buffer subpart_buff[MAX_SUBPARTS]; + bool repack; + size_t file_end_offset; +} ifwi; + +#define SUBPART_WITH_ALT(_index, _rname, _name, _aname) \ + [_index] = { _rname, _name, _aname } +#define SUBPART(_index, _rname, _name) \ + SUBPART_WITH_ALT(_index, _rname, _name, "") + +static const struct { + const char *readable_name; + const char *name; + const char *alt_name; +} subparts[] = { + SUBPART(SMIP, "OEM SMIP", "SMIP"), + SUBPART(CSE_RBE, "CSE RBE", "RBEP"), + SUBPART_WITH_ALT(CSE_BUP, "CSE BUP", "FTPR", "MFTP"), + SUBPART(UCODE, "Microcode", "UCOD"), + SUBPART(IBB, "Initial Boot Block", "IBBP"), + SUBPART(S_BPDT, "Secondary BPDT", "SBDT"), + SUBPART(OBB, "OEM Boot Block", "OBBP"), + SUBPART(CSE_MAIN, "CSE Main", "NFTP"), + SUBPART(ISH, "ISH Firmware", "ISHP"), + SUBPART(CSE_IDLM, "CSE IDLM", "DLMP"), + SUBPART(IFP_OVERRIDE, "IFP override", "IFPP"), + SUBPART(UTOK, "Debug tokens", "UTOK"), + SUBPART(UFS_PHY, "UFS Phy", "UFSP"), + SUBPART(UFS_GPP, "UFS GPP", "UFSG"), + SUBPART(PMC, "PMC Firmware", "PMCP"), + SUBPART(IUNIT, "IUNIT Firmware", "IUNP"), + SUBPART(NVM_CFG, "NVM CFG", "NVMC"), + SUBPART(UEP, "UEP", "UEPP"), + SUBPART(OEM_KM, "OEM Key Manifest", "OEMP"), + SUBPART(PAVP, "PAVP", "PAVP"), + SUBPART(IOM_FW, "IOM Firmware", "IOMP"), + SUBPART(NPHY_FW, "NPHY Firmware", "NPHY"), + SUBPART(TBT_FW, "TBT Firmware", "TBTP"), + SUBPART(ICC, "ICC Firmware", "PCHC"), +}; + +static const char *subpart_readable_name(enum bpdt_entry_type type) +{ + return subparts[type].readable_name; +} + +static const char *subpart_name(enum bpdt_entry_type type) +{ + return subparts[type].name; +} + +static const char *subpart_alt_name(enum bpdt_entry_type type) +{ + return subparts[type].alt_name; +} + +static struct buffer *subpart_buff(int type) +{ + return &ifwi.subpart_buff[type]; +} + +static int subpart_get_type_from_name(const char *name) +{ + int i; + + for (i = 0; i < MAX_SUBPARTS; i++) { + if (subpart_name(i) == NULL) + continue; + + if (!strcmp(subpart_name(i), name)) + return i; + + if (!strcmp(subpart_alt_name(i), name)) + return i; + } + + return -1; +} + +void write_member(struct buffer *buff, void *src, size_t size) +{ + void *dst = buffer_get(buff); + + switch (size) { + case 1: + write_le8(dst, *(uint8_t *)src); + break; + case 2: + write_le16(dst, *(uint16_t *)src); + break; + case 4: + write_le32(dst, *(uint32_t *)src); + break; + case 8: + write_le64(dst, *(uint64_t *)src); + break; + default: + memcpy(dst, src, size); + break; + } + + buffer_seek(buff, size); +} + +void read_member(struct buffer *buff, void *dst, size_t size) +{ + const void *src = buffer_get(buff); + + switch (size) { + case 1: + *(uint8_t *)dst = read_le8(src); + break; + case 2: + *(uint16_t *)dst = read_le16(src); + break; + case 4: + *(uint32_t *)dst = read_le32(src); + break; + case 8: + *(uint64_t *)dst = read_le64(src); + break; + default: + memcpy(dst, src, size); + break; + } + + buffer_seek(buff, size); +} + +static const struct bpdt_ops *get_bpdt_ops(const struct buffer *buff) +{ + assert(buff || params.version_str); + + for (size_t i = 0; i < ARRAY_SIZE(bpdt_ops_table); i++) { + if (params.version_str) { + if (!strcmp(params.version_str, bpdt_ops_table[i].version_str)) + return bpdt_ops_table[i].ops; + else + continue; + } + if (bpdt_ops_table[i].ops->match_version(buff)) + return bpdt_ops_table[i].ops; + } + + return NULL; +} + +static const struct subpart_hdr_ops *get_subpart_hdr_ops(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(subpart_hdr_ops_table); i++) { + if (subpart_hdr_ops_table[i].version == ifwi.bpdt_ops->subpart_hdr_version) + return subpart_hdr_ops_table[i].ops; + } + + return NULL; +} + +static const struct subpart_entry_ops *get_subpart_entry_ops(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(subpart_entry_ops_table); i++) { + if (subpart_entry_ops_table[i].version == ifwi.bpdt_ops->subpart_entry_version) + return subpart_entry_ops_table[i].ops; + } + + return NULL; +} + +static int subpart_read(struct buffer *input_buff) +{ + size_t input_size = buffer_size(input_buff); + struct bpdt_entry *e = &ifwi.bpdt_entries[0]; + struct buffer *buff; + + for (size_t i = 0; i < ifwi.bpdt_ops->get_entry_count(ifwi.bpdt_hdr); i++, e++) { + if (e->size == 0) + continue; + + if (e->type >= MAX_SUBPARTS) { + ERROR("Invalid part type(%d)\n", e->type); + return -1; + } + + if (e->offset + e->size > input_size) { + ERROR("Part(%d) exceeds file size. Part offset=0x%x, Part size = 0x%x, File size = 0x%zx\n", + e->type, e->offset, e->size, input_size); + return -1; + } + + buff = subpart_buff(e->type); + if (buffer_size(buff) != 0) { + ERROR("Multiple subparts of same type(%d %s)!\n", + e->type, subpart_name(e->type)); + return -1; + } + + buffer_splice(buff, input_buff, e->offset, e->size); + } + + return 0; +} + +static struct bpdt_entry *find_bpdt_entry(uint32_t type) +{ + struct bpdt_entry *e = &ifwi.bpdt_entries[0]; + + for (size_t i = 0; i < ifwi.bpdt_ops->get_entry_count(ifwi.bpdt_hdr); i++, e++) { + if (e->type == type) + return e; + } + + return NULL; +} + +static struct bpdt_entry *new_bpdt_entry(void) +{ + size_t count = ifwi.bpdt_ops->get_entry_count(ifwi.bpdt_hdr); + if (count == MAX_SUBPARTS) { + ERROR("No space for new BPDT entry!\n"); + return NULL; + } + + ifwi.bpdt_ops->inc_entry_count(ifwi.bpdt_hdr); + + return &ifwi.bpdt_entries[count]; +} + +static void set_file_end_offset(struct buffer *buff) +{ + struct bpdt_entry *e = &ifwi.bpdt_entries[0]; + size_t end_offset; + size_t count = ifwi.bpdt_ops->get_entry_count(ifwi.bpdt_hdr); + + ifwi.file_end_offset = ALIGN_UP(buffer_offset(buff), BUFF_SIZE_ALIGN); + + for (size_t i = 0; i < count; i++, e++) { + end_offset = e->offset + e->size; + if (end_offset > ifwi.file_end_offset) + ifwi.file_end_offset = end_offset; + + } +} + +static void read_bpdt_entries(struct buffer *buff) +{ + struct bpdt_entry *e = &ifwi.bpdt_entries[0]; + size_t count = ifwi.bpdt_ops->get_entry_count(ifwi.bpdt_hdr); + + for (size_t i = 0; i < count; i++, e++) { + READ_MEMBER(buff, e->type); + READ_MEMBER(buff, e->offset); + READ_MEMBER(buff, e->size); + } +} + +static int write_bpdt_entries(struct buffer *buff) +{ + struct bpdt_entry *e = &ifwi.bpdt_entries[0]; + size_t count = ifwi.bpdt_ops->get_entry_count(ifwi.bpdt_hdr); + + if (buffer_size(buff) < count * sizeof(*e)) { + ERROR("Not enough buffer space for bpdt entries!\n"); + return -1; + } + + for (size_t i = 0; i < count; i++, e++) { + WRITE_MEMBER(buff, e->type); + WRITE_MEMBER(buff, e->offset); + WRITE_MEMBER(buff, e->size); + } + + return 0; +} + +static void print_bpdt_entries(void) +{ + const size_t count = ifwi.bpdt_ops->get_entry_count(ifwi.bpdt_hdr); + + if (count == 0) + return; + + const struct bpdt_entry *e = &ifwi.bpdt_entries[0]; + + printf("\n * BPDT entries\n"); + + printf("%-25s%-25s%-25s%-25s%-25s%-25s\n", "Entry #", + "Partition Name", "Human readable name", "Type", "Offset", "Size"); + + printf("====================================================================" + "====================================================================\n"); + + for (size_t i = 0; i < count; i++) { + printf("%-25zd%-25s%-25s%-25d0x%-23x0x%-23x" + "\n", i+1, subpart_name(e[i].type), subpart_readable_name(e[i].type), + e[i].type, e[i].offset, e[i].size); + } + + printf("====================================================================" + "====================================================================\n"); +} + +static int ifwi_parse(const char *image_name) +{ + struct buffer *input_buff = &ifwi.input_buff; + struct buffer bpdt_buff; + + if (buffer_from_file(input_buff, image_name)) { + ERROR("Failed to read input file %s\n", image_name); + return -1; + } + + buffer_clone(&bpdt_buff, input_buff); + + ifwi.bpdt_ops = get_bpdt_ops(&bpdt_buff); + if (!ifwi.bpdt_ops) { + ERROR("No matching bpdt_ops!\n"); + return -1; + } + + ifwi.bpdt_hdr = ifwi.bpdt_ops->read_hdr(&bpdt_buff); + if (ifwi.bpdt_hdr == NULL) + return -1; + + read_bpdt_entries(&bpdt_buff); + set_file_end_offset(&bpdt_buff); + + if (!ifwi.bpdt_ops->validate_checksum(ifwi.bpdt_hdr, &ifwi.bpdt_entries[0])) { + ERROR("Checksum failed!\n"); + return -1; + } + + ifwi.subpart_hdr_ops = get_subpart_hdr_ops(); + if (ifwi.subpart_hdr_ops == NULL) { + ERROR("No matching subpart_hdr_ops for given BPDT!\n"); + return -1; + } + + ifwi.subpart_entry_ops = get_subpart_entry_ops(); + if (ifwi.subpart_entry_ops == NULL) { + ERROR("No matching subpart_entry_ops for given BPDT!\n"); + return -1; + } + + return subpart_read(&ifwi.input_buff); +} + +static int subpart_write(struct buffer *buff) +{ + struct bpdt_entry *e; + struct buffer *s_buff; + + for (size_t i = 0; i < ifwi.bpdt_ops->get_entry_count(ifwi.bpdt_hdr); i++) { + e = &ifwi.bpdt_entries[i]; + + if (e->size == 0) + continue; + + if (e->offset + e->size > buffer_size(buff)) { + ERROR("Subpart end(0x%x) overflows buffer size(0x%zx)\n", + e->offset + e->size, buffer_size(buff)); + return -1; + } + + s_buff = subpart_buff(e->type); + + if (buffer_size(s_buff) != e->size) { + ERROR("Subpart buffer size does not match BPDT entry size!\n"); + return -1; + } + + memcpy(buffer_get(buff) + e->offset, buffer_get(s_buff), e->size); + } + + return 0; +} + +static int ifwi_repack(void) +{ + if (!ifwi.repack) + return 0; + + struct buffer output_buff; + const size_t size = ifwi.file_end_offset; + struct buffer bpdt_buff; + + if (buffer_create(&output_buff, size, "Output IFWI")) { + ERROR("Unable to allocate output buff!\n"); + return -1; + } + + buffer_clone(&bpdt_buff, &output_buff); + + ifwi.bpdt_ops->update_checksum(ifwi.bpdt_hdr, &ifwi.bpdt_entries[0]); + + if (ifwi.bpdt_ops->write_hdr(&bpdt_buff, ifwi.bpdt_hdr)) + return -1; + + if (write_bpdt_entries(&bpdt_buff)) + return -1; + + subpart_write(&output_buff); + + if (buffer_write_file(&output_buff, params.image_name)) { + ERROR("File write error!\n"); + return -1; + } + + printf("Image written successfully to %s.\n", params.image_name); + return 0; +} + +static bool should_process_partition(int type) +{ + if (params.partition_name) { + const char *name = subpart_name(type); + + if (!name) + return false; + + if (strcmp(params.partition_name, name)) + return false; + } else if (params.partition_type != NO_PARTITION_TYPE) { + if (params.partition_type != type) + return false; + } + + return true; +} + +static int process_entries(int (*fn)(const struct bpdt_entry *e)) +{ + struct bpdt_entry *e = &ifwi.bpdt_entries[0]; + bool found = false; + + for (size_t i = 0; i < ifwi.bpdt_ops->get_entry_count(ifwi.bpdt_hdr); i++, e++) { + if (e->size == 0) + continue; + + if (!should_process_partition(e->type)) + continue; + + if (fn(e)) + return -1; + + found = true; + } + + if (!found && params.partition_name) { + ERROR("Partition %s not found!\n", params.partition_name); + return -1; + } + + if (!found && params.partition_type != NO_PARTITION_TYPE) { + ERROR("Partition type %d not found!\n", params.partition_type); + return -1; + } + + return 0; +} + +static int print_subpart(const struct bpdt_entry *e) +{ + struct buffer buff; + subpart_hdr_ptr hdr; + + printf("\n\n * Subpart entry #%d(%s)\n", e->type, subpart_readable_name(e->type)); + + buffer_clone(&buff, subpart_buff(e->type)); + hdr = ifwi.subpart_hdr_ops->read(&buff); + if (!hdr) { + ERROR("Failed to read subpart header!\n"); + return -1; + } + + ifwi.subpart_hdr_ops->print(hdr); + ifwi.subpart_entry_ops->print(&buff, ifwi.subpart_hdr_ops->get_entry_count(hdr)); + ifwi.subpart_hdr_ops->free(hdr); + + return 0; +} + +static int cmd_print(void) +{ + ifwi.bpdt_ops->print_hdr(ifwi.bpdt_hdr); + print_bpdt_entries(); + + if (!params.print_sub_parts && !params.partition_name && + params.partition_type == NO_PARTITION_TYPE) + return 0; + + return process_entries(print_subpart); +} + +static char *get_file_path(const char *name) +{ + size_t filename_len = strlen(name) + 1; + + /* output_dir name followed by '/' */ + if (params.output_dir) + filename_len += strlen(params.output_dir) + 1; + + char *filepath = malloc(filename_len); + if (!filepath) + return NULL; + + snprintf(filepath, filename_len, "%s%s%s", + params.output_dir ? : "", + params.output_dir ? "/" : "", + name); + + return filepath; +} + +static int write_partition_to_file(const struct bpdt_entry *e) +{ + size_t end_offset = e->offset + e->size - 1; + + if (end_offset > buffer_size(&ifwi.input_buff)) { + ERROR("Offset out of bounds!\n"); + return -1; + } + + const char *name = subpart_name(e->type); + char *filepath = get_file_path(name); + if (!filepath) { + ERROR("Failed to allocate filepath!\n"); + return -1; + } + + printf("Dumping %.4s in %s\n", name, filepath); + + struct buffer buff; + buffer_splice(&buff, &ifwi.input_buff, e->offset, e->size); + buffer_write_file(&buff, filepath); + + free(filepath); + return 0; +} + +static int cmd_dump(void) +{ + struct stat sb; + + if (params.output_dir && (stat(params.output_dir, &sb) == -1)) { + ERROR("Failed to stat %s: %s\n", params.output_dir, strerror(errno)); + return -1; + } + + return process_entries(write_partition_to_file); +} + +static int cmd_print_layout(void) +{ + if (params.version_str == NULL) { + ERROR("No version provided!\n"); + return -1; + } + + const struct bpdt_ops *ops = get_bpdt_ops(NULL); + if (!ops) { + ERROR("No matching bpdt_ops!\n"); + return -1; + } + + struct buffer buff; + if (buffer_from_file(&buff, params.image_name)) { + ERROR("Failed to read input file %s\n", params.image_name); + return -1; + } + + ifwi.cse_layout = ops->read_layout(&buff); + if (!ifwi.cse_layout) { + ERROR("Failed to read CSE layout!\n"); + return -1; + } + + ops->print_layout(ifwi.cse_layout); + + return 0; +} + +static int allocate_buffer(struct buffer *buff, struct buffer *wbuff, const char *str) +{ + if (params.version_str == NULL) { + ERROR("No version provided!\n"); + return -1; + } + + ifwi.bpdt_ops = get_bpdt_ops(NULL); + if (!ifwi.bpdt_ops) + return -1; + + if (buffer_create(buff, BUFF_SIZE_ALIGN, str)) { + ERROR("Buffer creation error!\n"); + return -1; + } + + void *data = buffer_get(buff); + memset(data, 0xff, buffer_size(buff)); + + buffer_clone(wbuff, buff); + + return 0; +} + +static int cmd_create_layout(void) +{ + struct buffer buff, wbuff; + + if (allocate_buffer(&buff, &wbuff, "CSE layout")) + return -1; + + ifwi.cse_layout = ifwi.bpdt_ops->create_layout(¶ms.layout_regions); + if (!ifwi.cse_layout) { + ERROR("Failed to create layout!\n"); + return -1; + } + + if (ifwi.bpdt_ops->write_layout(&wbuff, ifwi.cse_layout)) { + ERROR("Failed to write CSE layout!\n"); + return -1; + } + + buffer_write_file(&buff, params.image_name); + return 0; +} + +static int cmd_create_bpdt(void) +{ + struct buffer buff; + struct buffer wbuff; + + if (allocate_buffer(&buff, &wbuff, "BPDT header")) + return -1; + + ifwi.bpdt_hdr = ifwi.bpdt_ops->create_hdr(); + if (!ifwi.bpdt_hdr) { + ERROR("Failed to create BPDT header!\n"); + return -1; + } + + ifwi.bpdt_ops->update_checksum(ifwi.bpdt_hdr, NULL); + + if (ifwi.bpdt_ops->write_hdr(&wbuff, ifwi.bpdt_hdr)) { + ERROR("Failed to write BPDT header!\n"); + return -1; + } + + buffer_write_file(&buff, params.image_name); + return 0; +} + +static int cmd_add(void) +{ + if (!params.partition_name && params.partition_type == NO_PARTITION_TYPE) { + ERROR("Partition name/type is required for add!\n"); + return -1; + } + + int type; + + if (params.partition_name) { + type = subpart_get_type_from_name(params.partition_name); + if (type == NO_PARTITION_TYPE) { + ERROR("Invalid partition %s\n", params.partition_name); + return -1; + } + } else { + type = params.partition_type; + if (type > MAX_SUBPARTS) { + ERROR("Invalid type %d\n", type); + return -1; + } + } + + struct bpdt_entry *e = find_bpdt_entry(type); + if (e) { + ERROR("Partition %s(%d) already exists!\n", params.partition_name ? : "", type); + return -1; + } + + e = new_bpdt_entry(); + if (e == NULL) + return -1; + + e->type = type; + e->offset = 0; + e->size = 0; + + ifwi.repack = true; + + if (params.input_file == NULL) + return 0; + + struct buffer *buff = subpart_buff(type); + if (buffer_from_file_aligned_size(buff, params.input_file, BUFF_SIZE_ALIGN)) { + ERROR("Failed to read input file %s\n", params.input_file); + return -1; + } + + e->offset = ALIGN_UP(ifwi.file_end_offset, BUFF_SIZE_ALIGN); + e->size = buffer_size(buff); + + ifwi.file_end_offset = e->offset + e->size; + + return 0; +} + +static void parse_region(struct region *r, char *arg) +{ + char *tok; + + tok = strtok(arg, ":"); + r->offset = strtol(tok, NULL, 0); + + tok = strtok(NULL, ":"); + r->size = strtol(tok, NULL, 0); +} + +static struct command { + const char *name; + const char *optstring; + int (*cb)(void); + bool parse_ifwi; +} commands[] = { + { "print", "n:st:?", cmd_print, true }, + { "dump", "n:o:t:?", cmd_dump, true }, + { "create-layout", "v:?", cmd_create_layout, false }, + { "print-layout", "v:?", cmd_print_layout, false }, + { "create-bpdt", "v:?", cmd_create_bpdt, false }, + { "add", "f:n:t:v:?", cmd_add, true }, +}; + +enum { + LONGOPT_START = 256, + LONGOPT_BP1 = LONGOPT_START, + LONGOPT_BP2, + LONGOPT_BP3, + LONGOPT_BP4, + LONGOPT_DATA, + + LONGOPT_END, +}; + +static struct option long_options[] = { + {"help", required_argument, 0, 'h'}, + {"parition_name", required_argument, 0, 'n'}, + {"output_dir", required_argument, 0, 'o'}, + {"sub_partition", no_argument, 0, 's'}, + {"version", required_argument, 0, 'v'}, + {"bp1", required_argument, 0, LONGOPT_BP1}, + {"bp2", required_argument, 0, LONGOPT_BP2}, + {"bp3", required_argument, 0, LONGOPT_BP3}, + {"bp4", required_argument, 0, LONGOPT_BP4}, + {"dp", required_argument, 0, LONGOPT_DATA}, + {NULL, 0, 0, 0 } +}; + +static bool valid_opt(size_t i, int c) +{ + /* Check if it is one of the optstrings supported by the command. */ + if (strchr(commands[i].optstring, c)) + return true; + + /* + * Check if it is one of the non-ASCII characters. Currently, the + * non-ASCII characters are only checked against the valid list + * irrespective of the command. + */ + return c >= LONGOPT_START && c < LONGOPT_END; +} + +static void usage(const char *name) +{ + printf("%s: Utility for stitching CSE components\n" + "USAGE:\n" + " %s FILE COMMAND\n\n" + "COMMANDs:\n" + " print [-s][-n NAME][-t TYPE]\n" + " dump [-o DIR][-n NAME]\n" + " create-layout --dp --bp1 --bp2 -v VERSION\n" + " print-layout -v VERSION\n" + " create-bpdt -v VERSION\n" + " add [-n NAME][-t TYPE][-f INPUT_FILE]\n" + "\nOPTIONS:\n" + " -f INPUT_FILE : Input file\n" + " -n NAME : Sub-partition name\n" + " -o DIR : Output directory\n" + " -s : Print sub-partition info\n" + " -t TYPE : Sub-partition type\n" + " -v VERSION : BPDT version\n" + " --dp : Offset and size of data partition\n" + " --bp1 : Offset and size of BP1\n" + " --bp2 : Offset and size of BP2\n" + " --bp3 : Offset and size of BP3\n" + " --bp4 : Offset and size of BP4\n" + "\n", + name, name); +} + +int main(int argc, char **argv) +{ + if (argc < 3) { + printf("Incorrect number of args(%d)!\n", argc); + usage(argv[0]); + return 1; + } + + const char *prog_name = argv[0]; + const char *image_name = argv[1]; + const char *cmd = argv[2]; + + size_t i; + + params.partition_type = NO_PARTITION_TYPE; + params.image_name = image_name; + + for (i = 0; i < ARRAY_SIZE(commands); i++) { + if (strcmp(cmd, commands[i].name)) + continue; + + int c; + int option_index; + + while (1) { + c = getopt_long(argc, argv, commands[i].optstring, + long_options, &option_index); + + if (c == -1) + break; + + if (!valid_opt(i, c)) { + if (c < LONGOPT_START) { + ERROR("Invalid option -- '%c'\n", c); + } else { + ERROR("Invalid option -- '%d'\n", c); + } + usage(prog_name); + return 1; + } + + switch (c) { + case 'f': + params.input_file = optarg; + break; + case 'n': + params.partition_name = optarg; + break; + case 'o': + params.output_dir = optarg; + break; + case 's': + params.print_sub_parts = true; + break; + case 'v': + params.version_str = optarg; + break; + case 't': + params.partition_type = atoi(optarg); + break; + case LONGOPT_BP1: + parse_region(¶ms.layout_regions.bp1, optarg); + break; + case LONGOPT_BP2: + parse_region(¶ms.layout_regions.bp2, optarg); + break; + case LONGOPT_BP3: + parse_region(¶ms.layout_regions.bp3, optarg); + break; + case LONGOPT_BP4: + parse_region(¶ms.layout_regions.bp4, optarg); + break; + case LONGOPT_DATA: + parse_region(¶ms.layout_regions.data_partition, optarg); + break; + case 'h': + case '?': + default: + usage(prog_name); + return 1; + } + } + + break; + } + + if (i == ARRAY_SIZE(commands)) { + printf("No command match %s!\n", cmd); + usage(prog_name); + return 1; + } + + if (commands[i].parse_ifwi && ifwi_parse(image_name)) + return 1; + + if (commands[i].cb()) + return 1; + + return ifwi_repack(); +} diff --git a/util/cbfstool/cse_serger.h b/util/cbfstool/cse_serger.h new file mode 100644 index 00000000000..b60a9c7a0a0 --- /dev/null +++ b/util/cbfstool/cse_serger.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __CBFSTOOL_CSE_SERGER_H__ +#define __CBFSTOOL_CSE_SERGER_H__ + +#include +#include + +#include "common.h" + +#define BPDT_SIGNATURE (0x000055AA) + +#define BUFF_SIZE_ALIGN (4 * KiB) + +#define READ_MEMBER(_buff, _x) read_member(_buff, &(_x), sizeof(_x)) +#define WRITE_MEMBER(_buff, _x) write_member(_buff, &(_x), sizeof(_x)) + +enum bpdt_version { + BPDT_VERSION_1_6 = 1, + BPDT_VERSION_1_7 = 2, +}; + +enum subpart_hdr_version { + SUBPART_HDR_VERSION_1 = 1, + SUBPART_HDR_VERSION_2 = 2, +}; + +enum subpart_entry_version { + SUBPART_ENTRY_VERSION_1 = 1, +}; + +struct cse_layout_regions { + struct region data_partition; + struct region bp1; + struct region bp2; + struct region bp3; + struct region bp4; +}; + +typedef void *cse_layout_ptr; +typedef void *bpdt_hdr_ptr; +typedef void *subpart_hdr_ptr; + +struct bpdt_entry { + uint32_t type; + uint32_t offset; + uint32_t size; +} __packed; + +struct bpdt_ops { + bool (*match_version)(const struct buffer *buff); + + bpdt_hdr_ptr (*create_hdr)(void); + void (*print_hdr)(const bpdt_hdr_ptr ptr); + bpdt_hdr_ptr (*read_hdr)(struct buffer *buff); + int (*write_hdr)(struct buffer *buff, const bpdt_hdr_ptr ptr); + + size_t (*get_entry_count)(const bpdt_hdr_ptr ptr); + void (*inc_entry_count)(bpdt_hdr_ptr ptr); + + cse_layout_ptr (*create_layout)(const struct cse_layout_regions *regions); + void (*print_layout)(const cse_layout_ptr ptr); + cse_layout_ptr (*read_layout)(struct buffer *buff); + int (*write_layout)(struct buffer *buff, const cse_layout_ptr ptr); + + void (*update_checksum)(bpdt_hdr_ptr ptr, struct bpdt_entry *entry); + bool (*validate_checksum)(bpdt_hdr_ptr ptr, struct bpdt_entry *entry); + + enum subpart_hdr_version subpart_hdr_version; + enum subpart_entry_version subpart_entry_version; +}; + +struct subpart_hdr_ops { + subpart_hdr_ptr (*read)(struct buffer *buffer); + void (*print)(const subpart_hdr_ptr ptr); + size_t (*get_entry_count)(const subpart_hdr_ptr ptr); + void (*free)(subpart_hdr_ptr ptr); +}; + +struct subpart_entry_ops { + void (*print)(struct buffer *buff, size_t size); +}; + +extern const struct bpdt_ops bpdt_1_7_ops; +extern const struct bpdt_ops bpdt_1_6_ops; + +extern const struct subpart_hdr_ops subpart_hdr_1_ops; +extern const struct subpart_hdr_ops subpart_hdr_2_ops; + +extern const struct subpart_entry_ops subpart_entry_1_ops; + +void read_member(struct buffer *buff, void *dst, size_t size); +void write_member(struct buffer *buff, void *src, size_t size); + +#endif /* __CBFSTOOL_CSE_SERGER_H__ */ From 555f0407721ca1c29e3d6f3a6f4076fdcb550915 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 8 Oct 2021 15:18:33 -0700 Subject: [PATCH 201/320] util/cse*: Add cse_helpers.{c,h} This change moves `read_member` and `write_member` helper functions out of cse_fpt.c and cse_serger.c into cse_helpers.c to avoid duplication. BUG=b:189177186,b:189167923 Change-Id: I7b646b29c9058d892bb0fc9824ef1b4340d2510c Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58201 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- util/cbfstool/Makefile.inc | 2 ++ util/cbfstool/cse_fpt.c | 24 ---------------- util/cbfstool/cse_fpt.h | 5 +--- util/cbfstool/cse_helpers.c | 56 +++++++++++++++++++++++++++++++++++++ util/cbfstool/cse_helpers.h | 16 +++++++++++ util/cbfstool/cse_serger.c | 50 --------------------------------- util/cbfstool/cse_serger.h | 7 +---- 7 files changed, 76 insertions(+), 84 deletions(-) create mode 100644 util/cbfstool/cse_helpers.c create mode 100644 util/cbfstool/cse_helpers.h diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 0a445b5942b..4651f512a37 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -100,12 +100,14 @@ include $(top)/util/cbfstool/fpt_formats/Makefile.inc cse_fpt_obj := cse_fpt_obj += cse_fpt.o cse_fpt_obj += common.o +cse_fpt_obj += cse_helpers.o cse_fpt_obj += $(foreach var, $(fpt_formats_obj), $(var)) include $(top)/util/cbfstool/bpdt_formats/Makefile.inc cse_serger_obj := cse_serger_obj += cse_serger.o cse_serger_obj += common.o +cse_serger_obj += cse_helpers.o cse_serger_obj += $(foreach var, $(bpdt_formats_obj), $(var)) TOOLCFLAGS ?= -Werror -Wall -Wextra -Wshadow diff --git a/util/cbfstool/cse_fpt.c b/util/cbfstool/cse_fpt.c index bde3a8c1655..51fa9d0fbce 100644 --- a/util/cbfstool/cse_fpt.c +++ b/util/cbfstool/cse_fpt.c @@ -64,30 +64,6 @@ static void usage(const char *name) name, name); } -void read_member(struct buffer *buff, void *dst, size_t size) -{ - uint8_t *src = buffer_get(buff); - - switch (size) { - case 1: - *(uint8_t *)dst = read_le8(src); - break; - case 2: - *(uint16_t *)dst = read_le16(src); - break; - case 4: - *(uint32_t *)dst = read_le32(src); - break; - case 8: - *(uint64_t *)dst = read_le64(src); - break; - default: - memcpy(dst, src, size); - } - - buffer_seek(buff, size); -} - static int get_fpt_buff(struct buffer *input_buff, struct buffer *fpt_buff) { /* diff --git a/util/cbfstool/cse_fpt.h b/util/cbfstool/cse_fpt.h index eda8a079309..3f9c1855b40 100644 --- a/util/cbfstool/cse_fpt.h +++ b/util/cbfstool/cse_fpt.h @@ -7,12 +7,11 @@ #include #include "common.h" +#include "cse_helpers.h" #define FPT_MARKER "$FPT" #define FPT_ENTRY_VERSION 0x10 -#define READ_MEMBER(_buff, _x) read_member(_buff, &(_x), sizeof(_x)) - enum fpt_hdr_version { FPT_HDR_VERSION_20 = 0x20, FPT_HDR_VERSION_21 = 0x21, @@ -32,6 +31,4 @@ struct fpt_hdr_ops { extern const struct fpt_hdr_ops fpt_hdr_20_ops; extern const struct fpt_hdr_ops fpt_hdr_21_ops; -void read_member(struct buffer *buff, void *dst, size_t size); - #endif /* __CBFSTOOL_CSE_FPT_H__ */ diff --git a/util/cbfstool/cse_helpers.c b/util/cbfstool/cse_helpers.c new file mode 100644 index 00000000000..c60005a21ac --- /dev/null +++ b/util/cbfstool/cse_helpers.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Helper functions for cse_serger and cse_fpt */ + +#include + +#include "cse_helpers.h" + +void write_member(struct buffer *buff, void *src, size_t size) +{ + void *dst = buffer_get(buff); + + switch (size) { + case 1: + write_le8(dst, *(uint8_t *)src); + break; + case 2: + write_le16(dst, *(uint16_t *)src); + break; + case 4: + write_le32(dst, *(uint32_t *)src); + break; + case 8: + write_le64(dst, *(uint64_t *)src); + break; + default: + memcpy(dst, src, size); + break; + } + + buffer_seek(buff, size); +} + +void read_member(struct buffer *buff, void *dst, size_t size) +{ + const void *src = buffer_get(buff); + + switch (size) { + case 1: + *(uint8_t *)dst = read_le8(src); + break; + case 2: + *(uint16_t *)dst = read_le16(src); + break; + case 4: + *(uint32_t *)dst = read_le32(src); + break; + case 8: + *(uint64_t *)dst = read_le64(src); + break; + default: + memcpy(dst, src, size); + break; + } + + buffer_seek(buff, size); +} diff --git a/util/cbfstool/cse_helpers.h b/util/cbfstool/cse_helpers.h new file mode 100644 index 00000000000..58ba1287511 --- /dev/null +++ b/util/cbfstool/cse_helpers.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "common.h" + +#define READ_MEMBER(_buff, _x) read_member(_buff, &(_x), sizeof(_x)) +#define WRITE_MEMBER(_buff, _x) write_member(_buff, &(_x), sizeof(_x)) + +/* Write data from `src` of length `size` to buffer in little-endian format and seek the buffer + forward by `size` bytes. */ +void write_member(struct buffer *buff, void *src, size_t size); + +/* Read data from buffer in little-endian format of length `size` to `dst` and seek the buffer + forward by `size` bytes. */ +void read_member(struct buffer *buff, void *dst, size_t size); diff --git a/util/cbfstool/cse_serger.c b/util/cbfstool/cse_serger.c index cc49671d190..c8bd1040e3e 100644 --- a/util/cbfstool/cse_serger.c +++ b/util/cbfstool/cse_serger.c @@ -165,56 +165,6 @@ static int subpart_get_type_from_name(const char *name) return -1; } -void write_member(struct buffer *buff, void *src, size_t size) -{ - void *dst = buffer_get(buff); - - switch (size) { - case 1: - write_le8(dst, *(uint8_t *)src); - break; - case 2: - write_le16(dst, *(uint16_t *)src); - break; - case 4: - write_le32(dst, *(uint32_t *)src); - break; - case 8: - write_le64(dst, *(uint64_t *)src); - break; - default: - memcpy(dst, src, size); - break; - } - - buffer_seek(buff, size); -} - -void read_member(struct buffer *buff, void *dst, size_t size) -{ - const void *src = buffer_get(buff); - - switch (size) { - case 1: - *(uint8_t *)dst = read_le8(src); - break; - case 2: - *(uint16_t *)dst = read_le16(src); - break; - case 4: - *(uint32_t *)dst = read_le32(src); - break; - case 8: - *(uint64_t *)dst = read_le64(src); - break; - default: - memcpy(dst, src, size); - break; - } - - buffer_seek(buff, size); -} - static const struct bpdt_ops *get_bpdt_ops(const struct buffer *buff) { assert(buff || params.version_str); diff --git a/util/cbfstool/cse_serger.h b/util/cbfstool/cse_serger.h index b60a9c7a0a0..8727f594228 100644 --- a/util/cbfstool/cse_serger.h +++ b/util/cbfstool/cse_serger.h @@ -7,14 +7,12 @@ #include #include "common.h" +#include "cse_helpers.h" #define BPDT_SIGNATURE (0x000055AA) #define BUFF_SIZE_ALIGN (4 * KiB) -#define READ_MEMBER(_buff, _x) read_member(_buff, &(_x), sizeof(_x)) -#define WRITE_MEMBER(_buff, _x) write_member(_buff, &(_x), sizeof(_x)) - enum bpdt_version { BPDT_VERSION_1_6 = 1, BPDT_VERSION_1_7 = 2, @@ -89,7 +87,4 @@ extern const struct subpart_hdr_ops subpart_hdr_2_ops; extern const struct subpart_entry_ops subpart_entry_1_ops; -void read_member(struct buffer *buff, void *dst, size_t size); -void write_member(struct buffer *buff, void *src, size_t size); - #endif /* __CBFSTOOL_CSE_SERGER_H__ */ From 3959aa63518ed2a3fa6b62b82a9f6daf75dd38d8 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 1 Oct 2021 15:18:09 -0700 Subject: [PATCH 202/320] southbridge/intel/common: Add an option to allow stitching of CSE binary In the following changes, CSE binary for some platforms will be stitched at build time instead of adding a pre-built binary. This change adds a new Kconfig `STITCH_ME_BIN` which allows mainboard to select if it wants to stitch CSE binary instead of adding a pre-built one. In this case, ME_BIN_PATH is not visible to user and instead mainboard and/or SoC code is expected to provide the recipe for stitching the CSE image. BUG=b:189177580 Change-Id: I78ab377e110610f9ef4d86a2b6eeb4113897df85 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58083 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/southbridge/intel/common/firmware/Kconfig | 13 +++++++++++-- .../intel/common/firmware/Makefile.inc | 15 +++++++++++++-- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index ab0373a6081..b9b766c7083 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -37,10 +37,19 @@ config HAVE_ME_BIN coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME/TXE firmware on your flash ROM. +config STITCH_ME_BIN + bool "Stitch individual ME/CSE components" + default n + depends on HAVE_ME_BIN + help + This config can be selected by mainboard if it wants to stitch ME/CSE + components during build time instead of supplying a pre-stitched + binary. + config ME_BIN_PATH - string "Path to management engine firmware" + string "Path to management engine firmware" if !STITCH_ME_BIN default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/me.bin" - depends on HAVE_ME_BIN + depends on HAVE_ME_BIN && !STITCH_ME_BIN config CHECK_ME bool "Verify the integrity of the supplied ME/TXE firmware" diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index d5a48fd6f97..693bafb7a85 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -25,7 +25,18 @@ endif add_intel_firmware: $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) ifeq ($(CONFIG_HAVE_ME_BIN),y) -add_intel_firmware: $(call strip_quotes,$(CONFIG_ME_BIN_PATH)) + +OBJ_ME_BIN := $(obj)/me.bin + +ifneq ($(CONFIG_STITCH_ME_BIN),y) + +$(OBJ_ME_BIN): $(call strip_quotes,$(CONFIG_ME_BIN_PATH)) + cp $< $@ + +endif + +add_intel_firmware: $(OBJ_ME_BIN) + endif ifeq ($(CONFIG_HAVE_GBE_BIN),y) add_intel_firmware: $(call strip_quotes,$(CONFIG_GBE_BIN_PATH)) @@ -46,7 +57,7 @@ ifeq ($(CONFIG_HAVE_ME_BIN),y) printf " IFDTOOL me.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ $(IFDTOOL_USE_CHIPSET) \ - -i ME:$(CONFIG_ME_BIN_PATH) \ + -i ME:$(OBJ_ME_BIN) \ -O $(obj)/coreboot.pre \ $(obj)/coreboot.pre endif From 6ef863c5c43aaccbc99c8518832e786f8cd5e9d1 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 1 Oct 2021 11:39:48 -0700 Subject: [PATCH 203/320] soc/intel/common/cse: Add support for stitching CSE components This change adds support for allowing mainboards to stitch CSE components during build time instead of adding a pre-built CSE binary. Several Kconfig options are added to allow mainboard to provide the file names for different CSE region components. This makes use of the newly added cse_serger and cse_fpt tools to create following partitions: 1. BP1 - RO 2. BP2 - RW 3. Layout In addition to this, it accepts CSE data partition as an input using Kconfig CSE_DATA_FILE. All these partitions are then assembled together as per the following mainboard FMAP regions: 1. BP1(RO) : CSE_RO 2. BP2(RW) : CSE_RW 3. Layout : CSE_LAYOUT 4. Data : CSE_DATA Finally, it generates the target $(OBJ_ME_BIN) which is used to put together the binary in final coreboot.rom image. Several helper functions are added to soc/intel/Makefile.inc to allow SoCs to define which components use: 1. Decomposed files: Files decomposed from Intel release CSE binary in FPT format. 2. Input files: Mainboard provided input files using corresponding Kconfigs. 3. Dummy: Components that are required to have dummy entries in BPDT header. These helpers are added to soc/intel/Makefile.inc to ensure that the functions are defined by the time the invocations are encountered in SoC Makefile.inc. BUG=b:189177580 Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67 Signed-off-by: Bernardo Perez Priego Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/57353 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/Makefile.inc | 44 ++++++++++++++ src/soc/intel/common/block/cse/Kconfig | 64 +++++++++++++++++++++ src/soc/intel/common/block/cse/Makefile.inc | 62 ++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 src/soc/intel/Makefile.inc diff --git a/src/soc/intel/Makefile.inc b/src/soc/intel/Makefile.inc new file mode 100644 index 00000000000..bf0d52cd1aa --- /dev/null +++ b/src/soc/intel/Makefile.inc @@ -0,0 +1,44 @@ +ifeq ($(CONFIG_STITCH_ME_BIN),y) + +objcse := $(obj)/cse +additional-dirs += $(objcse) + +define cse_input_path +$(call strip_quotes,$(CONFIG_CSE_COMPONENTS_PATH))/$(call strip_quotes,$(1)) +endef + +define cse_add_dummy +$(eval cse_$(1)_ingredients+=$(2)) +endef + +define cse_add_dummy_to_bp1_bp2 +$(call cse_add_dummy,bp1,$(1)) +$(call cse_add_dummy,bp2,$(1)) +endef + +define cse_add_file +$(eval cse_$(3)_ingredients+=$(4)) +$(eval file=$(2)) +$(eval $(4)-file=$(file)) +$(eval $(1)+=$(if $(filter $(file),$($(1))),,$(file))) +endef + +define cse_add_decomp +$(call cse_add_file,cse_decomp_files,$(objcse)/$(2),$(1),$(2)) +endef + +define cse_add_decomp_to_bp1_bp2 +$(call cse_add_decomp,bp1,$(1)) +$(call cse_add_decomp,bp2,$(1)) +endef + +define cse_add_input +$(call cse_add_file,cse_input_files,$(call cse_input_path,$(CONFIG_CSE_$(2)_FILE)),$(1),$(2)) +endef + +define cse_add_input_to_bp1_bp2 +$(call cse_add_input,bp1,$(1)) +$(call cse_add_input,bp2,$(1)) +endef + +endif diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index e06895080e9..4305deaf2b6 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -85,3 +85,67 @@ config SOC_INTEL_CSE_SET_EOP This config ensures coreboot will send the CSE the End-of-POST message just prior to loading the payload. This is a security feature so the CSE will no longer respond to Pre-Boot commands. + +if STITCH_ME_BIN + +config CSE_COMPONENTS_PATH + string "Path to directory containing all CSE input components to stitch" + default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/firmware" + help + This is the file path containing all the input CSE component files. + These will be used by cse_serger tool to stitch CSE image. + +config CSE_FPT_FILE + string "Name of CSE FPT file" + default "cse_fpt.bin" + help + This file is the CSE input binary as released by Intel in a CSE kit. + +config CSE_DATA_FILE + string "Name of CSE data file" + default "cse_data.bin" + help + This file is the CSE data binary typically generated by Intel FIT tool. + +config CSE_PMCP_FILE + string "Name of PMC file" + default "pmc.bin" + help + This file is the PMC input binary as released by Intel in a CSE kit. + +config CSE_IOMP_FILE + string "Name of IOM file" + default "iom.bin" + help + This file is the IOM input binary as released by Intel in a CSE kit. + +config CSE_TBTP_FILE + string "Name of TBT file" + default "tbt.bin" + help + This file is the TBT input binary as released by Intel in a CSE kit. + +config CSE_NPHY_FILE + string "Name of NPHY file" + default "nphy.bin" + help + This file is the NPHY input binary as released by Intel in a CSE kit. + +config CSE_PCHC_FILE + string "Name of PCHC file" + default "pchc.bin" + help + This file is the PCHC input binary as released by Intel in a CSE kit. + +config CSE_IUNP_FILE + string "Name of IUNIT file" + default "iunit.bin" + help + This file is the PCHC input binary as released by Intel in a CSE kit. + +config CSE_BPDT_VERSION + string + help + This config indicates the BPDT version used by CSE for a given SoC. + +endif diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 9b50704a57c..5c81d892f8e 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -6,6 +6,68 @@ smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c +ifeq ($(CONFIG_STITCH_ME_BIN),y) + +CSE_BP1_BIN := $(objcse)/cse_bp1.bin +CSE_BP2_BIN := $(objcse)/cse_bp2.bin +CSE_LAYOUT_BIN := $(objcse)/cse_layout.bin + +CSE_BPDT_VERSION := $(call strip_quotes,$(CONFIG_CSE_BPDT_VERSION)) +ifeq ($(CONFIG_CSE_BPDT_VERSION),) +$(error "CONFIG_CSE_BPDT_VERSION is not set!") +endif + +CSE_FPT_INPUT=$(call cse_input_path,$(CONFIG_CSE_FPT_FILE)) +CSE_DATA_INPUT=$(call cse_input_path,$(CONFIG_CSE_DATA_FILE)) + +get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h) +get_cse_region_offset=$(call int-subtract,$(call get_fmap_value,$(1)) $(CSE_LAYOUT_OFFSET)) + +CSE_LAYOUT_OFFSET=$(call get_fmap_value,FMAP_SECTION_CSE_LAYOUT_START) +CSE_BP1_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_RO_START) +CSE_BP1_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_RO_SIZE) +CSE_BP2_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_RW_START) +CSE_BP2_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_RW_SIZE) +CSE_DP_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_DATA_START) +CSE_DP_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_DATA_SIZE) + +.PHONY: cse_inputs +cse_inputs: $(cse_input_files) + +$(cse_decomp_files): $(CSE_FPT_INPUT) $(CSE_FPT) + printf " DUMP $(@F)\n" + $(CSE_FPT) $< dump -o $(objcse) -n $(@F) > /dev/null + +define cse_add_ingredient + $(if $($(2)-file), \ + printf " CSEADD $(2) ($($(2)-file)) -> $(1)\n"; + $(CSE_SERGER) $@ add -n $(2) -f $($(2)-file) > /dev/null, + printf " CSEADD $(2) (dummy) -> $(1)\n"; + $(CSE_SERGER) $@ add -n $(2) > /dev/null) +endef + +$(objcse)/cse_%.bin: $(CSE_SERGER) cse_inputs $(cse_decomp_files) + printf " CREATE $(@F) (version $(CSE_BPDT_VERSION))\n" + $(CSE_SERGER) $@ create-bpdt -v $(CSE_BPDT_VERSION) > /dev/null + $(foreach ingredient,$(cse_$*_ingredients),\ + $(call cse_add_ingredient,$(@F),$(ingredient));) + +$(CSE_LAYOUT_BIN): $(obj)/fmap_config.h $(CSE_SERGER) + printf " CREATE $(@F) (version $(CSE_BPDT_VERSION))\n" + $(CSE_SERGER) $@ create-layout -v $(CSE_BPDT_VERSION) \ + --bp1 $(CSE_BP1_OFFSET):$(CSE_BP1_SIZE) \ + --bp2 $(CSE_BP2_OFFSET):$(CSE_BP2_SIZE) \ + --dp $(CSE_DP_OFFSET):$(CSE_DP_SIZE) > /dev/null + +$(OBJ_ME_BIN): $(CSE_BP1_BIN) $(CSE_BP2_BIN) $(CSE_DATA_INPUT) $(CSE_LAYOUT_BIN) + printf " CREATE $(@F)\n" + dd if=$(CSE_LAYOUT_BIN) of=$@ bs=1 conv=notrunc 2> /dev/null + dd if=$(CSE_BP1_BIN) of=$@ bs=1 conv=notrunc seek=$(CSE_BP1_OFFSET) 2> /dev/null + dd if=$(CSE_BP2_BIN) of=$@ bs=1 conv=notrunc seek=$(CSE_BP2_OFFSET) 2> /dev/null + dd if=$(CSE_DATA_INPUT) of=$@ bs=1 conv=notrunc seek=$(CSE_DP_OFFSET) 2> /dev/null + +endif + ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y) ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") From f888c682f80e950ef981251f3234569f3c367fc1 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 5 Oct 2021 21:37:33 -0700 Subject: [PATCH 204/320] soc/intel/alderlake: Enable support for CSE stitching This change enables support for stitching of BP1 and BP2 partitions for CSE. This currently mimics what Intel FIT tool does w.r.t. adding different components to the different partitions. BP1: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP. * Decomposed components from CSE FPT file: RBEP, MFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC. BP2: * Dummy components: DLMP, IFPP, SBDT, UFSP, UFSG, OEMP, ISHP. * Decomposed components from CSE FPT file: RBEP, FTPR, NFTP. * Input components: PMCP, IOMP, NPHY, TBTP, PCHC, IUNP. BUG=b:189177580,b:189177538 Change-Id: I2b14405aab2a4919431d9c16bc7ff2eb1abf1f6b Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58125 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/Kconfig | 7 +++++++ src/soc/intel/alderlake/Makefile.inc | 23 +++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a57d05e660a..530e76859b2 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -321,4 +321,11 @@ config SOC_INTEL_CRASHLOG help Enables CrashLog. +if STITCH_ME_BIN + +config CSE_BPDT_VERSION + default "1.7" + +endif + endif diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index c7e0abc492f..728c58c9672 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -56,4 +56,27 @@ smm-y += xhci.c CPPFLAGS_common += -I$(src)/soc/intel/alderlake CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include + +ifeq ($(CONFIG_STITCH_ME_BIN),y) + +$(call cse_add_dummy_to_bp1_bp2,DLMP) +$(call cse_add_dummy_to_bp1_bp2,IFPP) +$(call cse_add_dummy_to_bp1_bp2,SBDT) +$(call cse_add_decomp_to_bp1_bp2,RBEP) +$(call cse_add_dummy_to_bp1_bp2,UFSP) +$(call cse_add_dummy_to_bp1_bp2,UFSG) +$(call cse_add_dummy_to_bp1_bp2,OEMP) +$(call cse_add_input_to_bp1_bp2,PMCP) +$(call cse_add_decomp,bp1,MFTP) +$(call cse_add_decomp,bp2,FTPR) +$(call cse_add_input_to_bp1_bp2,IOMP) +$(call cse_add_input_to_bp1_bp2,NPHY) +$(call cse_add_input_to_bp1_bp2,TBTP) +$(call cse_add_input_to_bp1_bp2,PCHC) +$(call cse_add_decomp,bp2,NFTP) +$(call cse_add_dummy,bp2,ISHP) +$(call cse_add_input,bp2,IUNP) + +endif + endif From 0a0182e13d2124de3328a90b4a4d556f60d3bf8f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 5 Oct 2021 21:38:15 -0700 Subject: [PATCH 205/320] mb/google/brya: Add sub-regions to SI_ME in chromeos.fmd This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: I4da677da2e24b0398d04786e71490611db635ead Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58126 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/chromeos.fmd | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd index 9e4bfa92c37..4b918750b94 100644 --- a/src/mainboard/google/brya/chromeos.fmd +++ b/src/mainboard/google/brya/chromeos.fmd @@ -1,7 +1,13 @@ FLASH 32M { SI_ALL 5M { SI_DESC 4K - SI_ME + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1588K + CSE_DATA 512K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 3008K + } } SI_BIOS 27M { RW_SECTION_A 8M { From 3f0d64329cbf7c37ace03c98113f76e3862b11e4 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 Oct 2021 00:08:56 -0700 Subject: [PATCH 206/320] soc/intel/common/cse: Support RW update when stitching CSE binary This change updates the STITCH_ME_BIN path to enable support for including CSE RW update in CBFS. CSE_RW_FILE is set to either CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the selection of STITCH_ME_BIN config. BUG=b:189177580 Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58181 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/Kconfig | 2 +- src/soc/intel/common/block/cse/Makefile.inc | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 4305deaf2b6..d1f4d333425 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -64,7 +64,7 @@ config SOC_INTEL_CSE_RW_VERSION_CBFS_NAME CBFS name for Intel CSE CBFS RW version file config SOC_INTEL_CSE_RW_FILE - string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE + string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE && !STITCH_ME_BIN default "" help Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 5c81d892f8e..13f879ef9fe 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -11,6 +11,7 @@ ifeq ($(CONFIG_STITCH_ME_BIN),y) CSE_BP1_BIN := $(objcse)/cse_bp1.bin CSE_BP2_BIN := $(objcse)/cse_bp2.bin CSE_LAYOUT_BIN := $(objcse)/cse_layout.bin +CSE_RW_FILE := $(CSE_BP2_BIN) CSE_BPDT_VERSION := $(call strip_quotes,$(CONFIG_CSE_BPDT_VERSION)) ifeq ($(CONFIG_CSE_BPDT_VERSION),) @@ -70,16 +71,19 @@ endif ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y) +ifeq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"") +$(error "CSE RW version is missing and need to be set by mainboard config") +endif + +ifneq ($(CONFIG_STITCH_ME_BIN),y) + ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") $(error "CSE RW file path is missing and need to be set by mainboard config") endif +CSE_RW_FILE := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) -ifeq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"") -$(error "CSE RW version is missing and need to be set by mainboard config") endif -CSE_RW_FILE=$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) - CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) regions-for-file-$(CSE_LITE_ME_RW) = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME)), \ $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME)) From 5d8f4badda7b8cb0a26312454efef3beabc2f8f0 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 14 Oct 2021 10:02:51 -0700 Subject: [PATCH 207/320] mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_B CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region in case of firmware update. Ensure that the size of the regions match so that we do not have situations where ME_RW_A/B firmware grows bigger than what CSE_RW can hold. BUG=b:189177538 Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58213 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/chromeos.fmd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd index 4b918750b94..72c6429672b 100644 --- a/src/mainboard/google/brya/chromeos.fmd +++ b/src/mainboard/google/brya/chromeos.fmd @@ -14,7 +14,7 @@ FLASH 32M { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3M + ME_RW_A(CBFS) 3008K } RW_LEGACY(CBFS) 2M RW_MISC 1M { @@ -43,7 +43,7 @@ FLASH 32M { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3M + ME_RW_B(CBFS) 3008K } # Make WP_RO region align with SPI vendor # memory protected range specification. From 8b4ca15d7ef1b1397e8f21bd78e411397f43b9e5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 Oct 2021 23:06:09 -0700 Subject: [PATCH 208/320] util/cse_serger: Replace cse_layout_regions with array of regions This change replaces `struct cse_layout_regions` with an array of `struct region` and introduces enums for DP and BP[1-4]. This makes it easier to loop over the different regions in following changes. BUG=b:189177186 Change-Id: If3cced4506d26dc534047cb9c385aaa9418d8522 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58214 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- util/cbfstool/bpdt_formats/bpdt_1_6.c | 18 +++++++-------- util/cbfstool/bpdt_formats/bpdt_1_7.c | 22 +++++++++--------- util/cbfstool/cse_serger.c | 32 ++++++++++++++++++--------- util/cbfstool/cse_serger.h | 15 +++++++------ 4 files changed, 49 insertions(+), 38 deletions(-) diff --git a/util/cbfstool/bpdt_formats/bpdt_1_6.c b/util/cbfstool/bpdt_formats/bpdt_1_6.c index eaa29026702..b894936543e 100644 --- a/util/cbfstool/bpdt_formats/bpdt_1_6.c +++ b/util/cbfstool/bpdt_formats/bpdt_1_6.c @@ -142,21 +142,21 @@ static void inc_bpdt_entry_count(bpdt_hdr_ptr ptr) h->descriptor_count++; } -static cse_layout_ptr create_cse_layout(const struct cse_layout_regions *r) +static cse_layout_ptr create_cse_layout(const struct region *r) { struct cse_layout *l = malloc(sizeof(*l)); if (!l) return NULL; - l->data_offset = r->data_partition.offset; - l->data_size = r->data_partition.size; - l->bp1_offset = r->bp1.offset; - l->bp1_size = r->bp1.size; - l->bp2_offset = r->bp2.offset; - l->bp2_size = r->bp2.size; - l->bp3_offset = r->bp3.offset; - l->bp3_size = r->bp3.size; + l->data_offset = r[DP].offset; + l->data_size = r[DP].size; + l->bp1_offset = r[BP1].offset; + l->bp1_size = r[BP1].size; + l->bp2_offset = r[BP2].offset; + l->bp2_size = r[BP2].size; + l->bp3_offset = r[BP3].offset; + l->bp3_size = r[BP3].size; l->checksum = 0; /* unused */ return 0; diff --git a/util/cbfstool/bpdt_formats/bpdt_1_7.c b/util/cbfstool/bpdt_formats/bpdt_1_7.c index 53294242ca1..9badc82c119 100644 --- a/util/cbfstool/bpdt_formats/bpdt_1_7.c +++ b/util/cbfstool/bpdt_formats/bpdt_1_7.c @@ -185,7 +185,7 @@ static uint32_t calculate_layout_checksum(struct cse_layout *l) return calc_checksum; } -static cse_layout_ptr create_cse_layout(const struct cse_layout_regions *r) +static cse_layout_ptr create_cse_layout(const struct region *r) { struct cse_layout *l = calloc(1, sizeof(*l)); @@ -196,16 +196,16 @@ static cse_layout_ptr create_cse_layout(const struct cse_layout_regions *r) l->size = sizeof(struct cse_layout) - sizeof(l->rom_bypass); l->redundancy = 0; l->checksum = 0; - l->data_offset = r->data_partition.offset; - l->data_size = r->data_partition.size; - l->bp1_offset = r->bp1.offset; - l->bp1_size = r->bp1.size; - l->bp2_offset = r->bp2.offset; - l->bp2_size = r->bp2.size; - l->bp3_offset = r->bp3.offset; - l->bp3_size = r->bp3.size; - l->bp4_offset = r->bp4.offset; - l->bp4_size = r->bp4.size; + l->data_offset = r[DP].offset; + l->data_size = r[DP].size; + l->bp1_offset = r[BP1].offset; + l->bp1_size = r[BP1].size; + l->bp2_offset = r[BP2].offset; + l->bp2_size = r[BP2].size; + l->bp3_offset = r[BP3].offset; + l->bp3_size = r[BP3].size; + l->bp4_offset = r[BP4].offset; + l->bp4_size = r[BP4].size; l->bp5_offset = 0; l->bp5_size = 0; l->temp_base_addr = 0; diff --git a/util/cbfstool/cse_serger.c b/util/cbfstool/cse_serger.c index c8bd1040e3e..13afeab273e 100644 --- a/util/cbfstool/cse_serger.c +++ b/util/cbfstool/cse_serger.c @@ -21,7 +21,7 @@ static struct params { const char *image_name; const char *version_str; const char *input_file; - struct cse_layout_regions layout_regions; + struct region layout_regions[BP_TOTAL]; } params; static const struct { @@ -640,14 +640,14 @@ static int allocate_buffer(struct buffer *buff, struct buffer *wbuff, const char return 0; } -static int cmd_create_layout(void) +static int fill_layout_buffer(struct buffer *buff) { - struct buffer buff, wbuff; + struct buffer wbuff; - if (allocate_buffer(&buff, &wbuff, "CSE layout")) + if (allocate_buffer(buff, &wbuff, "CSE layout")) return -1; - ifwi.cse_layout = ifwi.bpdt_ops->create_layout(¶ms.layout_regions); + ifwi.cse_layout = ifwi.bpdt_ops->create_layout(¶ms.layout_regions[0]); if (!ifwi.cse_layout) { ERROR("Failed to create layout!\n"); return -1; @@ -658,6 +658,16 @@ static int cmd_create_layout(void) return -1; } + return 0; +} + +static int cmd_create_layout(void) +{ + struct buffer buff; + + if (fill_layout_buffer(&buff)) + return -1; + buffer_write_file(&buff, params.image_name); return 0; } @@ -815,7 +825,7 @@ static void usage(const char *name) "COMMANDs:\n" " print [-s][-n NAME][-t TYPE]\n" " dump [-o DIR][-n NAME]\n" - " create-layout --dp --bp1 --bp2 -v VERSION\n" + " create-layout --dp --bp* -v VERSION\n" " print-layout -v VERSION\n" " create-bpdt -v VERSION\n" " add [-n NAME][-t TYPE][-f INPUT_FILE]\n" @@ -896,19 +906,19 @@ int main(int argc, char **argv) params.partition_type = atoi(optarg); break; case LONGOPT_BP1: - parse_region(¶ms.layout_regions.bp1, optarg); + parse_region(¶ms.layout_regions[BP1], optarg); break; case LONGOPT_BP2: - parse_region(¶ms.layout_regions.bp2, optarg); + parse_region(¶ms.layout_regions[BP2], optarg); break; case LONGOPT_BP3: - parse_region(¶ms.layout_regions.bp3, optarg); + parse_region(¶ms.layout_regions[BP3], optarg); break; case LONGOPT_BP4: - parse_region(¶ms.layout_regions.bp4, optarg); + parse_region(¶ms.layout_regions[BP4], optarg); break; case LONGOPT_DATA: - parse_region(¶ms.layout_regions.data_partition, optarg); + parse_region(¶ms.layout_regions[DP], optarg); break; case 'h': case '?': diff --git a/util/cbfstool/cse_serger.h b/util/cbfstool/cse_serger.h index 8727f594228..e1f351abf58 100644 --- a/util/cbfstool/cse_serger.h +++ b/util/cbfstool/cse_serger.h @@ -27,12 +27,13 @@ enum subpart_entry_version { SUBPART_ENTRY_VERSION_1 = 1, }; -struct cse_layout_regions { - struct region data_partition; - struct region bp1; - struct region bp2; - struct region bp3; - struct region bp4; +enum { + DP, + BP1, + BP2, + BP3, + BP4, + BP_TOTAL, }; typedef void *cse_layout_ptr; @@ -56,7 +57,7 @@ struct bpdt_ops { size_t (*get_entry_count)(const bpdt_hdr_ptr ptr); void (*inc_entry_count)(bpdt_hdr_ptr ptr); - cse_layout_ptr (*create_layout)(const struct cse_layout_regions *regions); + cse_layout_ptr (*create_layout)(const struct region *regions); void (*print_layout)(const cse_layout_ptr ptr); cse_layout_ptr (*read_layout)(struct buffer *buff); int (*write_layout)(struct buffer *buff, const cse_layout_ptr ptr); From bf848ad4b297cf59f9107c6390159687d4429009 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 10 Oct 2021 23:07:09 -0700 Subject: [PATCH 209/320] util/cse_serger: Add command `create-cse-region` This change adds a new command `create-cse-region` to cse_serger tool which takes as inputs offset:size and file for different CSE partitions and generates the entire CSE region image. BUG=b:189177186 Change-Id: Ib087f5516e5beb6390831ef4e34b0b067d3fbc8b Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58215 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- util/cbfstool/cse_serger.c | 100 +++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/util/cbfstool/cse_serger.c b/util/cbfstool/cse_serger.c index 13afeab273e..f53b3904af5 100644 --- a/util/cbfstool/cse_serger.c +++ b/util/cbfstool/cse_serger.c @@ -22,6 +22,7 @@ static struct params { const char *version_str; const char *input_file; struct region layout_regions[BP_TOTAL]; + const char *layout_files[BP_TOTAL]; } params; static const struct { @@ -640,6 +641,20 @@ static int allocate_buffer(struct buffer *buff, struct buffer *wbuff, const char return 0; } +static size_t get_cse_region_end_offset(void) +{ + size_t offset = 0; + size_t end_offset; + + for (size_t i = 0; i < BP_TOTAL; i++) { + end_offset = region_end(¶ms.layout_regions[i]); + if (end_offset > offset) + offset = end_offset; + } + + return offset; +} + static int fill_layout_buffer(struct buffer *buff) { struct buffer wbuff; @@ -672,6 +687,58 @@ static int cmd_create_layout(void) return 0; } +static int cmd_create_cse_region(void) +{ + size_t file_size = get_cse_region_end_offset(); + struct buffer cse_buff, layout_buff; + + if (fill_layout_buffer(&layout_buff)) + return -1; + + if (file_size == 0) + file_size = buffer_size(&layout_buff); + + file_size = ALIGN_UP(file_size, BUFF_SIZE_ALIGN); + if (buffer_create(&cse_buff, file_size, "CSE buff")) { + ERROR("CSE buffer creation error!\n"); + return -1; + } + + memset(buffer_get(&cse_buff), 0xff, buffer_size(&cse_buff)); + memcpy(buffer_get(&cse_buff), buffer_get(&layout_buff), buffer_size(&layout_buff)); + + for (size_t i = 0; i < BP_TOTAL; i++) { + struct buffer wbuff, rbuff; + + if (region_sz(¶ms.layout_regions[i]) == 0) + continue; + + buffer_clone(&wbuff, &cse_buff); + buffer_seek(&wbuff, region_offset(¶ms.layout_regions[i])); + + if (params.layout_files[i] == NULL) { + if (i == 0) { + ERROR("File name not provided for DP!\n"); + } else { + ERROR("File name not provided for BP%zd!\n", i); + } + return -1; + } + + if (buffer_from_file(&rbuff, params.layout_files[i])) { + ERROR("Failed to read %s\n", params.layout_files[i]); + return -1; + } + + assert(buffer_size(&wbuff) >= buffer_size(&rbuff)); + memcpy(buffer_get(&wbuff), buffer_get(&rbuff), buffer_size(&rbuff)); + } + + buffer_write_file(&cse_buff, params.image_name); + + return 0; +} + static int cmd_create_bpdt(void) { struct buffer buff; @@ -776,6 +843,7 @@ static struct command { { "print-layout", "v:?", cmd_print_layout, false }, { "create-bpdt", "v:?", cmd_create_bpdt, false }, { "add", "f:n:t:v:?", cmd_add, true }, + { "create-cse-region", "v:?", cmd_create_cse_region, false }, }; enum { @@ -785,6 +853,11 @@ enum { LONGOPT_BP3, LONGOPT_BP4, LONGOPT_DATA, + LONGOPT_BP1_FILE, + LONGOPT_BP2_FILE, + LONGOPT_BP3_FILE, + LONGOPT_BP4_FILE, + LONGOPT_DATA_FILE, LONGOPT_END, }; @@ -796,10 +869,15 @@ static struct option long_options[] = { {"sub_partition", no_argument, 0, 's'}, {"version", required_argument, 0, 'v'}, {"bp1", required_argument, 0, LONGOPT_BP1}, + {"bp1_file", required_argument, 0, LONGOPT_BP1_FILE}, {"bp2", required_argument, 0, LONGOPT_BP2}, + {"bp2_file", required_argument, 0, LONGOPT_BP2_FILE}, {"bp3", required_argument, 0, LONGOPT_BP3}, + {"bp3_file", required_argument, 0, LONGOPT_BP3_FILE}, {"bp4", required_argument, 0, LONGOPT_BP4}, + {"bp4_file", required_argument, 0, LONGOPT_BP4_FILE}, {"dp", required_argument, 0, LONGOPT_DATA}, + {"dp_file", required_argument, 0, LONGOPT_DATA_FILE}, {NULL, 0, 0, 0 } }; @@ -826,6 +904,8 @@ static void usage(const char *name) " print [-s][-n NAME][-t TYPE]\n" " dump [-o DIR][-n NAME]\n" " create-layout --dp --bp* -v VERSION\n" + " create-cse-region --dp --dp_file --bp* " + " --bp*_file -v VERSION\n" " print-layout -v VERSION\n" " create-bpdt -v VERSION\n" " add [-n NAME][-t TYPE][-f INPUT_FILE]\n" @@ -837,10 +917,15 @@ static void usage(const char *name) " -t TYPE : Sub-partition type\n" " -v VERSION : BPDT version\n" " --dp : Offset and size of data partition\n" + " --dp_file : File for data partition\n" " --bp1 : Offset and size of BP1\n" + " --bp1_file : File for BP1 partition\n" " --bp2 : Offset and size of BP2\n" + " --bp2_file : File for BP2 partition\n" " --bp3 : Offset and size of BP3\n" + " --bp3_file : File for BP3 partition\n" " --bp4 : Offset and size of BP4\n" + " --bp4_file : File for BP4 partition\n" "\n", name, name); } @@ -920,6 +1005,21 @@ int main(int argc, char **argv) case LONGOPT_DATA: parse_region(¶ms.layout_regions[DP], optarg); break; + case LONGOPT_BP1_FILE: + params.layout_files[BP1] = optarg; + break; + case LONGOPT_BP2_FILE: + params.layout_files[BP2] = optarg; + break; + case LONGOPT_BP3_FILE: + params.layout_files[BP3] = optarg; + break; + case LONGOPT_BP4_FILE: + params.layout_files[BP4] = optarg; + break; + case LONGOPT_DATA_FILE: + params.layout_files[DP] = optarg; + break; case 'h': case '?': default: From d0975ff5d5eba13f8be8f8e99daf88d41f04579c Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 Oct 2021 23:13:08 -0700 Subject: [PATCH 210/320] soc/intel/common/block/cse: Use newly added `create-cse-region` This change uses the newly added `create-cse-region` command for cse_serger tool instead of performing `dd` operations for each partition. BUG=b:189177580 Change-Id: Ia915e3ac423f9461876e9ae186fb8ddce55f3194 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58216 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/Makefile.inc | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 13f879ef9fe..eac7d904244 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -53,19 +53,12 @@ $(objcse)/cse_%.bin: $(CSE_SERGER) cse_inputs $(cse_decomp_files) $(foreach ingredient,$(cse_$*_ingredients),\ $(call cse_add_ingredient,$(@F),$(ingredient));) -$(CSE_LAYOUT_BIN): $(obj)/fmap_config.h $(CSE_SERGER) - printf " CREATE $(@F) (version $(CSE_BPDT_VERSION))\n" - $(CSE_SERGER) $@ create-layout -v $(CSE_BPDT_VERSION) \ - --bp1 $(CSE_BP1_OFFSET):$(CSE_BP1_SIZE) \ - --bp2 $(CSE_BP2_OFFSET):$(CSE_BP2_SIZE) \ - --dp $(CSE_DP_OFFSET):$(CSE_DP_SIZE) > /dev/null - -$(OBJ_ME_BIN): $(CSE_BP1_BIN) $(CSE_BP2_BIN) $(CSE_DATA_INPUT) $(CSE_LAYOUT_BIN) +$(OBJ_ME_BIN): $(CSE_BP1_BIN) $(CSE_BP2_BIN) $(CSE_DATA_INPUT) $(obj)/fmap_config.h printf " CREATE $(@F)\n" - dd if=$(CSE_LAYOUT_BIN) of=$@ bs=1 conv=notrunc 2> /dev/null - dd if=$(CSE_BP1_BIN) of=$@ bs=1 conv=notrunc seek=$(CSE_BP1_OFFSET) 2> /dev/null - dd if=$(CSE_BP2_BIN) of=$@ bs=1 conv=notrunc seek=$(CSE_BP2_OFFSET) 2> /dev/null - dd if=$(CSE_DATA_INPUT) of=$@ bs=1 conv=notrunc seek=$(CSE_DP_OFFSET) 2> /dev/null + $(CSE_SERGER) $@ create-cse-region -v $(CSE_BPDT_VERSION) \ + --bp1 $(CSE_BP1_OFFSET):$(CSE_BP1_SIZE) --bp1_file $(CSE_BP1_BIN) \ + --bp2 $(CSE_BP2_OFFSET):$(CSE_BP2_SIZE) --bp2_file $(CSE_BP2_BIN) \ + --dp $(CSE_DP_OFFSET):$(CSE_DP_SIZE) --dp_file $(CSE_DATA_INPUT) > /dev/null endif From 2d2cc0dcb97c2ba95d223ed77fce8df1d5aed70e Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 12 Oct 2021 13:19:35 +0800 Subject: [PATCH 211/320] mb/google/brya/var/kano: Correct SSD power sequence M.2 spec describes PERST# should be sequenced after power enable. BUG=b:192137970 TEST=FW_NAME=kano emerge-brya coreboot and boot to OS. Signed-off-by: David Wu Change-Id: I20bf5ca66c6d05229c6d72058c5a73f38a58be3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58237 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/brya/variants/kano/Makefile.inc | 2 ++ src/mainboard/google/brya/variants/kano/gpio.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/src/mainboard/google/brya/variants/kano/Makefile.inc b/src/mainboard/google/brya/variants/kano/Makefile.inc index f2a624c0e8a..5c0f13f868d 100644 --- a/src/mainboard/google/brya/variants/kano/Makefile.inc +++ b/src/mainboard/google/brya/variants/kano/Makefile.inc @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += gpio.c + ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 161ddf1c85d..627354c4abf 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -103,6 +103,8 @@ static const struct pad_config override_gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -118,6 +120,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ @@ -154,6 +158,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), }; +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -165,3 +174,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} From e4047354ec69d09cbff7cbe8d515bad39f9864ed Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 12 Jul 2021 17:24:43 +0200 Subject: [PATCH 212/320] mb/intel/coffeelake_rvp: Rework Kconfig Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_COFFEELAKE_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: I3b3d3cff5ea7a3f4d1c4ddd911240763e4891e06 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/56217 Tested-by: build bot (Jenkins) Reviewed-by: Thomas Heijligen --- src/mainboard/intel/coffeelake_rvp/Kconfig | 58 ++++++++++++++----- .../intel/coffeelake_rvp/Kconfig.name | 9 ++- 2 files changed, 47 insertions(+), 20 deletions(-) diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 98debfb2312..4148b473e44 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,23 +1,51 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVPU - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU - select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU +config BOARD_INTEL_COFFEELAKE_RVP_COMMON + def_bool n + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_MAX98373 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select DRIVERS_I2C_HID - select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_DA7219 - select DRIVERS_I2C_MAX98373 - select DRIVERS_GENERIC_MAX98357A - select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 - select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU - select MAINBOARD_USES_IFD_EC_REGION - select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_USES_IFD_EC_REGION + +config BOARD_INTEL_COFFEELAKE_RVP8 + select BOARD_INTEL_COFFEELAKE_RVP_COMMON + select BOARD_ROMSIZE_KB_16384 + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + +config BOARD_INTEL_COFFEELAKE_RVP11 + select BOARD_INTEL_COFFEELAKE_RVP_COMMON + select BOARD_ROMSIZE_KB_16384 + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + +config BOARD_INTEL_COFFEELAKE_RVPU + select BOARD_INTEL_COFFEELAKE_RVP_COMMON + select BOARD_ROMSIZE_KB_32768 + select SOC_INTEL_COFFEELAKE + +config BOARD_INTEL_WHISKEYLAKE_RVP + select BOARD_INTEL_COFFEELAKE_RVP_COMMON + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_WHISKEYLAKE + +config BOARD_INTEL_COMETLAKE_RVPU + select BOARD_INTEL_COFFEELAKE_RVP_COMMON + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + +if BOARD_INTEL_COFFEELAKE_RVP_COMMON config MAINBOARD_DIR default "intel/coffeelake_rvp" diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index e03e862636c..bebdda4e751 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -2,16 +2,15 @@ comment "Coffeelake RVP" config BOARD_INTEL_COFFEELAKE_RVPU bool "-> Coffeelake U SO-DIMM DDR4 RVP" - select SOC_INTEL_COFFEELAKE + config BOARD_INTEL_COFFEELAKE_RVP11 bool "-> Coffeelake H SO-DIMM DDR4 RVP11" - select SOC_INTEL_COFFEELAKE + config BOARD_INTEL_WHISKEYLAKE_RVP bool "-> Whiskeylake U DDR4 RVP" - select SOC_INTEL_WHISKEYLAKE + config BOARD_INTEL_COFFEELAKE_RVP8 bool "-> Coffeelake S U-DIMM DDR4 RVP8" - select SOC_INTEL_COFFEELAKE + config BOARD_INTEL_COMETLAKE_RVPU bool "-> Cometlake U DDR4 RVP" - select SOC_INTEL_COMETLAKE_1 From e07f9ccc11af137ec3c95de2eef29e493be7bbac Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 12 Jul 2021 18:18:23 +0200 Subject: [PATCH 213/320] mb/intel/kblrvp: Rework Kconfig Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_KBLRVP_COMMON`, which is used as base for each variant. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: I2a9c12a15c098fcb64c006a707c94a1aed93d73a Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/56219 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/mainboard/intel/kblrvp/Kconfig | 36 +++++++++++++++++-------- src/mainboard/intel/kblrvp/Kconfig.name | 3 +++ 2 files changed, 28 insertions(+), 11 deletions(-) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 51f46ba1dfe..2abf8329f6e 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -1,21 +1,35 @@ -if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8 \ - || BOARD_INTEL_KBLRVP11 - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_INTEL_KBLRVP_COMMON + def_bool n select BOARD_ROMSIZE_KB_16384 select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_KBLRVP8 - select SOC_INTEL_KABYLAKE - select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 - select MAINBOARD_HAS_CHROMEOS select HAVE_SPD_IN_CBFS - select MAINBOARD_HAS_LPC_TPM select INTEL_LPSS_UART_FOR_CONSOLE - select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_KBLRVP8 + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_KABYLAKE + +config BOARD_INTEL_KBLRVP3 + select BOARD_INTEL_KBLRVP_COMMON + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + +config BOARD_INTEL_KBLRVP7 + select BOARD_INTEL_KBLRVP_COMMON + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + +config BOARD_INTEL_KBLRVP8 + select BOARD_INTEL_KBLRVP_COMMON + select MAINBOARD_USES_IFD_GBE_REGION + select SKYLAKE_SOC_PCH_H + +config BOARD_INTEL_KBLRVP11 + select BOARD_INTEL_KBLRVP_COMMON + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SKYLAKE_SOC_PCH_H + +if BOARD_INTEL_KBLRVP_COMMON config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/Kconfig.name b/src/mainboard/intel/kblrvp/Kconfig.name index df65e323183..f9cc33d637b 100644 --- a/src/mainboard/intel/kblrvp/Kconfig.name +++ b/src/mainboard/intel/kblrvp/Kconfig.name @@ -1,8 +1,11 @@ config BOARD_INTEL_KBLRVP3 bool "Kabylake LPDDR3 RVP3" + config BOARD_INTEL_KBLRVP7 bool "Kabylake DDR3L RVP7" + config BOARD_INTEL_KBLRVP8 bool "Kabylake DDR4 RVP8" + config BOARD_INTEL_KBLRVP11 bool "Kabylake DDR4 RVP11" From d23981998c81438a2eed6a1c2ba2d4ae54b090f0 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 19 Oct 2021 20:59:35 +0200 Subject: [PATCH 214/320] soc/intel/skl: Constify `soc_get_cstate_map()` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a follow-up to commit e9f10ff38b which changed the base signature and all other occurrences. To make gcc11 happy (which is pickier about these things), let skylake follow. Change-Id: I42a629d865baa53640213a03e54e85623a386e35 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/58458 Reviewed-by: Martin Roth Reviewed-by: Matt DeVillier Reviewed-by: Felix Singer Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 9bbfec3cd5c..4794a998f97 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -128,7 +128,7 @@ static int cstate_set_non_s0ix[] = { C_STATE_C7S_LONG_LAT, }; -acpi_cstate_t *soc_get_cstate_map(size_t *entries) +const acpi_cstate_t *soc_get_cstate_map(size_t *entries) { static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), ARRAY_SIZE(cstate_set_non_s0ix))]; From a61e781e4b7a9c2b918401d0e61a7c86e888ae01 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 12 Jul 2021 19:01:23 +0200 Subject: [PATCH 215/320] mb/intel/jasperlake_rvp: Rework Kconfig Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_JASPERLAKE_RVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: Ic7552195ed5a3ae6ab8e456d7d38d5539a052009 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/56222 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Subrata Banik --- src/mainboard/intel/jasperlake_rvp/Kconfig | 30 +++++++++++++------ .../intel/jasperlake_rvp/Kconfig.name | 6 ---- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 9409432eb56..a5b5c39fd4f 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -1,25 +1,37 @@ -if BOARD_INTEL_JASPERLAKE_RVP || BOARD_INTEL_JASPERLAKE_RVP_EXT_EC - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_INTEL_JASPERLAKE_RVP_COMMON + def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_DA7219 - select DRIVERS_I2C_HID - select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_ACPI - select HAVE_SPD_IN_CBFS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS - select SOC_INTEL_COMMON_BLOCK_IPU - select SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_JASPERLAKE + +config BOARD_INTEL_JASPERLAKE_RVP + select BOARD_INTEL_JASPERLAKE_RVP_COMMON + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + +config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC + select BOARD_INTEL_JASPERLAKE_RVP_COMMON + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_SWITCHES if VBOOT + select INTEL_LPSS_UART_FOR_CONSOLE + +if BOARD_INTEL_JASPERLAKE_RVP_COMMON config MAINBOARD_DIR default "intel/jasperlake_rvp" diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig.name b/src/mainboard/intel/jasperlake_rvp/Kconfig.name index 68419ac1f5f..1a56f05485d 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig.name +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig.name @@ -1,11 +1,5 @@ config BOARD_INTEL_JASPERLAKE_RVP bool "Jasperlake DDR4/LPDDR4 RVP" - select DRIVERS_UART_8250IO - select MAINBOARD_USES_IFD_EC_REGION config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC bool "Jasperlake DDR4/LPDDR4 RVP with Chrome EC" - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_LPC - select EC_GOOGLE_CHROMEEC_SWITCHES if VBOOT - select INTEL_LPSS_UART_FOR_CONSOLE From e874375394f81eddeb7f9a89e1351cb71c43670c Mon Sep 17 00:00:00 2001 From: Joey Peng Date: Wed, 13 Oct 2021 15:46:02 +0800 Subject: [PATCH 216/320] mb/google/brya/var/taeko: Add fw_config probe for ALC5682-VS ALC5682-VD/ALC5682-VS load different kernel driver by different _HID. Update the _HID depending on the AUDIO field of fw_config.Define fw config bit 5-7 in coreboot for codec. BUG=b:202913837 TEST=FW_NAME=taeko emerge-brya coreboot Change-Id: I635b173e0fe4c46d28f2c29fecee1998b29499b1 Signed-off-by: Joey Peng Reviewed-on: https://review.coreboot.org/c/coreboot/+/58292 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/brya/variants/taeko/fw_config.c | 6 ++++++ .../google/brya/variants/taeko/overridetree.cb | 15 +++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/src/mainboard/google/brya/variants/taeko/fw_config.c b/src/mainboard/google/brya/variants/taeko/fw_config.c index 8a7c6b45fd9..5068f84581f 100644 --- a/src/mainboard/google/brya/variants/taeko/fw_config.c +++ b/src/mainboard/google/brya/variants/taeko/fw_config.c @@ -52,5 +52,11 @@ static void fw_config_handle(void *unused) gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); } + + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98357_ALC5682I_VS_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I-VS.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 9c5a19c4cf5..8a76d35bd04 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -16,6 +16,7 @@ fw_config field AUDIO 5 7 option AUDIO_UNKNOWN 0 option AUDIO_MAX98357_ALC5682I_I2S 1 + option AUDIO_MAX98357_ALC5682I_VS_I2S 2 end field KB_LAYOUT 8 9 option KB_LAYOUT_DEFAULT 0 @@ -104,6 +105,20 @@ chip soc/intel/alderlake probe AUDIO AUDIO_MAX98357_ALC5682I_I2S end end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO AUDIO_MAX98357_ALC5682I_VS_I2S + end + end end device ref i2c1 on chip drivers/i2c/hid From bc5f51fa56166e6c2dff273fefba4f3ea7e8bac2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 18 Oct 2021 19:54:21 +0200 Subject: [PATCH 217/320] soc/intel/{skl,apl}: don't run or even include SGX code if disabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not run or include any code in case the user did not explicitly enable SGX through `SOC_INTEL_COMMON_BLOCK_SGX_ENABLE`. Also move the ifdef inside the ASL file. Change-Id: Iec4d3d3eb2811ec14d29aff9601ba325724bc28c Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58426 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons Reviewed-by: Felix Singer --- src/soc/intel/apollolake/acpi.c | 2 +- src/soc/intel/apollolake/acpi/southbridge.asl | 2 -- src/soc/intel/common/acpi/sgx.asl | 2 ++ src/soc/intel/common/block/sgx/Makefile.inc | 2 +- src/soc/intel/skylake/acpi/pch.asl | 2 -- 5 files changed, 4 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 6e3bde4bb99..4f5029e5acd 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -88,7 +88,7 @@ void soc_fill_gnvs(struct global_nvs *gnvs) gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio); } - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) sgx_fill_gnvs(gnvs); /* Fill in Above 4GB MMIO resource */ diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f4d1497223f..f857bb97a07 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -30,6 +30,4 @@ #include /* SGX */ -#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include -#endif diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl index c0b80407293..9aea7a8b09c 100644 --- a/src/soc/intel/common/acpi/sgx.asl +++ b/src/soc/intel/common/acpi/sgx.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) Scope(\_SB) { // Secure Enclave memory @@ -54,3 +55,4 @@ Scope(\_SB) } // end EPC Device } // End of Scope(\_SB) +#endif diff --git a/src/soc/intel/common/block/sgx/Makefile.inc b/src/soc/intel/common/block/sgx/Makefile.inc index 3fa18d88734..ce3c436141f 100644 --- a/src/soc/intel/common/block/sgx/Makefile.inc +++ b/src/soc/intel/common/block/sgx/Makefile.inc @@ -1 +1 @@ -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) += sgx.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) += sgx.c diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index e088ca1782f..0aa8f957611 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -62,6 +62,4 @@ Method (_OSC, 4) } /* SGX */ -#if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include -#endif From aa02363e688a10788f4e33ad8544478166b1f242 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Mon, 18 Oct 2021 13:43:08 +0900 Subject: [PATCH 218/320] mb/google/dedede/var/sasuke: Generate SPD ID for Samsung K4U6E3S4AB-MGCL Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim Change-Id: I91183f33b92569dd49967ef866d58043d79c287b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58408 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc | 2 +- .../google/dedede/variants/sasuke/memory/dram_id.generated.txt | 1 + .../google/dedede/variants/sasuke/memory/mem_parts_used.txt | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc b/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc index 730b0678dde..f87222db18b 100644 --- a/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc @@ -4,4 +4,4 @@ # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/sasuke/memory src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt index 893112a8a74..7834c02a4b0 100644 --- a/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt @@ -5,3 +5,4 @@ DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt index be1daedfeb7..476f0f5736a 100644 --- a/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt @@ -10,3 +10,4 @@ # Part Name K4U6E3S4AA-MGCR +K4U6E3S4AB-MGCL From cb588104263ded7b65389fff25e984636ff2d584 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Mon, 18 Oct 2021 13:44:56 +0900 Subject: [PATCH 219/320] mb/google/dedede/var/bugzzy: Generate SPD ID for Samsung K4U6E3S4AB-MGCL Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL BUG=None TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim Change-Id: I0720a51336f374f709c392c4bae4ad3e4c580a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58409 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc | 2 +- .../google/dedede/variants/bugzzy/memory/dram_id.generated.txt | 1 + .../google/dedede/variants/bugzzy/memory/mem_parts_used.txt | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc b/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc index f4aaf516662..f221aaef881 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc @@ -4,4 +4,4 @@ # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/bugzzy/memory src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL diff --git a/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt index f51f815abe1..d84f96cb13d 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt @@ -5,3 +5,4 @@ DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) diff --git a/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt index be1daedfeb7..476f0f5736a 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt @@ -10,3 +10,4 @@ # Part Name K4U6E3S4AA-MGCR +K4U6E3S4AB-MGCL From dd275f7a6c61d84da4ba743f4e0d82b7a4ebed68 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 15 Oct 2021 18:05:45 +0600 Subject: [PATCH 220/320] mb/google/brya/var/anahera: change from CLKREQ#2 to CLKREQ#6 for eMMC Based on the latest schematics, change eMMC CLKREQ from CLKREQ#2 to CLKREQ#6 BUG=b:197850509 TEST=build and boot into eMMC Signed-off-by: Wisley Chen Change-Id: I0fc87c864b62a37fc3fa7a4a9a7722bf286c007b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58366 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/anahera/gpio.c | 5 +++++ src/mainboard/google/brya/variants/anahera/overridetree.cb | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index 9344d4c0ad9..e67de78a040 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -39,6 +39,8 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_D3, NONE), /* D5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_D5, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), /* D13 : ISH_UART0_RXD ==> NC */ PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ @@ -56,6 +58,9 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E23 : DDPA_CTRLDATA ==> NC */ diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 79f7a974cb9..ad6746ebe82 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -125,7 +125,7 @@ chip soc/intel/alderlake # Enable PCIE eMMC bridge 7 using clk 6 register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 6, - .clk_req = 2, + .clk_req = 6, .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, }" end #PCIE7 EMMC From e3bb49e9058abb67f314e97623f07899b702302f Mon Sep 17 00:00:00 2001 From: Kevin Chang Date: Fri, 15 Oct 2021 13:51:49 +0800 Subject: [PATCH 221/320] mb/google/taeko: enable DPTF functionality for taeko Enable DPTF functionality for taeko BRANCH=None BUG=b:203035930 TEST=Built and tested on taeko board Change-Id: Ic9f3cbf5cd52ebc48b274b43fcdb57a51dcf94ec Signed-off-by: Kevin Chang Reviewed-on: https://review.coreboot.org/c/coreboot/+/58358 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Sumeet R Pawnikar --- .../brya/variants/taeko/overridetree.cb | 117 ++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 8a76d35bd04..6806d8b3a06 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -87,6 +87,123 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 74), + TEMP_PCT(75, 74), + TEMP_PCT(70, 74), + TEMP_PCT(65, 74), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(51, 74), + TEMP_PCT(47, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 45), + TEMP_PCT(37, 35), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(51, 74), + TEMP_PCT(47, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 45), + TEMP_PCT(37, 35), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(51, 74), + TEMP_PCT(47, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 45), + TEMP_PCT(37, 35), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 12000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 74, 4620, 115, 1150, }, + [4] = { 60, 4290, 90, 900, }, + [5] = { 45, 3980, 55, 550, }, + [6] = { 35, 3170, 30, 300, }, + [7] = { 30, 2640, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end device ref tbt_pcie_rp2 off end From a714848140b2c8233b88278f4802b3027ee34978 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 15 Oct 2021 13:35:35 +0600 Subject: [PATCH 222/320] mb/google/brya/anahera: Update HID to MX98360A Because of a change in the chromium OS kernel machine driver for the MAX98357A, a _HID that matches MAX98360A has to be used. (https://chromium- review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268/) BUG=b:200778066 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: Ic68373920d9135e614ff792149079de451ec6e60 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/58365 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/anahera/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index ad6746ebe82..ab6e3b81802 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -228,7 +228,7 @@ chip soc/intel/alderlake end device ref hda on chip drivers/generic/max98357a - register "hid" = ""MX98357A"" + register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" register "sdmode_delay" = "5" device generic 0 on end From aaa3b57a449f874bac5aa010788f024bd8697584 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Fri, 15 Oct 2021 19:55:35 +0600 Subject: [PATCH 223/320] mb/google/brya/anahera: Add two thermal sensor setting Anahera has 4 thermal sensors, so add the missing sensors settings. BUG=b:203187535 TEST=build and verified by thermal team. Change-Id: I0e5c0d9c09c88cc95fdfd77b96800a0f4929d7d2 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/58369 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/brya/variants/anahera/overridetree.cb | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index ab6e3b81802..0225f6c1336 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -74,19 +74,25 @@ chip soc/intel/alderlake chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""Regulator"" # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), }" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { From 26bb4aa1ad31b9028c1be97c6e39c3cf08aa3e82 Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Mon, 18 Oct 2021 15:31:45 +1100 Subject: [PATCH 224/320] psp_verstage: remove psp_ef_table struct psp_efs.h now has embedded_firmware struct which is copied from amdfwtool. Remove psp_ef_table from psp_verstage and use it instead to remove duplicates. TEST=boot on zork and guybrush Signed-off-by: Kangheui Won Change-Id: Ia362445cb7fc565b2d963f264461d833dc0338d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58411 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/cezanne/psp_verstage/chipset.c | 2 +- .../amd/common/psp_verstage/include/psp_verstage.h | 14 ++------------ src/soc/amd/common/psp_verstage/psp_verstage.c | 8 ++++---- src/soc/amd/picasso/psp_verstage/chipset.c | 2 +- 4 files changed, 8 insertions(+), 18 deletions(-) diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index f680456b1a5..183f1169cd4 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -13,7 +13,7 @@ uint32_t save_uapp_data(void *address, uint32_t size) return svc_save_uapp_data(address, size); } -uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table) +uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table) { return ef_table->bios3_entry; } diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index be6b23dfdd7..7687ac6da0a 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -4,6 +4,7 @@ #define PSP_VERSTAGE_H #include <2crypto.h> +#include #include #include #include @@ -43,17 +44,6 @@ #define MIN_TRANSFER_BUFFER_SIZE (8 * KiB) #define MIN_WORKBUF_TRANSFER_SIZE (MIN_TRANSFER_BUFFER_SIZE - TRANSFER_INFO_SIZE) -struct psp_ef_table { - uint32_t signature; /* 0x55aa55aa */ - uint32_t reserved0[4]; - uint32_t psp_table; - uint32_t bios0_entry; - uint32_t bios1_entry; - uint32_t bios2_entry; - uint32_t reserved1; - uint32_t bios3_entry; -} __attribute__((packed, aligned(16))); - void test_svc_calls(void); uint32_t unmap_fch_devices(void); uint32_t verstage_soc_early_init(void); @@ -63,7 +53,7 @@ uintptr_t *map_spi_rom(void); uint32_t get_max_workbuf_size(uint32_t *size); uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset); uint32_t save_uapp_data(void *address, uint32_t size); -uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table); +uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table); int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, struct sha_generic_data *sha_op); diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 7c37355594f..c03cf9b22e8 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -76,7 +76,7 @@ static uint32_t check_cmos_recovery(void) */ static uint32_t update_boot_region(struct vb2_context *ctx) { - struct psp_ef_table *ef_table; + struct embedded_firmware *ef_table; uint32_t psp_dir_addr, bios_dir_addr; uint32_t *psp_dir_in_spi, *bios_dir_in_spi; const char *fname; @@ -100,13 +100,13 @@ static uint32_t update_boot_region(struct vb2_context *ctx) printk(BIOS_ERR, "Error: AMD Firmware table not found.\n"); return POSTCODE_AMD_FW_MISSING; } - ef_table = (struct psp_ef_table *)amdfw_location; + ef_table = (struct embedded_firmware *)amdfw_location; if (ef_table->signature != EMBEDDED_FW_SIGNATURE) { printk(BIOS_ERR, "Error: ROMSIG address is not correct.\n"); return POSTCODE_ROMSIG_MISMATCH_ERROR; } - psp_dir_addr = ef_table->psp_table; + psp_dir_addr = ef_table->combo_psp_directory; bios_dir_addr = get_bios_dir_addr(ef_table); psp_dir_in_spi = (uint32_t *)((psp_dir_addr & SPI_ADDR_MASK) + (uint32_t)boot_dev_base); @@ -121,7 +121,7 @@ static uint32_t update_boot_region(struct vb2_context *ctx) return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR; } - if (update_psp_bios_dir((void *)&psp_dir_addr, (void *)&bios_dir_addr)) { + if (update_psp_bios_dir(&psp_dir_addr, &bios_dir_addr)) { printk(BIOS_ERR, "Error: Updated BIOS Directory could not be set.\n"); return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR; } diff --git a/src/soc/amd/picasso/psp_verstage/chipset.c b/src/soc/amd/picasso/psp_verstage/chipset.c index 83f956b236e..9577a5b632a 100644 --- a/src/soc/amd/picasso/psp_verstage/chipset.c +++ b/src/soc/amd/picasso/psp_verstage/chipset.c @@ -19,7 +19,7 @@ uint32_t get_max_workbuf_size(uint32_t *size) return svc_get_max_workbuf_size(size); } -uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table) +uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table) { return ef_table->bios1_entry; } From 0a1602217fd0d60c59a497cb83a23b44cf4973d9 Mon Sep 17 00:00:00 2001 From: Bernardo Perez Priego Date: Mon, 11 Oct 2021 19:47:06 -0700 Subject: [PATCH 225/320] mb/intel/adlrvp: Remove EC region Signed-off-by: Bernardo Perez Priego Change-Id: Ic76c29069beb510dd7620f340e0aab212668c3f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58235 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik --- src/mainboard/intel/adlrvp/chromeos.fmd | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 5c9ef474403..28cda245e46 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -1,7 +1,6 @@ FLASH 32M { SI_ALL 6M { SI_DESC 4K - SI_EC 512K SI_ME } SI_BIOS 26M { From 24e3d67004cd59f1c6e5bbff9661ddfdab88727a Mon Sep 17 00:00:00 2001 From: Bernardo Perez Priego Date: Wed, 22 Sep 2021 16:55:09 -0700 Subject: [PATCH 226/320] mb/intel/adlrvp_m: Enable touchpad These changes include ELAN touchpad to ACPI tables and configure GPIO's. BUG=None Test=Boot board, touchpad should be functional Signed-off-by: Bernardo Perez Priego Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik --- src/mainboard/intel/adlrvp/devicetree_m.cb | 10 ++++++++++ src/mainboard/intel/adlrvp/gpio_m.c | 8 +++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 1a8c641ae33..b73ded1e10f 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -275,6 +275,16 @@ chip soc/intel/alderlake register "hid_desc_reg_offset" = "0x01" device i2c 0a on end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0000"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D11_IRQ)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H1)" + register "generic.wake" = "GPE0_DW1_11" + register "generic.probed" = "1" + register "generic.has_power_resource" = "1" + device i2c 15 on end + end end device ref i2c1 on chip drivers/intel/mipi_camera diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 915b549e034..6eb670b7afe 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -172,7 +172,13 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_E4, 0, DEEP) + PAD_CFG_GPO(GPP_E4, 0, DEEP), + + /* H1 : GPPC_H1_TCH_PAD_TCH_PNL2_LS_EN */ + PAD_CFG_GPO(GPP_H1, 0, PLTRST), + + /* D11 : TCH_PAD_INT_N */ + PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST, LEVEL, INVERT) }; void variant_configure_gpio_pads(void) From fbf874fb381af8a0ef2c058538919d133e630d4d Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Mon, 18 Oct 2021 14:17:41 -0700 Subject: [PATCH 227/320] soc/intel/alderlake: Fix wrong FIVR configs assignment For PchFivrExtVnnRailSxEnabledStates, vnn_enable_bitmap config is used by mistake, instead of the expected vnn_sx_enable_bitmap Signed-off-by: Bora Guvendik Change-Id: Idf100be3ac4d6d97335c627e790c1870558d1210 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58430 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 6e90cf17f8d..9ed8acd7438 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -712,7 +712,7 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, config->ext_fivr_settings.vnn_supported_voltage_bitmap; s_cfg->PchFivrExtVnnRailSxEnabledStates = - config->ext_fivr_settings.vnn_enable_bitmap; + config->ext_fivr_settings.vnn_sx_enable_bitmap; /* Convert the voltages to increments of 2.5mv */ s_cfg->PchFivrExtV1p05RailVoltage = From a76e64709491664765e33b55826e5af87c1f20ce Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 23 Jul 2021 14:53:05 -0600 Subject: [PATCH 228/320] soc/amd/common/block/cpu: Remove magic number in memlayout The SPI DMA controller can only perform transactions on a cache line boundary. This change removes the magic number and uses the #define to make it clear. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 59631f3ada1..005bde093b2 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -103,8 +103,8 @@ SECTIONS * the payload on non-S3 boots, so we don't need to reserve it from the * OS. The 64 byte alignment is required by the SPI DMA controller. */ - . = ALIGN(64); - REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, 64) + . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); + REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, ARCH_CACHELINE_ALIGN_SIZE) #endif RAMSTAGE(CONFIG_RAMBASE, 8M) From 70fb5cb514399db41a95849827c039b6c66ddbd7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 17 Oct 2021 17:43:53 +0200 Subject: [PATCH 229/320] kconfig_lint: put $inside_choice together right in the first place MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of substituting the delimiter later, put $inside_choice together right in the first place. Signed-off-by: Michael Niewöhner Change-Id: Ia713510a683101c48c86a1c3722ebb1607a29288 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58400 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- util/lint/kconfig_lint | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 76dd78764c4..9e2c2078668 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -614,7 +614,7 @@ sub build_and_parse_kconfig_tree { $choice_symbol = $symbol; } $inside_config = ""; - $inside_choice = "$filename $line_no"; + $inside_choice = "$filename:$line_no"; $configs_inside_choice = 0; # Kconfig verifies that choice blocks have a prompt @@ -806,7 +806,7 @@ sub add_symbol { $symbols{$symbol}{choice} = 1; # remember the location of the choice - $symbols{$symbol}{choice_loc} = join(':', (split / /, $inside_choice)); + $symbols{$symbol}{choice_loc} = $inside_choice; } else { $symbols{$symbol}{choice} = 0; From 4396358fd314d5cf4dfb01b6d7176159707df226 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 17 Oct 2021 17:48:50 +0200 Subject: [PATCH 230/320] kconfig_lint: use just one variable for keeping track of choices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of using two variables, one for the boolean value and one for the path, use just one with the path. Since an empty string evalutes to false, this simplification does not change behaviour. Signed-off-by: Michael Niewöhner Change-Id: I2f1171789af6815094446f107f3c634332a3427e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58401 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- util/lint/kconfig_lint | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 9e2c2078668..a3495ce2bf9 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -374,7 +374,7 @@ sub check_defaults { # Symbols created/used inside a choice must not have a default set. The default is set by the choice itself. if ($symbols{$sym}{choice}) { show_error("Defining a default for symbol '$sym' at $filename:$line_no, used inside choice at " - . "$symbols{$sym}{choice_loc}, is not allowed."); + . "$symbols{$sym}{choice}, is not allowed."); } # skip good defaults @@ -802,15 +802,8 @@ sub add_symbol { #initialize the symbol or increment the use count. if ( ( !exists $symbols{$symbol} ) || ( !exists $symbols{$symbol}{count} ) ) { $symbols{$symbol}{count} = 0; - if ($inside_choice) { - $symbols{$symbol}{choice} = 1; - - # remember the location of the choice - $symbols{$symbol}{choice_loc} = $inside_choice; - } - else { - $symbols{$symbol}{choice} = 0; - } + # remember the location of the choice (or "") + $symbols{$symbol}{choice} = $inside_choice; } else { $symbols{$symbol}{count}++; From 3f41d3269e462c2c0a7d7c4cbdc20f0b07b166ee Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 23 Jul 2021 15:23:12 -0600 Subject: [PATCH 231/320] lib/cbfs: Call rdev_unmap on hash mismatch We don't want to leak any mappings. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel Change-Id: Ibcd28ce12cbd5e221e8f4fa910fd8472bedb802f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56576 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Karthik Ramasubramanian --- src/lib/cbfs.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 32b50da30ce..52f73736da6 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -309,8 +309,15 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, loc = allocator(arg, size, &mdata); } else if (compression == CBFS_COMPRESS_NONE) { void *mapping = rdev_mmap_full(&rdev); - if (!mapping || cbfs_file_hash_mismatch(mapping, size, file_hash)) + + if (!mapping) + return NULL; + + if (cbfs_file_hash_mismatch(mapping, size, file_hash)) { + rdev_munmap(&rdev, mapping); return NULL; + } + return mapping; } else if (!CBFS_CACHE_AVAILABLE) { ERROR("Cannot map compressed file %s on x86\n", mdata.h.filename); From 41ba01bb95e146fda62e2b778e50965024acf457 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 23 Jul 2021 14:53:05 -0600 Subject: [PATCH 232/320] util/cbfstool/rmodule: Omit undefined extern symbols from reloc table When using `DECLARE_OPTIONAL_REGION`, it is assumed that REGION_SIZE(name) == 0 if the region was not defined in the memlayout. When using non-rmodule stages (i.e., bootblock, romstage, etc), this assumption holds true, but breaks down in rmodule (i.e., ramstage) stages. The rmodule tool is not currently omitting undefined externals from the relocation table. e.g., extern u8 _##name##_size[]; This means that when the rmodule loader runs, it will rewrite the symbol from 0 (which is the default the linker assumed) to 0 + offset. This is wrong since the symbol doesn't actually exist. Instead we need to omit the relocation so it continues to keep the default value of 0. BUG=b:179699789 TEST=Print out REGION_SIZE(cbfs_cache) in ramstage and verify it is set to 0. I also see the following printed by the rmodtool now: DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone_size DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone DEBUG: Omitting relocation for absolute symbol: _stack_size DEBUG: Omitting relocation for absolute symbol: _program_size DEBUG: Omitting relocation for absolute symbol: _cbmem_init_hooks_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache DEBUG: Omitting relocation for undefined extern: _cbfs_cache DEBUG: Omitting relocation for undefined extern: _cbfs_cache_size As you can see the _watchdog_tombstone will also be fixed by this CL. Signed-off-by: Raul E Rangel Change-Id: Ib57e263fa9014da4f6854637000c1c8ad8eb351a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58376 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Karthik Ramasubramanian --- util/cbfstool/rmodule.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index ce005108edb..02f1d90785d 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -155,6 +155,19 @@ static int relocation_for_absolute_symbol(struct rmod_context *ctx, Elf64_Rela * return 0; } +static int relocation_for_weak_extern_symbols(struct rmod_context *ctx, Elf64_Rela *r) +{ + Elf64_Sym *s = &ctx->pelf.syms[ELF64_R_SYM(r->r_info)]; + + if (ELF64_ST_BIND(s->st_info) == STB_WEAK && ELF64_ST_TYPE(s->st_info) == STT_NOTYPE) { + DEBUG("Omitting relocation for undefined extern: %s\n", + &ctx->strtab[s->st_name]); + return 1; + } + + return 0; +} + /* * Relocation processing loops. */ @@ -197,6 +210,9 @@ static int for_each_reloc(struct rmod_context *ctx, struct reloc_filter *f, if (relocation_for_absolute_symbol(ctx, r)) continue; + if (relocation_for_weak_extern_symbols(ctx, r)) + continue; + /* Allow the provided filter to have precedence. */ if (f != NULL) { filter_emit = f->filter(f, r); From edc5af552a3c706f29ee6cd80d93052f61742737 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 19 Oct 2021 18:04:27 +0200 Subject: [PATCH 233/320] cpu/x86/mp_init: use types.h include Using types.h as include instead of stddef.h and stdint.h will also provide commonlib/bsd/cb_err.h which will be used in follow-up patches. Signed-off-by: Felix Held Change-Id: I08a68dc827d60c6c9a27b3ec8b74b9c8a2c96d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58452 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/cpu/x86/mp_init.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 497ed3cfc56..1061f81c8a6 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include #include #include @@ -25,6 +23,7 @@ #include #include #include +#include #include From b04e2bae7730c98d9722b6b908e1ec1e8f28853f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 19 Oct 2021 01:03:24 +0200 Subject: [PATCH 234/320] cpu/x86/mp_init: factor out send_sipi_to_aps function Apart from the SIPI number in the debug message the two instances of the SIPI sending code in start_aps are identical, so factor it out into a new send_sipi_to_aps function. Signed-off-by: Felix Held Change-Id: I6a921b81fce77fbf58c7ae3b50efd8c3e6e5aef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58453 Reviewed-by: Raul Rangel Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/cpu/x86/mp_init.c | 57 +++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 32 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 1061f81c8a6..13cfd4ce3a2 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -425,6 +425,29 @@ static int apic_wait_timeout(int total_delay, int delay_step) return timeout; } +/* Send Startup IPI to APs */ +static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_vector) +{ + if (lapic_busy()) { + printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); + if (apic_wait_timeout(1000 /* 1 ms */, 50)) { + printk(BIOS_ERR, "timed out. Aborting.\n"); + return CB_ERR; + } + printk(BIOS_DEBUG, "done.\n"); + } + + lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector, + 0); + printk(BIOS_DEBUG, "Waiting for SIPI to complete..."); + if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { + printk(BIOS_ERR, "timed out.\n"); + return CB_ERR; + } + printk(BIOS_DEBUG, "done.\n"); + return CB_SUCCESS; +} + static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) { int sipi_vector; @@ -466,23 +489,8 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) } /* Send 1st Startup IPI (SIPI) */ - if (lapic_busy()) { - printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); - if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_ERR, "timed out. Aborting.\n"); - return -1; - } - printk(BIOS_DEBUG, "done.\n"); - } - - lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector, - 0); - printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete..."); - if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_ERR, "timed out.\n"); + if (send_sipi_to_aps(ap_count, num_aps, sipi_vector) != CB_SUCCESS) return -1; - } - printk(BIOS_DEBUG, "done.\n"); /* Wait for CPUs to check in up to 200 us. */ wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); @@ -491,23 +499,8 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) return 0; /* Send 2nd SIPI */ - if (lapic_busy()) { - printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); - if (apic_wait_timeout(1000 /* 1 ms */, 50)) { - printk(BIOS_ERR, "timed out. Aborting.\n"); - return -1; - } - printk(BIOS_DEBUG, "done.\n"); - } - - lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector, - 0); - printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete..."); - if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { - printk(BIOS_ERR, "timed out.\n"); + if (send_sipi_to_aps(ap_count, num_aps, sipi_vector) != CB_SUCCESS) return -1; - } - printk(BIOS_DEBUG, "done.\n"); /* Wait for CPUs to check in. */ if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) { From b5376ff9725581e8000851e39867e0d48623a158 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 19 Oct 2021 17:44:37 +0200 Subject: [PATCH 235/320] cpu/x86/mp_init: add final new line to debug messages Since during AP startup it's not guaranteed that no AP console output will be printed between consecutive printk calls in send_sipi_to_aps, add a new line character to all printks to make sure to have the outputs from the APs on separate lines. For consistency also add a final new line character to the printk call in start_aps. Signed-off-by: Felix Held Change-Id: I3983b8a0e6b272ba5fb2a90a108d17a0c480c8b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58454 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/cpu/x86/mp_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 13cfd4ce3a2..637adaa39e7 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -429,7 +429,7 @@ static int apic_wait_timeout(int total_delay, int delay_step) static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_vector) { if (lapic_busy()) { - printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); + printk(BIOS_DEBUG, "Waiting for ICR not to be busy...\n"); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { printk(BIOS_ERR, "timed out. Aborting.\n"); return CB_ERR; @@ -439,7 +439,7 @@ static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_ve lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector, 0); - printk(BIOS_DEBUG, "Waiting for SIPI to complete..."); + printk(BIOS_DEBUG, "Waiting for SIPI to complete...\n"); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { printk(BIOS_ERR, "timed out.\n"); return CB_ERR; @@ -472,7 +472,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) printk(BIOS_DEBUG, "Starting CPUs in %s mode\n", x2apic_mode ? "x2apic" : "xapic"); if (lapic_busy()) { - printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); + printk(BIOS_DEBUG, "Waiting for ICR not to be busy...\n"); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { printk(BIOS_ERR, "timed out. Aborting.\n"); return -1; From 5911096e06a7558cef6ce1e108c97a689fb091dc Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 19 Oct 2021 18:32:41 +0200 Subject: [PATCH 236/320] cpu/x86/mp_init: use cb_err as start_aps return type Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held Change-Id: Icb96f28b4d59b3d00638a43c927df80f5d1643f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58455 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/cpu/x86/mp_init.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 637adaa39e7..806fc981236 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -448,14 +448,14 @@ static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_ve return CB_SUCCESS; } -static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) +static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) { int sipi_vector; /* Max location is 4KiB below 1MiB */ const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12; if (ap_count == 0) - return 0; + return CB_SUCCESS; /* The vector is sent as a 4k aligned address in one byte. */ sipi_vector = sipi_vector_location >> 12; @@ -463,7 +463,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) if (sipi_vector > max_vector_loc) { printk(BIOS_CRIT, "SIPI vector too large! 0x%08x\n", sipi_vector); - return -1; + return CB_ERR; } printk(BIOS_DEBUG, "Attempting to start %d APs\n", ap_count); @@ -475,7 +475,7 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) printk(BIOS_DEBUG, "Waiting for ICR not to be busy...\n"); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { printk(BIOS_ERR, "timed out. Aborting.\n"); - return -1; + return CB_ERR; } printk(BIOS_DEBUG, "done.\n"); } @@ -490,26 +490,26 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps) /* Send 1st Startup IPI (SIPI) */ if (send_sipi_to_aps(ap_count, num_aps, sipi_vector) != CB_SUCCESS) - return -1; + return CB_ERR; /* Wait for CPUs to check in up to 200 us. */ wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); if (CONFIG(X86_AMD_INIT_SIPI)) - return 0; + return CB_SUCCESS; /* Send 2nd SIPI */ if (send_sipi_to_aps(ap_count, num_aps, sipi_vector) != CB_SUCCESS) - return -1; + return CB_ERR; /* Wait for CPUs to check in. */ if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) { printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", atomic_read(num_aps), ap_count); - return -1; + return CB_ERR; } - return 0; + return CB_SUCCESS; } static int bsp_do_flight_plan(struct mp_params *mp_params) @@ -637,7 +637,7 @@ static int mp_init(struct bus *cpu_bus, struct mp_params *p) /* Start the APs providing number of APs and the cpus_entered field. */ global_num_aps = p->num_cpus - 1; - if (start_aps(cpu_bus, global_num_aps, ap_count) < 0) { + if (start_aps(cpu_bus, global_num_aps, ap_count) != CB_SUCCESS) { mdelay(1000); printk(BIOS_DEBUG, "%d/%d eventually checked in?\n", atomic_read(ap_count), global_num_aps); From d9ad49c25035f1ded97571ef3d23d092fe8a711d Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Thu, 16 Sep 2021 19:32:57 +0200 Subject: [PATCH 237/320] mb/intel/adlrvp: Rework Kconfig Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: If68c118f22579cc0a3db570119798f0f535f9804 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221 Reviewed-by: Nico Huber Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/Kconfig | 68 +++++++++++++++++-------- src/mainboard/intel/adlrvp/Kconfig.name | 10 ---- 2 files changed, 48 insertions(+), 30 deletions(-) diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index c62adbe7248..2b78515776e 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -1,33 +1,61 @@ -if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_INTEL_ADLRVP_COMMON + def_bool n select BOARD_ROMSIZE_KB_32768 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select MAINBOARD_HAS_CHROMEOS - select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_MIPI_CAMERA - select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP select DRIVERS_INTEL_SOUNDWIRE - select DRIVERS_USB_ACPI + select DRIVERS_SOUNDWIRE_ALC711 select DRIVERS_SPI_ACPI - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP if BOARD_INTEL_ADLRVP_P_MCHP - select SOC_INTEL_ALDERLAKE - select SOC_INTEL_ALDERLAKE_PCH_M if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC + select DRIVERS_USB_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS - select DRIVERS_SOUNDWIRE_ALC711 + select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CSE_LITE_SKU - select DRIVERS_I2C_MAX98373 - select FW_CONFIG if BOARD_INTEL_ADLRVP_M_EXT_EC - select FW_CONFIG_SOURCE_CHROMEEC_CBI if BOARD_INTEL_ADLRVP_M_EXT_EC - select MAINBOARD_HAS_TPM2 if BOARD_INTEL_ADLRVP_M_EXT_EC - select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_INTEL_ADLRVP_M_EXT_EC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - select SPI_TPM if BOARD_INTEL_ADLRVP_M_EXT_EC + +config BOARD_INTEL_ADLRVP_P + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + +config BOARD_INTEL_ADLRVP_P_EXT_EC + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_INTEL_PMC + select INTEL_LPSS_UART_FOR_CONSOLE + +config BOARD_INTEL_ADLRVP_P_MCHP + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_INTEL_MIPI_CAMERA + select DRIVERS_INTEL_PMC + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP + select EC_GOOGLE_CHROMEEC_MEC + select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_COMMON_BLOCK_IPU + +config BOARD_INTEL_ADLRVP_M + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_ALDERLAKE_PCH_M + +config BOARD_INTEL_ADLRVP_M_EXT_EC + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_INTEL_PMC + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_ALDERLAKE_PCH_M + select SPI_TPM + +if BOARD_INTEL_ADLRVP_COMMON config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name index af6ac480a5a..7ee2c13ef91 100644 --- a/src/mainboard/intel/adlrvp/Kconfig.name +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -1,24 +1,14 @@ config BOARD_INTEL_ADLRVP_P bool "Alderlake-P RVP" - select DRIVERS_UART_8250IO - select MAINBOARD_USES_IFD_EC_REGION config BOARD_INTEL_ADLRVP_P_EXT_EC bool "Alderlake-P RVP with Chrome EC" - select INTEL_LPSS_UART_FOR_CONSOLE config BOARD_INTEL_ADLRVP_P_MCHP bool "Alderlake-P RVP with Microchip EC" - select INTEL_LPSS_UART_FOR_CONSOLE - select DRIVERS_INTEL_MIPI_CAMERA - select SOC_INTEL_COMMON_BLOCK_IPU - select EC_GOOGLE_CHROMEEC_MEC config BOARD_INTEL_ADLRVP_M bool "Alderlake-M RVP" - select DRIVERS_UART_8250IO - select MAINBOARD_USES_IFD_EC_REGION config BOARD_INTEL_ADLRVP_M_EXT_EC bool "Alderlake-M RVP with Chrome EC" - select INTEL_LPSS_UART_FOR_CONSOLE From 62fcffb2474e86addd5a74830699f5db3beb87a3 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 19 Oct 2021 13:25:18 +0200 Subject: [PATCH 238/320] util/crossgcc/buildgcc: Remove CROSSGCC_COMMIT For reproducibility, the buildgcc script is copied to the destination folder of the toolchain. `CROSSGCC_COMMIT` is used as a file name extension for the script and was introduced when `CROSSGCC_VERSION` didn't contain the commit yet. Since this is not the case anymore, remove it. Change-Id: Id0a0b657eb828b2728ff787228eaa38be83d9517 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58450 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- util/crossgcc/buildgcc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 01c3ad910b1..f9fff89b387 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -17,7 +17,6 @@ cd "$(dirname "$0")" || exit 1 CROSSGCC_VERSION="$(git log -n 1 --pretty=%cd --date=short .)_$(git log -n 1 --pretty=%h .)" -CROSSGCC_COMMIT=$( git describe ) # default settings PACKAGE=GCC @@ -1252,7 +1251,7 @@ printf "Packages built ... ${green}ok${NC}\n" # for reproducibility PROGNAME=$(basename "$0") rm -f "$DESTDIR$TARGETDIR/share/$PROGNAME-*" -cp "$PROGNAME" "$DESTDIR$TARGETDIR/share/$PROGNAME-$CROSSGCC_VERSION-$CROSSGCC_COMMIT" +cp "$PROGNAME" "$DESTDIR$TARGETDIR/share/$PROGNAME-$CROSSGCC_VERSION" # Adding edk2 tools template mkdir -p "$DESTDIR$TARGETDIR/share/edk2config" From 60c56be85fed2fffa4bce2828ac9203aeb3f8c93 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 17 Oct 2021 14:54:12 +0200 Subject: [PATCH 239/320] util/crossgcc/buildgcc: Allow printing only the version In preperation to CB:58396, add the parameter `-W|--print-version`, which allows printing the content of `CROSSGCC_VERSION`. In combination with CB:58396, this can be used to pre-set the variable in case of the git history is not accessible. Change-Id: I9a205ca0ecb0ece47eb5d8fa73706478354512ff Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58395 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- util/crossgcc/buildgcc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f9fff89b387..a3d9cad4bb8 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -557,6 +557,7 @@ myhelp() printf " $0 [-h|--help]\n\n" printf "Options:\n" + printf " [-W|--print-version Print machine readable version\n" printf " [-V|--version] print version number and exit\n" printf " [-h|--help] print this help and exit\n" printf " [-c|--clean] remove temporary files before build\n" @@ -926,12 +927,12 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V 2>/dev/null | sed -e '1!d' -e 's,^\(......\).*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,bootstrap,bootstrap-only,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:,urls,nocolor -o Vhcd:bBp:l:P:j:D:tSys:un -- "$@") + args=$(getopt -l print-version,version,help,clean,directory:,bootstrap,bootstrap-only,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:,urls,nocolor -o WVhcd:bBp:l:P:j:D:tSys:un -- "$@") getopt_ret=$? eval set -- "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:bBp:l:P:j:D:tSys:un $*) + args=$(getopt WVhcd:bBp:l:P:j:D:tSys:un $*) getopt_ret=$? # shellcheck disable=SC2086 set -- $args @@ -944,6 +945,7 @@ fi while true ; do case "$1" in + -W|--print-version) shift; echo $CROSSGCC_VERSION; exit 0;; -V|--version) shift; myversion; exit 0;; -h|--help) shift; myhelp; exit 0;; -c|--clean) shift; clean=1;; From 3f137169cbefdc87d251c740db032bc53d4a34b3 Mon Sep 17 00:00:00 2001 From: Mac Chiang Date: Wed, 13 Oct 2021 15:21:22 +0800 Subject: [PATCH 240/320] mb/google/brya/var/redrix: Enable bt_offload support Enable CnviBtAudioOffload UPD and program the corresponding VGPIO pins BUG=b:191931762 TEST=emerge-coreboot Signed-off-by: Mac Chiang Change-Id: I81bae537d52592e878db56343970de6fc488950f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58288 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/brya/variants/redrix/fw_config.c | 13 +++++++++++++ .../google/brya/variants/redrix/overridetree.cb | 2 ++ 2 files changed, 15 insertions(+) diff --git a/src/mainboard/google/brya/variants/redrix/fw_config.c b/src/mainboard/google/brya/variants/redrix/fw_config.c index fea546a57f2..ac31d99c44c 100644 --- a/src/mainboard/google/brya/variants/redrix/fw_config.c +++ b/src/mainboard/google/brya/variants/redrix/fw_config.c @@ -38,6 +38,17 @@ static const struct pad_config i2s_disable_pads[] = { PAD_NC(GPP_S3, NONE), }; +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + static void fw_config_handle(void *unused) { if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { @@ -51,6 +62,8 @@ static void fw_config_handle(void *unused) printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n"); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + printk(BIOS_INFO, "BT offload enabled\n"); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 2e32b24b375..0ed6c529e37 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -33,6 +33,8 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" + register "CnviBtAudioOffload" = "true" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | From 64ed1f1f86826fa8f2e165b8ae27b9658546972a Mon Sep 17 00:00:00 2001 From: Philip Chen Date: Mon, 18 Oct 2021 18:28:14 -0700 Subject: [PATCH 241/320] google/trogdor: Support Parade ps8640 Support Parade ps8640 as the second source edp bridge for some trogdor board variants/revisions. BUG=b:194741013 BRANCH=trogdor TEST=verified firmware screen works on lazor rev9 Change-Id: Iae5ccd8d9d33d60e4c37011ecffdd7a05af59ab2 Signed-off-by: Philip Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/58437 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/mainboard/google/trogdor/Kconfig | 1 + src/mainboard/google/trogdor/board.h | 8 ++- src/mainboard/google/trogdor/mainboard.c | 64 ++++++++++++++++++++---- 3 files changed, 63 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index be45bb0aeb7..e70bc69e96e 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -37,6 +37,7 @@ config BOARD_SPECIFIC_OPTIONS select RTC if !BOARD_GOOGLE_BUBS select MISSING_BOARD_RESET if BOARD_GOOGLE_BUBS select DRIVERS_TI_SN65DSI86BRIDGE + select DRIVER_PARADE_PS8640 select SOC_QUALCOMM_SC7180 select SPI_FLASH select SPI_FLASH_MACRONIX diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index 19024eb3056..208cafc4da7 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -25,6 +25,9 @@ #define GPIO_VDD_RESET_1V8 GPIO(87) #define GPIO_EDP_BRIDGE_ENABLE dead_code_t(gpio_t) #define GPIO_EN_PP3300_DX_EDP dead_code_t(gpio_t) +#define GPIO_PS8640_EDP_BRIDGE_PD_L dead_code_t(gpio_t) +#define GPIO_PS8640_EDP_BRIDGE_RST_L dead_code_t(gpio_t) +#define GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE dead_code_t(gpio_t) #else #define GPIO_MIPI_1V8_ENABLE dead_code_t(gpio_t) #define GPIO_AVDD_LCD_ENABLE dead_code_t(gpio_t) @@ -36,6 +39,10 @@ (CONFIG(BOARD_GOOGLE_COACHZ) && board_id() == 0 ? GPIO(52) : \ (CONFIG(BOARD_GOOGLE_LAZOR) || CONFIG(BOARD_GOOGLE_POMPOM) ? GPIO(30) : \ GPIO(67))))) +/*PS8640 specific GPIOs */ +#define GPIO_PS8640_EDP_BRIDGE_PD_L GPIO_EDP_BRIDGE_ENABLE +#define GPIO_PS8640_EDP_BRIDGE_RST_L GPIO(11) +#define GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE GPIO(32) #endif /* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices (e.g. CoachZ). */ @@ -49,7 +56,6 @@ #define GPIO_EN_FP_RAILS dead_code_t(gpio_t) #endif - void setup_chromeos_gpios(void); #endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 2d9dac3ce69..55a341fecba 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -24,7 +25,8 @@ #include #define BRIDGE_BUS QUPV3_0_SE2 -#define BRIDGE_CHIP 0x2d +#define BRIDGE_SN65DSI86_CHIP 0x2d +#define BRIDGE_PS8640_CHIP 0x08 static struct usb_board_data usb0_board_data = { .pll_bias_control_2 = 0x22, @@ -71,7 +73,20 @@ static void load_qup_fw(void) qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* Codec I2C */ } -static void power_on_bridge(void) +static bool is_ps8640_bridge(void) +{ + /* + * Because the board_id pins for the early Homestar builds were + * misstuffed, after we enable tri-state board_id pins, a -rev1 + * board reports itself as -rev19, and a -rev2 board reports itself + * as -rev23. We need to account for those quirks here. + */ + return (CONFIG(BOARD_GOOGLE_HOMESTAR) && board_id() >= 4 && + board_id() != 19 && board_id() != 23) || + (CONFIG(BOARD_GOOGLE_LAZOR) && board_id() >= 9); +} + +static void power_on_sn65dsi86_bridge(void) { printk(BIOS_INFO, "%s: Bridge gpio init\n", __func__); @@ -82,6 +97,26 @@ static void power_on_bridge(void) gpio_output(GPIO_EN_PP3300_DX_EDP, 1); } +static void power_on_ps8640_bridge(void) +{ + printk(BIOS_INFO, "%s: Bridge gpio init\n", __func__); + + /* PP3300 EDP panel power supply */ + gpio_output(GPIO_EN_PP3300_DX_EDP, 1); + + gpio_output(GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE, 1); + gpio_output(GPIO_PS8640_EDP_BRIDGE_PD_L, 1); + gpio_output(GPIO_PS8640_EDP_BRIDGE_RST_L, 0); + + /* + * According to ps8640 app note v0.6, wait for 2ms ("t1") after + * VDD33 goes high and then deassert RST. + */ + mdelay(2); + + gpio_output(GPIO_PS8640_EDP_BRIDGE_RST_L, 1); +} + static void configure_mipi_panel(void) { int panel_id = sku_id() >> 8; @@ -154,14 +189,19 @@ static enum cb_err display_init(struct panel_serializable_data *panel) if (mdss_dsi_config(&panel->edid, lanes, dsi_bpp)) return CB_ERR; + if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) { if (mdss_dsi_panel_initialize(panel->init)) return CB_ERR; - } else { - sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, &panel->edid, - lanes, dsi_bpp); + } else if (!is_ps8640_bridge()) { + /* + * Parade ps8640 is auto-configured based on a pre-programmed + * SPI-ROM. Only TI sn65dsi86 needs to be configured here. + */ + sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_SN65DSI86_CHIP, + &panel->edid, lanes, dsi_bpp); if (CONFIG(TROGDOR_HAS_BRIDGE_BACKLIGHT)) - sn65dsi86_backlight_enable(BRIDGE_BUS, BRIDGE_CHIP); + sn65dsi86_backlight_enable(BRIDGE_BUS, BRIDGE_SN65DSI86_CHIP); } mdp_dsi_video_config(&panel->edid); @@ -190,12 +230,18 @@ static void display_startup(void) panel = get_mipi_panel(&orientation); if (!panel) return; + } else if (is_ps8640_bridge()) { + power_on_ps8640_bridge(); + ps8640_init(BRIDGE_BUS, BRIDGE_PS8640_CHIP); + if (ps8640_get_edid(BRIDGE_BUS, BRIDGE_PS8640_CHIP, &panel->edid) < 0) + return; } else { enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ; - power_on_bridge(); + power_on_sn65dsi86_bridge(); mdelay(250); /* Delay for the panel to be up */ - sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk); - if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &panel->edid) < 0) + sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_SN65DSI86_CHIP, ref_clk); + if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_SN65DSI86_CHIP, + &panel->edid) < 0) return; } From a8772dbb1ba4a8204c80a8ebf066e4107a7f7f7e Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 19 Oct 2021 02:57:22 +0200 Subject: [PATCH 242/320] cpu/x86/mp_init: rework start_aps to fix X86_AMD_INIT_SIPI case When CONFIG_X86_AMD_INIT_SIPI was set, the second/final SIPI that afterwards checks if all APs have checked in was skipped and if it got so far, start_aps returned CB_SUCCESS despite not having checked if all APs had checked in after the SIPI. This patch makes start_aps skip the first SIPI in the CONFIG_X86_AMD_INIT_SIPI case so we use the proper timeouts and error handling for the final and this case only SIPI and signal the caller an error when not all APs have checked in after the SIPI. A timeless build for lenovo/x230 which is a mainboard that doesn't select X86_AMD_INIT_SIPI results in identical binary, so this doesn't change the behavior of the !X86_AMD_INIT_SIPI case. Signed-off-by: Felix Held Change-Id: I39438229497c5d9c44dc7e247c7b2c81252b4bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58456 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Raul Rangel --- src/cpu/x86/mp_init.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 806fc981236..fd2add0b9b9 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -486,19 +486,16 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap if (!CONFIG(X86_AMD_INIT_SIPI)) { printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); mdelay(10); - } - - /* Send 1st Startup IPI (SIPI) */ - if (send_sipi_to_aps(ap_count, num_aps, sipi_vector) != CB_SUCCESS) - return CB_ERR; - /* Wait for CPUs to check in up to 200 us. */ - wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); + /* Send 1st Startup IPI (SIPI) */ + if (send_sipi_to_aps(ap_count, num_aps, sipi_vector) != CB_SUCCESS) + return CB_ERR; - if (CONFIG(X86_AMD_INIT_SIPI)) - return CB_SUCCESS; + /* Wait for CPUs to check in up to 200 us. */ + wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); + } - /* Send 2nd SIPI */ + /* Send final SIPI */ if (send_sipi_to_aps(ap_count, num_aps, sipi_vector) != CB_SUCCESS) return CB_ERR; From 0c39cd7dab5e7444c61d078968722124e1bfba48 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Tue, 19 Oct 2021 15:26:54 +0900 Subject: [PATCH 243/320] mb/google/dedede/var/bugzzy: Enable/disable LTE function based on FW_CONFIG Enable/disable LTE function based on DB_PORTS field of FW_CONFIG. - GPIO control - USB port setting BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim Change-Id: I8363f8e7052ff9cfa423063a7e8f5a0f9ce1df2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58442 Tested-by: build bot (Jenkins) Reviewed-by: Henry Sun Reviewed-by: Karthik Ramasubramanian --- .../google/dedede/variants/bugzzy/gpio.c | 16 ++++++++++++++++ .../dedede/variants/bugzzy/overridetree.cb | 4 +++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/bugzzy/gpio.c b/src/mainboard/google/dedede/variants/bugzzy/gpio.c index d089162db3f..a218c5ee5a6 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/gpio.c +++ b/src/mainboard/google/dedede/variants/bugzzy/gpio.c @@ -2,6 +2,8 @@ #include #include +#include +#include /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { @@ -53,8 +55,22 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_H17, 0, PLTRST), }; +static const struct pad_config lte_disable_pads[] = { + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_H17, NONE), +}; + const struct pad_config *variant_override_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } + +static void fw_config_handle(void *unused) +{ + if (!fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_1A_LTE))) + gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index 92a0497189e..453d8c3f526 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -155,7 +155,9 @@ chip soc/intel/jasperlake register "reset_off_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" register "enable_delay_ms" = "20" - device usb 3.3 on end + device usb 3.3 on + probe DB_PORTS DB_PORTS_1C_1A_LTE + end end end end From 9ce51c3585492a0f5dcfab27c9dc58deb632ac5a Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Tue, 19 Oct 2021 15:31:27 +0900 Subject: [PATCH 244/320] mb/google/dedede/var/bugzzy: Add LTE power off sequence This change adds LTE power off sequence for bugzzy. BUG=None BRANCH=dedede TEST=FW_NAME=bugzzy emerge-dedede coreboot Signed-off-by: Seunghwan Kim Change-Id: I6be0e23b9c2c2bed9745011920394006fdaabae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58443 Tested-by: build bot (Jenkins) Reviewed-by: Henry Sun Reviewed-by: Karthik Ramasubramanian --- .../dedede/variants/bugzzy/Makefile.inc | 2 ++ .../google/dedede/variants/bugzzy/variant.c | 23 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/bugzzy/variant.c diff --git a/src/mainboard/google/dedede/variants/bugzzy/Makefile.inc b/src/mainboard/google/dedede/variants/bugzzy/Makefile.inc index eb2c9bc021c..fd60a18b694 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/Makefile.inc +++ b/src/mainboard/google/dedede/variants/bugzzy/Makefile.inc @@ -1,3 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/bugzzy/variant.c b/src/mainboard/google/dedede/variants/bugzzy/variant.c new file mode 100644 index 00000000000..22caa069d37 --- /dev/null +++ b/src/mainboard/google/dedede/variants/bugzzy/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(20); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} From b22a435d228f3e2288736a84147a5713bf2424e5 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Fri, 15 Oct 2021 19:15:13 +0800 Subject: [PATCH 245/320] mb/google/trogdor: determine which panel to use by panel_id for quackingstick panel_id 6 for AUO B101UAN08.3. BUG=b:201263032 BRANCH=none TEST=make Signed-off-by: Sheng-Liang Pan Change-Id: I076ded9300c2ec1704a566722870bd0d1a20e9d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58363 Reviewed-by: Bob Moragues Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/mainboard/google/trogdor/mainboard.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 55a341fecba..f007f45dd12 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -157,6 +157,15 @@ static struct panel_serializable_data *get_mipi_panel(enum lb_fb_orientation *or } } + if (CONFIG(BOARD_GOOGLE_QUACKINGSTICK)) { + switch (panel_id) { + case 6: + cbfs_filename = "panel-AUO_B101UAN08_3"; + *orientation = LB_FB_ORIENTATION_LEFT_UP; + break; + } + } + if (CONFIG(BOARD_GOOGLE_WORMDINGLER)) { switch (panel_id) { case 0: From 02750d0400c3c75be6e6f68d0d35f1edfdbafd46 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 17 Oct 2021 15:43:21 +0200 Subject: [PATCH 246/320] util/crossgcc/buildgcc: Use pre-set CROSSGCC_VERSION if possible For reproducibility, a version string is appended to the version of the tools used in the cross-toolchain. Currently, git is used to determine that version string at runtime of this script. There are cases, where it's not possible to determine that version string, e.g. when a release tarball is used, and if so, the version string is just `v_`. Thus, allow pre-setting the variable `CROSSGCC_VERSION`. Change-Id: I888ccd877c93436b5e033528c43bd8667b8d2f10 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58396 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- util/crossgcc/buildgcc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a3d9cad4bb8..ab8cba444e3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -16,7 +16,9 @@ cd "$(dirname "$0")" || exit 1 -CROSSGCC_VERSION="$(git log -n 1 --pretty=%cd --date=short .)_$(git log -n 1 --pretty=%h .)" +if [ -z "$CROSSGCC_VERSION" ]; then + CROSSGCC_VERSION="$(git log -n 1 --pretty=%cd --date=short .)_$(git log -n 1 --pretty=%h .)" +fi # default settings PACKAGE=GCC From ff6416f737ff34be0f855c40d4e3c83ac354e4f2 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 17 Oct 2021 16:07:07 +0200 Subject: [PATCH 247/320] util/release/build-release: Create cross-toolchain version file Add cross-toolchain version file to the release tarball, which can be used for pre-setting the variables used in buildgcc. Change-Id: Iad1e0adaa95b71f161caf978276bfb0a63eac8f4 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/58399 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- util/release/build-release | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/release/build-release b/util/release/build-release index ce8e600bc12..95eead6c1dc 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -57,6 +57,8 @@ if [ -n "$COMMIT_ID" ]; then git reset --hard "$COMMIT_ID" fi +util/crossgcc/buildgcc -W > .crossgcc-version + git submodule update --init --checkout if [ -n "$GPG_KEY_ID" ]; then git tag -a -s -u "$GPG_KEY_ID" --force "$VERSION_NAME" -m "coreboot version $VERSION_NAME" From 5a76c79791e4787702b22d1cc7edf534dbf664af Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 18 Oct 2021 17:32:53 +0800 Subject: [PATCH 248/320] mb/google/brya/var/kano: Enable BT offload support Enable the CnviBtAudioOffload UPD and program the corresponding BT VPGIOs. BUG=b:202913826 TEST=emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu Change-Id: Id81cba82742f552c098ec3719a0b453b752dc5c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58415 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/brya/variants/kano/Makefile.inc | 2 +- .../google/brya/variants/kano/fw_config.c | 28 +++++++++++++++++++ .../google/brya/variants/kano/variant.c | 10 +++++++ 3 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/google/brya/variants/kano/variant.c diff --git a/src/mainboard/google/brya/variants/kano/Makefile.inc b/src/mainboard/google/brya/variants/kano/Makefile.inc index 5c0f13f868d..9ea19ded56d 100644 --- a/src/mainboard/google/brya/variants/kano/Makefile.inc +++ b/src/mainboard/google/brya/variants/kano/Makefile.inc @@ -4,5 +4,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c - +ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/kano/fw_config.c b/src/mainboard/google/brya/variants/kano/fw_config.c index 51638036f74..fdfee3ffff8 100644 --- a/src/mainboard/google/brya/variants/kano/fw_config.c +++ b/src/mainboard/google/brya/variants/kano/fw_config.c @@ -41,12 +41,35 @@ static const struct pad_config i2s_disable_pads[] = { PAD_NC(GPP_S3, NONE), }; +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + +static const struct pad_config bt_i2s_disable_pads[] = { + PAD_NC(GPP_VGPIO_30, NONE), + PAD_NC(GPP_VGPIO_31, NONE), + PAD_NC(GPP_VGPIO_32, NONE), + PAD_NC(GPP_VGPIO_33, NONE), + PAD_NC(GPP_VGPIO_34, NONE), + PAD_NC(GPP_VGPIO_35, NONE), + PAD_NC(GPP_VGPIO_36, NONE), + PAD_NC(GPP_VGPIO_37, NONE), +}; + static void fw_config_handle(void *unused) { if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); return; } @@ -54,6 +77,11 @@ static void fw_config_handle(void *unused) printk(BIOS_INFO, "Configure audio over I2S with MAX98373 NAU88L25B.\n"); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + printk(BIOS_INFO, "BT offload enabled\n"); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } else { + printk(BIOS_INFO, "BT offload disabled\n"); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/kano/variant.c b/src/mainboard/google/brya/variants/kano/variant.c new file mode 100644 index 00000000000..fef03f2b3ee --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/variant.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); +} From 1eae39f4cd9a8cbb574ad5f7fafc251930f18a3a Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 8 Oct 2021 13:10:38 -0600 Subject: [PATCH 249/320] arch/x86,cpu/x86: Fix 64-bit CPU_INFO_V2 build errors There are two possible code sections where the cpu_info macros can be included: .code32 and .code64 Doing a `push %eax` while in a .code64 section will result in a compiler error. This macro manually pushes the 32-bit register onto the stack so we can share the code between 32 and 64 bit builds. We also can't implicitly dereference per_cpu_segment_selector because it's a 32-bit address. Trying to do this results in the following: E: Invalid reloc type: 11 E: Illegal use of 32bit sign extended addressing at offset 0x1b2 If we load the address first, then dereference it, we can work around the limitation. With these fixes, 64-bit builds can now use CPU_INFO_V2. BUG=b:179699789 TEST=Boot qemu 64 bit build with CPU_INFO_V2 and 4 CPUs. See AP init work as expected. Signed-off-by: Raul E Rangel Change-Id: I4e72a808c9583bb2d0f697cbbd9cb9c0aa0ea2dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58232 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/arch/x86/c_start.S | 3 ++- src/cpu/x86/cpu_info.S.inc | 26 +++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 9e718fcab05..c3fdfd9f176 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -90,7 +90,8 @@ _start: */ set_segment_descriptor_base $per_cpu_segment_descriptors, %esp - mov per_cpu_segment_selector, %eax + mov $per_cpu_segment_selector, %eax + movl (%eax), %eax mov %eax, %gs #endif diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc index 9ffdd844444..6dca920ba0f 100644 --- a/src/cpu/x86/cpu_info.S.inc +++ b/src/cpu/x86/cpu_info.S.inc @@ -1,14 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Pushes a 32-bit register onto the stack. + * + * There are two possible code sections where this code can be included: + * .code32 and .code64 + * + * Doing a `push %eax` while in a .code64 section will result in a compiler + * error. This macro manually pushes the 32-bit register onto the stack so we + * can share the code between 32 and 64 bit builds. + */ +.macro pushr reg:req +#if ENV_X86_64 + movl $0, -4(%esp) + movl \reg, -8(%esp) + sub $8, %esp +#else + push \reg +#endif +.endm + /* Push struct cpu_info */ .macro push_cpu_info index=$0 - push \index /* index */ - push $0 /* *cpu */ + pushr \index /* index (size_t) */ + pushr $0 /* *cpu */ .endm /* Push struct per_cpu_segment_data */ .macro push_per_cpu_segment_data cpu_info_pointer=%esp - push \cpu_info_pointer /* *cpu_info */ + pushr \cpu_info_pointer /* *cpu_info */ .endm /* From 99c84787b87e0e30e57b152b41ca5998072feb90 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 8 Oct 2021 13:10:38 -0600 Subject: [PATCH 250/320] cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MP This will reduce the number of AP init paths we need to support. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and see all CPUs initialized correctly Signed-off-by: Raul E Rangel Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58146 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/x86/Kconfig | 1 + src/cpu/x86/mp_init.c | 24 ++++++------------------ src/cpu/x86/sipi_vector.S | 2 -- 3 files changed, 7 insertions(+), 20 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 99e33bb570f..fb5b5413b9b 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -2,6 +2,7 @@ config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT depends on SMP + select CPU_INFO_V2 help This option uses common MP infrastructure for bringing up APs in parallel. It additionally provides a more flexible mechanism diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index fd2add0b9b9..5d0cb194e94 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -182,14 +182,12 @@ static void park_this_cpu(void *unused) * been loaded. */ static void asmlinkage ap_init(unsigned int cpu) { - struct cpu_info *info; + struct cpu_info *info = cpu_info(); /* Ensure the local APIC is enabled */ enable_lapic(); - info = cpu_info(); - info->index = cpu; - info->cpu = cpus_dev[cpu]; + info->cpu = cpus_dev[info->index]; cpu_add_map_entry(info->index); @@ -197,10 +195,10 @@ static void asmlinkage ap_init(unsigned int cpu) info->cpu->path.apic.apic_id = lapicid(); if (cpu_is_intel()) - printk(BIOS_INFO, "AP: slot %d apic_id %x, MCU rev: 0x%08x\n", cpu, + printk(BIOS_INFO, "AP: slot %zu apic_id %x, MCU rev: 0x%08x\n", info->index, info->cpu->path.apic.apic_id, get_current_microcode_rev()); else - printk(BIOS_INFO, "AP: slot %d apic_id %x\n", cpu, + printk(BIOS_INFO, "AP: slot %zu apic_id %x\n", info->index, info->cpu->path.apic.apic_id); /* Walk the flight plan */ @@ -215,20 +213,10 @@ static void setup_default_sipi_vector_params(struct sipi_params *sp) sp->gdt = (uintptr_t)&gdt; sp->gdtlimit = (uintptr_t)&gdt_end - (uintptr_t)&gdt - 1; sp->idt_ptr = (uintptr_t)&idtarg; - if (CONFIG(CPU_INFO_V2)) { - sp->per_cpu_segment_descriptors = (uintptr_t)&per_cpu_segment_descriptors; - sp->per_cpu_segment_selector = per_cpu_segment_selector; - } + sp->per_cpu_segment_descriptors = (uintptr_t)&per_cpu_segment_descriptors; + sp->per_cpu_segment_selector = per_cpu_segment_selector; sp->stack_size = CONFIG_STACK_SIZE; sp->stack_top = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE); - /* - * In the CPU_INFO_V2 case, we don't need to pre-allocate the space on the stack. - * Instead we push them onto the top of the stack in the sipi vector. - */ - if (!CONFIG(CPU_INFO_V2)) { - /* Adjust the stack top to take into account cpu_info. */ - sp->stack_top -= sizeof(struct cpu_info); - } } #define NUM_FIXED_MTRRS 11 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 491f1de4354..55256de9203 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -104,7 +104,6 @@ _start: subl %eax, %edx mov %edx, %esp -#if CONFIG(CPU_INFO_V2) push_cpu_info index=%ecx push_per_cpu_segment_data @@ -118,7 +117,6 @@ _start: shl $3, %eax /* The index is << 3 in the segment selector */ add per_cpu_segment_selector, %eax mov %eax, %gs -#endif andl $0xfffffff0, %esp /* ensure stack alignment */ From 3671597b9428e6be2a72197c19b449c463a2f962 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 8 Oct 2021 13:10:38 -0600 Subject: [PATCH 251/320] cpu/x86: Remove cpu parameter to ap_init We now pre-populate cpu_info before jumping to the C handler. We no longer need this parameter. I moved the stack alignment closer to the actual invocation of the C handler so it's easier to reason about. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS and verify all CPUs still function Signed-off-by: Raul E Rangel Change-Id: I8997683b6613b7031784cabf7039a400f0efdea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58147 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/x86/mp_init.c | 2 +- src/cpu/x86/sipi_vector.S | 13 ++----------- 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5d0cb194e94..89030f45756 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -180,7 +180,7 @@ static void park_this_cpu(void *unused) /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ -static void asmlinkage ap_init(unsigned int cpu) +static void asmlinkage ap_init(void) { struct cpu_info *info = cpu_info(); diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 55256de9203..b8cac963412 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -118,11 +118,6 @@ _start: add per_cpu_segment_selector, %eax mov %eax, %gs - andl $0xfffffff0, %esp /* ensure stack alignment */ - - /* Save CPU number. */ - mov %ecx, %esi - /* * The following code only needs to run on Intel platforms and thus the caller * doesn't provide a microcode_ptr if not on Intel. @@ -235,19 +230,15 @@ load_msr: mov %eax, %cr4 #endif + andl $0xfffffff0, %esp /* ensure stack alignment */ + #if ENV_X86_64 /* entry64.inc preserves ebx. */ #include - mov %rsi, %rdi /* cpu_num */ - movabs c_handler, %eax call *%rax #else - /* c_handler(cpu_num), preserve proper stack alignment */ - sub $12, %esp - push %esi /* cpu_num */ - mov c_handler, %eax call *%eax #endif From d04835e1f7561ac2e8483a0e9f51a8d99bc6cd30 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 19:37:15 +0200 Subject: [PATCH 252/320] cpu/x86/mp_init: use cb_err as install_relocation_handler return type Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held Change-Id: I95f36ba628c7f3ce960a8f3bda730d1c720253cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58485 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/x86/mp_init.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 89030f45756..4e90d9e37ab 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -761,7 +761,7 @@ static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) stub_params->apic_id_to_cpu[i] = cpu_get_apic_id(i); } -static int install_relocation_handler(int num_cpus, size_t real_save_state_size, +static enum cb_err install_relocation_handler(int num_cpus, size_t real_save_state_size, size_t save_state_size, uintptr_t perm_smbase) { struct smm_loader_params smm_params = { @@ -779,13 +779,13 @@ static int install_relocation_handler(int num_cpus, size_t real_save_state_size, if (smm_setup_relocation_handler((void *)perm_smbase, &smm_params)) { printk(BIOS_ERR, "%s: smm setup failed\n", __func__); - return -1; + return CB_ERR; } adjust_smm_apic_id_map(&smm_params); mp_state.reloc_start32_offset = smm_params.stub_params->start32_offset; - return 0; + return CB_SUCCESS; } static int install_permanent_handler(int num_cpus, uintptr_t smbase, @@ -833,7 +833,8 @@ static void load_smm_handlers(void) /* Install handlers. */ if (install_relocation_handler(mp_state.cpu_count, real_save_state_size, - smm_save_state_size, mp_state.perm_smbase) < 0) { + smm_save_state_size, mp_state.perm_smbase) != + CB_SUCCESS) { printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); smm_disable(); } From 2461a09b4478d734cc749d059011c429515d59c7 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 18:21:21 +0200 Subject: [PATCH 253/320] cpu/x86/mp_init: use cb_err as install_permanent_handler return type Using cb_err as return type clarifies the meaning of the different return values. Signed-off-by: Felix Held Change-Id: Ifb64b5908b938bb162153433e5f744ab0b95c525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58486 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/x86/mp_init.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 4e90d9e37ab..eb6f1a27d10 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -788,7 +788,7 @@ static enum cb_err install_relocation_handler(int num_cpus, size_t real_save_sta return CB_SUCCESS; } -static int install_permanent_handler(int num_cpus, uintptr_t smbase, +static enum cb_err install_permanent_handler(int num_cpus, uintptr_t smbase, size_t smsize, size_t real_save_state_size, size_t save_state_size) { @@ -814,11 +814,11 @@ static int install_permanent_handler(int num_cpus, uintptr_t smbase, printk(BIOS_DEBUG, "Installing permanent SMM handler to 0x%08lx\n", smbase); if (smm_load_module((void *)smbase, smsize, &smm_params)) - return -1; + return CB_ERR; adjust_smm_apic_id_map(&smm_params); - return 0; + return CB_SUCCESS; } /* Load SMM handlers as part of MP flight record. */ @@ -841,7 +841,7 @@ static void load_smm_handlers(void) if (install_permanent_handler(mp_state.cpu_count, mp_state.perm_smbase, mp_state.perm_smsize, real_save_state_size, - smm_save_state_size) < 0) { + smm_save_state_size) != CB_SUCCESS) { printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); smm_disable(); } From 2939ebd05167d8681f973910b3bbcd68b3b2d1e6 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 18:33:06 +0200 Subject: [PATCH 254/320] cpu/x86/mp_init: use cb_err as apic_wait_timeout return type Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of apic_wait_timeout to not need a local timeout variable. Signed-off-by: Felix Held Change-Id: I2fe32c761492d252b154d2f50f2a330cf4f412d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58487 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/x86/mp_init.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index eb6f1a27d10..4b173a4888d 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -395,22 +395,21 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) return max_cpus; } -/* Returns 1 for timeout. 0 on success. */ -static int apic_wait_timeout(int total_delay, int delay_step) +static enum cb_err apic_wait_timeout(int total_delay, int delay_step) { int total = 0; - int timeout = 0; while (lapic_busy()) { udelay(delay_step); total += delay_step; if (total >= total_delay) { - timeout = 1; - break; + /* LAPIC not ready before the timeout */ + return CB_ERR; } } - return timeout; + /* LAPIC ready before the timeout */ + return CB_SUCCESS; } /* Send Startup IPI to APs */ @@ -418,7 +417,7 @@ static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_ve { if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy...\n"); - if (apic_wait_timeout(1000 /* 1 ms */, 50)) { + if (apic_wait_timeout(1000 /* 1 ms */, 50) != CB_SUCCESS) { printk(BIOS_ERR, "timed out. Aborting.\n"); return CB_ERR; } @@ -428,7 +427,7 @@ static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_ve lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector, 0); printk(BIOS_DEBUG, "Waiting for SIPI to complete...\n"); - if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { + if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */) != CB_SUCCESS) { printk(BIOS_ERR, "timed out.\n"); return CB_ERR; } @@ -461,7 +460,7 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy...\n"); - if (apic_wait_timeout(1000 /* 1 ms */, 50)) { + if (apic_wait_timeout(1000 /* 1 ms */, 50) != CB_SUCCESS) { printk(BIOS_ERR, "timed out. Aborting.\n"); return CB_ERR; } @@ -645,7 +644,7 @@ void smm_initiate_relocation_parallel(void) { if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); - if (apic_wait_timeout(1000 /* 1 ms */, 50)) { + if (apic_wait_timeout(1000 /* 1 ms */, 50) != CB_SUCCESS) { printk(BIOS_DEBUG, "timed out. Aborting.\n"); return; } @@ -655,7 +654,7 @@ void smm_initiate_relocation_parallel(void) lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid()); if (lapic_busy()) { - if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) { + if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */) != CB_SUCCESS) { printk(BIOS_DEBUG, "SMI Relocation timed out.\n"); return; } From 3dd9cfbdf57e8a2cdd48d51b81bf77662de25154 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 18:39:00 +0200 Subject: [PATCH 255/320] cpu/x86/mp_init: use cb_err as wait_for_aps return type Using cb_err as return type clarifies the meaning of the different return values. Also restructure the implementation of wait_for_aps to not need a local timeout variable. Signed-off-by: Felix Held Change-Id: I86b8c8b0849ae130c78125b83d159147ce11914c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58488 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/x86/mp_init.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 4b173a4888d..2af5b1f9f01 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -140,22 +140,21 @@ static inline void release_barrier(atomic_t *b) atomic_set(b, 1); } -/* Returns 1 if timeout waiting for APs. 0 if target aps found. */ -static int wait_for_aps(atomic_t *val, int target, int total_delay, +static enum cb_err wait_for_aps(atomic_t *val, int target, int total_delay, int delay_step) { - int timeout = 0; int delayed = 0; while (atomic_read(val) != target) { udelay(delay_step); delayed += delay_step; if (delayed >= total_delay) { - timeout = 1; - break; + /* Not all APs ready before timeout */ + return CB_ERR; } } - return timeout; + /* APs ready before timeout */ + return CB_SUCCESS; } static void ap_do_flight_plan(void) @@ -487,7 +486,7 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap return CB_ERR; /* Wait for CPUs to check in. */ - if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) { + if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */) != CB_SUCCESS) { printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", atomic_read(num_aps), ap_count); return CB_ERR; @@ -520,7 +519,7 @@ static int bsp_do_flight_plan(struct mp_params *mp_params) if (atomic_read(&rec->barrier) == 0) { /* Wait for the APs to check in. */ if (wait_for_aps(&rec->cpus_entered, num_aps, - timeout_us, step_us)) { + timeout_us, step_us) != CB_SUCCESS) { printk(BIOS_ERR, "MP record %d timeout.\n", i); ret = -1; } From c6f0ed789baaf102c128d1d45ddd531a2e6fcf4e Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 19:27:14 +0200 Subject: [PATCH 256/320] cpu/x86/mp_init: use cb_err as mp_init & bsp_do_flight_plan return type Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_init_with_smm which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of mp_init gets translated to the int values in mp_init_with_smm. This could also be done by a cast of the mp_init return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held Change-Id: I4129c1db06a877c47cca87782af965b62dcbbdc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58489 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/x86/mp_init.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 2af5b1f9f01..dd0cac073e3 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -495,10 +495,10 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap return CB_SUCCESS; } -static int bsp_do_flight_plan(struct mp_params *mp_params) +static enum cb_err bsp_do_flight_plan(struct mp_params *mp_params) { int i; - int ret = 0; + enum cb_err ret = CB_SUCCESS; /* * Set time out for flight plan to a huge minimum value (>=1 second). * CPUs with many APs may take longer if there is contention for @@ -521,7 +521,7 @@ static int bsp_do_flight_plan(struct mp_params *mp_params) if (wait_for_aps(&rec->cpus_entered, num_aps, timeout_us, step_us) != CB_SUCCESS) { printk(BIOS_ERR, "MP record %d timeout.\n", i); - ret = -1; + ret = CB_ERR; } } @@ -580,10 +580,8 @@ static void init_bsp(struct bus *cpu_bus) * Therefore, one cannot rely on this property or the order of devices in * the device tree unless the chipset or mainboard know the APIC ids * a priori. - * - * mp_init() returns < 0 on error, 0 on success. */ -static int mp_init(struct bus *cpu_bus, struct mp_params *p) +static enum cb_err mp_init(struct bus *cpu_bus, struct mp_params *p) { int num_cpus; atomic_t *ap_count; @@ -592,7 +590,7 @@ static int mp_init(struct bus *cpu_bus, struct mp_params *p) if (p == NULL || p->flight_plan == NULL || p->num_records < 1) { printk(BIOS_CRIT, "Invalid MP parameters\n"); - return -1; + return CB_ERR; } /* Default to currently running CPU. */ @@ -602,7 +600,7 @@ static int mp_init(struct bus *cpu_bus, struct mp_params *p) printk(BIOS_CRIT, "ERROR: More cpus requested (%d) than supported (%d).\n", p->num_cpus, num_cpus); - return -1; + return CB_ERR; } /* Copy needed parameters so that APs have a reference to the plan. */ @@ -612,7 +610,7 @@ static int mp_init(struct bus *cpu_bus, struct mp_params *p) /* Load the SIPI vector. */ ap_count = load_sipi_vector(p); if (ap_count == NULL) - return -1; + return CB_ERR; /* Make sure SIPI data hits RAM so the APs that come up will see * the startup code even if the caches are disabled. */ @@ -624,7 +622,7 @@ static int mp_init(struct bus *cpu_bus, struct mp_params *p) mdelay(1000); printk(BIOS_DEBUG, "%d/%d eventually checked in?\n", atomic_read(ap_count), global_num_aps); - return -1; + return CB_ERR; } /* Walk the flight plan for the BSP. */ @@ -1133,7 +1131,9 @@ int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) /* Perform backup of default SMM area. */ default_smm_area = backup_default_smm_area(); - ret = mp_init(cpu_bus, &mp_params); + /* TODO: Remove this return value translation after changing the return type of + mp_init_with_smm to enum cb_err */ + ret = mp_init(cpu_bus, &mp_params) == CB_SUCCESS ? 0 : -1; restore_default_smm_area(default_smm_area); From e198880732fd272715388afb8f6cc7edca502006 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 19:46:14 +0200 Subject: [PATCH 257/320] cpu/x86/mp_init: use cb_err as run_ap_work return type Using cb_err as return type clarifies the meaning of the different return values. To not change the return types of mp_run_on_aps which is exposed outside of this compilation unit to keep the scope of this patch limited, the return value of run_ap_work gets translated to the int values in mp_run_on_aps. This could also be done by a cast of the run_ap_work return value to int, but an explicit translation of the return values should be clearer about what it does there. Signed-off-by: Felix Held Change-Id: Id346c8edf06229a929b4783498d8c6774f54a8b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58490 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/x86/mp_init.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index dd0cac073e3..3efff2f1b41 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -886,7 +886,7 @@ static void store_callback(struct mp_callback **slot, struct mp_callback *val) ); } -static int run_ap_work(struct mp_callback *val, long expire_us) +static enum cb_err run_ap_work(struct mp_callback *val, long expire_us) { int i; int cpus_accepted; @@ -895,14 +895,14 @@ static int run_ap_work(struct mp_callback *val, long expire_us) if (!CONFIG(PARALLEL_MP_AP_WORK)) { printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n"); - return -1; + return CB_ERR; } cur_cpu = cpu_index(); if (cur_cpu < 0) { printk(BIOS_ERR, "Invalid CPU index.\n"); - return -1; + return CB_ERR; } /* Signal to all the APs to run the func. */ @@ -928,12 +928,12 @@ static int run_ap_work(struct mp_callback *val, long expire_us) } if (cpus_accepted == global_num_aps) - return 0; + return CB_SUCCESS; } while (expire_us <= 0 || !stopwatch_expired(&sw)); printk(BIOS_CRIT, "CRITICAL ERROR: AP call expired. %d/%d CPUs accepted.\n", cpus_accepted, global_num_aps); - return -1; + return CB_ERR; } static void ap_wait_for_instruction(void) @@ -979,7 +979,9 @@ int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num, { struct mp_callback lcb = { .func = func, .arg = arg, .logical_cpu_number = logical_cpu_num}; - return run_ap_work(&lcb, expire_us); + /* TODO: Remove this return value translation after changing the return type of + mp_run_on_aps to enum cb_err */ + return run_ap_work(&lcb, expire_us) == CB_SUCCESS ? 0 : -1; } int mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us, bool run_parallel) From 0bf9afed7f7f1cbcc42bfd5c98d40ba094cb8478 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 15 Oct 2021 16:36:07 -0600 Subject: [PATCH 258/320] mb/google/guybrush: Make DXIO Port Descriptor configurable Instead of a const port descriptor, make it configurable. This will help to avoid adding duplicate tables for every minor configuration updates. BUG=None TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and cold reboot cycles for 10 iterations each. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- .../google/guybrush/port_descriptors.c | 103 +++--------------- 1 file changed, 14 insertions(+), 89 deletions(-) diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 09bded05ce8..177b538e647 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -1,96 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include #include -/* All PCIe Resets are handled in coreboot */ -static const fsp_dxio_descriptor guybrush_czn_pci_wwan_descriptors[] = { - { /* WLAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = PCI_SLOT(WLAN_DEVFN), - .function_number = PCI_FUNC(WLAN_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* SD */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = PCI_SLOT(SD_DEVFN), - .function_number = PCI_FUNC(SD_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, - .gpio_group_id = GPIO_69, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* WWAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 2, - .device_number = PCI_SLOT(WWAN_DEVFN), - .function_number = PCI_FUNC(WWAN_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* NVME */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 4, - .end_logical_lane = 7, - .device_number = PCI_SLOT(NVME_DEVFN), - .function_number = PCI_FUNC(NVME_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ3, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* TODO: remove this temporary workaround */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 8, - .end_logical_lane = 11, - .device_number = PCIE_GPP_BRIDGE_2_DEV, - .function_number = PCIE_GPP_2_4_FUNC, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ5, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* TODO: remove this temporary workaround */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 16, - .end_logical_lane = 23, - .device_number = PCIE_GPP_BRIDGE_1_DEV, - .function_number = PCIE_GPP_1_0_FUNC, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ6, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - } +enum dxio_port_id { + WLAN, + SD, + WWAN_NVME, + NVME }; /* All PCIe Resets are handled in coreboot */ -static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { +static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { { /* WLAN */ .engine_type = PCIE_ENGINE, .port_present = true, @@ -205,13 +130,13 @@ void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - if (variant_has_pcie_wwan()) { - *dxio_descs = guybrush_czn_pci_wwan_descriptors; - *dxio_num = ARRAY_SIZE(guybrush_czn_pci_wwan_descriptors); - } else { - *dxio_descs = guybrush_czn_dxio_descriptors; - *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); - } + /* gpp_bridge_2 is used either for WWAN or NVME bridge. Mark it as PCIE_ENGINE when it + is enabled. */ + if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) + guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE; + + *dxio_descs = guybrush_czn_dxio_descriptors; + *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); *ddi_descs = guybrush_czn_ddi_descriptors; *ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors); From 72cc0467d7ca1036787011027fc4848772b3bca0 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 19 Oct 2021 15:38:36 -0600 Subject: [PATCH 259/320] mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO Descriptor WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be de-asserted before PCIe link training during S0i3 resume. Otherwise the concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume. This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so that SMU de-asserts this reset on S0i3 resume. BUG=b:199780346 TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for 500 iterations. Ensure that the PCIe devices enumerate fine. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Marshall Dawson --- src/mainboard/google/guybrush/port_descriptors.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 177b538e647..abb854e44c6 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -135,6 +135,9 @@ void mainboard_get_dxio_ddi_descriptors( if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE; + if (variant_has_pcie_wwan()) + guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18; + *dxio_descs = guybrush_czn_dxio_descriptors; *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); From 679f4fa46578267989b55635e50ef500f7327338 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 13 Oct 2021 22:45:18 -0600 Subject: [PATCH 260/320] mb/google/guybrush/var/nipperkin: Override GPIO configuration SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected in nipperkin. Override those GPIO configurations. BUG=None TEST=Build and boot to OS in Nipperkin. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Raul Rangel Reviewed-by: Kevin Chiu --- .../guybrush/variants/nipperkin/Makefile.inc | 4 ++ .../google/guybrush/variants/nipperkin/gpio.c | 41 +++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 src/mainboard/google/guybrush/variants/nipperkin/gpio.c diff --git a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc index 88e75bde52c..f7c97bafbf4 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc @@ -1,3 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c + subdirs-y += ./memory diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c new file mode 100644 index 00000000000..acdcc4f7f36 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static const struct soc_amd_gpio override_gpio_table[] = { + /* Unused TP1056 */ + PAD_NC(GPIO_4), + /* Unused TP1063 */ + PAD_NC(GPIO_17), + PAD_NC(GPIO_18), +}; + +static const struct soc_amd_gpio override_early_gpio_table[] = { + PAD_NC(GPIO_18), +}; + +static const struct soc_amd_gpio override_pcie_gpio_table[] = { + PAD_NC(GPIO_18), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(override_early_gpio_table); + return override_early_gpio_table; +} + +const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(override_pcie_gpio_table); + return override_pcie_gpio_table; +} From 38107fa80eb81fe5077dbee0dd9a46618c71a196 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 5 Oct 2021 22:22:21 +0200 Subject: [PATCH 261/320] acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some elements in the ACPI CPPC table allow static DWORDs. Instead of using a fake register resource, use a tagged union with the two types "register" and "DWORD" and respective macros for CPPC table entries. Test: dumped SSDT before and after do not differ. Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57886 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/acpi/acpigen.c | 12 +++---- src/cpu/intel/common/common.h | 1 + src/cpu/intel/common/common_init.c | 49 +++++++++++--------------- src/include/acpi/acpigen.h | 35 ++++++++++++------ src/soc/amd/cezanne/cppc.c | 42 +++++++++++----------- src/soc/amd/cezanne/include/soc/cppc.h | 1 + 6 files changed, 73 insertions(+), 67 deletions(-) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index e0892e654f9..37bfec16543 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1798,13 +1798,11 @@ void acpigen_write_CPPC_package(const struct cppc_config *config) acpigen_write_byte(config->version); for (i = 0; i < max; ++i) { - const acpi_addr_t *reg = &(config->regs[i]); - if (reg->space_id == ACPI_ADDRESS_SPACE_MEMORY && - reg->bit_width == 32 && reg->access_size == ACPI_ACCESS_SIZE_UNDEFINED) { - acpigen_write_dword(reg->addrl); - } else { - acpigen_write_register_resource(reg); - } + const cppc_entry_t *entry = &config->entries[i]; + if (entry->type == CPPC_TYPE_DWORD) + acpigen_write_dword(entry->dword); + else + acpigen_write_register_resource(&entry->reg); } acpigen_pop_len(); } diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index fdacd1f74bc..909f75ac409 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -4,6 +4,7 @@ #define _CPU_INTEL_COMMON_H #include +#include void set_vmx_and_lock(void); void set_feature_ctrl_vmx(void); diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 6203922fd82..765a174dd12 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -105,42 +105,35 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) { config->version = version; - config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8); - config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_PLATFORM_INFO, 8, 8); - config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8); - config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8); - config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8); - config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 16, 8); - config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 0, 8); - config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 8, 8); - config->regs[CPPC_PERF_REDUCE_TOLERANCE] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_TIME_WINDOW] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_COUNTER_WRAP] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(IA32_MPERF, 0, 64); - config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(IA32_APERF, 0, 64); - config->regs[CPPC_PERF_LIMITED] = ACPI_REG_MSR(IA32_HWP_STATUS, 2, 1); - config->regs[CPPC_ENABLE] = ACPI_REG_MSR(IA32_PM_ENABLE, 0, 1); + config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8); + config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_PLATFORM_INFO, 8, 8); + config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8); + config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8); + config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8); + config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(IA32_HWP_REQUEST, 16, 8); + config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(IA32_HWP_REQUEST, 0, 8); + config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(IA32_HWP_REQUEST, 8, 8); + config->entries[CPPC_PERF_REDUCE_TOLERANCE] = CPPC_UNSUPPORTED; + config->entries[CPPC_TIME_WINDOW] = CPPC_UNSUPPORTED; + config->entries[CPPC_COUNTER_WRAP] = CPPC_UNSUPPORTED; + config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(IA32_MPERF, 0, 64); + config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(IA32_APERF, 0, 64); + config->entries[CPPC_PERF_LIMITED] = CPPC_REG_MSR(IA32_HWP_STATUS, 2, 1); + config->entries[CPPC_ENABLE] = CPPC_REG_MSR(IA32_PM_ENABLE, 0, 1); if (version < 2) return; - config->regs[CPPC_AUTO_SELECT] = (acpi_addr_t){ - .space_id = ACPI_ADDRESS_SPACE_MEMORY, - .bit_width = 32, - .bit_offset = 0, - .access_size = ACPI_ACCESS_SIZE_UNDEFINED, - .addrl = 1, - }; - - config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_MSR(IA32_HWP_REQUEST, 32, 10); - config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(IA32_HWP_REQUEST, 24, 8); - config->regs[CPPC_REF_PERF] = ACPI_REG_UNSUPPORTED; + config->entries[CPPC_AUTO_SELECT] = CPPC_DWORD(1); + config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10); + config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(IA32_HWP_REQUEST, 24, 8); + config->entries[CPPC_REF_PERF] = CPPC_UNSUPPORTED; if (version < 3) return; - config->regs[CPPC_LOWEST_FREQ] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_NOMINAL_FREQ] = ACPI_REG_UNSUPPORTED; + config->entries[CPPC_LOWEST_FREQ] = CPPC_UNSUPPORTED; + config->entries[CPPC_NOMINAL_FREQ] = CPPC_UNSUPPORTED; } void set_aesni_lock(void) diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 3af0959cfd4..463c16d2b26 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -265,24 +265,37 @@ enum cppc_fields { CPPC_MAX_FIELDS_VER_3, }; +typedef struct cppc_entry { + enum { CPPC_TYPE_REG, CPPC_TYPE_DWORD } type; + union { + acpi_addr_t reg; + uint32_t dword; + }; +} cppc_entry_t; + +#define CPPC_DWORD(_dword) \ + (cppc_entry_t){ \ + .type = CPPC_TYPE_DWORD, \ + .dword = _dword, \ + } + +#define CPPC_REG(_reg) \ + (cppc_entry_t){ \ + .type = CPPC_TYPE_REG, \ + .reg = _reg, \ + } + +#define CPPC_REG_MSR(address, offset, width) CPPC_REG(ACPI_REG_MSR(address, offset, width)) +#define CPPC_UNSUPPORTED CPPC_REG(ACPI_REG_UNSUPPORTED) + struct cppc_config { u32 version; /* must be 1, 2, or 3 */ /* * The generic acpi_addr_t structure is being used, though * anything besides PPC or FFIXED generally requires checking * if the OS has advertised support for it (via _OSC). - * - * NOTE: some fields permit DWORDs to be used. If you - * provide a System Memory register with all zeros (which - * represents unsupported) then this will be used as-is. - * Otherwise, a System Memory register with a 32-bit - * width will be converted into a DWORD field (the value - * of which will be the value of 'addrl'. Any other use - * of System Memory register is currently undefined. - * (i.e., if you have an actual need for System Memory - * then you'll need to adjust this kludge). */ - acpi_addr_t regs[CPPC_MAX_FIELDS_VER_3]; + cppc_entry_t entries[CPPC_MAX_FIELDS_VER_3]; }; void acpigen_write_return_integer(uint64_t arg); diff --git a/src/soc/amd/cezanne/cppc.c b/src/soc/amd/cezanne/cppc.c index 9d681c6ba74..1afa26f3e1e 100644 --- a/src/soc/amd/cezanne/cppc.c +++ b/src/soc/amd/cezanne/cppc.c @@ -15,35 +15,35 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) { config->version = version; - config->regs[CPPC_HIGHEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); - config->regs[CPPC_NOMINAL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8); - config->regs[CPPC_LOWEST_NONL_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8); - config->regs[CPPC_LOWEST_PERF] = ACPI_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8); - config->regs[CPPC_GUARANTEED_PERF] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_DESIRED_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8); - config->regs[CPPC_MIN_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8); - config->regs[CPPC_MAX_PERF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8); - config->regs[CPPC_PERF_REDUCE_TOLERANCE] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_TIME_WINDOW] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_COUNTER_WRAP] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_REF_PERF_COUNTER] = ACPI_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); - config->regs[CPPC_DELIVERED_PERF_COUNTER] = ACPI_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); - config->regs[CPPC_PERF_LIMITED] = ACPI_REG_MSR(MSR_CPPC_STATUS, 1, 1); - config->regs[CPPC_ENABLE] = ACPI_REG_MSR(MSR_CPPC_ENABLE, 0, 1); + config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); + config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8); + config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8); + config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8); + config->entries[CPPC_GUARANTEED_PERF] = CPPC_UNSUPPORTED; + config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8); + config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8); + config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8); + config->entries[CPPC_PERF_REDUCE_TOLERANCE] = CPPC_UNSUPPORTED; + config->entries[CPPC_TIME_WINDOW] = CPPC_UNSUPPORTED; + config->entries[CPPC_COUNTER_WRAP] = CPPC_UNSUPPORTED; + config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); + config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); + config->entries[CPPC_PERF_LIMITED] = CPPC_REG_MSR(MSR_CPPC_STATUS, 1, 1); + config->entries[CPPC_ENABLE] = CPPC_REG_MSR(MSR_CPPC_ENABLE, 0, 1); if (version < 2) return; - config->regs[CPPC_AUTO_SELECT] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_PERF_PREF] = ACPI_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8); - config->regs[CPPC_REF_PERF] = ACPI_REG_UNSUPPORTED; + config->entries[CPPC_AUTO_SELECT] = CPPC_UNSUPPORTED; + config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_UNSUPPORTED; + config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8); + config->entries[CPPC_REF_PERF] = CPPC_UNSUPPORTED; if (version < 3) return; - config->regs[CPPC_LOWEST_FREQ] = ACPI_REG_UNSUPPORTED; - config->regs[CPPC_NOMINAL_FREQ] = ACPI_REG_UNSUPPORTED; + config->entries[CPPC_LOWEST_FREQ] = CPPC_UNSUPPORTED; + config->entries[CPPC_NOMINAL_FREQ] = CPPC_UNSUPPORTED; } diff --git a/src/soc/amd/cezanne/include/soc/cppc.h b/src/soc/amd/cezanne/include/soc/cppc.h index 60a5efd3341..e2f4daaf497 100644 --- a/src/soc/amd/cezanne/include/soc/cppc.h +++ b/src/soc/amd/cezanne/include/soc/cppc.h @@ -4,6 +4,7 @@ #define _CPU_AMD_COMMON_H #include +#include struct cppc_config; void cpu_init_cppc_config(struct cppc_config *config, u32 version); From 48bd8577895bdd0ff86f22010a74e13ffa620425 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Mon, 18 Oct 2021 16:39:20 +0800 Subject: [PATCH 262/320] mb/google/guybrush/var/nipperkin: Enable GPP2 for NVMe bridge eMMC storage BUG=b:195269555 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage eMMC sku is bootable Signed-off-by: Kevin Chiu Change-Id: If9e0fdc1667cbaac05fdf4c6689d47a561016c9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58413 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Karthik Ramasubramanian --- .../google/guybrush/variants/nipperkin/overridetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 77e35bc59fe..ef577bb6f2c 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -34,6 +34,15 @@ chip soc/amd/cezanne register "name" = ""NVME"" device pci 00.0 on end end + probe STORAGE STORAGE_EMMC + end # EMMC + device ref gpp_bridge_3 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + probe STORAGE STORAGE_SSD end # NVMe device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref acp on From e2c6d9c7cb7973cd1177184ac36153e1667386a0 Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 20 Oct 2021 10:17:40 +0800 Subject: [PATCH 263/320] mb/google/brya/var/brask: Correct SSD power sequence M.2 spec describes PERST# should be sequenced after power enable. BUG=b:197385770 TEST=emerge-brask coreboot and verify it builds without error. Signed-off-by: David Wu Change-Id: Ia7e5c7b1a2194d53d98865d33cf1bc6111572876 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58463 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/brya/variants/brask/Makefile.inc | 2 ++ src/mainboard/google/brya/variants/brask/gpio.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/src/mainboard/google/brya/variants/brask/Makefile.inc b/src/mainboard/google/brya/variants/brask/Makefile.inc index 8fe978f6eff..d38141ca247 100644 --- a/src/mainboard/google/brya/variants/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/brask/Makefile.inc @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += gpio.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c index 1f1d409f25a..a23135bc901 100644 --- a/src/mainboard/google/brya/variants/brask/gpio.c +++ b/src/mainboard/google/brya/variants/brask/gpio.c @@ -10,6 +10,8 @@ static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -25,6 +27,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ @@ -59,8 +63,19 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), }; +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} From 91e8c2a1d40c5a41869b2a9595fb2cc2c5f579f5 Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 18 Oct 2021 16:39:02 +0800 Subject: [PATCH 264/320] mb/google/brya/var/kano: Correct GPIO GPP_R6 and GPP_R7 setting Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1). BUG=b:202913826 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu Change-Id: Ibf8ff0e48c4bab435d082dee27bcd53bc85b088d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58414 Tested-by: build bot (Jenkins) Reviewed-by: CT Lin Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/kano/fw_config.c | 4 ++-- src/mainboard/google/brya/variants/kano/gpio.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/brya/variants/kano/fw_config.c b/src/mainboard/google/brya/variants/kano/fw_config.c index fdfee3ffff8..55a6fad7c69 100644 --- a/src/mainboard/google/brya/variants/kano/fw_config.c +++ b/src/mainboard/google/brya/variants/kano/fw_config.c @@ -8,8 +8,8 @@ static const struct pad_config dmic_enable_pads[] = { PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* DMIC_DATA1_R */ }; static const struct pad_config dmic_disable_pads[] = { diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 627354c4abf..6f40da1fc53 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -82,9 +82,9 @@ static const struct pad_config override_gpio_table[] = { /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), From 13ab1d787907e0af9744ce1afbb855e9c5a2bb50 Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Tue, 19 Oct 2021 01:45:12 +0000 Subject: [PATCH 265/320] arch/x86/smbios: Add support for wake-up type in smbios type 1 Add system wake-up type in smbios type 1 - system information. TESTED=On S9S, can override original value and show expected result using "dmidecode -t 1". Signed-off-by: Tim Chu Change-Id: If79ba65426f1f18ebb55a0f3ef022bee83c1a93b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58436 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Jonathan Zhang --- src/arch/x86/smbios.c | 1 + src/arch/x86/smbios_defaults.c | 5 +++++ src/include/smbios.h | 13 +++++++++++++ 3 files changed, 19 insertions(+) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 04f8717e724..ea429713ae4 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -489,6 +489,7 @@ static int smbios_write_type1(unsigned long *current, int handle) t->manufacturer = smbios_add_string(t->eos, smbios_system_manufacturer()); t->product_name = smbios_add_string(t->eos, smbios_system_product_name()); t->serial_number = smbios_add_string(t->eos, smbios_system_serial_number()); + t->wakeup_type = smbios_system_wakeup_type(); t->sku = smbios_add_string(t->eos, smbios_system_sku()); t->version = smbios_add_string(t->eos, smbios_system_version()); #ifdef CONFIG_MAINBOARD_FAMILY diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c index 30bbea1a8eb..8b62ebba147 100644 --- a/src/arch/x86/smbios_defaults.c +++ b/src/arch/x86/smbios_defaults.c @@ -27,6 +27,11 @@ __weak void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, struct smbi t->asset_tag = smbios_add_string(t->eos, buf); } +__weak smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_RESERVED; +} + __weak const char *smbios_mainboard_bios_version(void) { return NULL; diff --git a/src/include/smbios.h b/src/include/smbios.h index fd9fbd40c9a..2fb6297ea34 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -308,6 +308,18 @@ struct smbios_type0 { u8 eos[2]; } __packed; +typedef enum { + SMBIOS_WAKEUP_TYPE_RESERVED = 0x00, + SMBIOS_WAKEUP_TYPE_OTHER = 0x01, + SMBIOS_WAKEUP_TYPE_UNKNOWN = 0x02, + SMBIOS_WAKEUP_TYPE_APM_TIMER = 0x03, + SMBIOS_WAKEUP_TYPE_MODEM_RING = 0x04, + SMBIOS_WAKEUP_TYPE_LAN_REMOTE = 0x05, + SMBIOS_WAKEUP_TYPE_POWER_SWITCH = 0x06, + SMBIOS_WAKEUP_TYPE_PCI_PME = 0x07, + SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED = 0x08, +} smbios_wakeup_type; + struct smbios_type1 { struct smbios_header header; u8 manufacturer; @@ -962,6 +974,7 @@ void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t); +smbios_wakeup_type smbios_system_wakeup_type(void); smbios_board_type smbios_mainboard_board_type(void); smbios_enclosure_type smbios_mainboard_enclosure_type(void); From e0e49c858bc603ac8216cd3d87c6a4a9996a8083 Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Tue, 19 Oct 2021 02:48:34 +0000 Subject: [PATCH 266/320] include/memory_info.h: Increase DIMM_INFO_TOTAL number from 8 to 16 Increase the number of total dimm to 16 to support system with more than 8 dimms. Also, remove unneeded comment. TESTED=On S9S, dmidecode -t 17 shows expected results. Signed-off-by: Tim Chu Change-Id: Iead53e96f37c55ba1b7a13fb62db1a1c10fa2e1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58440 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/include/memory_info.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/memory_info.h b/src/include/memory_info.h index fed5bbe2656..2f1399388f4 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -9,7 +9,7 @@ #define DIMM_INFO_SERIAL_SIZE 4 #define DIMM_INFO_PART_NUMBER_SIZE 33 -#define DIMM_INFO_TOTAL 8 /* Maximum num of dimm is 8 */ +#define DIMM_INFO_TOTAL 16 /** * If this table is filled and put in CBMEM, From d27ef5bf6f5e444141dca6a89c46e667bca64652 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 20:18:12 +0200 Subject: [PATCH 267/320] cpu/x86/mp_init: use cb_err as mp_init_with_smm return type Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/cpu/intel/haswell/haswell_init.c | 3 ++- src/cpu/intel/model_1067x/mp_init.c | 3 ++- src/cpu/intel/model_2065x/model_2065x_init.c | 3 ++- src/cpu/intel/model_206ax/model_206ax_init.c | 3 ++- src/cpu/x86/mp_init.c | 12 +++++------- src/include/cpu/x86/mp.h | 12 +++++------- src/mainboard/emulation/qemu-i440fx/northbridge.c | 3 ++- src/soc/amd/cezanne/cpu.c | 3 ++- src/soc/amd/picasso/cpu.c | 3 ++- src/soc/amd/stoneyridge/cpu.c | 3 ++- src/soc/intel/alderlake/cpu.c | 3 ++- src/soc/intel/apollolake/cpu.c | 3 ++- src/soc/intel/baytrail/cpu.c | 3 ++- src/soc/intel/braswell/cpu.c | 3 ++- src/soc/intel/cannonlake/cpu.c | 3 ++- src/soc/intel/denverton_ns/cpu.c | 3 ++- src/soc/intel/elkhartlake/cpu.c | 3 ++- src/soc/intel/icelake/cpu.c | 3 ++- src/soc/intel/jasperlake/cpu.c | 3 ++- src/soc/intel/skylake/cpu.c | 3 ++- src/soc/intel/tigerlake/cpu.c | 3 ++- src/soc/intel/xeon_sp/cpx/cpu.c | 3 ++- src/soc/intel/xeon_sp/skx/cpu.c | 4 ++-- 23 files changed, 52 insertions(+), 36 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 90db95b8df5..40f5ce00133 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "haswell.h" #include "chip.h" @@ -641,7 +642,7 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index fd6a82ac177..38d3735f142 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -7,6 +7,7 @@ #include #include #include +#include /* Parallel MP initialization support. */ static void pre_mp_init(void) @@ -97,6 +98,6 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index f70d7b2f5f4..a31f2cb692c 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -19,6 +19,7 @@ #include #include #include +#include static void configure_thermal_target(void) { @@ -174,7 +175,7 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 09cad24b8bd..f3181cfaa61 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -19,6 +19,7 @@ #include #include #include +#include /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -430,7 +431,7 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3efff2f1b41..258b9df9da2 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1096,9 +1096,9 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation; } -int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) +enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) { - int ret; + enum cb_err ret; void *default_smm_area; struct mp_params mp_params; @@ -1111,7 +1111,7 @@ int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) if (mp_state.cpu_count <= 0) { printk(BIOS_ERR, "Invalid cpu_count: %d\n", mp_state.cpu_count); - return -1; + return CB_ERR; } /* Sanity check SMM state. */ @@ -1133,14 +1133,12 @@ int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) /* Perform backup of default SMM area. */ default_smm_area = backup_default_smm_area(); - /* TODO: Remove this return value translation after changing the return type of - mp_init_with_smm to enum cb_err */ - ret = mp_init(cpu_bus, &mp_params) == CB_SUCCESS ? 0 : -1; + ret = mp_init(cpu_bus, &mp_params); restore_default_smm_area(default_smm_area); /* Signal callback on success if it's provided. */ - if (ret == 0 && mp_state.ops.post_mp_init != NULL) + if (ret == CB_SUCCESS && mp_state.ops.post_mp_init != NULL) mp_state.ops.post_mp_init(); return ret; diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index bc44415fdbf..aa6289c18cb 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -5,8 +5,7 @@ #include #include -#include -#include +#include #define CACHELINE_SIZE 64 @@ -86,10 +85,9 @@ struct mp_ops { }; /* - * mp_init_with_smm() returns < 0 on failure and 0 on success. The mp_ops - * argument is used to drive the multiprocess initialization. Unless otherwise - * stated each callback is called on the BSP only. The sequence of operations - * is the following: + * The mp_ops argument is used to drive the multiprocess initialization. Unless + * otherwise stated each callback is called on the BSP only. The sequence of + * operations is the following: * 1. pre_mp_init() * 2. get_cpu_count() * 3. get_smm_info() @@ -103,7 +101,7 @@ struct mp_ops { * 10. mp_initialize_cpu() for each cpu * 11. post_mp_init() */ -int mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); +enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); enum { /* Function runs on all cores (both BSP and APs) */ diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 68410b03e74..b7630a138b3 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "memory.h" #include "fw_cfg.h" @@ -250,7 +251,7 @@ void mp_init_cpus(struct bus *cpu_bus) { const struct mp_ops *ops = CONFIG(SMM_TSEG) ? &mp_ops_with_smm : &mp_ops_no_smm; - if (mp_init_with_smm(cpu_bus, ops)) + if (mp_init_with_smm(cpu_bus, ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 2ac30b6b9fd..a2fa433a9b7 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -15,6 +15,7 @@ #include #include #include +#include _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); @@ -51,7 +52,7 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index b04d004f59c..087b1539984 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -19,6 +19,7 @@ #include #include #include +#include _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); @@ -55,7 +56,7 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 9283ff76e06..08f553351c9 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -18,6 +18,7 @@ #include #include #include +#include /* * MP and SMM loading initialization. @@ -53,7 +54,7 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 801d10dd00d..a4375591078 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -23,6 +23,7 @@ #include #include #include +#include static void soc_fsp_load(void) { @@ -126,7 +127,7 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index f2b14d73f64..645582b1326 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -28,6 +28,7 @@ #include #include #include +#include static const struct reg_script core_msr_script[] = { #if !CONFIG(SOC_INTEL_GEMINILAKE) @@ -250,7 +251,7 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index e624240d925..8e402651cea 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -17,6 +17,7 @@ #include #include #include +#include /* Core level MSRs */ static const struct reg_script core_msr_script[] = { @@ -196,6 +197,6 @@ void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 0c6f463438b..ead42b92f81 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -17,6 +17,7 @@ #include #include #include +#include /* Core level MSRs */ static const struct reg_script core_msr_script[] = { @@ -205,6 +206,6 @@ void soc_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 8c8cad098e5..23b944df2d5 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "chip.h" @@ -189,7 +190,7 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 60635483d49..ab4043bf094 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -20,6 +20,7 @@ #include #include #include +#include static struct smm_relocation_attrs relo_attrs; @@ -296,6 +297,6 @@ void denverton_init_cpus(struct device *dev) add_more_links(dev, 1); /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(dev->link_list, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 0788c679f38..bfbb87f804f 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -16,6 +16,7 @@ #include #include #include +#include static void soc_fsp_load(void) { @@ -117,7 +118,7 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 3ca2172212c..dea75b6ed4f 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -16,6 +16,7 @@ #include #include #include +#include static void soc_fsp_load(void) { @@ -153,6 +154,6 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index a58fe559690..18194c99a2f 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -16,6 +16,7 @@ #include #include #include +#include static void soc_fsp_load(void) { @@ -119,7 +120,7 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3abf19b747b..80bf251cc05 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "chip.h" @@ -211,7 +212,7 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 084b5d64845..f10f0cf85d0 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -22,6 +22,7 @@ #include #include #include +#include static void soc_fsp_load(void) { @@ -125,7 +126,7 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index cfd9e5c1535..9746972a385 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "chip.h" @@ -211,7 +212,7 @@ void cpx_init_cpus(struct device *dev) intel_microcode_load_unlocked(microcode_patch); - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(dev->link_list, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index df2b9b3a006..4d017406563 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -16,7 +16,7 @@ #include "chip.h" #include #include - +#include static const config_t *chip_config = NULL; @@ -231,7 +231,7 @@ void xeon_sp_init_cpus(struct device *dev) config_reset_cpl3_csrs(); /* calls src/cpu/x86/mp_init.c */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(dev->link_list, &mp_ops) != CB_SUCCESS) printk(BIOS_ERR, "MP initialization failure.\n"); /* update numa domain for all cpu devices */ From 30f703148839663a7d41ff72a22be3a9b49110d7 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 20:42:03 +0200 Subject: [PATCH 268/320] soc/intel/skylake/cpu: rework failure handling in post_mp_init Use a boolean type to store the information if any mp_run_on_all_cpus call failed. This is a preparation to change the return type of mp_run_on_all_cpus from int to enum cb_err which will be done in a follow-up patch. Signed-off-by: Felix Held Change-Id: Ic04ad3e4a781a00ee6edcd7dbd24bc7601be1384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58492 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/skylake/cpu.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 80bf251cc05..d88dd36ad67 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -163,7 +163,7 @@ static void fc_lock_configure(void *unused) static void post_mp_init(void) { - int ret = 0; + bool failure = false; /* Set Max Ratio */ cpu_set_max_ratio(); @@ -178,14 +178,17 @@ static void post_mp_init(void) if (CONFIG(HAVE_SMI_HANDLER)) smm_lock(); - ret |= mp_run_on_all_cpus(vmx_configure, NULL); + if (mp_run_on_all_cpus(vmx_configure, NULL)) + failure = true; if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) - ret |= mp_run_on_all_cpus(sgx_configure, NULL); + if (mp_run_on_all_cpus(sgx_configure, NULL)) + failure = true; - ret |= mp_run_on_all_cpus(fc_lock_configure, NULL); + if (mp_run_on_all_cpus(fc_lock_configure, NULL)) + failure = true; - if (ret) + if (failure) printk(BIOS_CRIT, "CRITICAL ERROR: MP post init failed\n"); } From 250988d943c322ac1720ae7cd6f88592f82a08c0 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 20:45:28 +0200 Subject: [PATCH 269/320] soc/amd/common/block/cpu/smm/finalize: simplify finalize_cores The local variable int r isn't needed, so remove it. This is a preparation to change the return type of mp_run_on_all_cpus from int to enum cb_err which will be done in a follow-up patch. Signed-off-by: Felix Held Change-Id: Ie4c454cbfcc581be41ea3463ea6f852a72886128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58493 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Arthur Heymans --- src/soc/amd/common/block/cpu/smm/finalize.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c index 2df55247cf0..2795100d861 100644 --- a/src/soc/amd/common/block/cpu/smm/finalize.c +++ b/src/soc/amd/common/block/cpu/smm/finalize.c @@ -29,11 +29,9 @@ static void per_core_finalize(void *unused) static void finalize_cores(void) { - int r; printk(BIOS_SPEW, "Lock SMM configuration\n"); - r = mp_run_on_all_cpus(per_core_finalize, NULL); - if (r) + if (mp_run_on_all_cpus(per_core_finalize, NULL)) printk(BIOS_WARNING, "Failed to finalize all cores\n"); } From 82faefb339a0853dd49f10bafd2c4f5ca1723fb3 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 20:50:58 +0200 Subject: [PATCH 270/320] cpu/x86/mp_init: use cb_err as status return type in remaining functions Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/cpu/x86/mp_init.c | 19 +++++++++---------- src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c | 8 +++++--- src/drivers/ocp/dmi/smbios.c | 4 +++- src/include/cpu/x86/mp.h | 11 +++++------ src/soc/amd/common/block/cpu/smm/finalize.c | 3 ++- src/soc/amd/common/pi/def_callouts.c | 7 +++++-- src/soc/intel/apollolake/chip.c | 3 ++- src/soc/intel/common/block/cpu/mp_init.c | 2 +- src/soc/intel/skylake/cpu.c | 6 +++--- 9 files changed, 35 insertions(+), 28 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 258b9df9da2..0624176b75d 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -974,17 +974,16 @@ static void ap_wait_for_instruction(void) } } -int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num, +enum cb_err mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num, long expire_us) { struct mp_callback lcb = { .func = func, .arg = arg, .logical_cpu_number = logical_cpu_num}; - /* TODO: Remove this return value translation after changing the return type of - mp_run_on_aps to enum cb_err */ - return run_ap_work(&lcb, expire_us) == CB_SUCCESS ? 0 : -1; + return run_ap_work(&lcb, expire_us); } -int mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us, bool run_parallel) +enum cb_err mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us, + bool run_parallel) { int ap_index, bsp_index; @@ -999,14 +998,14 @@ int mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us, bool run_ /* skip if BSP */ if (ap_index == bsp_index) continue; - if (mp_run_on_aps(func, arg, ap_index, expire_us)) + if (mp_run_on_aps(func, arg, ap_index, expire_us) != CB_SUCCESS) return CB_ERR; } return CB_SUCCESS; } -int mp_run_on_all_cpus(void (*func)(void *), void *arg) +enum cb_err mp_run_on_all_cpus(void (*func)(void *), void *arg) { /* Run on BSP first. */ func(arg); @@ -1015,10 +1014,10 @@ int mp_run_on_all_cpus(void (*func)(void *), void *arg) return mp_run_on_aps(func, arg, MP_RUN_ON_ALL_CPUS, 1000 * USECS_PER_MSEC); } -int mp_park_aps(void) +enum cb_err mp_park_aps(void) { struct stopwatch sw; - int ret; + enum cb_err ret; long duration_msecs; stopwatch_init(&sw); @@ -1028,7 +1027,7 @@ int mp_park_aps(void) duration_msecs = stopwatch_duration_msecs(&sw); - if (!ret) + if (ret == CB_SUCCESS) printk(BIOS_DEBUG, "%s done after %ld msecs.\n", __func__, duration_msecs); else diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index a795c722a61..3f1e83d5415 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -9,6 +9,7 @@ #include #include #include +#include #define BSP_CPU_SLOT 0 @@ -72,7 +73,8 @@ efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure, if (procedure == NULL) return FSP_INVALID_PARAMETER; - if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, !run_serial)) { + if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, !run_serial) != + CB_SUCCESS) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; } @@ -94,7 +96,7 @@ efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure, /* Run on APs */ if (mp_run_on_aps((void *)procedure, argument, - MP_RUN_ON_ALL_CPUS, timeout_usec)) { + MP_RUN_ON_ALL_CPUS, timeout_usec) != CB_SUCCESS) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; } @@ -118,7 +120,7 @@ efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure, return FSP_INVALID_PARAMETER; if (mp_run_on_aps((void *)procedure, argument, - processor_number, timeout_usec)) { + processor_number, timeout_usec) != CB_SUCCESS) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; } diff --git a/src/drivers/ocp/dmi/smbios.c b/src/drivers/ocp/dmi/smbios.c index d0ef11508d6..51c008d4059 100644 --- a/src/drivers/ocp/dmi/smbios.c +++ b/src/drivers/ocp/dmi/smbios.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "ocp_dmi.h" @@ -244,7 +245,8 @@ void ocp_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) if (CONFIG_MAX_SOCKET == 2 && CONFIG(PARALLEL_MP_AP_WORK)) { /* Read the last CPU MSR */ if (mp_run_on_aps(read_remote_ppin, (void *)&xeon_sp_ppin[1], - get_platform_thread_count() - 1, 100 * USECS_PER_MSEC)) { + get_platform_thread_count() - 1, 100 * USECS_PER_MSEC) != + CB_SUCCESS) { printk(BIOS_ERR, "Failed to read remote PPIN.\n"); t->count = smbios_add_oem_string(t->eos, TBF); } else { diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index aa6289c18cb..7ed82dda422 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -117,26 +117,25 @@ enum { * Input parameter expire_us <= 0 to specify an infinite timeout. * logical_cpu_num = MP_RUN_ON_ALL_CPUS to execute function over all cores (BSP * + APs) else specified AP number using logical_cpu_num. - * - * All functions return < 0 on error, 0 on success. */ -int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num, +enum cb_err mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num, long expire_us); /* * Runs func on all APs excluding BSP, with a provision to run calls in parallel * or serially per AP. */ -int mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us, bool run_parallel); +enum cb_err mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us, + bool run_parallel); /* Like mp_run_on_aps() but also runs func on BSP. */ -int mp_run_on_all_cpus(void (*func)(void *), void *arg); +enum cb_err mp_run_on_all_cpus(void (*func)(void *), void *arg); /* * Park all APs to prepare for OS boot. This is handled automatically * by the coreboot infrastructure. */ -int mp_park_aps(void); +enum cb_err mp_park_aps(void); /* * SMM helpers to use with initializing CPUs. diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c index 2795100d861..ec975bea278 100644 --- a/src/soc/amd/common/block/cpu/smm/finalize.c +++ b/src/soc/amd/common/block/cpu/smm/finalize.c @@ -7,6 +7,7 @@ #include #include #include +#include static void per_core_finalize(void *unused) { @@ -31,7 +32,7 @@ static void finalize_cores(void) { printk(BIOS_SPEW, "Lock SMM configuration\n"); - if (mp_run_on_all_cpus(per_core_finalize, NULL)) + if (mp_run_on_all_cpus(per_core_finalize, NULL) != CB_SUCCESS) printk(BIOS_WARNING, "Failed to finalize all cores\n"); } diff --git a/src/soc/amd/common/pi/def_callouts.c b/src/soc/amd/common/pi/def_callouts.c index 2ee7f460563..0d799b94d23 100644 --- a/src/soc/amd/common/pi/def_callouts.c +++ b/src/soc/amd/common/pi/def_callouts.c @@ -10,6 +10,7 @@ #include #include #include +#include #if ENV_BOOTBLOCK const BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -205,7 +206,8 @@ AGESA_STATUS agesa_RunFuncOnAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) agesadata.Func = Func; agesadata.Data = Data; agesadata.ConfigPtr = ConfigPtr; - if (mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, 100 * USECS_PER_MSEC)) + if (mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, 100 * USECS_PER_MSEC) != + CB_SUCCESS) return AGESA_ERROR; return AGESA_SUCCESS; @@ -219,7 +221,8 @@ AGESA_STATUS agesa_RunFcnOnAllAps(uint32_t Func, uintptr_t Data, agesadata.Func = Func; agesadata.Data = Data; agesadata.ConfigPtr = ConfigPtr; - if (mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, 100 * USECS_PER_MSEC)) + if (mp_run_on_aps(callout_ap_entry, NULL, MP_RUN_ON_ALL_CPUS, 100 * USECS_PER_MSEC) != + CB_SUCCESS) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 4cc29e6e211..057138c803f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "chip.h" @@ -704,7 +705,7 @@ struct chip_operations soc_intel_apollolake_ops = { static void drop_privilege_all(void) { /* Drop privilege level on all the CPUs */ - if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, NULL) < 0) + if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, NULL) != CB_SUCCESS) printk(BIOS_ERR, "failed to enable untrusted mode\n"); } diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 4a429ab8f87..acd15a8f2c4 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -157,7 +157,7 @@ static void wrapper_x86_setup_mtrrs(void *unused) /* Ensure to re-program all MTRRs based on DRAM resource settings */ static void post_cpus_init(void *unused) { - if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) < 0) + if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS) printk(BIOS_ERR, "MTRR programming failure\n"); x86_mtrr_check(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index d88dd36ad67..86e8e52797f 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -178,14 +178,14 @@ static void post_mp_init(void) if (CONFIG(HAVE_SMI_HANDLER)) smm_lock(); - if (mp_run_on_all_cpus(vmx_configure, NULL)) + if (mp_run_on_all_cpus(vmx_configure, NULL) != CB_SUCCESS) failure = true; if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) - if (mp_run_on_all_cpus(sgx_configure, NULL)) + if (mp_run_on_all_cpus(sgx_configure, NULL) != CB_SUCCESS) failure = true; - if (mp_run_on_all_cpus(fc_lock_configure, NULL)) + if (mp_run_on_all_cpus(fc_lock_configure, NULL) != CB_SUCCESS) failure = true; if (failure) From 4dd7d1196545f1dff71b8e70b7a9b80b8bcd4041 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 23:31:43 +0200 Subject: [PATCH 271/320] cpu/x86/mp_init: move printing of failure message into mp_init_with_smm Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/cpu/intel/haswell/haswell_init.c | 4 ++-- src/cpu/intel/model_1067x/mp_init.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x_init.c | 4 ++-- src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++-- src/cpu/x86/mp_init.c | 12 +++++++++++- src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 ++-- src/soc/amd/cezanne/cpu.c | 4 ++-- src/soc/amd/picasso/cpu.c | 4 ++-- src/soc/amd/stoneyridge/cpu.c | 4 ++-- src/soc/intel/alderlake/cpu.c | 4 ++-- src/soc/intel/apollolake/cpu.c | 4 ++-- src/soc/intel/baytrail/cpu.c | 4 ++-- src/soc/intel/braswell/cpu.c | 4 ++-- src/soc/intel/cannonlake/cpu.c | 4 ++-- src/soc/intel/denverton_ns/cpu.c | 4 ++-- src/soc/intel/elkhartlake/cpu.c | 4 ++-- src/soc/intel/icelake/cpu.c | 4 ++-- src/soc/intel/jasperlake/cpu.c | 4 ++-- src/soc/intel/skylake/cpu.c | 4 ++-- src/soc/intel/tigerlake/cpu.c | 4 ++-- src/soc/intel/xeon_sp/cpx/cpu.c | 4 ++-- src/soc/intel/xeon_sp/skx/cpu.c | 4 ++-- 22 files changed, 53 insertions(+), 43 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 40f5ce00133..2ab77b30443 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -642,8 +642,8 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 38d3735f142..9a1fc42d3e6 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -98,6 +98,6 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); } diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index a31f2cb692c..30519c02568 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -175,8 +175,8 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index f3181cfaa61..d240f53761c 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -431,8 +431,8 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 0624176b75d..c99732fb390 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1095,7 +1095,7 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation; } -enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) +static enum cb_err do_mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) { enum cb_err ret; void *default_smm_area; @@ -1142,3 +1142,13 @@ enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) return ret; } + +enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) +{ + enum cb_err ret = do_mp_init_with_smm(cpu_bus, mp_ops); + + if (ret != CB_SUCCESS) + printk(BIOS_ERR, "MP initialization failure.\n"); + + return ret; +} diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index b7630a138b3..d041b0c6736 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -251,8 +251,8 @@ void mp_init_cpus(struct bus *cpu_bus) { const struct mp_ops *ops = CONFIG(SMM_TSEG) ? &mp_ops_with_smm : &mp_ops_no_smm; - if (mp_init_with_smm(cpu_bus, ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, ops); } static void cpu_bus_init(struct device *dev) diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index a2fa433a9b7..c3d89bf5134 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -52,8 +52,8 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 087b1539984..9822326afe3 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -56,8 +56,8 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 08f553351c9..99b40a61318 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -54,8 +54,8 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index a4375591078..94658c7acbd 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -127,8 +127,8 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); /* Thermal throttle activation offset */ configure_tcc_thermal_target(); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 645582b1326..af0a6dcd185 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -251,8 +251,8 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); } void apollolake_init_cpus(struct device *dev) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 8e402651cea..98400d1a1ac 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -197,6 +197,6 @@ void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); } diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index ead42b92f81..ed5244270c5 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -206,6 +206,6 @@ void soc_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); } diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 23b944df2d5..4f6720850ef 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -190,8 +190,8 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); /* Thermal throttle activation offset */ configure_tcc_thermal_target(); diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index ab4043bf094..d8566927218 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -297,6 +297,6 @@ void denverton_init_cpus(struct device *dev) add_more_links(dev, 1); /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(dev->link_list, &mp_ops); } diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index bfbb87f804f..0fcc61d936f 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -118,8 +118,8 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); /* Thermal throttle activation offset */ configure_tcc_thermal_target(); diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index dea75b6ed4f..203cddd69f3 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -154,6 +154,6 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); } diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 18194c99a2f..9959bd5c637 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -120,8 +120,8 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); /* Thermal throttle activation offset */ configure_tcc_thermal_target(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 86e8e52797f..91db06b3a6b 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -215,8 +215,8 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); /* Thermal throttle activation offset */ configure_tcc_thermal_target(); diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index f10f0cf85d0..ce020ee151e 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -126,8 +126,8 @@ static const struct mp_ops mp_ops = { void soc_init_cpus(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); /* Thermal throttle activation offset */ configure_tcc_thermal_target(); diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 9746972a385..ba417a70602 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -212,8 +212,8 @@ void cpx_init_cpus(struct device *dev) intel_microcode_load_unlocked(microcode_patch); - if (mp_init_with_smm(dev->link_list, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(dev->link_list, &mp_ops); /* * chip_config is used in cpu device callback. Other than cpu 0, diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 4d017406563..fcdb2d7ea04 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -231,8 +231,8 @@ void xeon_sp_init_cpus(struct device *dev) config_reset_cpl3_csrs(); /* calls src/cpu/x86/mp_init.c */ - if (mp_init_with_smm(dev->link_list, &mp_ops) != CB_SUCCESS) - printk(BIOS_ERR, "MP initialization failure.\n"); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(dev->link_list, &mp_ops); /* update numa domain for all cpu devices */ xeonsp_init_cpu_config(); From 37e160efb5973ebe7b8b3f5e445d3bdf33c35dd5 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 23:43:12 +0200 Subject: [PATCH 272/320] soc/intel/baytrail: use mp_cpu_bus_init Implement mp_init_cpus and use mp_cpu_bus_init as init function in cpu_bus_ops. Signed-off-by: Felix Held Change-Id: I057ae8d95bdc510e9e7afb144b692531107fa45d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58506 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/intel/baytrail/chip.c | 2 +- src/soc/intel/baytrail/cpu.c | 5 ++--- src/soc/intel/baytrail/include/soc/ramstage.h | 1 - 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index c7eb149020f..1f72dc44902 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -17,7 +17,7 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = baytrail_init_cpus, + .init = mp_cpu_bus_init, }; static void enable_dev(struct device *dev) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 98400d1a1ac..1dbc3d7751b 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -193,10 +194,8 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void baytrail_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { - struct bus *cpu_bus = dev->link_list; - /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, &mp_ops); } diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index 51189cfd460..8b4727c2602 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -9,7 +9,6 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(struct device *dev); void southcluster_enable_dev(struct device *dev); /* The baytrail_run_reference_code() function is provided by either * native refcode or the ChromeBook refcode wrapper */ From e8601f47772c9a71486e15e19c2cdd2947034b49 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 20 Oct 2021 23:56:18 +0200 Subject: [PATCH 273/320] soc/intel/braswell: use mp_cpu_bus_init Implement mp_init_cpus and use mp_cpu_bus_init as init function in cpu_bus_ops. Signed-off-by: Felix Held Change-Id: I2adcb1e1d79ced804925c81095cc5c0c2e6f9948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58507 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/intel/braswell/chip.c | 2 +- src/soc/intel/braswell/cpu.c | 5 ++--- src/soc/intel/braswell/include/soc/ramstage.h | 1 - 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index e3c7aa850c5..e2ee0a93015 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -19,7 +19,7 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = soc_init_cpus + .init = mp_cpu_bus_init, }; static void enable_dev(struct device *dev) diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index ed5244270c5..7c7a15d19c0 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -202,10 +203,8 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void soc_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { - struct bus *cpu_bus = dev->link_list; - /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, &mp_ops); } diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index 9312b920fc0..a1a2ea54c00 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -83,7 +83,6 @@ enum { * initialization, but it's after console and cbmem has been reinitialized. */ void soc_init_pre_device(struct soc_intel_braswell_config *config); -void soc_init_cpus(struct device *dev); void southcluster_enable_dev(struct device *dev); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); int SocStepping(void); From 04a40379b0cbc96c25498ec69520cb7cd85f3fe4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 08:04:28 +0300 Subject: [PATCH 274/320] sb,soc/intel: Set IOAPIC redirection entry count MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The number of redirection table entries (aka interrupt vectors) inside an I/O APIC may depend of the SKU, with the related register being of type read/write-once. Provide support utilities to either lock or set this registers value. Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/arch/x86/include/arch/ioapic.h | 5 +++ src/arch/x86/ioapic.c | 50 ++++++++++++++++++------ src/soc/intel/broadwell/pch/lpc.c | 11 +----- src/soc/intel/common/block/lpc/lpc_lib.c | 14 ++----- src/soc/intel/denverton_ns/lpc.c | 13 ++---- src/southbridge/intel/bd82x6x/lpc.c | 5 +-- src/southbridge/intel/i82801ix/lpc.c | 9 +---- src/southbridge/intel/i82801jx/lpc.c | 9 +---- src/southbridge/intel/ibexpeak/lpc.c | 6 +-- src/southbridge/intel/lynxpoint/lpc.c | 14 +++---- 10 files changed, 62 insertions(+), 74 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index d8df39b4556..9e524e250f5 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -31,6 +31,11 @@ void io_apic_write(void *ioapic_base, u32 reg, u32 value); void set_ioapic_id(void *ioapic_base, u8 ioapic_id); u8 get_ioapic_id(void *ioapic_base); u8 get_ioapic_version(void *ioapic_base); + +unsigned int ioapic_get_max_vectors(void *ioapic_base); +void ioapic_set_max_vectors(void *ioapic_base, int mre_count); +void ioapic_lock_max_vectors(void *ioapic_base); + void setup_ioapic(void *ioapic_base, u8 ioapic_id); void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 1d30baad488..22d979dfda5 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -27,18 +27,44 @@ static void write_vector(void *ioapic_base, u8 vector, u32 high, u32 low) vector, high, low); } -static int ioapic_interrupt_count(void *ioapic_base) +/* Bits 23-16 of register 0x01 specify the maximum redirection entry, which + * is the number of interrupts minus 1. */ +unsigned int ioapic_get_max_vectors(void *ioapic_base) { - /* Read the available number of interrupts. */ - int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; - if (!ioapic_interrupts || ioapic_interrupts == 0xff) - ioapic_interrupts = 23; - ioapic_interrupts += 1; /* Bits 23-16 specify the maximum redirection - entry, which is the number of interrupts - minus 1. */ - printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); - - return ioapic_interrupts; + u32 reg; + u8 count; + + reg = io_apic_read(ioapic_base, 0x01); + count = reg >> 16; + + if (!count || count == 0xff) + count = 23; + count++; + + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", count); + return count; +} + +/* Set maximum number of redirection entries (MRE). It is write-once register + * for some chipsets, and a negative mre_count will lock it to the number + * of vectors read from the register. */ +void ioapic_set_max_vectors(void *ioapic_base, int mre_count) +{ + u32 reg; + u8 count; + + reg = io_apic_read(ioapic_base, 0x01); + count = reg >> 16; + if (mre_count > 0) + count = mre_count - 1; + reg &= ~(0xff << 16); + reg |= count << 16; + io_apic_write(ioapic_base, 0x01, count); +} + +void ioapic_lock_max_vectors(void *ioapic_base) +{ + ioapic_set_max_vectors(ioapic_base, -1); } static void clear_vectors(void *ioapic_base, u8 first, u8 last) @@ -134,6 +160,6 @@ void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb) void setup_ioapic(void *ioapic_base, u8 ioapic_id) { set_ioapic_id(ioapic_base, ioapic_id); - clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1); + clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1); route_i8259_irq0(ioapic_base); } diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 41da81e658a..40cc61e4b2c 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -25,8 +25,6 @@ static void pch_enable_ioapic(struct device *dev) { - u32 reg32; - /* Assign unique bus/dev/fn for I/O APIC */ pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); @@ -34,13 +32,8 @@ static void pch_enable_ioapic(struct device *dev) set_ioapic_id(VIO_APIC_VADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); - - /* PCH-LP has 39 redirection entries */ - reg32 &= ~0x00ff0000; - reg32 |= 0x00270000; - - io_apic_write(VIO_APIC_VADDR, 0x01, reg32); + /* PCH-LP has 40 redirection entries */ + ioapic_set_max_vectors(VIO_APIC_VADDR, 40); } static void enable_hpet(struct device *dev) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 0268245f34b..c2278df2486 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -274,22 +274,16 @@ void lpc_disable_clkrun(void) pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); } +/* PCH I/O APIC redirection entries */ +#define PCH_REDIR_ETR 120 + /* Enable PCH IOAPIC */ void pch_enable_ioapic(void) { - uint32_t reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); } static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index a099c31f2b2..7f47e5ed710 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -21,8 +21,8 @@ #include "chip.h" -/* PCH-LP redirection entries */ -#define PCH_LP_REDIR_ETR 120 +/* PCH I/O APIC redirection entries */ +#define PCH_REDIR_ETR 120 /** * Set miscellaneous static southbridge features. @@ -31,17 +31,10 @@ */ static void pch_enable_ioapic(struct device *dev) { - u32 reg32; - set_ioapic_id((void *)IO_APIC_ADDR, IO_APIC0); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (PCH_LP_REDIR_ETR - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); } /* interrupt router lookup for internal devices */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index dfebaf0dace..b1f5ec84303 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -37,8 +37,6 @@ typedef struct southbridge_intel_bd82x6x_config config_t; */ static void pch_enable_ioapic(struct device *dev) { - u32 reg32; - /* Assign unique bus/dev/fn for I/O APIC */ pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); @@ -46,8 +44,7 @@ static void pch_enable_ioapic(struct device *dev) set_ioapic_id(VIO_APIC_VADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); - io_apic_write(VIO_APIC_VADDR, 0x01, reg32); + ioapic_lock_max_vectors(VIO_APIC_VADDR); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 866ede9a504..21f1faa3b7b 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -27,20 +27,13 @@ typedef struct southbridge_intel_i82801ix_config config_t; static void i82801ix_enable_apic(struct device *dev) { - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable IOAPIC. Keep APIC Range Select at zero. */ RCBA8(0x31ff) = 0x03; /* We have to read 0x31ff back if bit0 changed. */ RCBA8(0x31ff); /* Lock maximum redirection entries (MRE), R/WO register. */ - *ioapic_index = 0x01; - reg32 = *ioapic_data; - *ioapic_index = 0x01; - *ioapic_data = reg32; + ioapic_lock_max_vectors(VIO_APIC_VADDR); setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */ } diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 69990ab8bac..106669d8831 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -28,20 +28,13 @@ typedef struct southbridge_intel_i82801jx_config config_t; static void i82801jx_enable_apic(struct device *dev) { - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable IOAPIC. Keep APIC Range Select at zero. */ RCBA8(0x31ff) = 0x03; /* We have to read 0x31ff back if bit0 changed. */ RCBA8(0x31ff); /* Lock maximum redirection entries (MRE), R/WO register. */ - *ioapic_index = 0x01; - reg32 = *ioapic_data; - *ioapic_index = 0x01; - *ioapic_data = reg32; + ioapic_lock_max_vectors(VIO_APIC_VADDR); setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */ } diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index c14c6a28b1e..f1cf7a3b7fb 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -34,12 +34,10 @@ typedef struct southbridge_intel_ibexpeak_config config_t; */ static void pch_enable_ioapic(struct device *dev) { - u32 reg32; - set_ioapic_id(VIO_APIC_VADDR, 0x01); + /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); - io_apic_write(VIO_APIC_VADDR, 0x01, reg32); + ioapic_lock_max_vectors(VIO_APIC_VADDR); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d0eb4b33f01..ef75d2f77d5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -31,8 +31,6 @@ */ static void pch_enable_ioapic(struct device *dev) { - u32 reg32; - /* Assign unique bus/dev/fn for I/O APIC */ pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); @@ -40,13 +38,11 @@ static void pch_enable_ioapic(struct device *dev) set_ioapic_id(VIO_APIC_VADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); - if (pch_is_lp()) { - /* PCH-LP has 39 redirection entries */ - reg32 &= ~0x00ff0000; - reg32 |= 0x00270000; - } - io_apic_write(VIO_APIC_VADDR, 0x01, reg32); + /* PCH-LP has 40 redirection entries */ + if (pch_is_lp()) + ioapic_set_max_vectors(VIO_APIC_VADDR, 40); + else + ioapic_lock_max_vectors(VIO_APIC_VADDR); } static void pch_enable_serial_irqs(struct device *dev) From 6139ff9c9aa0b941b1c178058e4d10baa23fff70 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 18 Oct 2021 19:43:49 +0300 Subject: [PATCH 275/320] arch/x86/ioapic: Allow IOAPIC with only one vector MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the test for count=0 that leaked from drivers/generic/ioapic implementation. See commit ea2fb8d80 and commit 8cc25d229. Change-Id: I26944b930851fbea160c844ea46e2faa61c9af8e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/58423 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/arch/x86/ioapic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 22d979dfda5..d299e6070de 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -35,9 +35,9 @@ unsigned int ioapic_get_max_vectors(void *ioapic_base) u8 count; reg = io_apic_read(ioapic_base, 0x01); - count = reg >> 16; + count = (reg >> 16) & 0xff; - if (!count || count == 0xff) + if (count == 0xff) count = 23; count++; @@ -54,7 +54,7 @@ void ioapic_set_max_vectors(void *ioapic_base, int mre_count) u8 count; reg = io_apic_read(ioapic_base, 0x01); - count = reg >> 16; + count = (reg >> 16) & 0xff; if (mre_count > 0) count = mre_count - 1; reg &= ~(0xff << 16); From ea6d12a0de8af000fb72a873b63364462f280643 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 8 Jun 2021 11:25:29 +0300 Subject: [PATCH 276/320] sb,soc/intel: Set IOAPIC max entries before APIC ID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows to replace set_ioapic_id() call with setup_ioapic() that also clears redirection table entries. Change-Id: I854f19c997a96bcdccb11a0906431e3291788cb6 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55308 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/broadwell/pch/lpc.c | 4 ++-- src/soc/intel/common/block/lpc/lpc_lib.c | 4 ++-- src/soc/intel/denverton_ns/lpc.c | 4 ++-- src/southbridge/intel/bd82x6x/lpc.c | 4 ++-- src/southbridge/intel/ibexpeak/lpc.c | 4 ++-- src/southbridge/intel/lynxpoint/lpc.c | 5 +++-- 6 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 40cc61e4b2c..a3de7ac213b 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -29,11 +29,11 @@ static void pch_enable_ioapic(struct device *dev) pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); - set_ioapic_id(VIO_APIC_VADDR, 0x02); - /* affirm full set of redirection table entries ("write once") */ /* PCH-LP has 40 redirection entries */ ioapic_set_max_vectors(VIO_APIC_VADDR, 40); + + set_ioapic_id(VIO_APIC_VADDR, 0x02); } static void enable_hpet(struct device *dev) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index c2278df2486..43434df0afd 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -280,10 +280,10 @@ void lpc_disable_clkrun(void) /* Enable PCH IOAPIC */ void pch_enable_ioapic(void) { - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - /* affirm full set of redirection table entries ("write once") */ ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); + + set_ioapic_id((void *)IO_APIC_ADDR, 0x02); } static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7f47e5ed710..f0a7058df58 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -31,10 +31,10 @@ */ static void pch_enable_ioapic(struct device *dev) { - set_ioapic_id((void *)IO_APIC_ADDR, IO_APIC0); - /* affirm full set of redirection table entries ("write once") */ ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); + + set_ioapic_id((void *)IO_APIC_ADDR, IO_APIC0); } /* interrupt router lookup for internal devices */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index b1f5ec84303..51d6b07064b 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -41,10 +41,10 @@ static void pch_enable_ioapic(struct device *dev) pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); - set_ioapic_id(VIO_APIC_VADDR, 0x02); - /* affirm full set of redirection table entries ("write once") */ ioapic_lock_max_vectors(VIO_APIC_VADDR); + + set_ioapic_id(VIO_APIC_VADDR, 0x02); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f1cf7a3b7fb..fa53db20f84 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -34,10 +34,10 @@ typedef struct southbridge_intel_ibexpeak_config config_t; */ static void pch_enable_ioapic(struct device *dev) { - set_ioapic_id(VIO_APIC_VADDR, 0x01); - /* affirm full set of redirection table entries ("write once") */ ioapic_lock_max_vectors(VIO_APIC_VADDR); + + set_ioapic_id(VIO_APIC_VADDR, 0x01); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ef75d2f77d5..72f6d809770 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -35,14 +35,15 @@ static void pch_enable_ioapic(struct device *dev) pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); - set_ioapic_id(VIO_APIC_VADDR, 0x02); - /* affirm full set of redirection table entries ("write once") */ /* PCH-LP has 40 redirection entries */ if (pch_is_lp()) ioapic_set_max_vectors(VIO_APIC_VADDR, 40); else ioapic_lock_max_vectors(VIO_APIC_VADDR); + + set_ioapic_id(VIO_APIC_VADDR, 0x02); + } static void pch_enable_serial_irqs(struct device *dev) From 682613f0653064eeeba2b4d15f6d50e32a692bd3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 8 Jun 2021 11:31:19 +0300 Subject: [PATCH 277/320] sb,soc/intel: Replace set_ioapic_id() with setup_ioapic() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds delivery of PIC/i8259 interrupts via ExtNMI on the affected platfoms. Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/broadwell/pch/lpc.c | 2 +- src/soc/intel/common/block/lpc/lpc_lib.c | 2 +- src/soc/intel/denverton_ns/lpc.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/i82371eb/isa.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index a3de7ac213b..b68a8cfb68f 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -33,7 +33,7 @@ static void pch_enable_ioapic(struct device *dev) /* PCH-LP has 40 redirection entries */ ioapic_set_max_vectors(VIO_APIC_VADDR, 40); - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); } static void enable_hpet(struct device *dev) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 43434df0afd..13937143931 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -283,7 +283,7 @@ void pch_enable_ioapic(void) /* affirm full set of redirection table entries ("write once") */ ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); + setup_ioapic((void *)IO_APIC_ADDR, 0x02); } static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index f0a7058df58..0fcaeb19fdd 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -34,7 +34,7 @@ static void pch_enable_ioapic(struct device *dev) /* affirm full set of redirection table entries ("write once") */ ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); - set_ioapic_id((void *)IO_APIC_ADDR, IO_APIC0); + setup_ioapic((void *)IO_APIC_ADDR, IO_APIC0); } /* interrupt router lookup for internal devices */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 51d6b07064b..ae92ca942ab 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -44,7 +44,7 @@ static void pch_enable_ioapic(struct device *dev) /* affirm full set of redirection table entries ("write once") */ ioapic_lock_max_vectors(VIO_APIC_VADDR); - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 3d586bdf80f..c2411f2b90d 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -61,7 +61,7 @@ static void isa_init(struct device *dev) pci_write_config16(dev, XBCS, reg16); /* Set and verify the IOAPIC ID. */ - set_ioapic_id(VIO_APIC_VADDR, ioapic_id); + setup_ioapic(VIO_APIC_VADDR, ioapic_id); if (ioapic_id != get_ioapic_id(VIO_APIC_VADDR)) die("IOAPIC error!\n"); } diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 321c6053662..34d93c48005 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -48,7 +48,7 @@ static void i82801dx_enable_ioapic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); ioapic_set_boot_config(VIO_APIC_VADDR, true); } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ababe675a90..794d34acdb1 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -33,7 +33,7 @@ */ static void i82801gx_enable_ioapic(struct device *dev) { - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); } static void i82801gx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index fa53db20f84..01836b16985 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -37,7 +37,7 @@ static void pch_enable_ioapic(struct device *dev) /* affirm full set of redirection table entries ("write once") */ ioapic_lock_max_vectors(VIO_APIC_VADDR); - set_ioapic_id(VIO_APIC_VADDR, 0x01); + setup_ioapic(VIO_APIC_VADDR, 0x01); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 72f6d809770..ea84def99a9 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -42,7 +42,7 @@ static void pch_enable_ioapic(struct device *dev) else ioapic_lock_max_vectors(VIO_APIC_VADDR); - set_ioapic_id(VIO_APIC_VADDR, 0x02); + setup_ioapic(VIO_APIC_VADDR, 0x02); } From 4bab5691cc9369ea3dd8427d1f54a7ae470a35f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 09:50:57 +0300 Subject: [PATCH 278/320] mb/emulation/qemu-i440fx: Select IOAPIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For SMP operation IOAPIC needs to be configured. For a build with MAX_CPUS=1 emulation might still decode the IOAPIC MMIO window, it does not really matter to have it always reserved. Change-Id: Ia340fc418cd9ceda56a2a10972e130d9f289c589 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55290 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/mainboard/emulation/qemu-i440fx/Kconfig | 1 + src/southbridge/intel/i82371eb/isa.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 1b9edf04b9c..eb745e7f9be 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ASAN_IN_ROMSTAGE select NO_SMM select BOOT_DEVICE_NOT_SPI_FLASH + select IOAPIC config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index c2411f2b90d..5eb1a82d178 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -85,13 +85,11 @@ static void sb_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; -#if CONFIG(IOAPIC) res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; -#endif } static const struct device_operations isa_ops = { From c25ecb54436ab1b20f99db363f71fa13fd3e9831 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 08:28:16 +0300 Subject: [PATCH 279/320] arch/x86/ioapic: Select IOAPIC with SMP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Raul Rangel --- src/Kconfig | 1 + src/mainboard/asus/p2b/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/Kconfig | 1 - src/soc/amd/cezanne/Kconfig | 1 - src/soc/amd/picasso/Kconfig | 1 - src/soc/amd/stoneyridge/Kconfig | 1 - src/soc/intel/alderlake/Kconfig | 1 - src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/broadwell/pch/Kconfig | 1 - src/soc/intel/cannonlake/Kconfig | 1 - src/soc/intel/denverton_ns/Kconfig | 1 - src/soc/intel/elkhartlake/Kconfig | 1 - src/soc/intel/icelake/Kconfig | 1 - src/soc/intel/jasperlake/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 1 - src/soc/intel/tigerlake/Kconfig | 1 - src/soc/intel/xeon_sp/Kconfig | 1 - src/southbridge/amd/agesa/hudson/Kconfig | 1 - src/southbridge/amd/cimx/sb800/Kconfig | 1 - src/southbridge/amd/pi/hudson/Kconfig | 1 - src/southbridge/intel/bd82x6x/Kconfig | 1 - src/southbridge/intel/i82801dx/Kconfig | 1 - src/southbridge/intel/i82801gx/Kconfig | 1 - src/southbridge/intel/i82801ix/Kconfig | 1 - src/southbridge/intel/i82801jx/Kconfig | 1 - src/southbridge/intel/ibexpeak/Kconfig | 1 - src/southbridge/intel/lynxpoint/Kconfig | 1 - 27 files changed, 1 insertion(+), 26 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index ea05215bdd4..be269b61953 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -717,6 +717,7 @@ config PCI_IO_CFG_EXT config IOAPIC bool + default y if SMP default n config USE_WATCHDOG_ON_BOOT diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index d56efd2b461..8e46fb9b138 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -6,7 +6,6 @@ config BASE_ASUS_P2B_D def_bool n select SDRAMPWR_4DIMM select HAVE_MP_TABLE - select IOAPIC config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index eb745e7f9be..1b9edf04b9c 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ASAN_IN_ROMSTAGE select NO_SMM select BOOT_DEVICE_NOT_SPI_FLASH - select IOAPIC config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index ae2f61f983f..c2423cd5abd 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -30,7 +30,6 @@ config SOC_SPECIFIC_OPTIONS select HAVE_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select IOAPIC select PARALLEL_MP_AP_WORK select PAYLOAD_PRELOAD select PLATFORM_USES_FSP2_0 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 71c9c27238f..5d1c0d49042 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS select DRIVERS_USB_PCI_XHCI select GENERIC_GPIO_LIB select IDT_IN_EVERY_STAGE - select IOAPIC select HAVE_ACPI_TABLES select HAVE_EM100_SUPPORT select SOC_AMD_COMMON diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 1f1e1a78bab..36eecb122f8 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_CF9_RESET select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS - select IOAPIC select PARALLEL_MP_AP_WORK select RTC select SOC_AMD_PI diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 530e76859b2..f646fc70e52 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_OPREGION_2_1 - select IOAPIC select INTEL_TME select MP_SERVICES_PPI_V2 select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0302546335e..45e21dd83a6 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -30,7 +30,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION - select IOAPIC select PCR_COMMON_IOSF_1_0 select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index c743049ca24..4e187ff1145 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -15,7 +15,6 @@ config PCH_SPECIFIC_OPTIONS select HAVE_USBDEBUG select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_LYNXPOINT_LP - select IOAPIC select RTC select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 227f680bcca..29315a1c015 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -67,7 +67,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select IOAPIC select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index a8ed92be289..5ed411bbcca 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 - select IOAPIC select HAVE_INTEL_FSP_REPO select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index e3fbfddb241..f23e8d7b8e0 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -25,7 +25,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select IOAPIC select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index fd05f2ec48c..5a825cbf54c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -25,7 +25,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select IOAPIC select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 43697602a2d..afa7a232194 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -26,7 +26,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select IOAPIC select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index bd3353d50e9..6c8a3763786 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select IOAPIC select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 1e9a85179ff..7a78f229bc7 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP - select IOAPIC select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 60786aa7cad..fa8403a2354 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select FSP_T_XIP select FSP_M_XIP select POSTCAR_STAGE - select IOAPIC select PARALLEL_MP_AP_WORK select PMC_GLOBAL_RESET_ENABLE_LOCK select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index cf5b21c3196..072f3fd53f9 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -10,7 +10,6 @@ if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y - select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index a151bae370b..fcfdfb4a68c 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -3,7 +3,6 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 bool default n - select IOAPIC select HAVE_USBDEBUG_OPTIONS select AMD_SB_CIMX select HAVE_CF9_RESET diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 10277c17794..0cec5cc7654 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -10,7 +10,6 @@ if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_KERN config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y - select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 701c98bf152..c9e86625d29 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET - select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 840aeb42dc7..fae592852b8 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -3,7 +3,6 @@ config SOUTHBRIDGE_INTEL_I82801DX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select IOAPIC select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index c8807935a2f..399d7e0bbb9 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -5,7 +5,6 @@ config SOUTHBRIDGE_INTEL_I82801GX select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT - select IOAPIC select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_GPIO diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 992562f5b9a..39f5e83b25a 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -8,7 +8,6 @@ config SOUTHBRIDGE_INTEL_I82801IX select HAVE_SMI_HANDLER if !NO_SMM select HAVE_USBDEBUG_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE - select IOAPIC select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index fa469ce0ae7..197ed523f6e 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -9,7 +9,6 @@ config SOUTHBRIDGE_INTEL_I82801JX select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE - select IOAPIC select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 117827fa6ea..6972da76138 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -9,7 +9,6 @@ config SOUTH_BRIDGE_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select AZALIA_PLUGIN_SUPPORT - select IOAPIC select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 25ed6efa122..891b06a4a57 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -19,7 +19,6 @@ config SOUTH_BRIDGE_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET - select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select USE_WATCHDOG_ON_BOOT From aed59b672177e5cec1727754c51dd6467b12a674 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 16 Jun 2021 10:14:41 +0300 Subject: [PATCH 280/320] AGESA binaryPI: Use common acpi_fill_madt() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I01ee0ba99eca6ad4c01848ab133166f8c922684d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55569 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/amd/persimmon/acpi_tables.c | 30 ----------------- src/mainboard/amd/south_station/acpi_tables.c | 30 ----------------- src/mainboard/amd/thatcher/acpi_tables.c | 29 ---------------- src/mainboard/amd/union_station/acpi_tables.c | 30 ----------------- src/mainboard/asrock/e350m1/acpi_tables.c | 30 ----------------- src/mainboard/asus/a88xm-e/acpi_tables.c | 29 ---------------- src/mainboard/asus/am1i-a/acpi_tables.c | 33 ------------------- src/mainboard/asus/f2a85-m/acpi_tables.c | 29 ---------------- src/mainboard/bap/ode_e20XX/acpi_tables.c | 33 ------------------- src/mainboard/biostar/a68n_5200/acpi_tables.c | 33 ------------------- src/mainboard/biostar/am1ml/acpi_tables.c | 33 ------------------- src/mainboard/elmex/pcm205400/acpi_tables.c | 30 ----------------- src/mainboard/gizmosphere/gizmo/acpi_tables.c | 30 ----------------- .../gizmosphere/gizmo2/acpi_tables.c | 33 ------------------- src/mainboard/hp/abm/acpi_tables.c | 33 ------------------- .../hp/pavilion_m6_1035dx/acpi_tables.c | 29 ---------------- .../jetway/nf81-t56n-lf/acpi_tables.c | 30 ----------------- src/mainboard/lenovo/g505s/acpi_tables.c | 29 ---------------- .../lippert/frontrunner-af/acpi_tables.c | 30 ----------------- src/mainboard/msi/ms7721/acpi_tables.c | 29 ---------------- src/mainboard/pcengines/apu1/acpi_tables.c | 30 ----------------- src/mainboard/pcengines/apu2/acpi_tables.c | 33 ------------------- .../amd/agesa/family14/Makefile.inc | 1 + .../amd/agesa/family14}/acpi_tables.c | 0 .../amd/agesa/family15tn/Makefile.inc | 1 + .../amd/agesa/family15tn}/acpi_tables.c | 0 .../amd/agesa/family16kb/Makefile.inc | 1 + .../amd/agesa/family16kb}/acpi_tables.c | 0 src/northbridge/amd/pi/00730F01/Makefile.inc | 1 + .../amd/pi/00730F01}/acpi_tables.c | 0 30 files changed, 4 insertions(+), 675 deletions(-) delete mode 100644 src/mainboard/amd/persimmon/acpi_tables.c delete mode 100644 src/mainboard/amd/south_station/acpi_tables.c delete mode 100644 src/mainboard/amd/thatcher/acpi_tables.c delete mode 100644 src/mainboard/amd/union_station/acpi_tables.c delete mode 100644 src/mainboard/asrock/e350m1/acpi_tables.c delete mode 100644 src/mainboard/asus/a88xm-e/acpi_tables.c delete mode 100644 src/mainboard/asus/am1i-a/acpi_tables.c delete mode 100644 src/mainboard/asus/f2a85-m/acpi_tables.c delete mode 100644 src/mainboard/bap/ode_e20XX/acpi_tables.c delete mode 100644 src/mainboard/biostar/a68n_5200/acpi_tables.c delete mode 100644 src/mainboard/biostar/am1ml/acpi_tables.c delete mode 100644 src/mainboard/elmex/pcm205400/acpi_tables.c delete mode 100644 src/mainboard/gizmosphere/gizmo/acpi_tables.c delete mode 100644 src/mainboard/gizmosphere/gizmo2/acpi_tables.c delete mode 100644 src/mainboard/hp/abm/acpi_tables.c delete mode 100644 src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c delete mode 100644 src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c delete mode 100644 src/mainboard/lenovo/g505s/acpi_tables.c delete mode 100644 src/mainboard/lippert/frontrunner-af/acpi_tables.c delete mode 100644 src/mainboard/msi/ms7721/acpi_tables.c delete mode 100644 src/mainboard/pcengines/apu1/acpi_tables.c delete mode 100644 src/mainboard/pcengines/apu2/acpi_tables.c rename src/{mainboard/amd/inagua => northbridge/amd/agesa/family14}/acpi_tables.c (100%) rename src/{mainboard/amd/parmer => northbridge/amd/agesa/family15tn}/acpi_tables.c (100%) rename src/{mainboard/amd/olivehill => northbridge/amd/agesa/family16kb}/acpi_tables.c (100%) rename src/{mainboard/asrock/imb-a180 => northbridge/amd/pi/00730F01}/acpi_tables.c (100%) diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c deleted file mode 100644 index f75f823f387..00000000000 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c deleted file mode 100644 index f75f823f387..00000000000 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c deleted file mode 100644 index ff4a3b97b62..00000000000 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Hudson IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c deleted file mode 100644 index f75f823f387..00000000000 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c deleted file mode 100644 index f75f823f387..00000000000 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c deleted file mode 100644 index ff4a3b97b62..00000000000 --- a/src/mainboard/asus/a88xm-e/acpi_tables.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Hudson IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/asus/am1i-a/acpi_tables.c b/src/mainboard/asus/am1i-a/acpi_tables.c deleted file mode 100644 index 86c448f3184..00000000000 --- a/src/mainboard/asus/am1i-a/acpi_tables.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Yangtze IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c deleted file mode 100644 index ff4a3b97b62..00000000000 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Hudson IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c deleted file mode 100644 index 2cc9bf58e11..00000000000 --- a/src/mainboard/bap/ode_e20XX/acpi_tables.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/biostar/a68n_5200/acpi_tables.c b/src/mainboard/biostar/a68n_5200/acpi_tables.c deleted file mode 100644 index 2cc9bf58e11..00000000000 --- a/src/mainboard/biostar/a68n_5200/acpi_tables.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/biostar/am1ml/acpi_tables.c b/src/mainboard/biostar/am1ml/acpi_tables.c deleted file mode 100644 index 86c448f3184..00000000000 --- a/src/mainboard/biostar/am1ml/acpi_tables.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Yangtze IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c deleted file mode 100644 index f75f823f387..00000000000 --- a/src/mainboard/elmex/pcm205400/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c deleted file mode 100644 index f75f823f387..00000000000 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c deleted file mode 100644 index 2cc9bf58e11..00000000000 --- a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/hp/abm/acpi_tables.c b/src/mainboard/hp/abm/acpi_tables.c deleted file mode 100644 index 2cc9bf58e11..00000000000 --- a/src/mainboard/hp/abm/acpi_tables.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c deleted file mode 100644 index ff4a3b97b62..00000000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Hudson IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c deleted file mode 100644 index f75f823f387..00000000000 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/lenovo/g505s/acpi_tables.c b/src/mainboard/lenovo/g505s/acpi_tables.c deleted file mode 100644 index ff4a3b97b62..00000000000 --- a/src/mainboard/lenovo/g505s/acpi_tables.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Hudson IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c deleted file mode 100644 index f75f823f387..00000000000 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/msi/ms7721/acpi_tables.c b/src/mainboard/msi/ms7721/acpi_tables.c deleted file mode 100644 index ff4a3b97b62..00000000000 --- a/src/mainboard/msi/ms7721/acpi_tables.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write Hudson IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/pcengines/apu1/acpi_tables.c b/src/mainboard/pcengines/apu1/acpi_tables.c deleted file mode 100644 index f75f823f387..00000000000 --- a/src/mainboard/pcengines/apu1/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c deleted file mode 100644 index 2cc9bf58e11..00000000000 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); - - /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); - - /* TODO: Remove the hardcode */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - - return current; -} diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index adcb86b34fb..e387ee5d247 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -3,6 +3,7 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c +ramstage-y += acpi_tables.c romstage-y += state_machine.c ramstage-y += state_machine.c diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/northbridge/amd/agesa/family14/acpi_tables.c similarity index 100% rename from src/mainboard/amd/inagua/acpi_tables.c rename to src/northbridge/amd/agesa/family14/acpi_tables.c diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index a865929d876..55103633064 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -4,6 +4,7 @@ romstage-y += dimmSpd.c ramstage-y += iommu.c ramstage-y += northbridge.c +ramstage-y += acpi_tables.c romstage-y += state_machine.c ramstage-y += state_machine.c diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/northbridge/amd/agesa/family15tn/acpi_tables.c similarity index 100% rename from src/mainboard/amd/parmer/acpi_tables.c rename to src/northbridge/amd/agesa/family15tn/acpi_tables.c diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc index adcb86b34fb..e387ee5d247 100644 --- a/src/northbridge/amd/agesa/family16kb/Makefile.inc +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -3,6 +3,7 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c +ramstage-y += acpi_tables.c romstage-y += state_machine.c ramstage-y += state_machine.c diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/northbridge/amd/agesa/family16kb/acpi_tables.c similarity index 100% rename from src/mainboard/amd/olivehill/acpi_tables.c rename to src/northbridge/amd/agesa/family16kb/acpi_tables.c diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc index b97b335b70d..8fc4ffce6e3 100644 --- a/src/northbridge/amd/pi/00730F01/Makefile.inc +++ b/src/northbridge/amd/pi/00730F01/Makefile.inc @@ -4,6 +4,7 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c ramstage-y += iommu.c +ramstage-y += acpi_tables.c romstage-y += state_machine.c ramstage-y += state_machine.c diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c similarity index 100% rename from src/mainboard/asrock/imb-a180/acpi_tables.c rename to src/northbridge/amd/pi/00730F01/acpi_tables.c From dc9b5efa8187ec886ab4ed360b8c4f9b2866c250 Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Wed, 20 Oct 2021 02:28:45 -0700 Subject: [PATCH 281/320] soc/intel/elkhartlake: Add PSE PCI devices into header file Since PSE devices could be initialized as either host owned (PCI devices) or PSE owned (will be hidden from coreboot and only visible to PSE interface), add all PSE devices in PCI list header file for future usage. Signed-off-by: Lean Sheng Tan Change-Id: Iaa40cdcb021d05e50504dd85f94e9c021e284d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58466 Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../intel/elkhartlake/include/soc/pci_devs.h | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h index 659de21ebd2..8cf193829cd 100644 --- a/src/soc/intel/elkhartlake/include/soc/pci_devs.h +++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h @@ -47,6 +47,24 @@ #define PCH_DEV_I2C7 _PCH_DEV(IEH, 1) #define PCH_DEV_IEH _PCH_DEV(IEH, 5) +#define PCH_DEV_SLOT_PSE0 0x11 +#define PCH_DEVFN_PSEUART0 _PCH_DEVFN(PSE0, 0) +#define PCH_DEVFN_PSEUART1 _PCH_DEVFN(PSE0, 1) +#define PCH_DEVFN_PSEUART2 _PCH_DEVFN(PSE0, 2) +#define PCH_DEVFN_PSEUART3 _PCH_DEVFN(PSE0, 3) +#define PCH_DEVFN_PSEUART4 _PCH_DEVFN(PSE0, 4) +#define PCH_DEVFN_PSEUART5 _PCH_DEVFN(PSE0, 5) +#define PCH_DEVFN_PSEIS20 _PCH_DEVFN(PSE0, 6) +#define PCH_DEVFN_PSEIS21 _PCH_DEVFN(PSE0, 7) +#define PCH_DEV_PSEUART0 _PCH_DEV(PSE0, 0) +#define PCH_DEV_PSEUART1 _PCH_DEV(PSE0, 1) +#define PCH_DEV_PSEUART2 _PCH_DEV(PSE0, 2) +#define PCH_DEV_PSEUART3 _PCH_DEV(PSE0, 3) +#define PCH_DEV_PSEUART4 _PCH_DEV(PSE0, 4) +#define PCH_DEV_PSEUART5 _PCH_DEV(PSE0, 5) +#define PCH_DEV_PSEIS20 _PCH_DEV(PSE0, 6) +#define PCH_DEV_PSEIS21 _PCH_DEV(PSE0, 7) + #define PCH_DEV_SLOT_SIO0 0x12 #define PCH_DEVFN_GSPI2 _PCH_DEVFN(SIO0, 0) #define PCH_DEVFN_CSE_UMA _PCH_DEVFN(SIO0, 3) @@ -59,6 +77,20 @@ #define PCH_DEV_UFS0 _PCH_DEV(SIO0, 5) #define PCH_DEV_UFS1 _PCH_DEV(SIO0, 7) +#define PCH_DEV_SLOT_PSE1 0x13 +#define PCH_DEVFN_PSEGSPI0 _PCH_DEVFN(PSE1, 0) +#define PCH_DEVFN_PSEGSPI1 _PCH_DEVFN(PSE1, 1) +#define PCH_DEVFN_PSEGSPI2 _PCH_DEVFN(PSE1, 2) +#define PCH_DEVFN_PSEGSPI3 _PCH_DEVFN(PSE1, 3) +#define PCH_DEVFN_PSEGPIO0 _PCH_DEVFN(PSE1, 4) +#define PCH_DEVFN_PSEGPIO1 _PCH_DEVFN(PSE1, 5) +#define PCH_DEV_PSEGSPI0 _PCH_DEV(PSE1, 0) +#define PCH_DEV_PSEGSPI1 _PCH_DEV(PSE1, 1) +#define PCH_DEV_PSEGSPI2 _PCH_DEV(PSE1, 2) +#define PCH_DEV_PSEGSPI3 _PCH_DEV(PSE1, 3) +#define PCH_DEV_PSEGPIO0 _PCH_DEV(PSE1, 4) +#define PCH_DEV_PSEGPIO1 _PCH_DEV(PSE1, 5) + #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) @@ -89,6 +121,22 @@ #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) #define PCH_DEV_SATA _PCH_DEV(SATA, 0) +#define PCH_DEV_SLOT_PSE2 0x18 +#define PCH_DEVFN_PSEI2C7 _PCH_DEVFN(PSE2, 0) +#define PCH_DEVFN_PSECAN0 _PCH_DEVFN(PSE2, 1) +#define PCH_DEVFN_PSECAN1 _PCH_DEVFN(PSE2, 2) +#define PCH_DEVFN_PSEQEP0 _PCH_DEVFN(PSE2, 3) +#define PCH_DEVFN_PSEQEP1 _PCH_DEVFN(PSE2, 4) +#define PCH_DEVFN_PSEQEP2 _PCH_DEVFN(PSE2, 5) +#define PCH_DEVFN_PSEQEP3 _PCH_DEVFN(PSE2, 6) +#define PCH_DEV_PSEI2C7 _PCH_DEV(PSE2, 0) +#define PCH_DEV_PSECAN0 _PCH_DEV(PSE2, 1) +#define PCH_DEV_PSECAN1 _PCH_DEV(PSE2, 2) +#define PCH_DEV_PSEQEP0 _PCH_DEV(PSE2, 3) +#define PCH_DEV_PSEQEP1 _PCH_DEV(PSE2, 4) +#define PCH_DEV_PSEQEP2 _PCH_DEV(PSE2, 5) +#define PCH_DEV_PSEQEP3 _PCH_DEV(PSE2, 6) + #define PCH_DEV_SLOT_SIO2 0x19 #define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) #define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) @@ -103,6 +151,22 @@ #define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) #define PCH_DEV_SDCARD _PCH_DEV(STORAGE, 1) +#define PCH_DEV_SLOT_PSE3 0x1b +#define PCH_DEVFN_PSEI2C0 _PCH_DEVFN(PSE3, 0) +#define PCH_DEVFN_PSEI2C1 _PCH_DEVFN(PSE3, 1) +#define PCH_DEVFN_PSEI2C2 _PCH_DEVFN(PSE3, 2) +#define PCH_DEVFN_PSEI2C3 _PCH_DEVFN(PSE3, 3) +#define PCH_DEVFN_PSEI2C4 _PCH_DEVFN(PSE3, 4) +#define PCH_DEVFN_PSEI2C5 _PCH_DEVFN(PSE3, 5) +#define PCH_DEVFN_PSEI2C6 _PCH_DEVFN(PSE3, 6) +#define PCH_DEV_PSEI2C0 _PCH_DEV(PSE3, 0) +#define PCH_DEV_PSEI2C1 _PCH_DEV(PSE3, 1) +#define PCH_DEV_PSEI2C2 _PCH_DEV(PSE3, 2) +#define PCH_DEV_PSEI2C3 _PCH_DEV(PSE3, 3) +#define PCH_DEV_PSEI2C4 _PCH_DEV(PSE3, 4) +#define PCH_DEV_PSEI2C5 _PCH_DEV(PSE3, 5) +#define PCH_DEV_PSEI2C6 _PCH_DEV(PSE3, 6) + #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) @@ -119,6 +183,24 @@ #define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) #define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_SLOT_PSE4 0x1d +#define PCH_DEVFN_PSEIPC _PCH_DEVFN(PSE4, 0) +#define PCH_DEVFN_PSEGBE0 _PCH_DEVFN(PSE4, 1) +#define PCH_DEVFN_PSEGBE1 _PCH_DEVFN(PSE4, 2) +#define PCH_DEVFN_PSEDMA0 _PCH_DEVFN(PSE4, 3) +#define PCH_DEVFN_PSEDMA1 _PCH_DEVFN(PSE4, 4) +#define PCH_DEVFN_PSEDMA2 _PCH_DEVFN(PSE4, 5) +#define PCH_DEVFN_PSEPWM _PCH_DEVFN(PSE4, 6) +#define PCH_DEVFN_PSEADC _PCH_DEVFN(PSE4, 7) +#define PCH_DEV_PSEIPC _PCH_DEV(PSE4, 0) +#define PCH_DEV_PSEGBE0 _PCH_DEV(PSE4, 1) +#define PCH_DEV_PSEGBE1 _PCH_DEV(PSE4, 2) +#define PCH_DEV_PSEDMA0 _PCH_DEV(PSE4, 3) +#define PCH_DEV_PSEDMA1 _PCH_DEV(PSE4, 4) +#define PCH_DEV_PSEDMA2 _PCH_DEV(PSE4, 5) +#define PCH_DEV_PSEPWM _PCH_DEV(PSE4, 6) +#define PCH_DEV_PSEADC _PCH_DEV(PSE4, 7) + #define PCH_DEV_SLOT_SIO3 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) #define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) From 60e9114c621095285314cc530016d7930b327f34 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 21 Oct 2021 02:03:04 +0200 Subject: [PATCH 282/320] include/device: ensure valid link/bus is passed to mp_cpu_bus_init When a chipset or mainboard devicetree doesn't have any LAPIC devices in its CPU cluster, not only the LAPIC device, but also the link/bus between the CPU cluster device and the LAPIC devices will be missing and the CPU cluster's dev->link_list will be NULL. This patch handles this case in the common code like commit 3c0ecd57c174b7391c66d22406effe18ce570cac (soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpus) and commit ba936ce5db819d5ecb34e83a998b2390ecbdc4b9 (soc/intel/denverton_ns: Ensure CPU device has a valid link) already did in the common Intel SoC and the Denverton code. With this change all CPUs and SoC that use the common mp_cpu_bus_init as init function in the CPU cluster's device operations struct won't require having at least one LAPIC device in the chipset or mainboard device tree. Signed-off-by: Felix Held Change-Id: Ib0d85de5cafb6390b8fbd512186899d6a815e972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58508 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/include/device/device.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/include/device/device.h b/src/include/device/device.h index 6bd6e0e5514..8610e0a4c67 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -228,6 +228,17 @@ void set_cpu_topology(struct device *cpu, unsigned int node, void mp_init_cpus(DEVTREE_CONST struct bus *cpu_bus); static inline void mp_cpu_bus_init(struct device *dev) { + /* + * When no LAPIC device is specified in the devietree inside the CPU cluster device, + * neither a LAPIC device nor the link/bus between the CPU cluster and the LAPIC device + * will be present in the static device tree and the link_list struct element of the + * CPU cluster device will be NULL. In this case add one link, so that the + * alloc_find_dev calls in init_bsp and allocate_cpu_devices will be able to add a + * LAPIC device for the BSP and the APs on this link/bus. + */ + if (!dev->link_list) + add_more_links(dev, 1); + mp_init_cpus(dev->link_list); } From af2da558763ef9ec7a888cdd56b6a536c8299c89 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 21 Oct 2021 02:13:36 +0200 Subject: [PATCH 283/320] soc/intel/denverton_ns: use mp_cpu_bus_init After adding the functionality to add a bus/link on the CPU cluster device in mp_cpu_bus_init if it is missing due to no LAPIC device being present in the devicetree below the CPU cluster device, we can use mp_cpu_bus_init as init function in cpu_bus_ops and implement mp_init_cpus. Signed-off-by: Felix Held Change-Id: I76aebeca1b3227cfd310b6c45f506c042b35ae04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58509 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/intel/denverton_ns/chip.c | 2 +- src/soc/intel/denverton_ns/cpu.c | 12 ++---------- src/soc/intel/denverton_ns/include/soc/cpu.h | 6 ------ src/soc/intel/denverton_ns/include/soc/ramstage.h | 1 - 4 files changed, 3 insertions(+), 18 deletions(-) diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 6a873530f60..c594a6f5f27 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -27,7 +27,7 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = denverton_init_cpus, + .init = mp_cpu_bus_init, #if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt = generate_cpu_entries, #endif diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index d8566927218..44cb297c6a8 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -286,17 +286,9 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void denverton_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { - /* - * Ensure there is at least one bus downstream to the CPU device. If not, then create a - * new link. This can occur if the mainboard does not add any APIC device in the device - * tree. - */ - if (!dev->link_list) - add_more_links(dev, 1); - /* Clear for take-off */ /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(dev->link_list, &mp_ops); + mp_init_with_smm(cpu_bus, &mp_ops); } diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h index f4b0d3c42a9..a7147647676 100644 --- a/src/soc/intel/denverton_ns/include/soc/cpu.h +++ b/src/soc/intel/denverton_ns/include/soc/cpu.h @@ -7,12 +7,6 @@ int get_cpu_count(void); -#ifndef __ASSEMBLER__ -#include - -void denverton_init_cpus(struct device *dev); -#endif - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ diff --git a/src/soc/intel/denverton_ns/include/soc/ramstage.h b/src/soc/intel/denverton_ns/include/soc/ramstage.h index 353d82daebc..c204849c11b 100644 --- a/src/soc/intel/denverton_ns/include/soc/ramstage.h +++ b/src/soc/intel/denverton_ns/include/soc/ramstage.h @@ -8,7 +8,6 @@ #include #include -void denverton_init_cpus(struct device *dev); void mainboard_silicon_init_params(FSPS_UPD *params); void southcluster_enable_dev(struct device *dev); void mainboard_add_dimm_info(struct memory_info *mem_info, int channel, From f9146ad569385698ecbf551eb2e022a4c4d80a84 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 21 Oct 2021 02:19:50 +0200 Subject: [PATCH 284/320] soc/amd/cezanne,picasso/chipset.cb: drop LAPIC device After adding code to handle the case of missing the link/bus on the CPU cluster device in mp_cpu_bus_init, there's no need to have the LAPIC device in the devicetree any more. TEST=Mandolin still boots successfully. Signed-off-by: Felix Held Change-Id: Icfc4fb61b373129f3bf4f4de09c38076a8f66733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58510 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/chipset.cb | 1 - src/soc/amd/picasso/chipset.cb | 1 - 2 files changed, 2 deletions(-) diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 2c685c3ad21..6ee79ebc9a2 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -1,6 +1,5 @@ chip soc/amd/cezanne device cpu_cluster 0 on - device lapic 0 on end end device domain 0 on device pci 00.0 alias gnb on end diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index 1730f8d95a8..dfa5418198a 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -2,7 +2,6 @@ chip soc/amd/picasso device cpu_cluster 0 on - device lapic 0 on end end device domain 0 on device pci 00.0 alias gnb on end From 308a5b9dd1a46299d87dc7215512c459d48d69b8 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Sat, 23 Oct 2021 21:44:02 +0800 Subject: [PATCH 285/320] arch/x86: fix a wrong variable in ioapic_set_max_vectors() The commit 04a40379b has a wrongly written variable, which sets an IOAPIC register to a wrong value and makes the Linux kernel unable to boot. Tested on HP EliteBook 2760p, the kernel boots after this patch. Change-Id: Ifda7bb61a431dbf9c2df2f738aa806dd6d8097b8 Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/58558 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Patrick Georgi Reviewed-by: Felix Held --- src/arch/x86/ioapic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index d299e6070de..d65637c662e 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -59,7 +59,7 @@ void ioapic_set_max_vectors(void *ioapic_base, int mre_count) count = mre_count - 1; reg &= ~(0xff << 16); reg |= count << 16; - io_apic_write(ioapic_base, 0x01, count); + io_apic_write(ioapic_base, 0x01, reg); } void ioapic_lock_max_vectors(void *ioapic_base) From 6c8008283cc54d324bde5be3d89e4234e858349b Mon Sep 17 00:00:00 2001 From: Timofey Komarov Date: Fri, 25 Jun 2021 12:07:32 +0300 Subject: [PATCH 286/320] util/inteltool: Add PCH IDs for 200 series chipsets Signed-off-by: Timofey Komarov Change-Id: Iadad5e79aef9da3fac627adc135525a5001a72b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55839 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- util/inteltool/gpio.c | 8 ++++++++ util/inteltool/gpio_groups.c | 8 ++++++++ util/inteltool/inteltool.c | 8 ++++++++ util/inteltool/inteltool.h | 9 +++++++++ util/inteltool/pcr.c | 8 ++++++++ 5 files changed, 41 insertions(+) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 22bad0e8fab..53164e1cf99 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1058,6 +1058,14 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_C621A_SUPER: case PCI_DEVICE_ID_INTEL_C627A_SUPER: case PCI_DEVICE_ID_INTEL_C629A_SUPER: + case PCI_DEVICE_ID_INTEL_H270: + case PCI_DEVICE_ID_INTEL_Z270: + case PCI_DEVICE_ID_INTEL_Q270: + case PCI_DEVICE_ID_INTEL_Q250: + case PCI_DEVICE_ID_INTEL_B250: + case PCI_DEVICE_ID_INTEL_Z370: + case PCI_DEVICE_ID_INTEL_H310C: + case PCI_DEVICE_ID_INTEL_X299: case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 0ff1c8629fb..7be1d5abf8c 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -102,6 +102,14 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s case PCI_DEVICE_ID_INTEL_QM170: case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_H270: + case PCI_DEVICE_ID_INTEL_Z270: + case PCI_DEVICE_ID_INTEL_Q270: + case PCI_DEVICE_ID_INTEL_Q250: + case PCI_DEVICE_ID_INTEL_B250: + case PCI_DEVICE_ID_INTEL_Z370: + case PCI_DEVICE_ID_INTEL_H310C: + case PCI_DEVICE_ID_INTEL_X299: *community_count = ARRAY_SIZE(sunrise_communities); return sunrise_communities; case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index f8c5e9161d5..0a8431a3295 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -295,6 +295,14 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C627_SUPER_2, "C627 Super SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C628_SUPER, "C628 Super SKU" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG, "Emmits Burg" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H270, "H270" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z270, "Z270" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q270, "Q270" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q250, "Q250" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B250, "B250" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z370, "Z370" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310C, "H310C" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X299, "X299" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 1ad12244517..40b739f4086 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -185,6 +185,15 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_EBG 0x1b81 +#define PCI_DEVICE_ID_INTEL_H270 0xa2c4 +#define PCI_DEVICE_ID_INTEL_Z270 0xa2c5 +#define PCI_DEVICE_ID_INTEL_Q270 0xa2c6 +#define PCI_DEVICE_ID_INTEL_Q250 0xa2c7 +#define PCI_DEVICE_ID_INTEL_B250 0xa2c8 +#define PCI_DEVICE_ID_INTEL_Z370 0xa2c9 +#define PCI_DEVICE_ID_INTEL_H310C 0xa2ca +#define PCI_DEVICE_ID_INTEL_X299 0xa2d2 + #define PCI_DEVICE_ID_INTEL_H310 0xa303 #define PCI_DEVICE_ID_INTEL_H370 0xa304 #define PCI_DEVICE_ID_INTEL_Z390 0xa305 diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index 307dc155c0c..921fdf04456 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -91,6 +91,14 @@ void pcr_init(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_HM175: case PCI_DEVICE_ID_INTEL_QM175: case PCI_DEVICE_ID_INTEL_CM238: + case PCI_DEVICE_ID_INTEL_H270: + case PCI_DEVICE_ID_INTEL_Z270: + case PCI_DEVICE_ID_INTEL_Q270: + case PCI_DEVICE_ID_INTEL_Q250: + case PCI_DEVICE_ID_INTEL_B250: + case PCI_DEVICE_ID_INTEL_Z370: + case PCI_DEVICE_ID_INTEL_H310C: + case PCI_DEVICE_ID_INTEL_X299: case PCI_DEVICE_ID_INTEL_C621: case PCI_DEVICE_ID_INTEL_C621A: case PCI_DEVICE_ID_INTEL_C622: From e1f392ea34404544b0a6f75d14d000cd74efc53d Mon Sep 17 00:00:00 2001 From: Ricardo Quesada Date: Wed, 22 Sep 2021 20:44:01 -0700 Subject: [PATCH 287/320] elogtool: add pytest for elogtool This CL adds a python test for elogtool. It tests the basic functionality of elogtool: list, clear and add. A future CL will include more complex tests. BUG=b:172210863 TEST=pytest elogtool_test.py Change-Id: If1241ad070d1c690c84f5ca61c0487ba27c2a287 Signed-off-by: Ricardo Quesada Reviewed-on: https://review.coreboot.org/c/coreboot/+/57869 Tested-by: build bot (Jenkins) Reviewed-by: Jack Rosenthal Reviewed-by: Patrick Georgi --- util/cbfstool/tests/README.md | 26 +++++ util/cbfstool/tests/conftest.py | 12 +++ util/cbfstool/tests/elogtool_test.py | 150 +++++++++++++++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 util/cbfstool/tests/README.md create mode 100644 util/cbfstool/tests/conftest.py create mode 100644 util/cbfstool/tests/elogtool_test.py diff --git a/util/cbfstool/tests/README.md b/util/cbfstool/tests/README.md new file mode 100644 index 00000000000..8ba69744cd0 --- /dev/null +++ b/util/cbfstool/tests/README.md @@ -0,0 +1,26 @@ +# CBFSTool tests + +To run the tests do `pytest name_of_the_file.py`. E.g: + +```shell +$ pytest elogtool_test.py +``` + +## Dependencies + +### Pytest + +Requires `pytest`. To install it do: + +```shell +$ pip install --user pytest +``` + +### Binaries + +Make sure that you have compiled the cbfstool binaries before running the test. e.g: + +```shell +$ cd $COREBOOT_SRC/util/cbfstool +$ make +``` diff --git a/util/cbfstool/tests/conftest.py b/util/cbfstool/tests/conftest.py new file mode 100644 index 00000000000..4e779245df6 --- /dev/null +++ b/util/cbfstool/tests/conftest.py @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: BSD-3-Clause + +import pathlib + + +def pytest_addoption(parser): + here = pathlib.Path(__file__).parent + parser.addoption( + "--elogtool-path", + type=pathlib.Path, + default=(here / ".." / "elogtool").resolve(), + ) diff --git a/util/cbfstool/tests/elogtool_test.py b/util/cbfstool/tests/elogtool_test.py new file mode 100644 index 00000000000..a798a4c16cd --- /dev/null +++ b/util/cbfstool/tests/elogtool_test.py @@ -0,0 +1,150 @@ +#!/usr/bin/python3 +# SPDX-License-Identifier: BSD-3-Clause + +import os +import pytest +import struct +import subprocess +from datetime import datetime +from datetime import timedelta + +# Defined in include/commonlib/bsd/elog.h +ELOG_TYPE_SYSTEM_BOOT = 0x17 +ELOG_TYPE_EOL = 0xff +ELOG_EVENT_HEADER_SIZE = 8 +ELOG_EVENT_CHECKSUM_SIZE = 1 + + +def convert_to_event(s: str) -> dict: + fields = s.split("|") + assert len(fields) == 3 or len(fields) == 4 + + return { + "index": int(fields[0]), + "timestamp": datetime.strptime(fields[1].strip(), "%Y-%m-%d %H:%M:%S"), + "desc": fields[2].strip(), + "data": fields[3].strip() if len(fields) == 4 else None, + } + + +def compare_event(expected: dict, got: dict) -> None: + # Ignore the keys that might be in "got", but not in "expected". + # In particular "timestamp" might not want to be tested. + for key in expected: + assert key in got.keys() + assert expected[key] == got[key] + + +@pytest.fixture(scope="session") +def elogtool_path(request): + exe = request.config.option.elogtool_path + assert os.path.exists(exe) + return exe + + +@pytest.fixture(scope="function") +def elogfile(tmp_path): + header_size = 8 + tail_size = 512 - header_size + + # Elog header: + # Magic (4 bytes) = "ELOG" + # Version (1 byte) = 1 + # Size (1 byte) = 8 + # Reserved (2 bytes) = 0xffff + header = struct.pack("4sBBH", bytes("ELOG", "utf-8"), 1, 8, 0xffff) + + # Fill the tail with EOL events. + tail = bytes([ELOG_TYPE_EOL] * tail_size) + buf = header + tail + + buf_path = tmp_path / "elog_empty.bin" + with buf_path.open("wb") as fd: + fd.write(buf) + fd.flush() + return str(buf_path) + assert False + + +def elog_list(elogtool_path: str, path: str) -> list: + output = subprocess.run([elogtool_path, 'list', '-f', path], + capture_output=True, check=True) + log = output.stdout.decode("utf-8").strip() + + lines = log.splitlines() + lines = [convert_to_event(s.strip()) for s in lines] + return lines + + +def elog_clear(elogtool_path: str, path: str) -> None: + subprocess.run([elogtool_path, 'clear', '-f', path], check=True) + + +def elog_add(elogtool_path: str, path: str, typ: int, data: bytearray) -> None: + subprocess.run([elogtool_path, 'add', '-f', path, + hex(typ), data.hex()], check=True) + + +def test_list_empty(elogtool_path, elogfile): + events = elog_list(elogtool_path, elogfile) + assert len(events) == 0 + + +def test_clear_empty(elogtool_path, elogfile): + elog_clear(elogtool_path, elogfile) + events = elog_list(elogtool_path, elogfile) + + # Must have one event, the "Log area cleared" event. + assert len(events) == 1 + + expected = {"index": 0, + "desc": "Log area cleared", + # "0", since it was an empty elog buffer. No bytes were cleared. + "data": "0"} + compare_event(expected, events[0]) + + +def test_clear_not_empty(elogtool_path, elogfile): + tot_events = 10 + data_size = 4 + event_size = ELOG_EVENT_HEADER_SIZE + data_size + ELOG_EVENT_CHECKSUM_SIZE + written_bytes = tot_events * event_size + + for i in range(tot_events): + # Adding boot_count for completeness. But it is ignored in this test. + boot_count = i.to_bytes(data_size, "little") + elog_add(elogtool_path, elogfile, ELOG_TYPE_SYSTEM_BOOT, boot_count) + elog_clear(elogtool_path, elogfile) + events = elog_list(elogtool_path, elogfile) + + # Must have one event, the "Log area cleared" event. + assert len(events) == 1 + + expected = {"index": 0, + "desc": "Log area cleared", + "data": str(written_bytes) + } + compare_event(expected, events[0]) + + +def test_add_single_event(elogtool_path, elogfile): + # "before - one second" is needed because datetime.now() fills the + # microsecond variable. But eventlog doesn't use it, and has it hardcoded to + # zero. + before = datetime.now() - timedelta(seconds=1) + boot_count = 128 + elog_add(elogtool_path, elogfile, ELOG_TYPE_SYSTEM_BOOT, + boot_count.to_bytes(4, "little")) + after = datetime.now() + + events = elog_list(elogtool_path, elogfile) + assert len(events) == 1 + + ev = events[0] + expected = {"index": 0, + "desc": "System boot", + "data": str(boot_count) + } + compare_event(expected, ev) + + assert before < ev["timestamp"] < after From 299649a31c7bccf5b7102b37e8f8bf0f151280f7 Mon Sep 17 00:00:00 2001 From: Mac Chiang Date: Thu, 21 Oct 2021 12:19:01 +0800 Subject: [PATCH 288/320] mb/google/brya/variants/gimble: Enable Bluetooth offload support Enable CnviBtAudioOffload UPD BUG=b:199180746 TEST=emerge-byra coreboot Signed-off-by: Mac Chiang Change-Id: Ic507b1d0f7c2f38de8d24247cd677b897a7463f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58514 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/gimble/variant.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/brya/variants/gimble/variant.c b/src/mainboard/google/brya/variants/gimble/variant.c index 6a79780f6e8..96ccf88ae7b 100644 --- a/src/mainboard/google/brya/variants/gimble/variant.c +++ b/src/mainboard/google/brya/variants/gimble/variant.c @@ -1,8 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include +#include const char *get_wifi_sar_cbfs_filename(void) { return "wifi_sar_0.hex"; } + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, + MAX98390_ALC5682I_I2S_SSP1)); +} From 92ab611c7055dc33aca822e098e19baa84eb975a Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Mon, 11 Oct 2021 15:27:12 +0200 Subject: [PATCH 289/320] drivers/pc80/tpm: Use stopwatch for timeout-loops MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are manual timeout-loops which use a fixed value and udelay(). In all cases there is a debug printk() inside this loop which, when enabled, takes way longer than the counted microsecond delay. This leads to the result that e.g. a 1 second delay takes nearly an eternity if the debug messages are enabled due to the longer function execution time. This patch uses the stopwatch scheme for the timeout-loops which still makes sure that the timeout period is maintained while it takes longer function calls like printk() into account. In order to keep the minimum delay between two register accesses on the TPM keep the udelay(1)-call. TEST=Enable TPM debug messages on a board where the TPM hits a timeout by failure and make sure that the debug messages occur in the log just in the timeout period. It still works as expected if the debug messages are disabled. Change-Id: I8fd261c9d60a9a60509c847dbc4983bc05f41d48 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58240 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel Reviewed-by: Angel Pons --- src/drivers/pc80/tpm/tis.c | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 2b29acfaa90..c209e5a39e3 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "chip.h" #define PREFIX "lpc_tpm: " @@ -84,7 +85,7 @@ #define TPM_DRIVER_ERR (~0) /* 1 second is plenty for anything TPM does.*/ -#define MAX_DELAY_US (1000 * 1000) +#define MAX_DELAY_US USECS_PER_SEC /* * Structures defined below allow creating descriptions of TPM vendor/device @@ -238,7 +239,7 @@ static inline u32 tpm_read_int_polarity(int locality) /* * tis_wait_sts() * - * Wait for at least a second for a status to change its state to match the + * Wait for at most a second for a status to change its state to match the * expected state. Normally the transition happens within microseconds. * * @locality - locality @@ -249,14 +250,15 @@ static inline u32 tpm_read_int_polarity(int locality) */ static int tis_wait_sts(int locality, u8 mask, u8 expected) { - u32 time_us = MAX_DELAY_US; - while (time_us > 0) { + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, MAX_DELAY_US); + do { u8 value = tpm_read_status(locality); if ((value & mask) == expected) return 0; - udelay(1); /* 1 us */ - time_us--; - } + udelay(1); + } while (!stopwatch_expired(&sw)); return TPM_TIMEOUT_ERR; } @@ -291,7 +293,7 @@ static inline int tis_expect_data(int locality) /* * tis_wait_access() * - * Wait for at least a second for a access to change its state to match the + * Wait for at most a second for a access to change its state to match the * expected state. Normally the transition happens within microseconds. * * @locality - locality @@ -302,14 +304,15 @@ static inline int tis_expect_data(int locality) */ static int tis_wait_access(int locality, u8 mask, u8 expected) { - u32 time_us = MAX_DELAY_US; - while (time_us > 0) { + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, MAX_DELAY_US); + do { u8 value = tpm_read_access(locality); if ((value & mask) == expected) return 0; - udelay(1); /* 1 us */ - time_us--; - } + udelay(1); + } while (!stopwatch_expired(&sw)); return TPM_TIMEOUT_ERR; } @@ -440,7 +443,6 @@ static u32 tis_senddata(const u8 *const data, u32 len) { u32 offset = 0; u16 burst = 0; - u32 max_cycles = 0; u8 locality = 0; if (tis_wait_ready(locality)) { @@ -452,10 +454,12 @@ static u32 tis_senddata(const u8 *const data, u32 len) while (1) { unsigned int count; + struct stopwatch sw; /* Wait till the device is ready to accept more data. */ + stopwatch_init_usecs_expire(&sw, MAX_DELAY_US); while (!burst) { - if (max_cycles++ == MAX_DELAY_US) { + if (stopwatch_expired(&sw)) { printf("%s:%d failed to feed %d bytes of %d\n", __FILE__, __LINE__, len - offset, len); return TPM_DRIVER_ERR; @@ -464,8 +468,6 @@ static u32 tis_senddata(const u8 *const data, u32 len) burst = tpm_read_burst_count(locality); } - max_cycles = 0; - /* * Calculate number of bytes the TPM is ready to accept in one * shot. From 66b2f2015688033a0d46d8fcc5d3f08aea1fb8b2 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 12 Oct 2021 15:14:22 +0200 Subject: [PATCH 290/320] drivers/pc80/tpm: Use '%u' as printf formatter for unsigned variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use %u instead of %d for printing unsigned variables. Change-Id: I0f4bf7b80dfbde0802af8ad96fd553cb75d60e6e Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58245 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons --- src/drivers/pc80/tpm/tis.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index c209e5a39e3..455bcf94192 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -460,7 +460,7 @@ static u32 tis_senddata(const u8 *const data, u32 len) stopwatch_init_usecs_expire(&sw, MAX_DELAY_US); while (!burst) { if (stopwatch_expired(&sw)) { - printf("%s:%d failed to feed %d bytes of %d\n", + printf("%s:%d failed to feed %u bytes of %u\n", __FILE__, __LINE__, len - offset, len); return TPM_DRIVER_ERR; } @@ -572,7 +572,7 @@ static u32 tis_readresponse(u8 *buffer, size_t *len) if ((expected_count < offset) || (expected_count > *len)) { - printf("%s:%d bad response size %d\n", + printf("%s:%d bad response size %u\n", __FILE__, __LINE__, expected_count); return TPM_DRIVER_ERR; @@ -602,7 +602,7 @@ static u32 tis_readresponse(u8 *buffer, size_t *len) /* * Make sure we indeed read all there was. */ if (tis_has_valid_data(locality)) { - printf("%s:%d wrong receive status: %x %d bytes left\n", + printf("%s:%d wrong receive status: %x %u bytes left\n", __FILE__, __LINE__, tpm_read_status(locality), tpm_read_burst_count(locality)); return TPM_DRIVER_ERR; @@ -649,7 +649,7 @@ int tis_open(void) /* did we get a lock? */ if (tis_wait_received_access(locality)) { - printf("%s:%d - failed to lock locality %d\n", + printf("%s:%d - failed to lock locality %u\n", __FILE__, __LINE__, locality); return TPM_DRIVER_ERR; } @@ -676,7 +676,7 @@ int tis_close(void) if (tis_has_access(locality)) { tis_drop_access(locality); if (tis_wait_dropped_access(locality)) { - printf("%s:%d - failed to release locality %d\n", + printf("%s:%d - failed to release locality %u\n", __FILE__, __LINE__, locality); return TPM_DRIVER_ERR; } From ac1bba8e34ea7b2c9112b19c4d7e63e74949a899 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 25 Oct 2021 11:23:54 +0530 Subject: [PATCH 291/320] soc/intel/common: Skip CSE post hook when CSE is disabled This patch fixes regression introduced by commit bee4bb5f0 (soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM) FAFT test case fail when doing `firmware_DevMode` test. If CSE is already hidden then accessing CSE registers would be wrong and will receive junk, hence, return as CSE is already disabled. BUG=b:203061531 TEST=Brya system can boot to OS with recovery mode. Change-Id: I2046eb19716c397a066c2c41e1b027a256bd6cf9 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/58513 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/cse_eop.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 1f544694b62..e47eb510fb2 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -175,6 +175,15 @@ static void handle_cse_eop_result(enum cse_eop_result result) static void set_cse_end_of_post(void *unused) { + /* + * If CSE is already hidden then accessing CSE registers would be wrong and will + * receive junk, hence, return as CSE is already disabled. + */ + if (!is_cse_enabled()) { + printk(BIOS_DEBUG, "CSE is disabled, cannot send End-of-Post (EOP) message\n"); + return; + } + set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); timestamp_add_now(TS_ME_BEFORE_END_OF_POST); From 2d4986c1683ca4a77a93a5ba63e481f7c5862693 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 22 Oct 2021 22:07:43 +0200 Subject: [PATCH 292/320] cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCs All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/cpu/amd/agesa/family14/Makefile.inc | 1 - src/cpu/amd/agesa/family15tn/Makefile.inc | 1 - src/cpu/amd/agesa/family16kb/Makefile.inc | 1 - src/cpu/amd/pi/00730F01/Makefile.inc | 1 - src/cpu/intel/haswell/Makefile.inc | 1 - src/cpu/intel/model_2065x/Makefile.inc | 1 - src/cpu/intel/model_206ax/Makefile.inc | 1 - src/cpu/intel/slot_1/Makefile.inc | 1 - src/cpu/intel/socket_441/Makefile.inc | 1 - src/cpu/intel/socket_BGA956/Makefile.inc | 1 - src/cpu/intel/socket_FCBGA559/Makefile.inc | 1 - src/cpu/intel/socket_LGA775/Makefile.inc | 1 - src/cpu/intel/socket_m/Makefile.inc | 1 - src/cpu/intel/socket_mPGA604/Makefile.inc | 1 - src/cpu/intel/socket_p/Makefile.inc | 1 - src/cpu/qemu-x86/Makefile.inc | 1 - src/cpu/x86/Makefile.inc | 1 + src/soc/amd/cezanne/Makefile.inc | 1 - src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/stoneyridge/Makefile.inc | 1 - src/soc/example/min86/Makefile.inc | 2 -- src/soc/intel/alderlake/Makefile.inc | 1 - src/soc/intel/apollolake/Makefile.inc | 1 - src/soc/intel/baytrail/Makefile.inc | 1 - src/soc/intel/braswell/Makefile.inc | 1 - src/soc/intel/cannonlake/Makefile.inc | 1 - src/soc/intel/denverton_ns/Makefile.inc | 1 - src/soc/intel/elkhartlake/Makefile.inc | 1 - src/soc/intel/icelake/Makefile.inc | 1 - src/soc/intel/jasperlake/Makefile.inc | 1 - src/soc/intel/quark/Makefile.inc | 1 - src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/tigerlake/Makefile.inc | 1 - src/soc/intel/xeon_sp/cpx/Makefile.inc | 1 - src/soc/intel/xeon_sp/skx/Makefile.inc | 1 - 35 files changed, 1 insertion(+), 35 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index c9074d87ac5..14971009d9a 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -9,5 +9,4 @@ ramstage-y += model_14_init.c subdirs-y += ../../mtrr subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 42e1c2c7b2b..af06dd17a04 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -12,5 +12,4 @@ subdirs-y += ../../mtrr subdirs-y += ../../smm subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 05e61ea36de..f466bbcff73 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -9,5 +9,4 @@ ramstage-y += model_16_init.c subdirs-y += ../../mtrr subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 446be5d14f2..9f410824a49 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -10,5 +10,4 @@ ramstage-y += update_microcode.c subdirs-y += ../../mtrr subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index ebdcc91b963..a46effe8742 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += bootblock.c postcar-y += ../car/non-evict/exit_car.S -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 85602deca43..544755a1cb2 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -1,7 +1,6 @@ ramstage-y += model_2065x_init.c subdirs-y += ../../x86/name subdirs-y += ../../x86/cache -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 2b28eb4fbcc..1217f3383cd 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -2,7 +2,6 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name subdirs-y += ../smm/gen1 -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index df7a0bd4f8d..28df10ea239 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -7,7 +7,6 @@ subdirs-y += ../model_65x subdirs-y += ../model_67x subdirs-y += ../model_68x subdirs-y += ../model_6bx -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index 47fa296f0ef..dfed16c7177 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_106cx -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index bdf90a97bd7..a39798449b7 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_1067x -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 3a0db369070..64d0c36507c 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_106cx -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index f684bfbd101..a16f670fca3 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../model_f4x #subdirs-y += ../model_f6x #subdirs-y += ../model_1066x subdirs-y += ../model_1067x -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 21923286db2..2bcd580abc2 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_6ex subdirs-y += ../model_6fx -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 345e4e0746b..2bca94ea2d6 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_f2x -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 2565493a47b..8588c371358 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_6fx subdirs-y += ../model_1067x -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 1b1b60343ea..42e18060b2b 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -7,5 +7,4 @@ romstage-y += ../intel/car/romstage.c ramstage-y += qemu.c -subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 1ad04b53161..016b6014114 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,3 +1,4 @@ +subdirs-y += mtrr subdirs-y += pae subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm subdirs-$(CONFIG_UDELAY_TSC) += tsc diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 918aa814475..5e6b2570295 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d873079b2c7..e95a1735654 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/cache -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index fb6e20488b6..46e5b9d3838 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/cache -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/pae bootblock-y += uart.c diff --git a/src/soc/example/min86/Makefile.inc b/src/soc/example/min86/Makefile.inc index 9c1c7f0331c..c3cc195af4b 100644 --- a/src/soc/example/min86/Makefile.inc +++ b/src/soc/example/min86/Makefile.inc @@ -10,6 +10,4 @@ romstage-y += romstage.c ramstage-y += chip.c ramstage-y += timer.c -subdirs-y += ../../../cpu/x86/mtrr - endif diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 728c58c9672..bd554b995a9 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 49707da1a6e..6ef79fcdc3a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 5500da9e445..33aaba0d8fd 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 0080d72c24d..07bd26fe265 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 49e9f0c707d..bc15e1f0254 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/intel/common bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index c222920d734..d49be2410fb 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y) subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index e3cf119ba51..c32ba1f245d 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index a53a225b128..847418de1c9 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index f450257b547..276f3c0cd54 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index c0b213eb601..8b0c8bf88bd 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/mtrr bootblock-y += bootblock/esram_init.S bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index c191aac607f..775bec1ce62 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr bootblock-y += bootblock/bootblock.c bootblock-y += i2c.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index bce36538ee1..9e5a3c82317 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 2df370ae2bb..ef38ce8acc5 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic -subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c ddr.c diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 5840580334a..eafd8002297 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic -subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/cache postcar-y += soc_util.c From f77d78dcfb664bc23649bcd9bc39b4b37ca1af52 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 22 Oct 2021 22:12:39 +0200 Subject: [PATCH 293/320] cpu,soc/amd/*/Makefile: don't add cpu/x86/pae a second time Since cpu/x86/Makefile.inc already adds the pae sub-directory, there is no need to include it in the Makefile of a CPU or SoC, so remove it from those Makefiles. Signed-off-by: Felix Held Change-Id: I78368f7eb880fb64f511a2fa8c8acde222d0dca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58546 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/amd/agesa/family14/Makefile.inc | 1 - src/cpu/amd/agesa/family15tn/Makefile.inc | 1 - src/cpu/amd/agesa/family16kb/Makefile.inc | 1 - src/cpu/amd/pi/00730F01/Makefile.inc | 1 - src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/stoneyridge/Makefile.inc | 1 - 6 files changed, 6 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 14971009d9a..aeecbe48528 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -9,4 +9,3 @@ ramstage-y += model_14_init.c subdirs-y += ../../mtrr subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index af06dd17a04..03aadd3d38d 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -12,4 +12,3 @@ subdirs-y += ../../mtrr subdirs-y += ../../smm subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index f466bbcff73..7eb39e3394a 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -9,4 +9,3 @@ ramstage-y += model_16_init.c subdirs-y += ../../mtrr subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 9f410824a49..2e9d82bddbb 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -10,4 +10,3 @@ ramstage-y += update_microcode.c subdirs-y += ../../mtrr subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/pae diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e95a1735654..5e0c318eb8e 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/cache -subdirs-y += ../../../cpu/x86/pae subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 46e5b9d3838..7b0d709962e 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/cache -subdirs-y += ../../../cpu/x86/pae bootblock-y += uart.c bootblock-y += BiosCallOuts.c From 4690b0370496db827a50638c27710fca364b7c73 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 22 Oct 2021 04:07:17 +0200 Subject: [PATCH 294/320] soc/amd/common/block/lpc/Makefile: simplify handling spi_dma.c Use the verstage_x86 class for the spi_dma.c target instead of using the verstage class and guarding it with !VBOOT_STARTS_BEFORE_BOOTBLOCK. Signed-off-by: Felix Held Change-Id: I9b8cafd1ef17df8c485f6594bc0928cea88e436b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58544 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/lpc/Makefile.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc index b1fed7eb01d..040517d947b 100644 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -13,9 +13,7 @@ endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) bootblock-y += spi_dma.c -ifneq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -verstage-y += spi_dma.c -endif +verstage_x86-y += spi_dma.c romstage-y += spi_dma.c ramstage-y += spi_dma.c smm-y += spi_dma.c From f8e4ba0085cb8f0d54236825abe0487c733bb25d Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Thu, 21 Oct 2021 20:14:09 +0530 Subject: [PATCH 295/320] soc/qualcomm/sc7280: define the aop symbols BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka Change-Id: I62044f6fcb301c0ca35c42598f998913f9b94b95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58528 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/soc/qualcomm/sc7280/memlayout.ld | 5 +++-- src/soc/qualcomm/sc7280/soc.c | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 6398dbabeae..620e5b55db9 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -20,7 +20,8 @@ SECTIONS REGION(shrm, 0x09060000, 64K , 4K) AOPSRAM_START(0x0B000000) - REGION(aop, 0x0B000000, 0x100000, 4096) + REGION(aop_code_ram, 0x0B000000, 0x80000, 4096) + REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4096) AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) @@ -51,7 +52,7 @@ SECTIONS DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ - REGION(dram_aop, 0x80800000, 0x040000, 0x1000) + REGION(dram_aop, 0x80800000, 0x080000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) BL31(0x80B00000, 1M) REGION(dram_wlan, 0x80C00000, 0xC00000, 0x1000) diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index c0fa32f691d..96a4d5a2b23 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -16,6 +15,8 @@ static void soc_read_resources(struct device *dev) REGION_SIZE(dram_wlan) / KiB); reserved_ram_resource(dev, 3, (uintptr_t)_dram_wpss / KiB, REGION_SIZE(dram_wpss) / KiB); + reserved_ram_resource(dev, 4, (uintptr_t)_dram_aop / KiB, + REGION_SIZE(dram_aop) / KiB); } static void soc_init(struct device *dev) From 64f7eaafa7ca8e5908e6e1dd1be6f6df6cae06d9 Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Fri, 15 Oct 2021 23:02:41 +0530 Subject: [PATCH 296/320] soc/qualcomm: Commonize AOP firmware support Move AOP firmware support from qualcomm/sc7180 into qualcomm/common BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec Signed-off-by: Ravi Kumar Bokka Reviewed-on: https://review.coreboot.org/c/coreboot/+/49767 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/soc/qualcomm/{sc7180 => common}/aop_load_reset.c | 11 ++++------- src/soc/qualcomm/common/include/soc/aop_common.h | 8 ++++++++ src/soc/qualcomm/common/mmu.c | 8 ++++++-- src/soc/qualcomm/sc7180/Makefile.inc | 2 +- src/soc/qualcomm/sc7180/include/soc/aop.h | 8 -------- src/soc/qualcomm/sc7180/mmu.c | 6 ------ src/soc/qualcomm/sc7180/soc.c | 2 +- 7 files changed, 20 insertions(+), 25 deletions(-) rename src/soc/qualcomm/{sc7180 => common}/aop_load_reset.c (60%) create mode 100644 src/soc/qualcomm/common/include/soc/aop_common.h delete mode 100644 src/soc/qualcomm/sc7180/include/soc/aop.h diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/common/aop_load_reset.c similarity index 60% rename from src/soc/qualcomm/sc7180/aop_load_reset.c rename to src/soc/qualcomm/common/aop_load_reset.c index d48a422991f..1b3a1d50ab1 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/common/aop_load_reset.c @@ -1,23 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include #include -#include +#include #include void aop_fw_load_reset(void) { - bool aop_fw_entry; - struct prog aop_fw_prog = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); - aop_fw_entry = selfload(&aop_fw_prog); - if (!aop_fw_entry) + if (!selfload(&aop_fw_prog)) die("SOC image: AOP load failed"); clock_reset_aop(); - printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); + printk(BIOS_DEBUG, "SOC:AOP brought out of reset.\n"); } diff --git a/src/soc/qualcomm/common/include/soc/aop_common.h b/src/soc/qualcomm/common/include/soc/aop_common.h new file mode 100644 index 00000000000..5b0de4eb678 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/aop_common.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_COMMON_AOP_H__ +#define _SOC_QUALCOMM_COMMON_AOP_H__ + +void aop_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_COMMON_AOP_H__ diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c index ba1173edf9b..0f12555a7f4 100644 --- a/src/soc/qualcomm/common/mmu.c +++ b/src/soc/qualcomm/common/mmu.c @@ -3,9 +3,9 @@ #include #include #include +#include __weak bool soc_modem_carve_out(void **start, void **end) { return false; } -__weak void soc_mmu_dram_config_post_dram_init(void) { /* no-op */ } void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size) { @@ -18,5 +18,9 @@ void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size) mmu_config_range(ddr_base, start - ddr_base, CACHED_RAM); mmu_config_range(end, ddr_base + ddr_size - end, CACHED_RAM); } - soc_mmu_dram_config_post_dram_init(); + + mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), + CACHED_RAM); + mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), + CACHED_RAM); } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 7c393b3fac5..df565b4c0ed 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -36,7 +36,7 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ ramstage-y += soc.c ramstage-y += carve_out.c -ramstage-y += aop_load_reset.c +ramstage-y += ../common/aop_load_reset.c ramstage-y += usb.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h deleted file mode 100644 index bdf3f83cbdc..00000000000 --- a/src/soc/qualcomm/sc7180/include/soc/aop.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_QUALCOMM_SC7180_AOP_H__ -#define _SOC_QUALCOMM_SC7180_AOP_H__ - -void aop_fw_load_reset(void); - -#endif // _SOC_QUALCOMM_SC7180_AOP_H__ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index 03e62e507e2..6aff9a99f4b 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -19,9 +19,3 @@ void sc7180_mmu_init(void) mmu_enable(); } - -void soc_mmu_dram_config_post_dram_init(void) -{ - mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), CACHED_RAM); - mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), CACHED_RAM); -} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index e7efff45a37..af274d20131 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include static void soc_read_resources(struct device *dev) { From 5fa09cb17f4c99c5736c63f71f812dd6fe62e846 Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Thu, 21 Oct 2021 20:18:12 +0530 Subject: [PATCH 297/320] sc7280: Add AOP FW download support AOP firmware support from sc7280. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka Change-Id: Ib7027cdf78a9cdcccc8cfff7eef3cc540fb4093e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58371 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/soc/qualcomm/sc7280/Makefile.inc | 9 +++++++++ src/soc/qualcomm/sc7280/soc.c | 2 ++ 2 files changed, 11 insertions(+) diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 9c02826ae0e..37ed21eaa3d 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -36,6 +36,7 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ramstage-y += soc.c ramstage-y += cbmem.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c +ramstage-y += ../common/aop_load_reset.c ################################################################################ @@ -102,6 +103,14 @@ $(I2C_FW_CBFS)-type := raw $(I2C_FW_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) cbfs-files-y += $(I2C_FW_CBFS) +################################################################################ +AOP_FILE := $(SC7280_BLOB)/aop/aop.mbn +AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop +$(AOP_CBFS)-file := $(AOP_FILE) +$(AOP_CBFS)-type := payload +$(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(AOP_CBFS) + ################################################################################ SHRM_FILE := $(SC7280_BLOB)/shrm/shrm.elf SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index 96a4d5a2b23..ff2b7cc6504 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -4,6 +4,7 @@ #include #include #include +#include static void soc_read_resources(struct device *dev) { @@ -21,6 +22,7 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { + aop_fw_load_reset(); } static struct device_operations soc_ops = { From 1a950d6466473e0f5047cff33929c7da1b3f6787 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Mon, 18 Oct 2021 19:45:37 +0800 Subject: [PATCH 298/320] mb/google/guybrush/var/nipperkin: override dxio to turn off WLAN ASPM L1.2/L1.2 turn off WLAN ASPM L1.1/L1.2 as a short-term w/a for WLAN AP probe failure. BUG=b:198258604 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage AP is able to be probed by wlan module Signed-off-by: Kevin Chiu Change-Id: Ic7be523626b0ff6e4b1c66ba6af13b15061ef4cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58417 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/google/guybrush/port_descriptors.c | 13 ++++++------- .../variants/baseboard/include/baseboard/variants.h | 10 ++++++++++ .../google/guybrush/variants/nipperkin/Makefile.inc | 3 +++ .../google/guybrush/variants/nipperkin/variant.c | 10 ++++++++++ 4 files changed, 29 insertions(+), 7 deletions(-) create mode 100644 src/mainboard/google/guybrush/variants/nipperkin/variant.c diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index abb854e44c6..cf8153412a0 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -7,13 +7,6 @@ #include #include -enum dxio_port_id { - WLAN, - SD, - WWAN_NVME, - NVME -}; - /* All PCIe Resets are handled in coreboot */ static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { { /* WLAN */ @@ -126,6 +119,10 @@ static const fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { } }; +void __weak variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) +{ +} + void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) @@ -138,6 +135,8 @@ void mainboard_get_dxio_ddi_descriptors( if (variant_has_pcie_wwan()) guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18; + variant_update_dxio_descriptors(guybrush_czn_dxio_descriptors); + *dxio_descs = guybrush_czn_dxio_descriptors; *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index aab905bad98..eabce1f4cdc 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -5,6 +5,7 @@ #include #include +#include #define WLAN_DEVFN PCIE_GPP_2_0_DEVFN #define SD_DEVFN PCIE_GPP_2_1_DEVFN @@ -48,4 +49,13 @@ bool variant_has_fpmcu(void); bool variant_has_pcie_wwan(void); +void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); + +enum dxio_port_id { + WLAN, + SD, + WWAN_NVME, + NVME +}; + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc index f7c97bafbf4..03c9c8bac46 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc @@ -3,5 +3,8 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +bootblock-y += variant.c +romstage-y += variant.c +ramstage-y += variant.c subdirs-y += ./memory diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c new file mode 100644 index 00000000000..3315fa0249b --- /dev/null +++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) +{ + dxio_descriptors[WLAN].link_aspm_L1_1 = false; + dxio_descriptors[WLAN].link_aspm_L1_2 = false; +} From 9a7fbbc98e8610a0a5314470edd8d5dafe676a06 Mon Sep 17 00:00:00 2001 From: MAULIK V VAGHELA Date: Wed, 13 Oct 2021 11:52:17 +0530 Subject: [PATCH 299/320] soc/intel/adl: Skip sending MBP HOB to save boot time MBP Hob is being generated by FSP after getting data from ME. coreboot does not consume this HOB and FSP provides an option for bootloader to skip generation of MBP HOB. This will help in saving ~14 ms of boot time. Here is the data from Brya P1 Board: Before: 955 returning from FspSiliconInit 879,432 (99,156) After: 955 returning from FspSiliconInit 1,177,513 (84,506) BUG=b:188577893 BRANCH=None TEST=No functional impact on Brya system and boot time is reduced with this patch. Change-Id: Ibb64e4d0f4ae7212defb6704b05a78e754f75cd7 Signed-off-by: MAULIK V VAGHELA Reviewed-on: https://review.coreboot.org/c/coreboot/+/58289 Reviewed-by: Subrata Banik Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/romstage/fsp_params.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 698cff67ce3..be71a02c0a6 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -203,6 +203,9 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, /* Skip GPIO configuration from FSP */ m_cfg->GpioOverride = 0x1; + + /* Skip generation of MBP HOB from FSP. coreboot doesn't consume it */ + m_cfg->SkipMbpHob = 1; } static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, From cb2fd20c7f5cf43776dddfe2dbafeb19475e81f3 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 9 Jun 2021 19:27:06 +0530 Subject: [PATCH 300/320] soc/intel/common: Add HECI Reset flow in the CSE driver This change is required as part of HECI Interface initialization in order to put the host and CSE into a known good state for communication. Please refer ME BIOS specification for more details. The change adds HECI interface reset flow in the CSE driver. It enables coreboot to send HECI commands before DRAM Init. BUG=b:175516533 TEST=Run 50 cold reset cycles on Brya Signed-off-by: Sridhar Siricilla Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba Reviewed-on: https://review.coreboot.org/c/coreboot/+/55363 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/cse.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index e41e3375501..68a41e869cf 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -111,6 +111,9 @@ void heci_init(uintptr_t tempbar) /* Enable Bus Master and MMIO Space */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + /* Trigger HECI Reset and make Host ready for communication with CSE */ + heci_reset(); } static uint32_t read_bar(pci_devfn_t dev, uint32_t offset) From 3a79633920850cb1d44f515a9cfe8372c6c01341 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 22 Oct 2021 22:38:21 +0200 Subject: [PATCH 301/320] soc/*/Makefile: don't add cpu/x86/cache No SoC uses the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held Suggested-by: Angel Pons Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/stoneyridge/Makefile.inc | 1 - src/soc/intel/apollolake/Makefile.inc | 1 - src/soc/intel/denverton_ns/Makefile.inc | 1 - src/soc/intel/xeon_sp/skx/Makefile.inc | 1 - 5 files changed, 5 deletions(-) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 5e0c318eb8e..e3eab29e35d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/cache subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 7b0d709962e..4a126d8e2d6 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/cache bootblock-y += uart.c bootblock-y += BiosCallOuts.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 6ef79fcdc3a..3a723dcbb31 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-y += ../common/block/cpu/pm_timer_emulation.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index d49be2410fb..3fdff0d1973 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y) subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-y += spi.c diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index eafd8002297..b0714d4ef76 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -5,7 +5,6 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic -subdirs-y += ../../../../cpu/x86/cache postcar-y += soc_util.c From 8023eabde1dd3e830ee9a34437591070e60a1a75 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 22 Oct 2021 23:41:33 +0200 Subject: [PATCH 302/320] cpu/amd,intel/*/Makefile: don't add cpu/x86/cache Some CPUs don't use the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held Suggested-by: Angel Pons Change-Id: Ia44c7b150cd12d76e463903966f67d86750cbdd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58548 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/cpu/amd/pi/00730F01/Makefile.inc | 1 - src/cpu/intel/haswell/Makefile.inc | 1 - src/cpu/intel/model_2065x/Makefile.inc | 1 - src/cpu/intel/model_206ax/Makefile.inc | 1 - 4 files changed, 4 deletions(-) diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 2e9d82bddbb..f2263d042e8 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -9,4 +9,3 @@ ramstage-y += update_microcode.c subdirs-y += ../../mtrr subdirs-y += ../../../x86/lapic -subdirs-y += ../../../x86/cache diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index a46effe8742..ec0ceea06d2 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += bootblock.c postcar-y += ../car/non-evict/exit_car.S subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode subdirs-y += ../turbo diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 544755a1cb2..fb85bdf4d55 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -1,6 +1,5 @@ ramstage-y += model_2065x_init.c subdirs-y += ../../x86/name -subdirs-y += ../../x86/cache subdirs-y += ../../x86/lapic subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 1217f3383cd..fec509c193e 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += ../../x86/name subdirs-y += ../smm/gen1 subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode subdirs-y += ../turbo From e2783daa84e16873c4ca2a4aa99e08420d7bd287 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 22 Oct 2021 23:54:53 +0200 Subject: [PATCH 303/320] cpu/x86: Introduce `CPU_X86_CACHE_HELPER` There's no need for relative paths with Kconfig options. Change-Id: Ib9b9b29a158c34a30480aaabf6d0b23819d28427 Signed-off-by: Angel Pons Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/44226 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Marshall Dawson --- src/cpu/amd/agesa/family14/Kconfig | 1 + src/cpu/amd/agesa/family14/Makefile.inc | 1 - src/cpu/amd/agesa/family15tn/Kconfig | 1 + src/cpu/amd/agesa/family15tn/Makefile.inc | 1 - src/cpu/amd/agesa/family16kb/Kconfig | 1 + src/cpu/amd/agesa/family16kb/Makefile.inc | 1 - src/cpu/intel/slot_1/Kconfig | 1 + src/cpu/intel/slot_1/Makefile.inc | 1 - src/cpu/intel/socket_441/Kconfig | 1 + src/cpu/intel/socket_441/Makefile.inc | 1 - src/cpu/intel/socket_BGA956/Kconfig | 1 + src/cpu/intel/socket_BGA956/Makefile.inc | 1 - src/cpu/intel/socket_FCBGA559/Kconfig | 1 + src/cpu/intel/socket_FCBGA559/Makefile.inc | 1 - src/cpu/intel/socket_LGA775/Kconfig | 1 + src/cpu/intel/socket_LGA775/Makefile.inc | 1 - src/cpu/intel/socket_m/Kconfig | 1 + src/cpu/intel/socket_m/Makefile.inc | 1 - src/cpu/intel/socket_mPGA604/Kconfig | 1 + src/cpu/intel/socket_mPGA604/Makefile.inc | 1 - src/cpu/intel/socket_p/Kconfig | 1 + src/cpu/intel/socket_p/Makefile.inc | 1 - src/cpu/x86/Kconfig | 6 ++++++ src/cpu/x86/Makefile.inc | 1 + 24 files changed, 18 insertions(+), 11 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 103903fc1e4..e617c19c8a7 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -3,6 +3,7 @@ config CPU_AMD_AGESA_FAMILY14 bool select X86_AMD_FIXED_MTRRS + select CPU_X86_CACHE_HELPER if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index aeecbe48528..5ee0f82fe35 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -8,4 +8,3 @@ ramstage-y += model_14_init.c subdirs-y += ../../mtrr subdirs-y += ../../../x86/lapic -subdirs-y += ../../../x86/cache diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 8c52e9a9b66..68fd82cd6e9 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_AGESA_FAMILY15_TN bool select IDS_OPTIONS_HOOKED_UP select X86_AMD_FIXED_MTRRS + select CPU_X86_CACHE_HELPER if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 03aadd3d38d..86d840bff28 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -11,4 +11,3 @@ smm-y += udelay.c subdirs-y += ../../mtrr subdirs-y += ../../smm subdirs-y += ../../../x86/lapic -subdirs-y += ../../../x86/cache diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index e41ddece4d6..ee568ece653 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -3,6 +3,7 @@ config CPU_AMD_AGESA_FAMILY16_KB bool select X86_AMD_FIXED_MTRRS + select CPU_X86_CACHE_HELPER if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 7eb39e3394a..1cc8eff9b21 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -8,4 +8,3 @@ ramstage-y += model_16_init.c subdirs-y += ../../mtrr subdirs-y += ../../../x86/lapic -subdirs-y += ../../../x86/cache diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index c30e0664447..9cbe5026544 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -12,6 +12,7 @@ config SLOT_SPECIFIC_OPTIONS select CPU_INTEL_MODEL_68X select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX + select CPU_X86_CACHE_HELPER select NO_SMM select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 28df10ea239..b2422f4957b 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../model_67x subdirs-y += ../model_68x subdirs-y += ../model_6bx subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode bootblock-y += ../car/p3/cache_as_ram.S diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 5b6ae7f61dc..8df6fbd4168 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -6,6 +6,7 @@ if CPU_INTEL_SOCKET_441 config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_106CX + select CPU_X86_CACHE_HELPER select MMX select SSE select SETUP_XIP_CACHE diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index dfed16c7177..e338ea1836a 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_106cx subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 638653c1621..1cad83f43b3 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_SOCKET_BGA956 bool select CPU_INTEL_MODEL_1067X + select CPU_X86_CACHE_HELPER select MMX select SSE diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index a39798449b7..5f92919e17d 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_1067x subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 5105f095e91..87c419fe481 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -8,6 +8,7 @@ if CPU_INTEL_SOCKET_FCBGA559 config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_106CX + select CPU_X86_CACHE_HELPER select MMX select SSE select CPU_HAS_L2_ENABLE_MSR diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 64d0c36507c..48ba3a95a21 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_106cx subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 0848d2648e6..f162599e77e 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS # select CPU_INTEL_MODEL_F6X # select CPU_INTEL_MODEL_1066X select CPU_INTEL_MODEL_1067X + select CPU_X86_CACHE_HELPER select MMX select SSE select SIPI_VECTOR_IN_ROM diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index a16f670fca3..1f1008e6587 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../model_f4x #subdirs-y += ../model_1066x subdirs-y += ../model_1067x subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 50eb7e3f0c9..d3d81c56763 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -7,6 +7,7 @@ config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX + select CPU_X86_CACHE_HELPER select MMX select SSE diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 2bcd580abc2..6c53ec2c5b8 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -1,7 +1,6 @@ subdirs-y += ../model_6ex subdirs-y += ../model_6fx subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 7b086990f75..f95cd02f20d 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -6,6 +6,7 @@ if CPU_INTEL_SOCKET_MPGA604 config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_F2X + select CPU_X86_CACHE_HELPER select MMX select SSE select UDELAY_TSC diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 2bca94ea2d6..f9dfc67b0c5 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_f2x subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode bootblock-y += ../car/p4-netburst/cache_as_ram.S diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index a7c8ab1bb8c..9239fe71fd4 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -2,6 +2,7 @@ config CPU_INTEL_SOCKET_P bool select CPU_INTEL_MODEL_1067X select CPU_INTEL_MODEL_6FX + select CPU_X86_CACHE_HELPER select MMX select SSE diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 8588c371358..64bb8beaa66 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -1,7 +1,6 @@ subdirs-y += ../model_6fx subdirs-y += ../model_1067x subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index fb5b5413b9b..bae38891ad7 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,3 +1,9 @@ +config CPU_X86_CACHE_HELPER + bool + default n + help + Add the x86_enable_cache ramstage helper function to the build. + config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 016b6014114..05df6e0f927 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,3 +1,4 @@ +subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache subdirs-y += mtrr subdirs-y += pae subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm From 57f09803bb6c356e05d1051f8b27ff60ec0d8c4e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 14 Oct 2021 14:13:50 +0200 Subject: [PATCH 304/320] mb/prodrive/hermes: Reorganize per-port PCIe settings Move per-port PCIe settings inside the corresponding PCIe root port device. Also, remove several unnecessary and/or redundant comments. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I3f64d56b3b2c592194b18ae7b7c63ef41a1e060f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58325 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../hermes/variants/baseboard/overridetree.cb | 69 ++++++++----------- 1 file changed, 30 insertions(+), 39 deletions(-) diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 0690167b01a..16ba724e9e1 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -32,37 +32,6 @@ chip soc/intel/cannonlake register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - # Enumeration starts at 0 for PCIE1 - # Ports are not hotplugable - register "PcieRpEnable[0]" = "1" # Slot3 x4 - # Set MaxPayload to 256 bytes - register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[0]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" - # Disable Aspm - register "PcieRpAspm[0]" = "AspmDisabled" - - - register "PcieRpEnable[4]" = "1" # PHY ETH3 - register "PcieRpEnable[5]" = "1" # PHY ETH4 - register "PcieRpEnable[6]" = "1" # PHY ETH2 - register "PcieRpEnable[7]" = "1" # PHY ETH1 - register "PcieRpEnable[8]" = "1" # M2 Slot M x4, depends on SATAXPCIE1 - register "PcieRpEnable[13]" = "1" # PHY ETH0 - register "PcieRpEnable[14]" = "1" # BMC - register "PcieRpEnable[15]" = "1" # M2 Slot E x1 - register "PcieRpEnable[20]" = "1" # Slot 1 x4 - # Set MaxPayload to 256 bytes - register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[20]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[20]" = "1" - # Disable Aspm - register "PcieRpAspm[20]" = "AspmDisabled" - # Controls the CLKREQ, not the output directly. # Depends on the CLKREQ to CLK gen mapping below register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # BMC, PCIe Slot1, Slot2, Slot4, Slot6 @@ -183,31 +152,53 @@ chip soc/intel/cannonlake end device pci 1b.4 on # PCIe root port 21 (Slot 1) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" + register "PcieRpEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "1" register "PcieRpSlotImplemented[20]" = "1" + register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" + register "PcieRpAdvancedErrorReporting[20]" = "1" + register "PcieRpAspm[20]" = "AspmDisabled" end device pci 1c.0 on # PCIe root port 1 (Slot 3) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" + register "PcieRpEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" register "PcieRpSlotImplemented[0]" = "1" + register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpAspm[0]" = "AspmDisabled" + end + device pci 1c.4 on # PCIe root port 5 (PHY 3) + register "PcieRpEnable[4]" = "1" + end + device pci 1c.5 on # PCIe root port 6 (PHY 4) + register "PcieRpEnable[5]" = "1" + end + device pci 1c.6 on # PCIe root port 7 (PHY 2) + register "PcieRpEnable[6]" = "1" + end + device pci 1c.7 on # PCIe root port 8 (PHY 1) + register "PcieRpEnable[7]" = "1" end - device pci 1c.4 on end # PCIe root port 5 (PHY 3) - device pci 1c.5 on end # PCIe root port 6 (PHY 4) - device pci 1c.6 on end # PCIe root port 7 (PHY 2) - device pci 1c.7 on end # PCIe root port 8 (PHY 1) - device pci 1d.0 on # PCIe root port 9 (M2 M) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" + register "PcieRpEnable[8]" = "1" register "PcieRpSlotImplemented[8]" = "1" end - device pci 1d.5 on end # PCIe root port 14 (PHY 0) - device pci 1d.6 on end # PCIe root port 15 (BMC) + device pci 1d.5 on # PCIe root port 14 (PHY 0) + register "PcieRpEnable[13]" = "1" + end + device pci 1d.6 on # PCIe root port 15 (BMC) + register "PcieRpEnable[14]" = "1" + end device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi) # Disabled when CNVi is present + register "PcieRpEnable[15]" = "1" register "PcieRpSlotImplemented[15]" = "1" end device pci 1e.0 on end # UART #0 device pci 1e.1 on end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - end end From 0515aa1978ad9795ea0e9a1b0dcada7f3a13f21c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 15 Oct 2021 14:22:30 +0200 Subject: [PATCH 305/320] mb/prodrive/hermes: Remove overridetree There's no need to have an overridetree with a single board variant. TEST=Compare static.c and observe only device order has changed. Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/prodrive/hermes/Kconfig | 3 - src/mainboard/prodrive/hermes/devicetree.cb | 197 ++++++++++++++++- .../hermes/variants/baseboard/overridetree.cb | 204 ------------------ 3 files changed, 193 insertions(+), 211 deletions(-) delete mode 100644 src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index bdb8e497b25..2fecc06f6df 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -51,9 +51,6 @@ config MAX_CPUS int default 16 -config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - config CONSOLE_POST bool default y diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index cafc81e6ba3..69658211f93 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -1,4 +1,132 @@ chip soc/intel/cannonlake + # FSP configuration + + register "SataMode" = "0" # AHCI + register "SataSalpSupport" = "0" + register "satapwroptimize" = "1" + register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1 + + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" # depends on SATAXPCIE1 + register "SataPortsEnable[2]" = "0" # Not used for SATA + register "SataPortsEnable[3]" = "0" # Not used for SATA + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "SataPortsHotPlug[0]" = "1" + register "SataPortsHotPlug[1]" = "1" + register "SataPortsHotPlug[2]" = "0" + register "SataPortsHotPlug[3]" = "0" + register "SataPortsHotPlug[4]" = "1" + register "SataPortsHotPlug[5]" = "1" + register "SataPortsHotPlug[6]" = "1" + register "SataPortsHotPlug[7]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + # Controls the CLKREQ, not the output directly. + # Depends on the CLKREQ to CLK gen mapping below + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # BMC, PCIe Slot1, Slot2, Slot4, Slot6 + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # PHY3 + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # RP9 M2 Slot M x4 + register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" # RP16 M2 Slot E x1 + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[11]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[12]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE" # PHY 0, PHY 1, PHY 2, PHY 4 + register "PcieClkSrcUsage[14]" = "PCIE_CLK_FREE" # PB + register "PcieClkSrcUsage[15]" = "PCIE_CLK_FREE" # PCIe Slot3 + + # Only map M2 CLKREQ to CLK gen + register "PcieClkSrcClkReq[4]" = "4" # M2_M_CLK_REQ_n + register "PcieClkSrcClkReq[5]" = "5" # M2_E_CLK_REQ_n + + # USB OC5-7: not connected + register "usb2_ports" = "{ + +#define HERMES_USB2_CONFIG(pin) { \ + .enable = 1, \ + .ocpin = (pin), \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_28P15MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ +} + [0] = HERMES_USB2_CONFIG(OC0), /* USB3 rear panel 1 */ + [1] = HERMES_USB2_CONFIG(OC0), + [2] = HERMES_USB2_CONFIG(OC1), /* USB3 rear panel 2 */ + [3] = HERMES_USB2_CONFIG(OC1), + [4] = HERMES_USB2_CONFIG(OC2), /* USB3 internal header CN_USB3_HDR */ + [5] = HERMES_USB2_CONFIG(OC2), + [6] = HERMES_USB2_CONFIG(OC3), /* USB2 internal header USB2_HDR1 */ + [7] = HERMES_USB2_CONFIG(OC3), + [8] = HERMES_USB2_CONFIG(OC4), /* USB2 internal header USB2_HDR1 */ + [9] = HERMES_USB2_CONFIG(OC4), + [10] = HERMES_USB2_CONFIG(OC_SKIP), /* BMC */ + [11] = USB2_PORT_EMPTY, + [12] = HERMES_USB2_CONFIG(OC_SKIP), /* piggy-back */ + [13] = HERMES_USB2_CONFIG(OC_SKIP), /* M.2 key E */ + }" + + # USB Config 2.0/3.0 + # Enumeration starts at 0 + # USB 3.0 + # USB OC0: RP1 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + + # USB OC1: RP2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + # USB OC2: Internal Header CN_USB3_HDR + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" + + # Thermal + register "tcc_offset" = "1" # TCC of 99C + + # Disable S0ix + register "s0ix_enable" = "0" + + # Enable Turbo + register "eist_enable" = "1" + + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + # VR Power Delivery Design + register "VrPowerDeliveryDesign" = "0x12" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoPci, + }" + + register "DisableHeciRetry" = "1" + device cpu_cluster 0 on device lapic 0 on end end @@ -14,24 +142,86 @@ chip soc/intel/cannonlake device pci 01.2 on # PEG x4 or disabled / Slot 4 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT4" "SlotDataBusWidth4X" end + device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA Thermal device device pci 08.0 on end # Gaussian Mixture device pci 12.0 on end # Thermal Subsystem device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # RAM controller + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard - device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 on end # Management Engine Interface 2 device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA - device pci 1d.6 on # PCIe root port 15 - device pci 00.0 on # Aspeed PCI Bridge + # This device does not have any function on CNP-H, but it needs + # to be here so that the resource allocator is aware of UART 2. + device pci 19.0 hidden end + chip soc/intel/common/block/uart + device pci 19.2 hidden + register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2" + end # UART #2, in ACPI mode + end + device pci 1b.4 on # PCIe root port 21 (Slot 1) + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" + register "PcieRpEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "1" + register "PcieRpSlotImplemented[20]" = "1" + register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" + register "PcieRpAdvancedErrorReporting[20]" = "1" + register "PcieRpAspm[20]" = "AspmDisabled" + end + device pci 1c.0 on # PCIe root port 1 (Slot 3) + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" + register "PcieRpEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpSlotImplemented[0]" = "1" + register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpAspm[0]" = "AspmDisabled" + end + device pci 1c.4 on # PCIe root port 5 (PHY 3) + register "PcieRpEnable[4]" = "1" + end + device pci 1c.5 on # PCIe root port 6 (PHY 4) + register "PcieRpEnable[5]" = "1" + end + device pci 1c.6 on # PCIe root port 7 (PHY 2) + register "PcieRpEnable[6]" = "1" + end + device pci 1c.7 on # PCIe root port 8 (PHY 1) + register "PcieRpEnable[7]" = "1" + end + device pci 1d.0 on # PCIe root port 9 (M2 M) + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" + register "PcieRpEnable[8]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + end + device pci 1d.5 on # PCIe root port 14 (PHY 0) + register "PcieRpEnable[13]" = "1" + end + device pci 1d.6 on # PCIe root port 15 (BMC) + device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2500 VGA end + register "PcieRpEnable[14]" = "1" register "PcieRpSlotImplemented[14]" = "1" end + device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi) + # Disabled when CNVi is present + register "PcieRpEnable[15]" = "1" + register "PcieRpSlotImplemented[15]" = "1" + end + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface chip drivers/pc80/tpm device pnp 0c31.0 on end @@ -44,5 +234,4 @@ chip soc/intel/cannonlake device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI end - end diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb deleted file mode 100644 index 16ba724e9e1..00000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ /dev/null @@ -1,204 +0,0 @@ -chip soc/intel/cannonlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - - register "SataMode" = "0" # AHCI - register "SataSalpSupport" = "0" - register "satapwroptimize" = "1" - register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1 - - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" # depends on SATAXPCIE1 - register "SataPortsEnable[2]" = "0" # Not used for SATA - register "SataPortsEnable[3]" = "0" # Not used for SATA - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "1" - register "SataPortsEnable[7]" = "1" - - register "SataPortsHotPlug[0]" = "1" - register "SataPortsHotPlug[1]" = "1" - register "SataPortsHotPlug[2]" = "0" - register "SataPortsHotPlug[3]" = "0" - register "SataPortsHotPlug[4]" = "1" - register "SataPortsHotPlug[5]" = "1" - register "SataPortsHotPlug[6]" = "1" - register "SataPortsHotPlug[7]" = "1" - - register "PchHdaDspEnable" = "0" - register "PchHdaAudioLinkHda" = "1" - - # Controls the CLKREQ, not the output directly. - # Depends on the CLKREQ to CLK gen mapping below - register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # BMC, PCIe Slot1, Slot2, Slot4, Slot6 - register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # PHY3 - register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # RP9 M2 Slot M x4 - register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE" # RP16 M2 Slot E x1 - register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[11]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[12]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[13]" = "PCIE_CLK_FREE" # PHY 0, PHY 1, PHY 2, PHY 4 - register "PcieClkSrcUsage[14]" = "PCIE_CLK_FREE" # PB - register "PcieClkSrcUsage[15]" = "PCIE_CLK_FREE" # PCIe Slot3 - - # Only map M2 CLKREQ to CLK gen - register "PcieClkSrcClkReq[4]" = "4" # M2_M_CLK_REQ_n - register "PcieClkSrcClkReq[5]" = "5" # M2_E_CLK_REQ_n - - # USB OC5-7: not connected - register "usb2_ports" = "{ - -#define HERMES_USB2_CONFIG(pin) { \ - .enable = 1, \ - .ocpin = (pin), \ - .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_28P15MV, \ - .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ -} - [0] = HERMES_USB2_CONFIG(OC0), /* USB3 rear panel 1 */ - [1] = HERMES_USB2_CONFIG(OC0), - [2] = HERMES_USB2_CONFIG(OC1), /* USB3 rear panel 2 */ - [3] = HERMES_USB2_CONFIG(OC1), - [4] = HERMES_USB2_CONFIG(OC2), /* USB3 internal header CN_USB3_HDR */ - [5] = HERMES_USB2_CONFIG(OC2), - [6] = HERMES_USB2_CONFIG(OC3), /* USB2 internal header USB2_HDR1 */ - [7] = HERMES_USB2_CONFIG(OC3), - [8] = HERMES_USB2_CONFIG(OC4), /* USB2 internal header USB2_HDR1 */ - [9] = HERMES_USB2_CONFIG(OC4), - [10] = HERMES_USB2_CONFIG(OC_SKIP), /* BMC */ - [11] = USB2_PORT_EMPTY, - [12] = HERMES_USB2_CONFIG(OC_SKIP), /* piggy-back */ - [13] = HERMES_USB2_CONFIG(OC_SKIP), /* M.2 key E */ - }" - - # USB Config 2.0/3.0 - # Enumeration starts at 0 - # USB 3.0 - # USB OC0: RP1 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - - # USB OC1: RP2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" - - # USB OC2: Internal Header CN_USB3_HDR - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" - - # Thermal - register "tcc_offset" = "1" # TCC of 99C - - - # Disable S0ix - register "s0ix_enable" = "0" - - # Enable Turbo - register "eist_enable" = "1" - - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - }" - - # VR Power Delivery Design - register "VrPowerDeliveryDesign" = "0x12" - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoPci, - [PchSerialIoIndexUART1] = PchSerialIoPci, - [PchSerialIoIndexUART2] = PchSerialIoPci, - }" - - register "DisableHeciRetry" = "1" - - device domain 0 on - device pci 02.0 on end # Integrated Graphics Device - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device generic 0 on end - end - end # CNVi wifi - - # This device does not have any function on CNP-H, but it needs - # to be here so that the resource allocator is aware of UART 2. - device pci 19.0 hidden end - chip soc/intel/common/block/uart - device pci 19.2 hidden - register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2" - end # UART #2, in ACPI mode - end - device pci 1b.4 on # PCIe root port 21 (Slot 1) - smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" - register "PcieRpEnable[20]" = "1" - register "PcieRpLtrEnable[20]" = "1" - register "PcieRpSlotImplemented[20]" = "1" - register "PcieRpMaxPayload[20]" = "RpMaxPayload_256" - register "PcieRpAdvancedErrorReporting[20]" = "1" - register "PcieRpAspm[20]" = "AspmDisabled" - end - device pci 1c.0 on # PCIe root port 1 (Slot 3) - smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" - register "PcieRpEnable[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" - register "PcieRpSlotImplemented[0]" = "1" - register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpAspm[0]" = "AspmDisabled" - end - device pci 1c.4 on # PCIe root port 5 (PHY 3) - register "PcieRpEnable[4]" = "1" - end - device pci 1c.5 on # PCIe root port 6 (PHY 4) - register "PcieRpEnable[5]" = "1" - end - device pci 1c.6 on # PCIe root port 7 (PHY 2) - register "PcieRpEnable[6]" = "1" - end - device pci 1c.7 on # PCIe root port 8 (PHY 1) - register "PcieRpEnable[7]" = "1" - end - device pci 1d.0 on # PCIe root port 9 (M2 M) - smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" - register "PcieRpEnable[8]" = "1" - register "PcieRpSlotImplemented[8]" = "1" - end - device pci 1d.5 on # PCIe root port 14 (PHY 0) - register "PcieRpEnable[13]" = "1" - end - device pci 1d.6 on # PCIe root port 15 (BMC) - register "PcieRpEnable[14]" = "1" - end - device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi) - # Disabled when CNVi is present - register "PcieRpEnable[15]" = "1" - register "PcieRpSlotImplemented[15]" = "1" - end - device pci 1e.0 on end # UART #0 - device pci 1e.1 on end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - end -end From 965b05adafe3384c3a2a74d642b3e95c00814668 Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Thu, 21 Oct 2021 10:54:36 +0000 Subject: [PATCH 306/320] Documentation/releases/4.15: Add note about libpayload improvements Change-Id: I3043e70523db1b7f1df90789a69eadd155848bb0 Signed-off-by: Jakub Czapiga Reviewed-on: https://review.coreboot.org/c/coreboot/+/58521 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- Documentation/releases/coreboot-4.15-relnotes.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/releases/coreboot-4.15-relnotes.md b/Documentation/releases/coreboot-4.15-relnotes.md index 5701eb0c96f..334d4cae06f 100644 --- a/Documentation/releases/coreboot-4.15-relnotes.md +++ b/Documentation/releases/coreboot-4.15-relnotes.md @@ -25,5 +25,16 @@ Previously, the default behaviour for Intel chipset lockdown was to let the FSP do it. Since all related mainboards used the coreboot mechanisms for chipset lockdown, the default behaviour was changed to that. +### Payloads unit testing + +Libpayload now supports the mock architecture, which can be used for unit testing +payloads. (For examples see +[depthcharge](https://chromium.googlesource.com/chromiumos/platform/depthcharge/) +payload) + +### Unit testing infrastructure + +Unit testing of libpayload is now possible in the same fashion as in the main +coreboot tree. ### Add significant changes here From 8290f4c3d7c23002dfd49a2ebb5a225e3e9038ad Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 23 Oct 2021 00:06:28 +0200 Subject: [PATCH 307/320] cpu/intel/*/Kconfig: move selection of CPU_X86_CACHE_HELPER Move the selection of CPU_X86_CACHE_HELPER to the Kconfig file of the CPU models which call the x86_enable_cache function that gets added to the build by selecting this option. Change-Id: Ie75682f5d20a79fc2f3aab9b8a2c3ccf79d1ad5c Signed-off-by: Angel Pons Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/44227 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/cpu/intel/model_65x/Kconfig | 1 + src/cpu/intel/model_67x/Kconfig | 1 + src/cpu/intel/model_68x/Kconfig | 1 + src/cpu/intel/model_6bx/Kconfig | 1 + src/cpu/intel/model_6ex/Kconfig | 1 + src/cpu/intel/model_6fx/Kconfig | 1 + src/cpu/intel/model_6xx/Kconfig | 1 + src/cpu/intel/model_f2x/Kconfig | 1 + src/cpu/intel/model_f3x/Kconfig | 1 + src/cpu/intel/model_f4x/Kconfig | 1 + src/cpu/intel/slot_1/Kconfig | 1 - src/cpu/intel/socket_441/Kconfig | 1 - src/cpu/intel/socket_BGA956/Kconfig | 1 - src/cpu/intel/socket_FCBGA559/Kconfig | 1 - src/cpu/intel/socket_LGA775/Kconfig | 1 - src/cpu/intel/socket_m/Kconfig | 1 - src/cpu/intel/socket_mPGA604/Kconfig | 1 - src/cpu/intel/socket_p/Kconfig | 1 - 18 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index 6d41d94f57d..42bdc3f3a8f 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_65X bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index 26a303be017..da57caa2da1 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_67X bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index 796290770f2..0ab1e7af515 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_68X bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index 14274a32367..cb9d6f36770 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_6BX bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index c7d54c5f8c3..37bfa14ad1c 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -9,3 +9,4 @@ config CPU_INTEL_MODEL_6EX select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 499972600a2..8e035608ad1 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -10,3 +10,4 @@ config CPU_INTEL_MODEL_6FX select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select SETUP_XIP_CACHE + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index e05cf895173..95e175e0526 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_6XX bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 672cf75517e..3339b66b00a 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_F2X select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG select CPU_INTEL_COMMON + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index b0a9f7ce64d..943d9cc155e 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -3,3 +3,4 @@ config CPU_INTEL_MODEL_F3X select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 550a978e855..4dd40384fb2 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_F4X bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 9cbe5026544..c30e0664447 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -12,7 +12,6 @@ config SLOT_SPECIFIC_OPTIONS select CPU_INTEL_MODEL_68X select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX - select CPU_X86_CACHE_HELPER select NO_SMM select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 8df6fbd4168..5b6ae7f61dc 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -6,7 +6,6 @@ if CPU_INTEL_SOCKET_441 config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_106CX - select CPU_X86_CACHE_HELPER select MMX select SSE select SETUP_XIP_CACHE diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 1cad83f43b3..638653c1621 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -1,7 +1,6 @@ config CPU_INTEL_SOCKET_BGA956 bool select CPU_INTEL_MODEL_1067X - select CPU_X86_CACHE_HELPER select MMX select SSE diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 87c419fe481..5105f095e91 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -8,7 +8,6 @@ if CPU_INTEL_SOCKET_FCBGA559 config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_106CX - select CPU_X86_CACHE_HELPER select MMX select SSE select CPU_HAS_L2_ENABLE_MSR diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index f162599e77e..0848d2648e6 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS # select CPU_INTEL_MODEL_F6X # select CPU_INTEL_MODEL_1066X select CPU_INTEL_MODEL_1067X - select CPU_X86_CACHE_HELPER select MMX select SSE select SIPI_VECTOR_IN_ROM diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index d3d81c56763..50eb7e3f0c9 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -7,7 +7,6 @@ config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX - select CPU_X86_CACHE_HELPER select MMX select SSE diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index f95cd02f20d..7b086990f75 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -6,7 +6,6 @@ if CPU_INTEL_SOCKET_MPGA604 config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_F2X - select CPU_X86_CACHE_HELPER select MMX select SSE select UDELAY_TSC diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index 9239fe71fd4..a7c8ab1bb8c 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -2,7 +2,6 @@ config CPU_INTEL_SOCKET_P bool select CPU_INTEL_MODEL_1067X select CPU_INTEL_MODEL_6FX - select CPU_X86_CACHE_HELPER select MMX select SSE From 71dfa82380a682d4e3214bd9e139b45fc3391dff Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 23 Oct 2021 00:09:23 +0200 Subject: [PATCH 308/320] cpu/intel/socket_LGA775: Drop commented-out entries The code for these CPU models isn't present in coreboot. These lines have been commented-out since they where added, so drop them. Change-Id: I8fc53fea4225217bc5bb70d839c280ebb64fd3a6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/44218 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/cpu/intel/socket_LGA775/Kconfig | 2 -- src/cpu/intel/socket_LGA775/Makefile.inc | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 0848d2648e6..7d0bce704e1 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -8,8 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_INTEL_MODEL_6FX select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X -# select CPU_INTEL_MODEL_F6X -# select CPU_INTEL_MODEL_1066X select CPU_INTEL_MODEL_1067X select MMX select SSE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 1f1008e6587..520016808fe 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -1,8 +1,6 @@ subdirs-y += ../model_6fx subdirs-y += ../model_f3x subdirs-y += ../model_f4x -#subdirs-y += ../model_f6x -#subdirs-y += ../model_1066x subdirs-y += ../model_1067x subdirs-y += ../../x86/lapic subdirs-y += ../microcode From 02164027b2c9678bd4f5616e0ec34694da351a2c Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 23 Oct 2021 00:34:43 +0200 Subject: [PATCH 309/320] cpu/x86: Introduce and use `CPU_X86_LAPIC` With using a Kconfig option to add the x86 LAPIC support code to the build, there's no need for adding the corresponding directory to subdirs in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added (cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding MTRR code selection patch and having verified that all platforms added the MTRR code on that patch shows that soc/example/min86 and soc/intel/quark are the only platforms that don't end up selecting the LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y which gets overridden to n in the Kconfig of the two SoCs mentioned above. Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a Signed-off-by: Angel Pons Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Marshall Dawson --- src/cpu/amd/agesa/family14/Makefile.inc | 1 - src/cpu/amd/agesa/family15tn/Makefile.inc | 1 - src/cpu/amd/agesa/family16kb/Makefile.inc | 1 - src/cpu/amd/pi/00730F01/Makefile.inc | 1 - src/cpu/intel/haswell/Makefile.inc | 1 - src/cpu/intel/model_2065x/Makefile.inc | 1 - src/cpu/intel/model_206ax/Makefile.inc | 1 - src/cpu/intel/slot_1/Makefile.inc | 1 - src/cpu/intel/socket_441/Makefile.inc | 1 - src/cpu/intel/socket_BGA956/Makefile.inc | 1 - src/cpu/intel/socket_FCBGA559/Makefile.inc | 1 - src/cpu/intel/socket_LGA775/Makefile.inc | 1 - src/cpu/qemu-x86/Makefile.inc | 2 -- src/cpu/x86/Kconfig | 4 ++++ src/cpu/x86/Makefile.inc | 1 + src/soc/amd/cezanne/Makefile.inc | 2 -- src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/stoneyridge/Makefile.inc | 1 - src/soc/example/min86/Kconfig | 4 ++++ src/soc/intel/alderlake/Makefile.inc | 1 - src/soc/intel/apollolake/Makefile.inc | 1 - src/soc/intel/baytrail/Makefile.inc | 1 - src/soc/intel/braswell/Makefile.inc | 1 - src/soc/intel/cannonlake/Makefile.inc | 1 - src/soc/intel/denverton_ns/Makefile.inc | 1 - src/soc/intel/elkhartlake/Makefile.inc | 1 - src/soc/intel/icelake/Makefile.inc | 1 - src/soc/intel/jasperlake/Makefile.inc | 1 - src/soc/intel/quark/Kconfig | 4 ++++ src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/tigerlake/Makefile.inc | 1 - src/soc/intel/xeon_sp/cpx/Makefile.inc | 1 - src/soc/intel/xeon_sp/skx/Makefile.inc | 1 - 33 files changed, 13 insertions(+), 31 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 5ee0f82fe35..003aa1f532e 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -7,4 +7,3 @@ ramstage-y += chip_name.c ramstage-y += model_14_init.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/lapic diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 86d840bff28..a5914475e88 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -10,4 +10,3 @@ smm-y += udelay.c subdirs-y += ../../mtrr subdirs-y += ../../smm -subdirs-y += ../../../x86/lapic diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 1cc8eff9b21..9464372d22b 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -7,4 +7,3 @@ ramstage-y += chip_name.c ramstage-y += model_16_init.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/lapic diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index f2263d042e8..51f90ef6e92 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -8,4 +8,3 @@ ramstage-y += model_16_init.c ramstage-y += update_microcode.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/lapic diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index ec0ceea06d2..b425efd5d6b 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += bootblock.c postcar-y += ../car/non-evict/exit_car.S -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../turbo diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index fb85bdf4d55..b676eb6a775 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -1,6 +1,5 @@ ramstage-y += model_2065x_init.c subdirs-y += ../../x86/name -subdirs-y += ../../x86/lapic subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode subdirs-y += ../smm/gen1 diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index fec509c193e..90dfeb3a660 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -2,7 +2,6 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name subdirs-y += ../smm/gen1 -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../turbo diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index b2422f4957b..856ecf66976 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -7,7 +7,6 @@ subdirs-y += ../model_65x subdirs-y += ../model_67x subdirs-y += ../model_68x subdirs-y += ../model_6bx -subdirs-y += ../../x86/lapic subdirs-y += ../microcode bootblock-y += ../car/p3/cache_as_ram.S diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index e338ea1836a..58ec230d18e 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_106cx -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 5f92919e17d..8cafa7e65aa 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_1067x -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 48ba3a95a21..f6d54c9f8ad 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_106cx -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 520016808fe..9b08be6cf6f 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -2,7 +2,6 @@ subdirs-y += ../model_6fx subdirs-y += ../model_f3x subdirs-y += ../model_f4x subdirs-y += ../model_1067x -subdirs-y += ../../x86/lapic subdirs-y += ../microcode subdirs-y += ../speedstep diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 42e18060b2b..b50dee5ccc3 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -6,5 +6,3 @@ bootblock-y += bootblock.c romstage-y += ../intel/car/romstage.c ramstage-y += qemu.c - -subdirs-y += ../x86/lapic diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index bae38891ad7..a2893255233 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -4,6 +4,10 @@ config CPU_X86_CACHE_HELPER help Add the x86_enable_cache ramstage helper function to the build. +config CPU_X86_LAPIC + bool + default y + config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 05df6e0f927..a6c51d023ab 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,4 +1,5 @@ subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache +subdirs-$(CONFIG_CPU_X86_LAPIC) += lapic subdirs-y += mtrr subdirs-y += pae subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 5e6b2570295..87874418c3d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -2,8 +2,6 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) -subdirs-y += ../../../cpu/x86/lapic - subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage # Beware that all-y also adds the compilation unit to verstage on PSP diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e3eab29e35d..45e9c803307 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y) -subdirs-y += ../../../cpu/x86/lapic subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../common/psp_verstage diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 4a126d8e2d6..fd3ebf7a668 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ -subdirs-y += ../../../cpu/x86/lapic bootblock-y += uart.c bootblock-y += BiosCallOuts.c diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig index 660bf369e7e..560f2200f6b 100644 --- a/src/soc/example/min86/Kconfig +++ b/src/soc/example/min86/Kconfig @@ -19,6 +19,10 @@ config SOC_SPECIFIC_OPTIONS select NO_MMCONF_SUPPORT select UNKNOWN_TSC_RATE +config CPU_X86_LAPIC + bool + default n + config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld default 0x100 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index bd554b995a9..d857e8b59b1 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3a723dcbb31..a557d1ea401 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic bootblock-y += bootblock/bootblock.c bootblock-y += ../common/block/cpu/pm_timer_emulation.c diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 33aaba0d8fd..2bd558d5da5 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 07bd26fe265..4ecb4e79f18 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index bc15e1f0254..3c8bf5798a4 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_BASE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/intel/common bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 3fdff0d1973..5d9b32773bd 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y) subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic bootblock-y += bootblock/bootblock.c bootblock-y += spi.c diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index c32ba1f245d..3ac46ef2b28 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_ELKHARTLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 847418de1c9..90c3036a8bd 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_ICELAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 276f3c0cd54..d718dd875ff 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 1a9bfef9429..bf9d475cd52 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -24,6 +24,10 @@ config CPU_SPECIFIC_OPTIONS select USE_MARCH_586 select NO_SMM +config CPU_X86_LAPIC + bool + default n + ##### # Debug serial output # The following options configure the debug serial port diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 775bec1ce62..ea96caada7a 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic bootblock-y += bootblock/bootblock.c bootblock-y += i2c.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 9e5a3c82317..6da5e007136 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/lapic # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index ef38ce8acc5..0cd267b7125 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c ddr.c diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index b0714d4ef76..f7599a34c12 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -4,7 +4,6 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/x86/lapic postcar-y += soc_util.c From 74f4e48e855c665adcf161c8367a9fb92d069047 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 23 Oct 2021 00:38:11 +0200 Subject: [PATCH 310/320] soc/example/min86/Kconfig: don't unselect CPU_X86_LAPIC Since all multi-core x86 CPUs need to have LAPICs, this option should be selected for soc/example/min86. TEST=The example/min86 mainboard still builds. Signed-off-by: Felix Held Change-Id: I5aa6e850f0b4dca27309385ba889b04335fe4f0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58549 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/soc/example/min86/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig index 560f2200f6b..660bf369e7e 100644 --- a/src/soc/example/min86/Kconfig +++ b/src/soc/example/min86/Kconfig @@ -19,10 +19,6 @@ config SOC_SPECIFIC_OPTIONS select NO_MMCONF_SUPPORT select UNKNOWN_TSC_RATE -config CPU_X86_LAPIC - bool - default n - config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld default 0x100 From aaec8095b92e315a0502a027879352517f72f329 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Wed, 15 Sep 2021 15:52:51 -0700 Subject: [PATCH 311/320] soc/intel: Update api name for getting spi destination id Update api name and comments to be more generic as spi destination id is not DMI specific. Update api name as soc_get_spi_psf_destination_id and comments. And move PSF definition from pcr_ids.h as it's not pcr id. Signed-off-by: Wonkyu Kim Change-Id: Ie338d05649d23bddae5355dc6ce8440dfb183073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58433 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Jamie Ryu --- src/soc/intel/alderlake/include/soc/pcr_ids.h | 5 ----- src/soc/intel/alderlake/spi.c | 7 ++++--- src/soc/intel/common/block/fast_spi/fast_spi.c | 4 ++-- .../intel/common/block/include/intelblocks/fast_spi.h | 4 ++-- src/soc/intel/tigerlake/include/soc/pcr_ids.h | 9 --------- src/soc/intel/tigerlake/spi.c | 10 +++++++--- 6 files changed, 15 insertions(+), 24 deletions(-) diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h index 9ea075a78e0..f125ee20cd7 100644 --- a/src/soc/intel/alderlake/include/soc/pcr_ids.h +++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h @@ -40,9 +40,4 @@ #define PID_CPU_GPIOCOM4 0xb9 #define PID_CPU_GPIOCOM5 0xba -/* - * SPI - DMI Destination ID - */ -#define SPI_DMI_DESTINATION_ID 0x23a8 - #endif diff --git a/src/soc/intel/alderlake/spi.c b/src/soc/intel/alderlake/spi.c index b02f2a20fda..d1ef6cd5708 100644 --- a/src/soc/intel/alderlake/spi.c +++ b/src/soc/intel/alderlake/spi.c @@ -9,7 +9,8 @@ #include #include #include -#include + +#define PSF_SPI_DESTINATION_ID 0x23a8 int spi_soc_devfn_to_bus(unsigned int devfn) { @@ -28,7 +29,7 @@ int spi_soc_devfn_to_bus(unsigned int devfn) return -1; } -uint32_t soc_get_spi_dmi_destination_id(void) +uint32_t soc_get_spi_psf_destination_id(void) { - return SPI_DMI_DESTINATION_ID; + return PSF_SPI_DESTINATION_ID; } diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 93de2ecb872..0e012316d1c 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -325,9 +325,9 @@ static void fast_spi_enable_ext_bios(void) "Only 32MiB windows are supported for extended BIOS!"); #endif - /* Configure DMI Source decode for Extended BIOS Region */ + /* Configure Source decode for Extended BIOS Region */ if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, - soc_get_spi_dmi_destination_id()) == CB_ERR) + soc_get_spi_psf_destination_id()) == CB_ERR) return; /* Program EXT_BIOS_BAR1 with obtained ext_bios_base */ diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index d5d3cd560c9..a903ea839e6 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -87,9 +87,9 @@ void fast_spi_disable_wp(void); */ void fast_spi_get_ext_bios_window(uintptr_t *base, size_t *size); /* - * SOC function to get SPI-DMI Destination Id + * SOC function to get SPI PSF Destination Id */ -uint32_t soc_get_spi_dmi_destination_id(void); +uint32_t soc_get_spi_psf_destination_id(void); /* * Add MTRR for extended BIOS region(when supported) to postcar frame */ diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h index be5f1fb26b3..22f08d73d1d 100644 --- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h +++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h @@ -39,13 +39,4 @@ #define PID_CPU_GPIOCOM4 0xb9 #define PID_CPU_GPIOCOM5 0xba -/* - * SPI - DMI Destination ID - */ -#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) -#define SPI_DMI_DESTINATION_ID 0x23b0 -#else -#define SPI_DMI_DESTINATION_ID 0x23a8 -#endif - #endif diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c index ef86feafbf8..697128aaf2a 100644 --- a/src/soc/intel/tigerlake/spi.c +++ b/src/soc/intel/tigerlake/spi.c @@ -9,7 +9,9 @@ #include #include #include -#include + +#define PSF_SPI_DESTINATION_ID_H 0x23b0 +#define PSF_SPI_DESTINATION_ID 0x23a8 int spi_soc_devfn_to_bus(unsigned int devfn) { @@ -26,7 +28,9 @@ int spi_soc_devfn_to_bus(unsigned int devfn) return -1; } -uint32_t soc_get_spi_dmi_destination_id(void) +uint32_t soc_get_spi_psf_destination_id(void) { - return SPI_DMI_DESTINATION_ID; + if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)) + return PSF_SPI_DESTINATION_ID_H; + return PSF_SPI_DESTINATION_ID; } From 4010d4a3b5cb43b6932d744bce0486cb95230fc5 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 13 Oct 2021 20:31:27 -0700 Subject: [PATCH 312/320] soc/intel/alderlake: set lock offset for gpio pad communities Initialize the pad_cfg_lock_offset field for the various gpio pad_community structures in the adl_communities. BUG=b:201430600 TEST='emerge-brya coreboot' and verify it compiles successfully. Change-Id: I2cd3e43a84b0140bb2aeae5de1e299db714d419b Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/58350 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/gpio.c | 5 +++++ src/soc/intel/alderlake/include/soc/gpio_defs.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index f845defdaa1..8275241c606 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -95,6 +95,7 @@ static const struct pad_community adl_communities[] = { .last_pad = GPIO_COM0_END, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, @@ -118,6 +119,7 @@ static const struct pad_community adl_communities[] = { .last_pad = GPIO_COM1_END, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, @@ -140,6 +142,7 @@ static const struct pad_community adl_communities[] = { .last_pad = GPIO_COM2_END, .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, @@ -180,6 +183,7 @@ static const struct pad_community adl_communities[] = { .last_pad = GPIO_COM4_END, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, @@ -203,6 +207,7 @@ static const struct pad_community adl_communities[] = { .last_pad = GPIO_COM5_END, .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, .host_own_reg_0 = HOSTSW_OWN_REG_0, .gpi_int_sts_reg_0 = GPI_INT_STS_0, .gpi_int_en_reg_0 = GPI_INT_EN_0, diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h index b329f3cdac1..e4f84ec2b38 100644 --- a/src/soc/intel/alderlake/include/soc/gpio_defs.h +++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h @@ -26,6 +26,9 @@ (NUM_GPIO_COM2_GPI_REGS) +\ (NUM_GPIO_COM4_GPI_REGS) +\ (NUM_GPIO_COM5_GPI_REGS)) + +#define PAD_CFG_LOCK_OFFSET 0x80 + /* * IOxAPIC IRQs for the GPIOs */ From a3c7cacbed30ac180f0d4ae5b6bb6fb7693de8a7 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 25 Oct 2021 21:25:59 +0200 Subject: [PATCH 313/320] include/device/pci_ids: fix typo in PCI_DEVICE_ID_AMD_FE_GATE_700D The definitions isn't used in either spelling. Signed-off-by: Felix Held Change-Id: Id6faea2b9c89f0bd3c164a6dc76fac5ea712d313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58581 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Paul Menzel --- src/include/device/pci_ids.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index be4ce760875..6723b9855f6 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -632,7 +632,7 @@ #define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 #define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 #define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C -#define PCI_DEVIDE_ID_AMD_FE_GATE_700D 0x700D +#define PCI_DEVICE_ID_AMD_FE_GATE_700D 0x700D #define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E #define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F #define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400 From 1fe6ddbd392555f00eb3b57e7aaa212a4470362b Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 25 Oct 2021 21:29:53 +0200 Subject: [PATCH 314/320] include/device/pci_ids: move AMD device IDs below AMD vendor ID Half of the AMD PCI device ID definitions were below the ATI vendor ID, so move those below the AMD PCI vendor ID definition. The entries are kept in the order they were before and added before the existing AMD device ID definitions below the AMD vendor ID definition. Signed-off-by: Felix Held Change-Id: I34ffdc49884737541b8653bebf023a68050375d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58582 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/include/device/pci_ids.h | 266 ++++++++++++++++++----------------- 1 file changed, 134 insertions(+), 132 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6723b9855f6..0e4da419219 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -293,23 +293,6 @@ #define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146 #define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 -#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 -#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 -#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT 0x1400 -#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT 0x141A -#define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT 0x1570 -#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT 0x15B0 -#define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 -#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 -#define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 -#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB 0x1630 -#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 -#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 -#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 -#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 -#define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU 0x15D1 -#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU 0x1631 - #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 #define PCI_DEVICE_ID_ATI_SB600_IDE 0x438C @@ -363,31 +346,6 @@ #define PCI_DEVICE_ID_ATI_SB800_USB_22_2 0x4396 #define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699 -#define PCI_DEVICE_ID_AMD_SB900_LPC 0x780E -#define PCI_DEVICE_ID_AMD_SB900_SATA 0x7800 -#define PCI_DEVICE_ID_AMD_SB900_SATA_AHCI 0x7801 -#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID 0x7802 -#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID5 0x7803 -#define PCI_DEVICE_ID_AMD_SB900_SATA_AMDAHCI 0x7804 -#define PCI_DEVICE_ID_AMD_SB900_IDE 0x780C -#define PCI_DEVICE_ID_AMD_SB900_HDA 0x780D -#define PCI_DEVICE_ID_AMD_SB900_PCI 0x780F -#define PCI_DEVICE_ID_AMD_SB900_PCIEA 0x43A0 -#define PCI_DEVICE_ID_AMD_SB900_PCIEB 0x43A1 -#define PCI_DEVICE_ID_AMD_SB900_PCIEC 0x43A2 -#define PCI_DEVICE_ID_AMD_SB900_PCIED 0x43A3 -#define PCI_DEVICE_ID_AMD_SB900_SM 0x780B -#define PCI_DEVICE_ID_AMD_SB900_USB_16_0 0x7812 -#define PCI_DEVICE_ID_AMD_SB900_USB_16_1 0x7812 -#define PCI_DEVICE_ID_AMD_SB900_USB_18_0 0x7807 -#define PCI_DEVICE_ID_AMD_SB900_USB_18_2 0x7808 -#define PCI_DEVICE_ID_AMD_SB900_USB_19_0 0x7807 -#define PCI_DEVICE_ID_AMD_SB900_USB_19_2 0x7808 -#define PCI_DEVICE_ID_AMD_SB900_USB_20_5 0x7809 -#define PCI_DEVICE_ID_AMD_SB900_GEC 0x7806 -#define PCI_DEVICE_ID_AMD_HUDSON_SD 0x7806 -#define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813 - #define PCI_DEVICE_ID_ATI_RS690_HT 0x7910 #define PCI_DEVICE_ID_ATI_RS740_HT 0x7911 #define PCI_DEVICE_ID_ATI_RS690_PCIE 0x7912 @@ -402,17 +360,6 @@ #define PCI_DEVICE_ID_ATI_RS690MT_INT_GFX 0x791f #define PCI_DEVICE_ID_ATI_RS740_INT_GFX 0x796e -#define PCI_DEVICE_ID_AMD_RS780_HT 0x9600 -#define PCI_DEVICE_ID_AMD_RS780_PCIE 0x9602 -#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV2 0x9603 -#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV3 0x960B -#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV4 0x9604 -#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV5 0x9605 -#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV6 0x9606 -#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV7 0x9607 -#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV9 0x9608 -#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV10 0x9609 -#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV8 0x960A #define PCI_DEVICE_ID_ATI_RS780_INT_GFX 0x9610 #define PCI_DEVICE_ID_ATI_RS780C_INT_GFX 0x9611 #define PCI_DEVICE_ID_ATI_RS780M_INT_GFX 0x9612 @@ -424,85 +371,6 @@ #define PCI_DEVICE_ID_ATI_RS785MC_INT_GFX 0x9713 #define PCI_DEVICE_ID_ATI_RS785D_INT_GFX 0x9714 -#define PCI_DEVICE_ID_AMD_RD890TV_HT 0x5956 -#define PCI_DEVICE_ID_AMD_RX780_HT 0x5957 -#define PCI_DEVICE_ID_AMD_RD780_HT 0x5958 -#define PCI_DEVICE_ID_AMD_SR5690_HT 0x5A10 -#define PCI_DEVICE_ID_AMD_RD890_HT 0x5A11 -#define PCI_DEVICE_ID_AMD_SR5670_HT 0x5A12 -#define PCI_DEVICE_ID_AMD_SR5650_HT 0x5A13 -#define PCI_DEVICE_ID_AMD_990FX_HT 0x5A14 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE 0x5A12 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV2 0x5A16 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV3 0x5A17 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV4 0x5A18 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV5 0x5A19 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV6 0x5A1A -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV7 0x5A1B -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV9 0x5A1C -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV10 0x5A1D -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV11 0x5A1F -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV12 0x5A20 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13 0x5A1E -#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21 -#define PCI_DEVICE_ID_AMD_SR5650_IOMMU 0x5A23 - -#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A -#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E -#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 -#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 -#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 -#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 -#define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 -#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B - -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP 0x15D3 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 0x1633 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2 0x1634 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA 0x15DB -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB 0x15DC -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC 0x1635 -#define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 -#define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI 0x1639 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3 0x15EB -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4 0x15EC -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5 0x15ED -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6 0x15EE -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF7 0x15EF -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0 0x1448 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1 0x1449 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2 0x144A -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3 0x144B -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4 0x144C -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5 0x144D -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6 0x144E -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7 0x144F -#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0 0x166A -#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1 0x166B -#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2 0x166C -#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3 0x166D -#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4 0x166E -#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5 0x166F -#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6 0x1670 -#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7 0x1671 -#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0 0x7901 -#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1 0x7904 -#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 -#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1 0x7917 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD 0x7906 -#define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B -#define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458 -#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE 0x1641 -#define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97 0x1644 - #define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU 0x15D8 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_GPU 0x1636 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL68H_GPU 0x164C @@ -624,6 +492,140 @@ #define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060 #define PCI_VENDOR_ID_AMD 0x1022 + +#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 +#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 +#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_HT 0x1400 +#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT 0x141A +#define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT 0x1570 +#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT 0x15B0 +#define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 +#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 +#define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 +#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB 0x1630 +#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 +#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 +#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 +#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 +#define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU 0x15D1 +#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU 0x1631 + +#define PCI_DEVICE_ID_AMD_SB900_LPC 0x780E +#define PCI_DEVICE_ID_AMD_SB900_SATA 0x7800 +#define PCI_DEVICE_ID_AMD_SB900_SATA_AHCI 0x7801 +#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID 0x7802 +#define PCI_DEVICE_ID_AMD_SB900_SATA_RAID5 0x7803 +#define PCI_DEVICE_ID_AMD_SB900_SATA_AMDAHCI 0x7804 +#define PCI_DEVICE_ID_AMD_SB900_IDE 0x780C +#define PCI_DEVICE_ID_AMD_SB900_HDA 0x780D +#define PCI_DEVICE_ID_AMD_SB900_PCI 0x780F +#define PCI_DEVICE_ID_AMD_SB900_PCIEA 0x43A0 +#define PCI_DEVICE_ID_AMD_SB900_PCIEB 0x43A1 +#define PCI_DEVICE_ID_AMD_SB900_PCIEC 0x43A2 +#define PCI_DEVICE_ID_AMD_SB900_PCIED 0x43A3 +#define PCI_DEVICE_ID_AMD_SB900_SM 0x780B +#define PCI_DEVICE_ID_AMD_SB900_USB_16_0 0x7812 +#define PCI_DEVICE_ID_AMD_SB900_USB_16_1 0x7812 +#define PCI_DEVICE_ID_AMD_SB900_USB_18_0 0x7807 +#define PCI_DEVICE_ID_AMD_SB900_USB_18_2 0x7808 +#define PCI_DEVICE_ID_AMD_SB900_USB_19_0 0x7807 +#define PCI_DEVICE_ID_AMD_SB900_USB_19_2 0x7808 +#define PCI_DEVICE_ID_AMD_SB900_USB_20_5 0x7809 +#define PCI_DEVICE_ID_AMD_SB900_GEC 0x7806 +#define PCI_DEVICE_ID_AMD_HUDSON_SD 0x7806 +#define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813 + +#define PCI_DEVICE_ID_AMD_RS780_HT 0x9600 +#define PCI_DEVICE_ID_AMD_RS780_PCIE 0x9602 +#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV2 0x9603 +#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV3 0x960B +#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV4 0x9604 +#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV5 0x9605 +#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV6 0x9606 +#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV7 0x9607 +#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV9 0x9608 +#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV10 0x9609 +#define PCI_DEVICE_ID_AMD_RS780_PCIE_DEV8 0x960A + +#define PCI_DEVICE_ID_AMD_RD890TV_HT 0x5956 +#define PCI_DEVICE_ID_AMD_RX780_HT 0x5957 +#define PCI_DEVICE_ID_AMD_RD780_HT 0x5958 +#define PCI_DEVICE_ID_AMD_SR5690_HT 0x5A10 +#define PCI_DEVICE_ID_AMD_RD890_HT 0x5A11 +#define PCI_DEVICE_ID_AMD_SR5670_HT 0x5A12 +#define PCI_DEVICE_ID_AMD_SR5650_HT 0x5A13 +#define PCI_DEVICE_ID_AMD_990FX_HT 0x5A14 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE 0x5A12 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV2 0x5A16 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV3 0x5A17 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV4 0x5A18 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV5 0x5A19 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV6 0x5A1A +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV7 0x5A1B +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV9 0x5A1C +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV10 0x5A1D +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV11 0x5A1F +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV12 0x5A20 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13 0x5A1E +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21 +#define PCI_DEVICE_ID_AMD_SR5650_IOMMU 0x5A23 + +#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A +#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E +#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 +#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 +#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 +#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 +#define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 +#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B + +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP 0x15D3 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 0x1633 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2 0x1634 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA 0x15DB +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB 0x15DC +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC 0x1635 +#define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 +#define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI 0x1639 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3 0x15EB +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4 0x15EC +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5 0x15ED +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6 0x15EE +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF7 0x15EF +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0 0x1448 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1 0x1449 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2 0x144A +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3 0x144B +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4 0x144C +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5 0x144D +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6 0x144E +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7 0x144F +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0 0x166A +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1 0x166B +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2 0x166C +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3 0x166D +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4 0x166E +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5 0x166F +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6 0x1670 +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7 0x1671 +#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0 0x7901 +#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1 0x7904 +#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 +#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1 0x7917 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD 0x7906 +#define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B +#define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE 0x1641 +#define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97 0x1644 + #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 #define PCI_DEVICE_ID_AMD_LX 0x1054 From 5c78ff9b4a0eeb6332868f6df1ad7361d176706b Mon Sep 17 00:00:00 2001 From: Yongkun Yu Date: Tue, 19 Oct 2021 15:43:38 +0800 Subject: [PATCH 315/320] mb/google/dedede/var/blipper: Add fw_config probe for multi audio codec Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS" BUG=b:197694580 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Yongkun Yu Change-Id: I422f206b8f1f3705a65808041f1a1544c461b431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58449 Tested-by: build bot (Jenkins) Reviewed-by: Wentao Qin Reviewed-by: Karthik Ramasubramanian --- .../dedede/variants/blipper/overridetree.cb | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb index 7c4c83dff63..2a33a443209 100644 --- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb +++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end + chip soc/intel/jasperlake # Intel Common SoC Config @@ -171,7 +179,23 @@ chip soc/intel/jasperlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end end end # I2C 4 device pci 1f.3 on From cefee5e40f4e7567b25bce9df786a0fbf594a268 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 23 Oct 2021 00:43:07 +0200 Subject: [PATCH 316/320] soc/intel/quark/Kconfig: don't unselect CPU_X86_LAPIC The Intel Quark SoC does have a LAPIC on its x86 CPU core, so we should select CPU_X86_LAPIC. This will additionally include the Makefile from cpu/x86/lapic. Since none of AP_IN_SIPI_WAIT, LEGACY_SMP_INIT and UDELAY_LAPIC gets selected, only the boot_cpu.c and lapic.c targets will be added to the build. Since SMP isn't set, adding the boot_cpu.c target won't change the resulting binary of a timeless build, since the only function inside will be removed by the compiler's pre-processor in the !SMP case. So the only thing that will change the resulting binary is the addition of the lapic.c target. From this target only the function cpu_get_lapic_addr will be used which overrides the weak implementation in acpi/acpi.c. The call in arch/x86/mpspec.c can be ignored, since GENERATE_MP_TABLE isn't selected. So this change will result in the LAPIC address in the MADT being changed from 0 to to LAPIC_DEFAULT_BASE. Since the documentation of the Quark SoC mentions that it has a LAPIC on its one x86 core, this should work. TEST=None Signed-off-by: Felix Held Change-Id: I2f163bd608f0548abb0e8de90843d2a796b8ef6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58550 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons --- src/soc/intel/quark/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index bf9d475cd52..1a9bfef9429 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -24,10 +24,6 @@ config CPU_SPECIFIC_OPTIONS select USE_MARCH_586 select NO_SMM -config CPU_X86_LAPIC - bool - default n - ##### # Debug serial output # The following options configure the debug serial port From 39789eb6955040a26b5b9d7614790e565be2fada Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 23 Oct 2021 00:45:40 +0200 Subject: [PATCH 317/320] cpu/x86: drop CPU_X86_LAPIC Kconfig option All x86 CPUs in the coreboot tree have a local APIC, so the corresponding code can be unconditionally included in the build. Signed-off-by: Felix Held Change-Id: Ifc354fb386977b0fca4caa72c03aa77a20bc348e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58551 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/cpu/x86/Kconfig | 4 ---- src/cpu/x86/Makefile.inc | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index a2893255233..bae38891ad7 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -4,10 +4,6 @@ config CPU_X86_CACHE_HELPER help Add the x86_enable_cache ramstage helper function to the build. -config CPU_X86_LAPIC - bool - default y - config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index a6c51d023ab..19c9e03a021 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,5 +1,5 @@ subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache -subdirs-$(CONFIG_CPU_X86_LAPIC) += lapic +subdirs-y += lapic subdirs-y += mtrr subdirs-y += pae subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm From 761e2ae676e8f7e577dca710b4d574f46c54b203 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 23 Oct 2021 01:13:04 +0200 Subject: [PATCH 318/320] cpu/x86/Kconfig.debug_cpu: drop HAVE_DISPLAY_MTRRS option Since all x86 CPUs in tree have MTRR support, there is no need to guard the DISPLAY_MTRRS option with HAVE_DISPLAY_MTRRS. Also all x86 CPUs/SoCs have a display_mtrrs call at least somewhere in their code, so selecting the DISPLAY_MTRRS option will always have an effect. All SoCs that don't select RESET_VECTOR_IN_RAM have the postcar stage where it gets called. The two AMD SoCs that select RESET_VECTOR_IN_RAM use the FSP2 driver which contains plenty of display_mtrrs calls. Signed-off-by: Felix Held Change-Id: I2894689ce58e7404d9d5a894f3c288bc4016ea19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51575 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/cpu/intel/haswell/Kconfig | 1 - src/cpu/x86/Kconfig.debug_cpu | 4 ---- src/soc/intel/common/Kconfig.common | 1 - 3 files changed, 6 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 98303057834..4a7a7fd9a82 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select HAVE_ASAN_IN_ROMSTAGE - select HAVE_DISPLAY_MTRRS select CPU_INTEL_COMMON_VOLTAGE config SMM_TSEG_SIZE diff --git a/src/cpu/x86/Kconfig.debug_cpu b/src/cpu/x86/Kconfig.debug_cpu index 056934107cc..f8ed370486a 100644 --- a/src/cpu/x86/Kconfig.debug_cpu +++ b/src/cpu/x86/Kconfig.debug_cpu @@ -5,12 +5,8 @@ config DEBUG_CAR bool "Output verbose Cache-as-RAM debug messages" depends on HAVE_DEBUG_CAR -config HAVE_DISPLAY_MTRRS - bool - config DISPLAY_MTRRS bool "Display intermediate MTRR settings" - depends on HAVE_DISPLAY_MTRRS config DEBUG_SMM_RELOCATION bool "Debug SMM relocation code" diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index f39571ee442..5f1f608c4e4 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -1,7 +1,6 @@ config SOC_INTEL_COMMON bool select AZALIA_PLUGIN_SUPPORT - select HAVE_DISPLAY_MTRRS select ACPI_SOC_NVS help common code for Intel SOCs From 10796d8c1e446d677c563280f9d7ca1905218041 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 25 Oct 2021 17:52:49 +0200 Subject: [PATCH 319/320] src/cpu: drop CPU_X86_CACHE_HELPER and x86_enable_cache wrapper function Selecting CPU_X86_CACHE_HELPER only added the x86_enable_cache wrapper function around enable_cache which additionally wrote a POST code to port 0x80 and printed a message to the console. This function was only called during multi-processor initialization in ramstage via the init function pointer in the CPU's device operations struct and was run on all cores, so the message on the console was printed once per CPU core. This patch replaces all x86_enable_cache calls by calls to enable_cache and removes the wrapper function and the Kconfig symbol CPU_X86_CACHE_HELPER which was used to only add this when the corresponding CPUs used the x86_enable_cache wrapper function. Signed-off-by: Felix Held Suggested-by: Angel Pons Change-Id: I5866b6bf014821ff9e3a48052a5eaf69319b003a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58579 Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/family14/Kconfig | 1 - src/cpu/amd/agesa/family14/model_14_init.c | 2 +- src/cpu/amd/agesa/family15tn/Kconfig | 1 - src/cpu/amd/agesa/family15tn/model_15_init.c | 4 ++-- src/cpu/amd/agesa/family16kb/Kconfig | 1 - src/cpu/amd/agesa/family16kb/model_16_init.c | 4 ++-- src/cpu/intel/model_65x/Kconfig | 1 - src/cpu/intel/model_65x/model_65x_init.c | 2 +- src/cpu/intel/model_67x/Kconfig | 1 - src/cpu/intel/model_67x/model_67x_init.c | 2 +- src/cpu/intel/model_68x/Kconfig | 1 - src/cpu/intel/model_68x/model_68x_init.c | 2 +- src/cpu/intel/model_6bx/Kconfig | 1 - src/cpu/intel/model_6bx/model_6bx_init.c | 2 +- src/cpu/intel/model_6ex/Kconfig | 1 - src/cpu/intel/model_6ex/model_6ex_init.c | 2 +- src/cpu/intel/model_6fx/Kconfig | 1 - src/cpu/intel/model_6fx/model_6fx_init.c | 2 +- src/cpu/intel/model_6xx/Kconfig | 1 - src/cpu/intel/model_6xx/model_6xx_init.c | 2 +- src/cpu/intel/model_f2x/Kconfig | 1 - src/cpu/intel/model_f2x/model_f2x_init.c | 2 +- src/cpu/intel/model_f3x/Kconfig | 1 - src/cpu/intel/model_f3x/model_f3x_init.c | 2 +- src/cpu/intel/model_f4x/Kconfig | 1 - src/cpu/intel/model_f4x/model_f4x_init.c | 2 +- src/cpu/x86/Kconfig | 6 ------ src/cpu/x86/Makefile.inc | 1 - src/cpu/x86/cache/Makefile.inc | 1 - src/cpu/x86/cache/cache.c | 11 ----------- src/include/cpu/x86/cache.h | 2 -- 31 files changed, 15 insertions(+), 49 deletions(-) delete mode 100644 src/cpu/x86/cache/Makefile.inc delete mode 100644 src/cpu/x86/cache/cache.c diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index e617c19c8a7..103903fc1e4 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_AGESA_FAMILY14 bool select X86_AMD_FIXED_MTRRS - select CPU_X86_CACHE_HELPER if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 9539c3deefb..78234b663e7 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -54,7 +54,7 @@ static void model_14_init(struct device *dev) restore_mtrr(); x86_mtrr_check(); - x86_enable_cache(); + enable_cache(); /* zero the machine check error status registers */ mca_clear_status(); diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 68fd82cd6e9..8c52e9a9b66 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -4,7 +4,6 @@ config CPU_AMD_AGESA_FAMILY15_TN bool select IDS_OPTIONS_HOOKED_UP select X86_AMD_FIXED_MTRRS - select CPU_X86_CACHE_HELPER if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 9d4da761c64..245cdf34f9b 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -25,7 +25,7 @@ static void model_15_init(struct device *dev) u32 siblings; #endif - //x86_enable_cache(); + //enable_cache(); //amd_setup_mtrrs(); //x86_mtrr_check(); disable_cache(); @@ -53,7 +53,7 @@ static void model_15_init(struct device *dev) restore_mtrr(); x86_mtrr_check(); - x86_enable_cache(); + enable_cache(); /* zero the machine check error status registers */ mca_clear_status(); diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index ee568ece653..e41ddece4d6 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_AGESA_FAMILY16_KB bool select X86_AMD_FIXED_MTRRS - select CPU_X86_CACHE_HELPER if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 9fadc7e3e36..c86f8acdef9 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -23,7 +23,7 @@ static void model_16_init(struct device *dev) u32 siblings; #endif - //x86_enable_cache(); + //enable_cache(); //amd_setup_mtrrs(); //x86_mtrr_check(); disable_cache(); @@ -51,7 +51,7 @@ static void model_16_init(struct device *dev) restore_mtrr(); x86_mtrr_check(); - x86_enable_cache(); + enable_cache(); /* zero the machine check error status registers */ mca_clear_status(); diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index 42bdc3f3a8f..6d41d94f57d 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_65X bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index cf1394add89..9a17f7093f5 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -16,7 +16,7 @@ static void model_65x_init(struct device *dev) p6_configure_l2_cache(); /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index da57caa2da1..26a303be017 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_67X bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 427d6586829..6a2689ddb13 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -17,7 +17,7 @@ static void model_67x_init(struct device *cpu) p6_configure_l2_cache(); /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); /* Setup MTRRs */ x86_setup_mtrrs(); diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index 0ab1e7af515..796290770f2 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -4,4 +4,3 @@ config CPU_INTEL_MODEL_68X bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 3402c603e06..2344cb7e9ff 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -14,7 +14,7 @@ static void model_68x_init(struct device *cpu) char processor_name[49]; /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); /* Update the microcode */ intel_update_microcode_from_cbfs(); diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index cb9d6f36770..14274a32367 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_6BX bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index 2e7069c0a4e..f27a63ac508 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -14,7 +14,7 @@ static void model_6bx_init(struct device *cpu) char processor_name[49]; /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); /* Update the microcode */ intel_update_microcode_from_cbfs(); diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 37bfa14ad1c..c7d54c5f8c3 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -9,4 +9,3 @@ config CPU_INTEL_MODEL_6EX select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 16c6866f45f..34646ad5e9d 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -97,7 +97,7 @@ static void model_6ex_init(struct device *cpu) char processor_name[49]; /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 8e035608ad1..499972600a2 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -10,4 +10,3 @@ config CPU_INTEL_MODEL_6FX select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select SETUP_XIP_CACHE - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index d0987b4a63a..72ece23935d 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -111,7 +111,7 @@ static void model_6fx_init(struct device *cpu) char processor_name[49]; /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); /* Print processor name */ fill_processor_name(processor_name); diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index 95e175e0526..e05cf895173 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_6XX bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 2e93507b5b3..48a045ecc89 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -10,7 +10,7 @@ static void model_6xx_init(struct device *dev) { /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 3339b66b00a..672cf75517e 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -4,4 +4,3 @@ config CPU_INTEL_MODEL_F2X select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG select CPU_INTEL_COMMON - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index fc919a7cde9..9f365c6ebc4 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -12,7 +12,7 @@ static void model_f2x_init(struct device *cpu) { /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); if (!intel_ht_sibling()) { /* MTRRs are shared between threads */ diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 943d9cc155e..b0a9f7ce64d 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_F3X select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index bf08d7b23c5..ba3a4d60dad 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -12,7 +12,7 @@ static void model_f3x_init(struct device *cpu) { /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) { /* MTRRs are shared between threads */ diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 4dd40384fb2..550a978e855 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_F4X bool select ARCH_X86 select SUPPORT_CPU_UCODE_IN_CBFS - select CPU_X86_CACHE_HELPER diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 5ebddc06fe2..ee6761ed13f 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -8,7 +8,7 @@ static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ - x86_enable_cache(); + enable_cache(); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index bae38891ad7..fb5b5413b9b 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,9 +1,3 @@ -config CPU_X86_CACHE_HELPER - bool - default n - help - Add the x86_enable_cache ramstage helper function to the build. - config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 19c9e03a021..b9f6417a22b 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,4 +1,3 @@ -subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache subdirs-y += lapic subdirs-y += mtrr subdirs-y += pae diff --git a/src/cpu/x86/cache/Makefile.inc b/src/cpu/x86/cache/Makefile.inc deleted file mode 100644 index b33b9eeff03..00000000000 --- a/src/cpu/x86/cache/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-y += cache.c diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c deleted file mode 100644 index 7ed3866c93b..00000000000 --- a/src/cpu/x86/cache/cache.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void x86_enable_cache(void) -{ - post_code(POST_ENABLING_CACHE); - printk(BIOS_INFO, "Enabling cache\n"); - enable_cache(); -} diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 62341104a44..27b727bcb9f 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -56,7 +56,5 @@ static __always_inline void disable_cache(void) wbinvd(); } -void x86_enable_cache(void); - #endif /* !__ASSEMBLER__ */ #endif /* CPU_X86_CACHE */ From d06c09179a277a22ee3c14afe0e8f0c51ea74277 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 25 Oct 2021 15:47:39 -0700 Subject: [PATCH 320/320] intel/adlrvp: Add sub-regions to SI_ME in chromeos.fmd This change adds sub-regions to SI_ME in chromeos.fmd. These are required to support stitching of CSE components. BUG=b:189177538 Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/chromeos.fmd | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 28cda245e46..ef3320f746d 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -1,14 +1,20 @@ FLASH 32M { SI_ALL 6M { SI_DESC 4K - SI_ME + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1588K + CSE_DATA 512K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 4032K + } } SI_BIOS 26M { RW_SECTION_A 8M { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3M + ME_RW_A(CBFS) 4032K } RW_LEGACY(CBFS) 1M RW_MISC 1M { @@ -32,7 +38,7 @@ FLASH 32M { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3M + ME_RW_B(CBFS) 4032K } # Make WP_RO region align with SPI vendor # memory protected range specification.