From 02cc3fc83e884a1b02941bee37a1b676c915d415 Mon Sep 17 00:00:00 2001 From: Maxim Poliakovski Date: Wed, 24 Jan 2018 17:49:50 +0100 Subject: [PATCH] Minor spelling corrections. --- docs/ir-why-not.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/ir-why-not.md b/docs/ir-why-not.md index 9fd501d1..1c482f85 100644 --- a/docs/ir-why-not.md +++ b/docs/ir-why-not.md @@ -23,8 +23,8 @@ BinNavi REIL, Valgrind VEX -------------------------- All these decompiler IRs are designed with CISC X86 architecture in -mind, and take for granted that single machine instructions is -converted to number of IR instructions. That alone makes them not +mind, and take for granted that a single machine instructions will be +converted to several IR instructions. That alone makes them not human-friendly, but they also feature over-explicit, verbose syntax. VEX is [used by angr](https://docs.angr.io/docs/ir.html). They also @@ -124,7 +124,7 @@ Miasm IR https://github.com/cea-sec/miasm -Miasm has [own IR](https://github.com/cea-sec/miasm#intermediate-representation). +Miasm has its [own IR](https://github.com/cea-sec/miasm#intermediate-representation). References ----------