From 5bca4104ad79369472790b1668a8adf661c1bae3 Mon Sep 17 00:00:00 2001 From: WANG Xuerui Date: Wed, 29 Dec 2021 16:54:13 +0800 Subject: [PATCH] app-emulation/qemu: re-fork, tcg port is already upstream --- ...Add-machine-type-value-for-LoongArch.patch | 38 - ...dd-tcg-loongarch64-entry-with-myself.patch | 37 - ...oongarch64-Add-the-tcg-target.h-file.patch | 208 ---- ...64-Add-generated-instruction-opcodes.patch | 1001 ----------------- ...64-Add-register-names-allocation-ord.patch | 140 --- ...rch64-Define-the-operand-constraints.patch | 114 -- ...64-Implement-necessary-relocation-op.patch | 89 -- ...ch64-Implement-the-memory-barrier-op.patch | 58 - ...64-Implement-tcg_out_mov-and-tcg_out.patch | 170 --- ...0-tcg-loongarch64-Implement-goto_ptr.patch | 68 -- ...64-Implement-sign-zero-extension-ops.patch | 185 --- ...64-Implement-not-and-or-xor-nor-andc.patch | 186 --- ...arch64-Implement-deposit-extract-ops.patch | 97 -- ...garch64-Implement-bswap-16-32-64-ops.patch | 93 -- ...cg-loongarch64-Implement-clz-ctz-ops.patch | 119 -- ...64-Implement-shl-shr-sar-rotl-rotr-o.patch | 163 --- ...cg-loongarch64-Implement-add-sub-ops.patch | 98 -- ...64-Implement-mul-mulsh-muluh-div-div.patch | 161 --- ...-loongarch64-Implement-br-brcond-ops.patch | 109 -- ...cg-loongarch64-Implement-setcond-ops.patch | 121 -- ...g-loongarch64-Implement-tcg_out_call.patch | 66 -- ...ch64-Implement-simple-load-store-ops.patch | 194 ---- ...64-Add-softmmu-load-store-helpers-im.patch | 422 ------- ...64-Implement-tcg_target_qemu_prologu.patch | 97 -- ...oongarch64-Implement-exit_tb-goto_tb.patch | 44 - ...oongarch64-Implement-tcg_target_init.patch | 49 - ...027-tcg-loongarch64-Register-the-JIT.patch | 66 -- ...d-safe-syscall-handling-for-loongarc.patch | 144 --- ...r-exec-Implement-CPU-specific-signal.patch | 103 -- ...on.build-Mark-support-for-loongarch6.patch | 78 -- .../files/qemu-5.2.0-cleaner-werror.patch | 40 - .../qemu/files/qemu-5.2.0-dce-locks.patch | 18 - .../qemu/files/qemu-5.2.0-strings.patch | 23 - .../files/qemu-6.1.0-automagic-libbpf.patch | 21 + .../files/qemu-6.1.0-data-corruption.patch | 114 ++ .../qemu-6.1.0-fix-unix-socket-copy.patch | 76 ++ app-emulation/qemu/metadata.xml | 13 +- app-emulation/qemu/qemu-9999.ebuild | 35 +- 38 files changed, 221 insertions(+), 4637 deletions(-) delete mode 100644 app-emulation/qemu/files/loongarch/v6-0001-elf-Add-machine-type-value-for-LoongArch.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0002-MAINTAINERS-Add-tcg-loongarch64-entry-with-myself.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0003-tcg-loongarch64-Add-the-tcg-target.h-file.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0004-tcg-loongarch64-Add-generated-instruction-opcodes.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0005-tcg-loongarch64-Add-register-names-allocation-ord.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0006-tcg-loongarch64-Define-the-operand-constraints.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0007-tcg-loongarch64-Implement-necessary-relocation-op.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0008-tcg-loongarch64-Implement-the-memory-barrier-op.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0009-tcg-loongarch64-Implement-tcg_out_mov-and-tcg_out.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0010-tcg-loongarch64-Implement-goto_ptr.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0011-tcg-loongarch64-Implement-sign-zero-extension-ops.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0012-tcg-loongarch64-Implement-not-and-or-xor-nor-andc.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0013-tcg-loongarch64-Implement-deposit-extract-ops.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0014-tcg-loongarch64-Implement-bswap-16-32-64-ops.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0015-tcg-loongarch64-Implement-clz-ctz-ops.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0016-tcg-loongarch64-Implement-shl-shr-sar-rotl-rotr-o.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0017-tcg-loongarch64-Implement-add-sub-ops.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0018-tcg-loongarch64-Implement-mul-mulsh-muluh-div-div.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0019-tcg-loongarch64-Implement-br-brcond-ops.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0020-tcg-loongarch64-Implement-setcond-ops.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0021-tcg-loongarch64-Implement-tcg_out_call.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0022-tcg-loongarch64-Implement-simple-load-store-ops.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0023-tcg-loongarch64-Add-softmmu-load-store-helpers-im.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0024-tcg-loongarch64-Implement-tcg_target_qemu_prologu.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0025-tcg-loongarch64-Implement-exit_tb-goto_tb.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0026-tcg-loongarch64-Implement-tcg_target_init.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0027-tcg-loongarch64-Register-the-JIT.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0028-linux-user-Add-safe-syscall-handling-for-loongarc.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0029-accel-tcg-user-exec-Implement-CPU-specific-signal.patch delete mode 100644 app-emulation/qemu/files/loongarch/v6-0030-configure-meson.build-Mark-support-for-loongarch6.patch delete mode 100644 app-emulation/qemu/files/qemu-5.2.0-cleaner-werror.patch delete mode 100644 app-emulation/qemu/files/qemu-5.2.0-dce-locks.patch delete mode 100644 app-emulation/qemu/files/qemu-5.2.0-strings.patch create mode 100644 app-emulation/qemu/files/qemu-6.1.0-automagic-libbpf.patch create mode 100644 app-emulation/qemu/files/qemu-6.1.0-data-corruption.patch create mode 100644 app-emulation/qemu/files/qemu-6.1.0-fix-unix-socket-copy.patch diff --git a/app-emulation/qemu/files/loongarch/v6-0001-elf-Add-machine-type-value-for-LoongArch.patch b/app-emulation/qemu/files/loongarch/v6-0001-elf-Add-machine-type-value-for-LoongArch.patch deleted file mode 100644 index adf679d..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0001-elf-Add-machine-type-value-for-LoongArch.patch +++ /dev/null @@ -1,38 +0,0 @@ -From c41357070892b1a28a9285f542240acf1278c048 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 19:51:29 +0800 -Subject: [PATCH v6 01/30] elf: Add machine type value for LoongArch -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This is already officially allocated as recorded in GNU binutils -repo [1], and the description is updated in [2]. Add to enable further -work. - -[1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4cf2ad720078a9f490dd5b5bc8893a926479196e -[2]: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=01a8c731aacbdbed0eb5682d13cc074dc7e25fb3 - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - include/elf.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/elf.h b/include/elf.h -index 811bf4a1cb..3a4bcb646a 100644 ---- a/include/elf.h -+++ b/include/elf.h -@@ -182,6 +182,8 @@ typedef struct mips_elf_abiflags_v0 { - - #define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */ - -+#define EM_LOONGARCH 258 /* LoongArch */ -+ - /* - * This is an interim value that we will use until the committee comes - * up with a final number. --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0002-MAINTAINERS-Add-tcg-loongarch64-entry-with-myself.patch b/app-emulation/qemu/files/loongarch/v6-0002-MAINTAINERS-Add-tcg-loongarch64-entry-with-myself.patch deleted file mode 100644 index 5822974..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0002-MAINTAINERS-Add-tcg-loongarch64-entry-with-myself.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 74d9f923f3a85c92b7b7c91b08e7ca4f5110bccb Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 21:39:21 +0800 -Subject: [PATCH v6 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself - as maintainer -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -I ported the initial code, so I should maintain it of course. - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - MAINTAINERS | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/MAINTAINERS b/MAINTAINERS -index d7915ec128..859e5b5ba2 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3114,6 +3114,11 @@ S: Maintained - F: tcg/i386/ - F: disas/i386.c - -+LoongArch64 TCG target -+M: WANG Xuerui -+S: Maintained -+F: tcg/loongarch64/ -+ - MIPS TCG target - M: Philippe Mathieu-Daudé - R: Aurelien Jarno --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0003-tcg-loongarch64-Add-the-tcg-target.h-file.patch b/app-emulation/qemu/files/loongarch/v6-0003-tcg-loongarch64-Add-the-tcg-target.h-file.patch deleted file mode 100644 index af122b8..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0003-tcg-loongarch64-Add-the-tcg-target.h-file.patch +++ /dev/null @@ -1,208 +0,0 @@ -From 9dfcba482baf958c484e4f93da34c97e665e286a Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 21:55:01 +0800 -Subject: [PATCH v6 03/30] tcg/loongarch64: Add the tcg-target.h file -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Support for all optional TCG ops are initially marked disabled; the bits -are to be set in individual commits later. - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target.h | 180 +++++++++++++++++++++++++++++++++++ - 1 file changed, 180 insertions(+) - create mode 100644 tcg/loongarch64/tcg-target.h - -diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h -new file mode 100644 -index 0000000000..5fc097b3c1 ---- /dev/null -+++ b/tcg/loongarch64/tcg-target.h -@@ -0,0 +1,180 @@ -+/* -+ * Tiny Code Generator for QEMU -+ * -+ * Copyright (c) 2021 WANG Xuerui -+ * -+ * Based on tcg/riscv/tcg-target.h -+ * -+ * Copyright (c) 2018 SiFive, Inc -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a copy -+ * of this software and associated documentation files (the "Software"), to deal -+ * in the Software without restriction, including without limitation the rights -+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -+ * copies of the Software, and to permit persons to whom the Software is -+ * furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -+ * THE SOFTWARE. -+ */ -+ -+#ifndef LOONGARCH_TCG_TARGET_H -+#define LOONGARCH_TCG_TARGET_H -+ -+/* -+ * Loongson removed the (incomplete) 32-bit support from kernel and toolchain -+ * for the initial upstreaming of this architecture, so don't bother and just -+ * support the LP64 ABI for now. -+ */ -+#if defined(__loongarch64) -+# define TCG_TARGET_REG_BITS 64 -+#else -+# error unsupported LoongArch register size -+#endif -+ -+#define TCG_TARGET_INSN_UNIT_SIZE 4 -+#define TCG_TARGET_NB_REGS 32 -+#define MAX_CODE_GEN_BUFFER_SIZE SIZE_MAX -+ -+typedef enum { -+ TCG_REG_ZERO, -+ TCG_REG_RA, -+ TCG_REG_TP, -+ TCG_REG_SP, -+ TCG_REG_A0, -+ TCG_REG_A1, -+ TCG_REG_A2, -+ TCG_REG_A3, -+ TCG_REG_A4, -+ TCG_REG_A5, -+ TCG_REG_A6, -+ TCG_REG_A7, -+ TCG_REG_T0, -+ TCG_REG_T1, -+ TCG_REG_T2, -+ TCG_REG_T3, -+ TCG_REG_T4, -+ TCG_REG_T5, -+ TCG_REG_T6, -+ TCG_REG_T7, -+ TCG_REG_T8, -+ TCG_REG_RESERVED, -+ TCG_REG_S9, -+ TCG_REG_S0, -+ TCG_REG_S1, -+ TCG_REG_S2, -+ TCG_REG_S3, -+ TCG_REG_S4, -+ TCG_REG_S5, -+ TCG_REG_S6, -+ TCG_REG_S7, -+ TCG_REG_S8, -+ -+ /* aliases */ -+ TCG_AREG0 = TCG_REG_S0, -+ TCG_REG_TMP0 = TCG_REG_T8, -+ TCG_REG_TMP1 = TCG_REG_T7, -+ TCG_REG_TMP2 = TCG_REG_T6, -+} TCGReg; -+ -+/* used for function call generation */ -+#define TCG_REG_CALL_STACK TCG_REG_SP -+#define TCG_TARGET_STACK_ALIGN 16 -+#define TCG_TARGET_CALL_ALIGN_ARGS 1 -+#define TCG_TARGET_CALL_STACK_OFFSET 0 -+ -+/* optional instructions */ -+#define TCG_TARGET_HAS_movcond_i32 0 -+#define TCG_TARGET_HAS_div_i32 0 -+#define TCG_TARGET_HAS_rem_i32 0 -+#define TCG_TARGET_HAS_div2_i32 0 -+#define TCG_TARGET_HAS_rot_i32 0 -+#define TCG_TARGET_HAS_deposit_i32 0 -+#define TCG_TARGET_HAS_extract_i32 0 -+#define TCG_TARGET_HAS_sextract_i32 0 -+#define TCG_TARGET_HAS_extract2_i32 0 -+#define TCG_TARGET_HAS_add2_i32 0 -+#define TCG_TARGET_HAS_sub2_i32 0 -+#define TCG_TARGET_HAS_mulu2_i32 0 -+#define TCG_TARGET_HAS_muls2_i32 0 -+#define TCG_TARGET_HAS_muluh_i32 0 -+#define TCG_TARGET_HAS_mulsh_i32 0 -+#define TCG_TARGET_HAS_ext8s_i32 0 -+#define TCG_TARGET_HAS_ext16s_i32 0 -+#define TCG_TARGET_HAS_ext8u_i32 0 -+#define TCG_TARGET_HAS_ext16u_i32 0 -+#define TCG_TARGET_HAS_bswap16_i32 0 -+#define TCG_TARGET_HAS_bswap32_i32 0 -+#define TCG_TARGET_HAS_not_i32 0 -+#define TCG_TARGET_HAS_neg_i32 0 -+#define TCG_TARGET_HAS_andc_i32 0 -+#define TCG_TARGET_HAS_orc_i32 0 -+#define TCG_TARGET_HAS_eqv_i32 0 -+#define TCG_TARGET_HAS_nand_i32 0 -+#define TCG_TARGET_HAS_nor_i32 0 -+#define TCG_TARGET_HAS_clz_i32 0 -+#define TCG_TARGET_HAS_ctz_i32 0 -+#define TCG_TARGET_HAS_ctpop_i32 0 -+#define TCG_TARGET_HAS_direct_jump 0 -+#define TCG_TARGET_HAS_brcond2 0 -+#define TCG_TARGET_HAS_setcond2 0 -+#define TCG_TARGET_HAS_qemu_st8_i32 0 -+ -+/* 64-bit operations */ -+#define TCG_TARGET_HAS_movcond_i64 0 -+#define TCG_TARGET_HAS_div_i64 0 -+#define TCG_TARGET_HAS_rem_i64 0 -+#define TCG_TARGET_HAS_div2_i64 0 -+#define TCG_TARGET_HAS_rot_i64 0 -+#define TCG_TARGET_HAS_deposit_i64 0 -+#define TCG_TARGET_HAS_extract_i64 0 -+#define TCG_TARGET_HAS_sextract_i64 0 -+#define TCG_TARGET_HAS_extract2_i64 0 -+#define TCG_TARGET_HAS_extrl_i64_i32 0 -+#define TCG_TARGET_HAS_extrh_i64_i32 0 -+#define TCG_TARGET_HAS_ext8s_i64 0 -+#define TCG_TARGET_HAS_ext16s_i64 0 -+#define TCG_TARGET_HAS_ext32s_i64 0 -+#define TCG_TARGET_HAS_ext8u_i64 0 -+#define TCG_TARGET_HAS_ext16u_i64 0 -+#define TCG_TARGET_HAS_ext32u_i64 0 -+#define TCG_TARGET_HAS_bswap16_i64 0 -+#define TCG_TARGET_HAS_bswap32_i64 0 -+#define TCG_TARGET_HAS_bswap64_i64 0 -+#define TCG_TARGET_HAS_not_i64 0 -+#define TCG_TARGET_HAS_neg_i64 0 -+#define TCG_TARGET_HAS_andc_i64 0 -+#define TCG_TARGET_HAS_orc_i64 0 -+#define TCG_TARGET_HAS_eqv_i64 0 -+#define TCG_TARGET_HAS_nand_i64 0 -+#define TCG_TARGET_HAS_nor_i64 0 -+#define TCG_TARGET_HAS_clz_i64 0 -+#define TCG_TARGET_HAS_ctz_i64 0 -+#define TCG_TARGET_HAS_ctpop_i64 0 -+#define TCG_TARGET_HAS_add2_i64 0 -+#define TCG_TARGET_HAS_sub2_i64 0 -+#define TCG_TARGET_HAS_mulu2_i64 0 -+#define TCG_TARGET_HAS_muls2_i64 0 -+#define TCG_TARGET_HAS_muluh_i64 0 -+#define TCG_TARGET_HAS_mulsh_i64 0 -+ -+/* not defined -- call should be eliminated at compile time */ -+void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); -+ -+#define TCG_TARGET_DEFAULT_MO (0) -+ -+#ifdef CONFIG_SOFTMMU -+#define TCG_TARGET_NEED_LDST_LABELS -+#endif -+ -+#define TCG_TARGET_HAS_MEMORY_BSWAP 0 -+ -+#endif /* LOONGARCH_TCG_TARGET_H */ --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0004-tcg-loongarch64-Add-generated-instruction-opcodes.patch b/app-emulation/qemu/files/loongarch/v6-0004-tcg-loongarch64-Add-generated-instruction-opcodes.patch deleted file mode 100644 index 38bbcaf..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0004-tcg-loongarch64-Add-generated-instruction-opcodes.patch +++ /dev/null @@ -1,1001 +0,0 @@ -From a0b41af7113d75b8571aed5a31d0b18aec372111 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 23:17:30 +0800 -Subject: [PATCH v6 04/30] tcg/loongarch64: Add generated instruction opcodes - and encoding helpers - -Signed-off-by: WANG Xuerui -Acked-by: Richard Henderson ---- - tcg/loongarch64/tcg-insn-defs.c.inc | 979 ++++++++++++++++++++++++++++ - 1 file changed, 979 insertions(+) - create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc - -diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn-defs.c.inc -new file mode 100644 -index 0000000000..d162571856 ---- /dev/null -+++ b/tcg/loongarch64/tcg-insn-defs.c.inc -@@ -0,0 +1,979 @@ -+/* SPDX-License-Identifier: MIT */ -+/* -+ * LoongArch instruction formats, opcodes, and encoders for TCG use. -+ * -+ * This file is auto-generated by genqemutcgdefs from -+ * https://github.com/loongson-community/loongarch-opcodes, -+ * from commit 961f0c60f5b63e574d785995600c71ad5413fdc4. -+ * DO NOT EDIT. -+ */ -+ -+typedef enum { -+ OPC_CLZ_W = 0x00001400, -+ OPC_CTZ_W = 0x00001c00, -+ OPC_CLZ_D = 0x00002400, -+ OPC_CTZ_D = 0x00002c00, -+ OPC_REVB_2H = 0x00003000, -+ OPC_REVB_2W = 0x00003800, -+ OPC_REVB_D = 0x00003c00, -+ OPC_SEXT_H = 0x00005800, -+ OPC_SEXT_B = 0x00005c00, -+ OPC_ADD_W = 0x00100000, -+ OPC_ADD_D = 0x00108000, -+ OPC_SUB_W = 0x00110000, -+ OPC_SUB_D = 0x00118000, -+ OPC_SLT = 0x00120000, -+ OPC_SLTU = 0x00128000, -+ OPC_MASKEQZ = 0x00130000, -+ OPC_MASKNEZ = 0x00138000, -+ OPC_NOR = 0x00140000, -+ OPC_AND = 0x00148000, -+ OPC_OR = 0x00150000, -+ OPC_XOR = 0x00158000, -+ OPC_ORN = 0x00160000, -+ OPC_ANDN = 0x00168000, -+ OPC_SLL_W = 0x00170000, -+ OPC_SRL_W = 0x00178000, -+ OPC_SRA_W = 0x00180000, -+ OPC_SLL_D = 0x00188000, -+ OPC_SRL_D = 0x00190000, -+ OPC_SRA_D = 0x00198000, -+ OPC_ROTR_W = 0x001b0000, -+ OPC_ROTR_D = 0x001b8000, -+ OPC_MUL_W = 0x001c0000, -+ OPC_MULH_W = 0x001c8000, -+ OPC_MULH_WU = 0x001d0000, -+ OPC_MUL_D = 0x001d8000, -+ OPC_MULH_D = 0x001e0000, -+ OPC_MULH_DU = 0x001e8000, -+ OPC_DIV_W = 0x00200000, -+ OPC_MOD_W = 0x00208000, -+ OPC_DIV_WU = 0x00210000, -+ OPC_MOD_WU = 0x00218000, -+ OPC_DIV_D = 0x00220000, -+ OPC_MOD_D = 0x00228000, -+ OPC_DIV_DU = 0x00230000, -+ OPC_MOD_DU = 0x00238000, -+ OPC_SLLI_W = 0x00408000, -+ OPC_SLLI_D = 0x00410000, -+ OPC_SRLI_W = 0x00448000, -+ OPC_SRLI_D = 0x00450000, -+ OPC_SRAI_W = 0x00488000, -+ OPC_SRAI_D = 0x00490000, -+ OPC_ROTRI_W = 0x004c8000, -+ OPC_ROTRI_D = 0x004d0000, -+ OPC_BSTRINS_W = 0x00600000, -+ OPC_BSTRPICK_W = 0x00608000, -+ OPC_BSTRINS_D = 0x00800000, -+ OPC_BSTRPICK_D = 0x00c00000, -+ OPC_SLTI = 0x02000000, -+ OPC_SLTUI = 0x02400000, -+ OPC_ADDI_W = 0x02800000, -+ OPC_ADDI_D = 0x02c00000, -+ OPC_CU52I_D = 0x03000000, -+ OPC_ANDI = 0x03400000, -+ OPC_ORI = 0x03800000, -+ OPC_XORI = 0x03c00000, -+ OPC_LU12I_W = 0x14000000, -+ OPC_CU32I_D = 0x16000000, -+ OPC_PCADDU2I = 0x18000000, -+ OPC_PCALAU12I = 0x1a000000, -+ OPC_PCADDU12I = 0x1c000000, -+ OPC_PCADDU18I = 0x1e000000, -+ OPC_LD_B = 0x28000000, -+ OPC_LD_H = 0x28400000, -+ OPC_LD_W = 0x28800000, -+ OPC_LD_D = 0x28c00000, -+ OPC_ST_B = 0x29000000, -+ OPC_ST_H = 0x29400000, -+ OPC_ST_W = 0x29800000, -+ OPC_ST_D = 0x29c00000, -+ OPC_LD_BU = 0x2a000000, -+ OPC_LD_HU = 0x2a400000, -+ OPC_LD_WU = 0x2a800000, -+ OPC_LDX_B = 0x38000000, -+ OPC_LDX_H = 0x38040000, -+ OPC_LDX_W = 0x38080000, -+ OPC_LDX_D = 0x380c0000, -+ OPC_STX_B = 0x38100000, -+ OPC_STX_H = 0x38140000, -+ OPC_STX_W = 0x38180000, -+ OPC_STX_D = 0x381c0000, -+ OPC_LDX_BU = 0x38200000, -+ OPC_LDX_HU = 0x38240000, -+ OPC_LDX_WU = 0x38280000, -+ OPC_DBAR = 0x38720000, -+ OPC_JIRL = 0x4c000000, -+ OPC_B = 0x50000000, -+ OPC_BL = 0x54000000, -+ OPC_BEQ = 0x58000000, -+ OPC_BNE = 0x5c000000, -+ OPC_BGT = 0x60000000, -+ OPC_BLE = 0x64000000, -+ OPC_BGTU = 0x68000000, -+ OPC_BLEU = 0x6c000000, -+} LoongArchInsn; -+ -+static int32_t __attribute__((unused)) -+encode_d_slot(LoongArchInsn opc, uint32_t d) -+{ -+ return opc | d; -+} -+ -+static int32_t __attribute__((unused)) -+encode_dj_slots(LoongArchInsn opc, uint32_t d, uint32_t j) -+{ -+ return opc | d | j << 5; -+} -+ -+static int32_t __attribute__((unused)) -+encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k) -+{ -+ return opc | d | j << 5 | k << 10; -+} -+ -+static int32_t __attribute__((unused)) -+encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k, -+ uint32_t m) -+{ -+ return opc | d | j << 5 | k << 10 | m << 16; -+} -+ -+static int32_t __attribute__((unused)) -+encode_dk_slots(LoongArchInsn opc, uint32_t d, uint32_t k) -+{ -+ return opc | d | k << 10; -+} -+ -+static int32_t __attribute__((unused)) -+encode_dj_insn(LoongArchInsn opc, TCGReg d, TCGReg j) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(j >= 0 && j <= 0x1f); -+ return encode_dj_slots(opc, d, j); -+} -+ -+static int32_t __attribute__((unused)) -+encode_djk_insn(LoongArchInsn opc, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(j >= 0 && j <= 0x1f); -+ tcg_debug_assert(k >= 0 && k <= 0x1f); -+ return encode_djk_slots(opc, d, j, k); -+} -+ -+static int32_t __attribute__((unused)) -+encode_djsk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(j >= 0 && j <= 0x1f); -+ tcg_debug_assert(sk12 >= -0x800 && sk12 <= 0x7ff); -+ return encode_djk_slots(opc, d, j, sk12 & 0xfff); -+} -+ -+static int32_t __attribute__((unused)) -+encode_djsk16_insn(LoongArchInsn opc, TCGReg d, TCGReg j, int32_t sk16) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(j >= 0 && j <= 0x1f); -+ tcg_debug_assert(sk16 >= -0x8000 && sk16 <= 0x7fff); -+ return encode_djk_slots(opc, d, j, sk16 & 0xffff); -+} -+ -+static int32_t __attribute__((unused)) -+encode_djuk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk12) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(j >= 0 && j <= 0x1f); -+ tcg_debug_assert(uk12 <= 0xfff); -+ return encode_djk_slots(opc, d, j, uk12); -+} -+ -+static int32_t __attribute__((unused)) -+encode_djuk5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk5) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(j >= 0 && j <= 0x1f); -+ tcg_debug_assert(uk5 <= 0x1f); -+ return encode_djk_slots(opc, d, j, uk5); -+} -+ -+static int32_t __attribute__((unused)) -+encode_djuk5um5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk5, -+ uint32_t um5) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(j >= 0 && j <= 0x1f); -+ tcg_debug_assert(uk5 <= 0x1f); -+ tcg_debug_assert(um5 <= 0x1f); -+ return encode_djkm_slots(opc, d, j, uk5, um5); -+} -+ -+static int32_t __attribute__((unused)) -+encode_djuk6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(j >= 0 && j <= 0x1f); -+ tcg_debug_assert(uk6 <= 0x3f); -+ return encode_djk_slots(opc, d, j, uk6); -+} -+ -+static int32_t __attribute__((unused)) -+encode_djuk6um6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6, -+ uint32_t um6) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(j >= 0 && j <= 0x1f); -+ tcg_debug_assert(uk6 <= 0x3f); -+ tcg_debug_assert(um6 <= 0x3f); -+ return encode_djkm_slots(opc, d, j, uk6, um6); -+} -+ -+static int32_t __attribute__((unused)) -+encode_dsj20_insn(LoongArchInsn opc, TCGReg d, int32_t sj20) -+{ -+ tcg_debug_assert(d >= 0 && d <= 0x1f); -+ tcg_debug_assert(sj20 >= -0x80000 && sj20 <= 0x7ffff); -+ return encode_dj_slots(opc, d, sj20 & 0xfffff); -+} -+ -+static int32_t __attribute__((unused)) -+encode_sd10k16_insn(LoongArchInsn opc, int32_t sd10k16) -+{ -+ tcg_debug_assert(sd10k16 >= -0x2000000 && sd10k16 <= 0x1ffffff); -+ return encode_dk_slots(opc, (sd10k16 >> 16) & 0x3ff, sd10k16 & 0xffff); -+} -+ -+static int32_t __attribute__((unused)) -+encode_ud15_insn(LoongArchInsn opc, uint32_t ud15) -+{ -+ tcg_debug_assert(ud15 <= 0x7fff); -+ return encode_d_slot(opc, ud15); -+} -+ -+/* Emits the `clz.w d, j` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_clz_w(TCGContext *s, TCGReg d, TCGReg j) -+{ -+ tcg_out32(s, encode_dj_insn(OPC_CLZ_W, d, j)); -+} -+ -+/* Emits the `ctz.w d, j` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ctz_w(TCGContext *s, TCGReg d, TCGReg j) -+{ -+ tcg_out32(s, encode_dj_insn(OPC_CTZ_W, d, j)); -+} -+ -+/* Emits the `clz.d d, j` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_clz_d(TCGContext *s, TCGReg d, TCGReg j) -+{ -+ tcg_out32(s, encode_dj_insn(OPC_CLZ_D, d, j)); -+} -+ -+/* Emits the `ctz.d d, j` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ctz_d(TCGContext *s, TCGReg d, TCGReg j) -+{ -+ tcg_out32(s, encode_dj_insn(OPC_CTZ_D, d, j)); -+} -+ -+/* Emits the `revb.2h d, j` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_revb_2h(TCGContext *s, TCGReg d, TCGReg j) -+{ -+ tcg_out32(s, encode_dj_insn(OPC_REVB_2H, d, j)); -+} -+ -+/* Emits the `revb.2w d, j` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_revb_2w(TCGContext *s, TCGReg d, TCGReg j) -+{ -+ tcg_out32(s, encode_dj_insn(OPC_REVB_2W, d, j)); -+} -+ -+/* Emits the `revb.d d, j` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_revb_d(TCGContext *s, TCGReg d, TCGReg j) -+{ -+ tcg_out32(s, encode_dj_insn(OPC_REVB_D, d, j)); -+} -+ -+/* Emits the `sext.h d, j` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sext_h(TCGContext *s, TCGReg d, TCGReg j) -+{ -+ tcg_out32(s, encode_dj_insn(OPC_SEXT_H, d, j)); -+} -+ -+/* Emits the `sext.b d, j` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sext_b(TCGContext *s, TCGReg d, TCGReg j) -+{ -+ tcg_out32(s, encode_dj_insn(OPC_SEXT_B, d, j)); -+} -+ -+/* Emits the `add.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_add_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_ADD_W, d, j, k)); -+} -+ -+/* Emits the `add.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_add_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_ADD_D, d, j, k)); -+} -+ -+/* Emits the `sub.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sub_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SUB_W, d, j, k)); -+} -+ -+/* Emits the `sub.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sub_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SUB_D, d, j, k)); -+} -+ -+/* Emits the `slt d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_slt(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SLT, d, j, k)); -+} -+ -+/* Emits the `sltu d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sltu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SLTU, d, j, k)); -+} -+ -+/* Emits the `maskeqz d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_maskeqz(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MASKEQZ, d, j, k)); -+} -+ -+/* Emits the `masknez d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_masknez(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MASKNEZ, d, j, k)); -+} -+ -+/* Emits the `nor d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_nor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_NOR, d, j, k)); -+} -+ -+/* Emits the `and d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_and(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_AND, d, j, k)); -+} -+ -+/* Emits the `or d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_or(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_OR, d, j, k)); -+} -+ -+/* Emits the `xor d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_xor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_XOR, d, j, k)); -+} -+ -+/* Emits the `orn d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_orn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_ORN, d, j, k)); -+} -+ -+/* Emits the `andn d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_andn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_ANDN, d, j, k)); -+} -+ -+/* Emits the `sll.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sll_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SLL_W, d, j, k)); -+} -+ -+/* Emits the `srl.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_srl_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SRL_W, d, j, k)); -+} -+ -+/* Emits the `sra.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sra_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SRA_W, d, j, k)); -+} -+ -+/* Emits the `sll.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sll_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SLL_D, d, j, k)); -+} -+ -+/* Emits the `srl.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_srl_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SRL_D, d, j, k)); -+} -+ -+/* Emits the `sra.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sra_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_SRA_D, d, j, k)); -+} -+ -+/* Emits the `rotr.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_rotr_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_ROTR_W, d, j, k)); -+} -+ -+/* Emits the `rotr.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_rotr_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_ROTR_D, d, j, k)); -+} -+ -+/* Emits the `mul.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mul_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MUL_W, d, j, k)); -+} -+ -+/* Emits the `mulh.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mulh_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MULH_W, d, j, k)); -+} -+ -+/* Emits the `mulh.wu d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mulh_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MULH_WU, d, j, k)); -+} -+ -+/* Emits the `mul.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mul_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MUL_D, d, j, k)); -+} -+ -+/* Emits the `mulh.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mulh_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MULH_D, d, j, k)); -+} -+ -+/* Emits the `mulh.du d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mulh_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MULH_DU, d, j, k)); -+} -+ -+/* Emits the `div.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_div_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_DIV_W, d, j, k)); -+} -+ -+/* Emits the `mod.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mod_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MOD_W, d, j, k)); -+} -+ -+/* Emits the `div.wu d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_div_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_DIV_WU, d, j, k)); -+} -+ -+/* Emits the `mod.wu d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mod_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MOD_WU, d, j, k)); -+} -+ -+/* Emits the `div.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_div_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_DIV_D, d, j, k)); -+} -+ -+/* Emits the `mod.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mod_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MOD_D, d, j, k)); -+} -+ -+/* Emits the `div.du d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_div_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_DIV_DU, d, j, k)); -+} -+ -+/* Emits the `mod.du d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_mod_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_MOD_DU, d, j, k)); -+} -+ -+/* Emits the `slli.w d, j, uk5` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_slli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) -+{ -+ tcg_out32(s, encode_djuk5_insn(OPC_SLLI_W, d, j, uk5)); -+} -+ -+/* Emits the `slli.d d, j, uk6` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_slli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) -+{ -+ tcg_out32(s, encode_djuk6_insn(OPC_SLLI_D, d, j, uk6)); -+} -+ -+/* Emits the `srli.w d, j, uk5` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_srli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) -+{ -+ tcg_out32(s, encode_djuk5_insn(OPC_SRLI_W, d, j, uk5)); -+} -+ -+/* Emits the `srli.d d, j, uk6` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_srli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) -+{ -+ tcg_out32(s, encode_djuk6_insn(OPC_SRLI_D, d, j, uk6)); -+} -+ -+/* Emits the `srai.w d, j, uk5` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_srai_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) -+{ -+ tcg_out32(s, encode_djuk5_insn(OPC_SRAI_W, d, j, uk5)); -+} -+ -+/* Emits the `srai.d d, j, uk6` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_srai_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) -+{ -+ tcg_out32(s, encode_djuk6_insn(OPC_SRAI_D, d, j, uk6)); -+} -+ -+/* Emits the `rotri.w d, j, uk5` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_rotri_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5) -+{ -+ tcg_out32(s, encode_djuk5_insn(OPC_ROTRI_W, d, j, uk5)); -+} -+ -+/* Emits the `rotri.d d, j, uk6` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_rotri_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6) -+{ -+ tcg_out32(s, encode_djuk6_insn(OPC_ROTRI_D, d, j, uk6)); -+} -+ -+/* Emits the `bstrins.w d, j, uk5, um5` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_bstrins_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5, -+ uint32_t um5) -+{ -+ tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRINS_W, d, j, uk5, um5)); -+} -+ -+/* Emits the `bstrpick.w d, j, uk5, um5` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_bstrpick_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5, -+ uint32_t um5) -+{ -+ tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRPICK_W, d, j, uk5, um5)); -+} -+ -+/* Emits the `bstrins.d d, j, uk6, um6` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_bstrins_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6, -+ uint32_t um6) -+{ -+ tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRINS_D, d, j, uk6, um6)); -+} -+ -+/* Emits the `bstrpick.d d, j, uk6, um6` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_bstrpick_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6, -+ uint32_t um6) -+{ -+ tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRPICK_D, d, j, uk6, um6)); -+} -+ -+/* Emits the `slti d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_slti(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_SLTI, d, j, sk12)); -+} -+ -+/* Emits the `sltui d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_sltui(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_SLTUI, d, j, sk12)); -+} -+ -+/* Emits the `addi.w d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_addi_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_ADDI_W, d, j, sk12)); -+} -+ -+/* Emits the `addi.d d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_addi_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_ADDI_D, d, j, sk12)); -+} -+ -+/* Emits the `cu52i.d d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_cu52i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_CU52I_D, d, j, sk12)); -+} -+ -+/* Emits the `andi d, j, uk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_andi(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) -+{ -+ tcg_out32(s, encode_djuk12_insn(OPC_ANDI, d, j, uk12)); -+} -+ -+/* Emits the `ori d, j, uk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) -+{ -+ tcg_out32(s, encode_djuk12_insn(OPC_ORI, d, j, uk12)); -+} -+ -+/* Emits the `xori d, j, uk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_xori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12) -+{ -+ tcg_out32(s, encode_djuk12_insn(OPC_XORI, d, j, uk12)); -+} -+ -+/* Emits the `lu12i.w d, sj20` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, int32_t sj20) -+{ -+ tcg_out32(s, encode_dsj20_insn(OPC_LU12I_W, d, sj20)); -+} -+ -+/* Emits the `cu32i.d d, sj20` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_cu32i_d(TCGContext *s, TCGReg d, int32_t sj20) -+{ -+ tcg_out32(s, encode_dsj20_insn(OPC_CU32I_D, d, sj20)); -+} -+ -+/* Emits the `pcaddu2i d, sj20` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_pcaddu2i(TCGContext *s, TCGReg d, int32_t sj20) -+{ -+ tcg_out32(s, encode_dsj20_insn(OPC_PCADDU2I, d, sj20)); -+} -+ -+/* Emits the `pcalau12i d, sj20` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_pcalau12i(TCGContext *s, TCGReg d, int32_t sj20) -+{ -+ tcg_out32(s, encode_dsj20_insn(OPC_PCALAU12I, d, sj20)); -+} -+ -+/* Emits the `pcaddu12i d, sj20` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_pcaddu12i(TCGContext *s, TCGReg d, int32_t sj20) -+{ -+ tcg_out32(s, encode_dsj20_insn(OPC_PCADDU12I, d, sj20)); -+} -+ -+/* Emits the `pcaddu18i d, sj20` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_pcaddu18i(TCGContext *s, TCGReg d, int32_t sj20) -+{ -+ tcg_out32(s, encode_dsj20_insn(OPC_PCADDU18I, d, sj20)); -+} -+ -+/* Emits the `ld.b d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ld_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_LD_B, d, j, sk12)); -+} -+ -+/* Emits the `ld.h d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ld_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_LD_H, d, j, sk12)); -+} -+ -+/* Emits the `ld.w d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ld_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_LD_W, d, j, sk12)); -+} -+ -+/* Emits the `ld.d d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ld_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_LD_D, d, j, sk12)); -+} -+ -+/* Emits the `st.b d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_st_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_ST_B, d, j, sk12)); -+} -+ -+/* Emits the `st.h d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_st_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_ST_H, d, j, sk12)); -+} -+ -+/* Emits the `st.w d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_st_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_ST_W, d, j, sk12)); -+} -+ -+/* Emits the `st.d d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_st_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_ST_D, d, j, sk12)); -+} -+ -+/* Emits the `ld.bu d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ld_bu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_LD_BU, d, j, sk12)); -+} -+ -+/* Emits the `ld.hu d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ld_hu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_LD_HU, d, j, sk12)); -+} -+ -+/* Emits the `ld.wu d, j, sk12` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ld_wu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12) -+{ -+ tcg_out32(s, encode_djsk12_insn(OPC_LD_WU, d, j, sk12)); -+} -+ -+/* Emits the `ldx.b d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ldx_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_LDX_B, d, j, k)); -+} -+ -+/* Emits the `ldx.h d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ldx_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_LDX_H, d, j, k)); -+} -+ -+/* Emits the `ldx.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ldx_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_LDX_W, d, j, k)); -+} -+ -+/* Emits the `ldx.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ldx_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_LDX_D, d, j, k)); -+} -+ -+/* Emits the `stx.b d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_stx_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_STX_B, d, j, k)); -+} -+ -+/* Emits the `stx.h d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_stx_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_STX_H, d, j, k)); -+} -+ -+/* Emits the `stx.w d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_stx_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_STX_W, d, j, k)); -+} -+ -+/* Emits the `stx.d d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_stx_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_STX_D, d, j, k)); -+} -+ -+/* Emits the `ldx.bu d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ldx_bu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_LDX_BU, d, j, k)); -+} -+ -+/* Emits the `ldx.hu d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ldx_hu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_LDX_HU, d, j, k)); -+} -+ -+/* Emits the `ldx.wu d, j, k` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ldx_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k) -+{ -+ tcg_out32(s, encode_djk_insn(OPC_LDX_WU, d, j, k)); -+} -+ -+/* Emits the `dbar ud15` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_dbar(TCGContext *s, uint32_t ud15) -+{ -+ tcg_out32(s, encode_ud15_insn(OPC_DBAR, ud15)); -+} -+ -+/* Emits the `jirl d, j, sk16` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_jirl(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) -+{ -+ tcg_out32(s, encode_djsk16_insn(OPC_JIRL, d, j, sk16)); -+} -+ -+/* Emits the `b sd10k16` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_b(TCGContext *s, int32_t sd10k16) -+{ -+ tcg_out32(s, encode_sd10k16_insn(OPC_B, sd10k16)); -+} -+ -+/* Emits the `bl sd10k16` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_bl(TCGContext *s, int32_t sd10k16) -+{ -+ tcg_out32(s, encode_sd10k16_insn(OPC_BL, sd10k16)); -+} -+ -+/* Emits the `beq d, j, sk16` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_beq(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) -+{ -+ tcg_out32(s, encode_djsk16_insn(OPC_BEQ, d, j, sk16)); -+} -+ -+/* Emits the `bne d, j, sk16` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_bne(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) -+{ -+ tcg_out32(s, encode_djsk16_insn(OPC_BNE, d, j, sk16)); -+} -+ -+/* Emits the `bgt d, j, sk16` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_bgt(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) -+{ -+ tcg_out32(s, encode_djsk16_insn(OPC_BGT, d, j, sk16)); -+} -+ -+/* Emits the `ble d, j, sk16` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_ble(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) -+{ -+ tcg_out32(s, encode_djsk16_insn(OPC_BLE, d, j, sk16)); -+} -+ -+/* Emits the `bgtu d, j, sk16` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_bgtu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) -+{ -+ tcg_out32(s, encode_djsk16_insn(OPC_BGTU, d, j, sk16)); -+} -+ -+/* Emits the `bleu d, j, sk16` instruction. */ -+static void __attribute__((unused)) -+tcg_out_opc_bleu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16) -+{ -+ tcg_out32(s, encode_djsk16_insn(OPC_BLEU, d, j, sk16)); -+} -+ -+/* End of generated code. */ --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0005-tcg-loongarch64-Add-register-names-allocation-ord.patch b/app-emulation/qemu/files/loongarch/v6-0005-tcg-loongarch64-Add-register-names-allocation-ord.patch deleted file mode 100644 index d1784eb..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0005-tcg-loongarch64-Add-register-names-allocation-ord.patch +++ /dev/null @@ -1,140 +0,0 @@ -From f5a07d670ba91a9d5989fe1b1d545ea31b3c17c1 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 23:23:30 +0800 -Subject: [PATCH v6 05/30] tcg/loongarch64: Add register names, allocation - order and input/output sets - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target.c.inc | 118 +++++++++++++++++++++++++++++++ - 1 file changed, 118 insertions(+) - create mode 100644 tcg/loongarch64/tcg-target.c.inc - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -new file mode 100644 -index 0000000000..42eebef78e ---- /dev/null -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -0,0 +1,118 @@ -+/* -+ * Tiny Code Generator for QEMU -+ * -+ * Copyright (c) 2021 WANG Xuerui -+ * -+ * Based on tcg/riscv/tcg-target.c.inc -+ * -+ * Copyright (c) 2018 SiFive, Inc -+ * Copyright (c) 2008-2009 Arnaud Patard -+ * Copyright (c) 2009 Aurelien Jarno -+ * Copyright (c) 2008 Fabrice Bellard -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a copy -+ * of this software and associated documentation files (the "Software"), to deal -+ * in the Software without restriction, including without limitation the rights -+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -+ * copies of the Software, and to permit persons to whom the Software is -+ * furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in -+ * all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -+ * THE SOFTWARE. -+ */ -+ -+#ifdef CONFIG_DEBUG_TCG -+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { -+ "zero", -+ "ra", -+ "tp", -+ "sp", -+ "a0", -+ "a1", -+ "a2", -+ "a3", -+ "a4", -+ "a5", -+ "a6", -+ "a7", -+ "t0", -+ "t1", -+ "t2", -+ "t3", -+ "t4", -+ "t5", -+ "t6", -+ "t7", -+ "t8", -+ "r21", /* reserved in the LP64 ABI, hence no ABI name */ -+ "s9", -+ "s0", -+ "s1", -+ "s2", -+ "s3", -+ "s4", -+ "s5", -+ "s6", -+ "s7", -+ "s8" -+}; -+#endif -+ -+static const int tcg_target_reg_alloc_order[] = { -+ /* Registers preserved across calls */ -+ /* TCG_REG_S0 reserved for TCG_AREG0 */ -+ TCG_REG_S1, -+ TCG_REG_S2, -+ TCG_REG_S3, -+ TCG_REG_S4, -+ TCG_REG_S5, -+ TCG_REG_S6, -+ TCG_REG_S7, -+ TCG_REG_S8, -+ TCG_REG_S9, -+ -+ /* Registers (potentially) clobbered across calls */ -+ TCG_REG_T0, -+ TCG_REG_T1, -+ TCG_REG_T2, -+ TCG_REG_T3, -+ TCG_REG_T4, -+ TCG_REG_T5, -+ TCG_REG_T6, -+ TCG_REG_T7, -+ TCG_REG_T8, -+ -+ /* Argument registers, opposite order of allocation. */ -+ TCG_REG_A7, -+ TCG_REG_A6, -+ TCG_REG_A5, -+ TCG_REG_A4, -+ TCG_REG_A3, -+ TCG_REG_A2, -+ TCG_REG_A1, -+ TCG_REG_A0, -+}; -+ -+static const int tcg_target_call_iarg_regs[] = { -+ TCG_REG_A0, -+ TCG_REG_A1, -+ TCG_REG_A2, -+ TCG_REG_A3, -+ TCG_REG_A4, -+ TCG_REG_A5, -+ TCG_REG_A6, -+ TCG_REG_A7, -+}; -+ -+static const int tcg_target_call_oarg_regs[] = { -+ TCG_REG_A0, -+ TCG_REG_A1, -+}; --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0006-tcg-loongarch64-Define-the-operand-constraints.patch b/app-emulation/qemu/files/loongarch/v6-0006-tcg-loongarch64-Define-the-operand-constraints.patch deleted file mode 100644 index 00c95a9..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0006-tcg-loongarch64-Define-the-operand-constraints.patch +++ /dev/null @@ -1,114 +0,0 @@ -From 13e54b1dcd4a4916490a1614be0031d871b7580a Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 23:28:56 +0800 -Subject: [PATCH v6 06/30] tcg/loongarch64: Define the operand constraints -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target-con-str.h | 28 +++++++++++++++ - tcg/loongarch64/tcg-target.c.inc | 52 ++++++++++++++++++++++++++++ - 2 files changed, 80 insertions(+) - create mode 100644 tcg/loongarch64/tcg-target-con-str.h - -diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-target-con-str.h -new file mode 100644 -index 0000000000..c3986a4fd4 ---- /dev/null -+++ b/tcg/loongarch64/tcg-target-con-str.h -@@ -0,0 +1,28 @@ -+/* SPDX-License-Identifier: MIT */ -+/* -+ * Define LoongArch target-specific operand constraints. -+ * -+ * Copyright (c) 2021 WANG Xuerui -+ * -+ * Based on tcg/riscv/tcg-target-con-str.h -+ * -+ * Copyright (c) 2021 Linaro -+ */ -+ -+/* -+ * Define constraint letters for register sets: -+ * REGS(letter, register_mask) -+ */ -+REGS('r', ALL_GENERAL_REGS) -+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) -+ -+/* -+ * Define constraint letters for constants: -+ * CONST(letter, TCG_CT_CONST_* bit set) -+ */ -+CONST('I', TCG_CT_CONST_S12) -+CONST('N', TCG_CT_CONST_N12) -+CONST('U', TCG_CT_CONST_U12) -+CONST('Z', TCG_CT_CONST_ZERO) -+CONST('C', TCG_CT_CONST_C12) -+CONST('W', TCG_CT_CONST_WSZ) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 42eebef78e..64e57bd055 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -116,3 +116,55 @@ static const int tcg_target_call_oarg_regs[] = { - TCG_REG_A0, - TCG_REG_A1, - }; -+ -+#define TCG_CT_CONST_ZERO 0x100 -+#define TCG_CT_CONST_S12 0x200 -+#define TCG_CT_CONST_N12 0x400 -+#define TCG_CT_CONST_U12 0x800 -+#define TCG_CT_CONST_C12 0x1000 -+#define TCG_CT_CONST_WSZ 0x2000 -+ -+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -+/* -+ * For softmmu, we need to avoid conflicts with the first 5 -+ * argument registers to call the helper. Some of these are -+ * also used for the tlb lookup. -+ */ -+#ifdef CONFIG_SOFTMMU -+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) -+#else -+#define SOFTMMU_RESERVE_REGS 0 -+#endif -+ -+ -+static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) -+{ -+ return sextract64(val, pos, len); -+} -+ -+/* test if a constant matches the constraint */ -+static bool tcg_target_const_match(int64_t val, TCGType type, int ct) -+{ -+ if (ct & TCG_CT_CONST) { -+ return true; -+ } -+ if ((ct & TCG_CT_CONST_ZERO) && val == 0) { -+ return true; -+ } -+ if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { -+ return true; -+ } -+ if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { -+ return true; -+ } -+ if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { -+ return true; -+ } -+ if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { -+ return true; -+ } -+ if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { -+ return true; -+ } -+ return false; -+} --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0007-tcg-loongarch64-Implement-necessary-relocation-op.patch b/app-emulation/qemu/files/loongarch/v6-0007-tcg-loongarch64-Implement-necessary-relocation-op.patch deleted file mode 100644 index ac03921..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0007-tcg-loongarch64-Implement-necessary-relocation-op.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 1dabb378b5a9b68e963d613dd67528c2b62a0549 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 23:44:50 +0800 -Subject: [PATCH v6 07/30] tcg/loongarch64: Implement necessary relocation - operations - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target.c.inc | 66 ++++++++++++++++++++++++++++++++ - 1 file changed, 66 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 64e57bd055..fbacaef862 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -168,3 +168,69 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) - } - return false; - } -+ -+/* -+ * Relocations -+ */ -+ -+/* -+ * Relocation records defined in LoongArch ELF psABI v1.00 is way too -+ * complicated; a whopping stack machine is needed to stuff the fields, at -+ * the very least one SOP_PUSH and one SOP_POP (of the correct format) are -+ * needed. -+ * -+ * Hence, define our own simpler relocation types. Numbers are chosen as to -+ * not collide with potential future additions to the true ELF relocation -+ * type enum. -+ */ -+ -+/* Field Sk16, shifted right by 2; suitable for conditional jumps */ -+#define R_LOONGARCH_BR_SK16 256 -+/* Field Sd10k16, shifted right by 2; suitable for B and BL */ -+#define R_LOONGARCH_BR_SD10K16 257 -+ -+static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) -+{ -+ const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); -+ intptr_t offset = (intptr_t)target - (intptr_t)src_rx; -+ -+ tcg_debug_assert((offset & 3) == 0); -+ offset >>= 2; -+ if (offset == sextreg(offset, 0, 16)) { -+ *src_rw = deposit64(*src_rw, 10, 16, offset); -+ return true; -+ } -+ -+ return false; -+} -+ -+static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, -+ const tcg_insn_unit *target) -+{ -+ const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); -+ intptr_t offset = (intptr_t)target - (intptr_t)src_rx; -+ -+ tcg_debug_assert((offset & 3) == 0); -+ offset >>= 2; -+ if (offset == sextreg(offset, 0, 26)) { -+ *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ -+ *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ -+ return true; -+ } -+ -+ return false; -+} -+ -+static bool patch_reloc(tcg_insn_unit *code_ptr, int type, -+ intptr_t value, intptr_t addend) -+{ -+ tcg_debug_assert(addend == 0); -+ switch (type) { -+ case R_LOONGARCH_BR_SK16: -+ return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); -+ case R_LOONGARCH_BR_SD10K16: -+ return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); -+ default: -+ g_assert_not_reached(); -+ } -+} --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0008-tcg-loongarch64-Implement-the-memory-barrier-op.patch b/app-emulation/qemu/files/loongarch/v6-0008-tcg-loongarch64-Implement-the-memory-barrier-op.patch deleted file mode 100644 index ff44f5b..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0008-tcg-loongarch64-Implement-the-memory-barrier-op.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 35523518f8ca04a501132b57b2c234ca13787c39 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:25:04 +0800 -Subject: [PATCH v6 08/30] tcg/loongarch64: Implement the memory barrier op -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++++ - 1 file changed, 32 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index fbacaef862..f12955723d 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -234,3 +234,35 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, - g_assert_not_reached(); - } - } -+ -+#include "tcg-insn-defs.c.inc" -+ -+/* -+ * TCG intrinsics -+ */ -+ -+static void tcg_out_mb(TCGContext *s, TCGArg a0) -+{ -+ /* Baseline LoongArch only has the full barrier, unfortunately. */ -+ tcg_out_opc_dbar(s, 0); -+} -+ -+/* -+ * Entry-points -+ */ -+ -+static void tcg_out_op(TCGContext *s, TCGOpcode opc, -+ const TCGArg args[TCG_MAX_OP_ARGS], -+ const int const_args[TCG_MAX_OP_ARGS]) -+{ -+ TCGArg a0 = args[0]; -+ -+ switch (opc) { -+ case INDEX_op_mb: -+ tcg_out_mb(s, a0); -+ break; -+ -+ default: -+ g_assert_not_reached(); -+ } -+} --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0009-tcg-loongarch64-Implement-tcg_out_mov-and-tcg_out.patch b/app-emulation/qemu/files/loongarch/v6-0009-tcg-loongarch64-Implement-tcg_out_mov-and-tcg_out.patch deleted file mode 100644 index 961d52d..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0009-tcg-loongarch64-Implement-tcg_out_mov-and-tcg_out.patch +++ /dev/null @@ -1,170 +0,0 @@ -From 04b19fe565fe52d84d8ff569787f2a7d6dd78247 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 23:48:40 +0800 -Subject: [PATCH v6 09/30] tcg/loongarch64: Implement tcg_out_mov and - tcg_out_movi - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target.c.inc | 137 +++++++++++++++++++++++++++++++ - 1 file changed, 137 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index f12955723d..4487851b5e 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -247,6 +247,141 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) - tcg_out_opc_dbar(s, 0); - } - -+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) -+{ -+ if (ret == arg) { -+ return true; -+ } -+ switch (type) { -+ case TCG_TYPE_I32: -+ case TCG_TYPE_I64: -+ /* -+ * Conventional register-register move used in LoongArch is -+ * `or dst, src, zero`. -+ */ -+ tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); -+ break; -+ default: -+ g_assert_not_reached(); -+ } -+ return true; -+} -+ -+static bool imm_part_needs_loading(bool high_bits_are_ones, -+ tcg_target_long part) -+{ -+ if (high_bits_are_ones) { -+ return part != -1; -+ } else { -+ return part != 0; -+ } -+} -+ -+/* Loads a 32-bit immediate into rd, sign-extended. */ -+static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) -+{ -+ tcg_target_long lo = sextreg(val, 0, 12); -+ tcg_target_long hi12 = sextreg(val, 12, 20); -+ -+ /* Single-instruction cases. */ -+ if (lo == val) { -+ /* val fits in simm12: addi.w rd, zero, val */ -+ tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); -+ return; -+ } -+ if (0x800 <= val && val <= 0xfff) { -+ /* val fits in uimm12: ori rd, zero, val */ -+ tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); -+ return; -+ } -+ -+ /* High bits must be set; load with lu12i.w + optional ori. */ -+ tcg_out_opc_lu12i_w(s, rd, hi12); -+ if (lo != 0) { -+ tcg_out_opc_ori(s, rd, rd, lo & 0xfff); -+ } -+} -+ -+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, -+ tcg_target_long val) -+{ -+ /* -+ * LoongArch conventionally loads 64-bit immediates in at most 4 steps, -+ * with dedicated instructions for filling the respective bitfields -+ * below: -+ * -+ * 6 5 4 3 -+ * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 -+ * +-----------------------+---------------------------------------+... -+ * | hi52 | hi32 | -+ * +-----------------------+---------------------------------------+... -+ * 3 2 1 -+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 -+ * ...+-------------------------------------+-------------------------+ -+ * | hi12 | lo | -+ * ...+-------------------------------------+-------------------------+ -+ * -+ * Check if val belong to one of the several fast cases, before falling -+ * back to the slow path. -+ */ -+ -+ intptr_t pc_offset; -+ tcg_target_long val_lo, val_hi, pc_hi, offset_hi; -+ tcg_target_long hi32, hi52; -+ bool rd_high_bits_are_ones; -+ -+ /* Value fits in signed i32. */ -+ if (type == TCG_TYPE_I32 || val == (int32_t)val) { -+ tcg_out_movi_i32(s, rd, val); -+ return; -+ } -+ -+ /* PC-relative cases. */ -+ pc_offset = tcg_pcrel_diff(s, (void *)val); -+ if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) { -+ /* Single pcaddu2i. */ -+ tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); -+ return; -+ } -+ -+ if (pc_offset == (int32_t)pc_offset) { -+ /* Offset within 32 bits; load with pcalau12i + ori. */ -+ val_lo = sextreg(val, 0, 12); -+ val_hi = val >> 12; -+ pc_hi = (val - pc_offset) >> 12; -+ offset_hi = val_hi - pc_hi; -+ -+ tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20)); -+ tcg_out_opc_pcalau12i(s, rd, offset_hi); -+ if (val_lo != 0) { -+ tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff); -+ } -+ return; -+ } -+ -+ hi32 = sextreg(val, 32, 20); -+ hi52 = sextreg(val, 52, 12); -+ -+ /* Single cu52i.d case. */ -+ if (ctz64(val) >= 52) { -+ tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); -+ return; -+ } -+ -+ /* Slow path. Initialize the low 32 bits, then concat high bits. */ -+ tcg_out_movi_i32(s, rd, val); -+ rd_high_bits_are_ones = (int32_t)val < 0; -+ -+ if (imm_part_needs_loading(rd_high_bits_are_ones, hi32)) { -+ tcg_out_opc_cu32i_d(s, rd, hi32); -+ rd_high_bits_are_ones = hi32 < 0; -+ } -+ -+ if (imm_part_needs_loading(rd_high_bits_are_ones, hi52)) { -+ tcg_out_opc_cu52i_d(s, rd, rd, hi52); -+ } -+} -+ - /* - * Entry-points - */ -@@ -262,6 +397,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_mb(s, a0); - break; - -+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ -+ case INDEX_op_mov_i64: - default: - g_assert_not_reached(); - } --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0010-tcg-loongarch64-Implement-goto_ptr.patch b/app-emulation/qemu/files/loongarch/v6-0010-tcg-loongarch64-Implement-goto_ptr.patch deleted file mode 100644 index 955a2df..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0010-tcg-loongarch64-Implement-goto_ptr.patch +++ /dev/null @@ -1,68 +0,0 @@ -From fbafc1602e133425bff0ac0a6f4faea04e345a7f Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 00:57:21 +0800 -Subject: [PATCH v6 10/30] tcg/loongarch64: Implement goto_ptr - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target-con-set.h | 17 +++++++++++++++++ - tcg/loongarch64/tcg-target.c.inc | 15 +++++++++++++++ - 2 files changed, 32 insertions(+) - create mode 100644 tcg/loongarch64/tcg-target-con-set.h - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -new file mode 100644 -index 0000000000..5cc4407367 ---- /dev/null -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: MIT */ -+/* -+ * Define LoongArch target-specific constraint sets. -+ * -+ * Copyright (c) 2021 WANG Xuerui -+ * -+ * Based on tcg/riscv/tcg-target-con-set.h -+ * -+ * Copyright (c) 2021 Linaro -+ */ -+ -+/* -+ * C_On_Im(...) defines a constraint set with outputs and inputs. -+ * Each operand should be a sequence of constraint letters as defined by -+ * tcg-target-con-str.h; the constraint combination is inclusive or. -+ */ -+C_O0_I1(r) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 4487851b5e..17f869dbd2 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -397,9 +397,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_mb(s, a0); - break; - -+ case INDEX_op_goto_ptr: -+ tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: - g_assert_not_reached(); - } - } -+ -+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) -+{ -+ switch (op) { -+ case INDEX_op_goto_ptr: -+ return C_O0_I1(r); -+ -+ default: -+ g_assert_not_reached(); -+ } -+} --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0011-tcg-loongarch64-Implement-sign-zero-extension-ops.patch b/app-emulation/qemu/files/loongarch/v6-0011-tcg-loongarch64-Implement-sign-zero-extension-ops.patch deleted file mode 100644 index 107257b..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0011-tcg-loongarch64-Implement-sign-zero-extension-ops.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 07d003dc4f96b1f34d761812eff8f5e2734e7d98 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 00:03:02 +0800 -Subject: [PATCH v6 11/30] tcg/loongarch64: Implement sign-/zero-extension ops -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target-con-set.h | 1 + - tcg/loongarch64/tcg-target.c.inc | 82 ++++++++++++++++++++++++++++ - tcg/loongarch64/tcg-target.h | 24 ++++---- - 3 files changed, 95 insertions(+), 12 deletions(-) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index 5cc4407367..7e459490ea 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -15,3 +15,4 @@ - * tcg-target-con-str.h; the constraint combination is inclusive or. - */ - C_O0_I1(r) -+C_O1_I1(r, r) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 17f869dbd2..0c075c7521 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -382,6 +382,36 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, - } - } - -+static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) -+{ -+ tcg_out_opc_andi(s, ret, arg, 0xff); -+} -+ -+static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) -+{ -+ tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); -+} -+ -+static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) -+{ -+ tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); -+} -+ -+static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) -+{ -+ tcg_out_opc_sext_b(s, ret, arg); -+} -+ -+static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) -+{ -+ tcg_out_opc_sext_h(s, ret, arg); -+} -+ -+static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) -+{ -+ tcg_out_opc_addi_w(s, ret, arg, 0); -+} -+ - /* - * Entry-points - */ -@@ -391,6 +421,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const int const_args[TCG_MAX_OP_ARGS]) - { - TCGArg a0 = args[0]; -+ TCGArg a1 = args[1]; - - switch (opc) { - case INDEX_op_mb: -@@ -401,6 +432,41 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); - break; - -+ case INDEX_op_ext8s_i32: -+ case INDEX_op_ext8s_i64: -+ tcg_out_ext8s(s, a0, a1); -+ break; -+ -+ case INDEX_op_ext8u_i32: -+ case INDEX_op_ext8u_i64: -+ tcg_out_ext8u(s, a0, a1); -+ break; -+ -+ case INDEX_op_ext16s_i32: -+ case INDEX_op_ext16s_i64: -+ tcg_out_ext16s(s, a0, a1); -+ break; -+ -+ case INDEX_op_ext16u_i32: -+ case INDEX_op_ext16u_i64: -+ tcg_out_ext16u(s, a0, a1); -+ break; -+ -+ case INDEX_op_ext32u_i64: -+ case INDEX_op_extu_i32_i64: -+ tcg_out_ext32u(s, a0, a1); -+ break; -+ -+ case INDEX_op_ext32s_i64: -+ case INDEX_op_extrl_i64_i32: -+ case INDEX_op_ext_i32_i64: -+ tcg_out_ext32s(s, a0, a1); -+ break; -+ -+ case INDEX_op_extrh_i64_i32: -+ tcg_out_opc_srai_d(s, a0, a1, 32); -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: -@@ -414,6 +480,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_goto_ptr: - return C_O0_I1(r); - -+ case INDEX_op_ext8s_i32: -+ case INDEX_op_ext8s_i64: -+ case INDEX_op_ext8u_i32: -+ case INDEX_op_ext8u_i64: -+ case INDEX_op_ext16s_i32: -+ case INDEX_op_ext16s_i64: -+ case INDEX_op_ext16u_i32: -+ case INDEX_op_ext16u_i64: -+ case INDEX_op_ext32s_i64: -+ case INDEX_op_ext32u_i64: -+ case INDEX_op_extu_i32_i64: -+ case INDEX_op_extrl_i64_i32: -+ case INDEX_op_extrh_i64_i32: -+ case INDEX_op_ext_i32_i64: -+ return C_O1_I1(r, r); -+ - default: - g_assert_not_reached(); - } -diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h -index 5fc097b3c1..2b7d5a19b9 100644 ---- a/tcg/loongarch64/tcg-target.h -+++ b/tcg/loongarch64/tcg-target.h -@@ -107,10 +107,10 @@ typedef enum { - #define TCG_TARGET_HAS_muls2_i32 0 - #define TCG_TARGET_HAS_muluh_i32 0 - #define TCG_TARGET_HAS_mulsh_i32 0 --#define TCG_TARGET_HAS_ext8s_i32 0 --#define TCG_TARGET_HAS_ext16s_i32 0 --#define TCG_TARGET_HAS_ext8u_i32 0 --#define TCG_TARGET_HAS_ext16u_i32 0 -+#define TCG_TARGET_HAS_ext8s_i32 1 -+#define TCG_TARGET_HAS_ext16s_i32 1 -+#define TCG_TARGET_HAS_ext8u_i32 1 -+#define TCG_TARGET_HAS_ext16u_i32 1 - #define TCG_TARGET_HAS_bswap16_i32 0 - #define TCG_TARGET_HAS_bswap32_i32 0 - #define TCG_TARGET_HAS_not_i32 0 -@@ -138,14 +138,14 @@ typedef enum { - #define TCG_TARGET_HAS_extract_i64 0 - #define TCG_TARGET_HAS_sextract_i64 0 - #define TCG_TARGET_HAS_extract2_i64 0 --#define TCG_TARGET_HAS_extrl_i64_i32 0 --#define TCG_TARGET_HAS_extrh_i64_i32 0 --#define TCG_TARGET_HAS_ext8s_i64 0 --#define TCG_TARGET_HAS_ext16s_i64 0 --#define TCG_TARGET_HAS_ext32s_i64 0 --#define TCG_TARGET_HAS_ext8u_i64 0 --#define TCG_TARGET_HAS_ext16u_i64 0 --#define TCG_TARGET_HAS_ext32u_i64 0 -+#define TCG_TARGET_HAS_extrl_i64_i32 1 -+#define TCG_TARGET_HAS_extrh_i64_i32 1 -+#define TCG_TARGET_HAS_ext8s_i64 1 -+#define TCG_TARGET_HAS_ext16s_i64 1 -+#define TCG_TARGET_HAS_ext32s_i64 1 -+#define TCG_TARGET_HAS_ext8u_i64 1 -+#define TCG_TARGET_HAS_ext16u_i64 1 -+#define TCG_TARGET_HAS_ext32u_i64 1 - #define TCG_TARGET_HAS_bswap16_i64 0 - #define TCG_TARGET_HAS_bswap32_i64 0 - #define TCG_TARGET_HAS_bswap64_i64 0 --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0012-tcg-loongarch64-Implement-not-and-or-xor-nor-andc.patch b/app-emulation/qemu/files/loongarch/v6-0012-tcg-loongarch64-Implement-not-and-or-xor-nor-andc.patch deleted file mode 100644 index 42e0022..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0012-tcg-loongarch64-Implement-not-and-or-xor-nor-andc.patch +++ /dev/null @@ -1,186 +0,0 @@ -From 04ba9d47f1a8a0ce485007ea548578ea8cbb9a17 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 00:16:46 +0800 -Subject: [PATCH v6 12/30] tcg/loongarch64: Implement - not/and/or/xor/nor/andc/orc ops -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target-con-set.h | 2 + - tcg/loongarch64/tcg-target.c.inc | 88 ++++++++++++++++++++++++++++ - tcg/loongarch64/tcg-target.h | 16 ++--- - 3 files changed, 98 insertions(+), 8 deletions(-) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index 7e459490ea..9ac24b8ad0 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -16,3 +16,5 @@ - */ - C_O0_I1(r) - C_O1_I1(r, r) -+C_O1_I2(r, r, rC) -+C_O1_I2(r, r, rU) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 0c075c7521..d610b83c37 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -422,6 +422,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - { - TCGArg a0 = args[0]; - TCGArg a1 = args[1]; -+ TCGArg a2 = args[2]; -+ int c2 = const_args[2]; - - switch (opc) { - case INDEX_op_mb: -@@ -467,6 +469,68 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_opc_srai_d(s, a0, a1, 32); - break; - -+ case INDEX_op_not_i32: -+ case INDEX_op_not_i64: -+ tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO); -+ break; -+ -+ case INDEX_op_nor_i32: -+ case INDEX_op_nor_i64: -+ if (c2) { -+ tcg_out_opc_ori(s, a0, a1, a2); -+ tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO); -+ } else { -+ tcg_out_opc_nor(s, a0, a1, a2); -+ } -+ break; -+ -+ case INDEX_op_andc_i32: -+ case INDEX_op_andc_i64: -+ if (c2) { -+ /* guaranteed to fit due to constraint */ -+ tcg_out_opc_andi(s, a0, a1, ~a2); -+ } else { -+ tcg_out_opc_andn(s, a0, a1, a2); -+ } -+ break; -+ -+ case INDEX_op_orc_i32: -+ case INDEX_op_orc_i64: -+ if (c2) { -+ /* guaranteed to fit due to constraint */ -+ tcg_out_opc_ori(s, a0, a1, ~a2); -+ } else { -+ tcg_out_opc_orn(s, a0, a1, a2); -+ } -+ break; -+ -+ case INDEX_op_and_i32: -+ case INDEX_op_and_i64: -+ if (c2) { -+ tcg_out_opc_andi(s, a0, a1, a2); -+ } else { -+ tcg_out_opc_and(s, a0, a1, a2); -+ } -+ break; -+ -+ case INDEX_op_or_i32: -+ case INDEX_op_or_i64: -+ if (c2) { -+ tcg_out_opc_ori(s, a0, a1, a2); -+ } else { -+ tcg_out_opc_or(s, a0, a1, a2); -+ } -+ break; -+ -+ case INDEX_op_xor_i32: -+ case INDEX_op_xor_i64: -+ if (c2) { -+ tcg_out_opc_xori(s, a0, a1, a2); -+ } else { -+ tcg_out_opc_xor(s, a0, a1, a2); -+ } -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: -@@ -494,8 +558,32 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_extrl_i64_i32: - case INDEX_op_extrh_i64_i32: - case INDEX_op_ext_i32_i64: -+ case INDEX_op_not_i32: -+ case INDEX_op_not_i64: - return C_O1_I1(r, r); - -+ case INDEX_op_andc_i32: -+ case INDEX_op_andc_i64: -+ case INDEX_op_orc_i32: -+ case INDEX_op_orc_i64: -+ /* -+ * LoongArch insns for these ops don't have reg-imm forms, but we -+ * can express using andi/ori if ~constant satisfies -+ * TCG_CT_CONST_U12. -+ */ -+ return C_O1_I2(r, r, rC); -+ -+ case INDEX_op_and_i32: -+ case INDEX_op_and_i64: -+ case INDEX_op_nor_i32: -+ case INDEX_op_nor_i64: -+ case INDEX_op_or_i32: -+ case INDEX_op_or_i64: -+ case INDEX_op_xor_i32: -+ case INDEX_op_xor_i64: -+ /* LoongArch reg-imm bitops have their imms ZERO-extended */ -+ return C_O1_I2(r, r, rU); -+ - default: - g_assert_not_reached(); - } -diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h -index 2b7d5a19b9..cb1739a54a 100644 ---- a/tcg/loongarch64/tcg-target.h -+++ b/tcg/loongarch64/tcg-target.h -@@ -113,13 +113,13 @@ typedef enum { - #define TCG_TARGET_HAS_ext16u_i32 1 - #define TCG_TARGET_HAS_bswap16_i32 0 - #define TCG_TARGET_HAS_bswap32_i32 0 --#define TCG_TARGET_HAS_not_i32 0 -+#define TCG_TARGET_HAS_not_i32 1 - #define TCG_TARGET_HAS_neg_i32 0 --#define TCG_TARGET_HAS_andc_i32 0 --#define TCG_TARGET_HAS_orc_i32 0 -+#define TCG_TARGET_HAS_andc_i32 1 -+#define TCG_TARGET_HAS_orc_i32 1 - #define TCG_TARGET_HAS_eqv_i32 0 - #define TCG_TARGET_HAS_nand_i32 0 --#define TCG_TARGET_HAS_nor_i32 0 -+#define TCG_TARGET_HAS_nor_i32 1 - #define TCG_TARGET_HAS_clz_i32 0 - #define TCG_TARGET_HAS_ctz_i32 0 - #define TCG_TARGET_HAS_ctpop_i32 0 -@@ -149,13 +149,13 @@ typedef enum { - #define TCG_TARGET_HAS_bswap16_i64 0 - #define TCG_TARGET_HAS_bswap32_i64 0 - #define TCG_TARGET_HAS_bswap64_i64 0 --#define TCG_TARGET_HAS_not_i64 0 -+#define TCG_TARGET_HAS_not_i64 1 - #define TCG_TARGET_HAS_neg_i64 0 --#define TCG_TARGET_HAS_andc_i64 0 --#define TCG_TARGET_HAS_orc_i64 0 -+#define TCG_TARGET_HAS_andc_i64 1 -+#define TCG_TARGET_HAS_orc_i64 1 - #define TCG_TARGET_HAS_eqv_i64 0 - #define TCG_TARGET_HAS_nand_i64 0 --#define TCG_TARGET_HAS_nor_i64 0 -+#define TCG_TARGET_HAS_nor_i64 1 - #define TCG_TARGET_HAS_clz_i64 0 - #define TCG_TARGET_HAS_ctz_i64 0 - #define TCG_TARGET_HAS_ctpop_i64 0 --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0013-tcg-loongarch64-Implement-deposit-extract-ops.patch b/app-emulation/qemu/files/loongarch/v6-0013-tcg-loongarch64-Implement-deposit-extract-ops.patch deleted file mode 100644 index 73218a5..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0013-tcg-loongarch64-Implement-deposit-extract-ops.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 66ade64913b65cb4c6144d0ef954d547b200c293 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 00:23:47 +0800 -Subject: [PATCH v6 13/30] tcg/loongarch64: Implement deposit/extract ops - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target-con-set.h | 1 + - tcg/loongarch64/tcg-target.c.inc | 21 +++++++++++++++++++++ - tcg/loongarch64/tcg-target.h | 8 ++++---- - 3 files changed, 26 insertions(+), 4 deletions(-) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index 9ac24b8ad0..d958183020 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -18,3 +18,4 @@ C_O0_I1(r) - C_O1_I1(r, r) - C_O1_I2(r, r, rC) - C_O1_I2(r, r, rU) -+C_O1_I2(r, 0, rZ) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index d610b83c37..1d903d05d6 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -531,6 +531,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - } - break; - -+ case INDEX_op_extract_i32: -+ tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); -+ break; -+ case INDEX_op_extract_i64: -+ tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); -+ break; -+ -+ case INDEX_op_deposit_i32: -+ tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); -+ break; -+ case INDEX_op_deposit_i64: -+ tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: -@@ -560,6 +574,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_ext_i32_i64: - case INDEX_op_not_i32: - case INDEX_op_not_i64: -+ case INDEX_op_extract_i32: -+ case INDEX_op_extract_i64: - return C_O1_I1(r, r); - - case INDEX_op_andc_i32: -@@ -584,6 +600,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - /* LoongArch reg-imm bitops have their imms ZERO-extended */ - return C_O1_I2(r, r, rU); - -+ case INDEX_op_deposit_i32: -+ case INDEX_op_deposit_i64: -+ /* Must deposit into the same register as input */ -+ return C_O1_I2(r, 0, rZ); -+ - default: - g_assert_not_reached(); - } -diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h -index cb1739a54a..084d635a8e 100644 ---- a/tcg/loongarch64/tcg-target.h -+++ b/tcg/loongarch64/tcg-target.h -@@ -97,8 +97,8 @@ typedef enum { - #define TCG_TARGET_HAS_rem_i32 0 - #define TCG_TARGET_HAS_div2_i32 0 - #define TCG_TARGET_HAS_rot_i32 0 --#define TCG_TARGET_HAS_deposit_i32 0 --#define TCG_TARGET_HAS_extract_i32 0 -+#define TCG_TARGET_HAS_deposit_i32 1 -+#define TCG_TARGET_HAS_extract_i32 1 - #define TCG_TARGET_HAS_sextract_i32 0 - #define TCG_TARGET_HAS_extract2_i32 0 - #define TCG_TARGET_HAS_add2_i32 0 -@@ -134,8 +134,8 @@ typedef enum { - #define TCG_TARGET_HAS_rem_i64 0 - #define TCG_TARGET_HAS_div2_i64 0 - #define TCG_TARGET_HAS_rot_i64 0 --#define TCG_TARGET_HAS_deposit_i64 0 --#define TCG_TARGET_HAS_extract_i64 0 -+#define TCG_TARGET_HAS_deposit_i64 1 -+#define TCG_TARGET_HAS_extract_i64 1 - #define TCG_TARGET_HAS_sextract_i64 0 - #define TCG_TARGET_HAS_extract2_i64 0 - #define TCG_TARGET_HAS_extrl_i64_i32 1 --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0014-tcg-loongarch64-Implement-bswap-16-32-64-ops.patch b/app-emulation/qemu/files/loongarch/v6-0014-tcg-loongarch64-Implement-bswap-16-32-64-ops.patch deleted file mode 100644 index 5acc79e..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0014-tcg-loongarch64-Implement-bswap-16-32-64-ops.patch +++ /dev/null @@ -1,93 +0,0 @@ -From f0c8d7d38f8c148fb4f5abc29f0b9b2ce76d35bb Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 00:24:39 +0800 -Subject: [PATCH v6 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++++ - tcg/loongarch64/tcg-target.h | 10 +++++----- - 2 files changed, 37 insertions(+), 5 deletions(-) - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 1d903d05d6..9adac5b3fc 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -545,6 +545,33 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); - break; - -+ case INDEX_op_bswap16_i32: -+ case INDEX_op_bswap16_i64: -+ tcg_out_opc_revb_2h(s, a0, a1); -+ if (a2 & TCG_BSWAP_OS) { -+ tcg_out_ext16s(s, a0, a0); -+ } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { -+ tcg_out_ext16u(s, a0, a0); -+ } -+ break; -+ -+ case INDEX_op_bswap32_i32: -+ /* All 32-bit values are computed sign-extended in the register. */ -+ a2 = TCG_BSWAP_OS; -+ /* fallthrough */ -+ case INDEX_op_bswap32_i64: -+ tcg_out_opc_revb_2w(s, a0, a1); -+ if (a2 & TCG_BSWAP_OS) { -+ tcg_out_ext32s(s, a0, a0); -+ } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { -+ tcg_out_ext32u(s, a0, a0); -+ } -+ break; -+ -+ case INDEX_op_bswap64_i64: -+ tcg_out_opc_revb_d(s, a0, a1); -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: -@@ -576,6 +603,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_not_i64: - case INDEX_op_extract_i32: - case INDEX_op_extract_i64: -+ case INDEX_op_bswap16_i32: -+ case INDEX_op_bswap16_i64: -+ case INDEX_op_bswap32_i32: -+ case INDEX_op_bswap32_i64: -+ case INDEX_op_bswap64_i64: - return C_O1_I1(r, r); - - case INDEX_op_andc_i32: -diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h -index 084d635a8e..02d17d2f6d 100644 ---- a/tcg/loongarch64/tcg-target.h -+++ b/tcg/loongarch64/tcg-target.h -@@ -111,8 +111,8 @@ typedef enum { - #define TCG_TARGET_HAS_ext16s_i32 1 - #define TCG_TARGET_HAS_ext8u_i32 1 - #define TCG_TARGET_HAS_ext16u_i32 1 --#define TCG_TARGET_HAS_bswap16_i32 0 --#define TCG_TARGET_HAS_bswap32_i32 0 -+#define TCG_TARGET_HAS_bswap16_i32 1 -+#define TCG_TARGET_HAS_bswap32_i32 1 - #define TCG_TARGET_HAS_not_i32 1 - #define TCG_TARGET_HAS_neg_i32 0 - #define TCG_TARGET_HAS_andc_i32 1 -@@ -146,9 +146,9 @@ typedef enum { - #define TCG_TARGET_HAS_ext8u_i64 1 - #define TCG_TARGET_HAS_ext16u_i64 1 - #define TCG_TARGET_HAS_ext32u_i64 1 --#define TCG_TARGET_HAS_bswap16_i64 0 --#define TCG_TARGET_HAS_bswap32_i64 0 --#define TCG_TARGET_HAS_bswap64_i64 0 -+#define TCG_TARGET_HAS_bswap16_i64 1 -+#define TCG_TARGET_HAS_bswap32_i64 1 -+#define TCG_TARGET_HAS_bswap64_i64 1 - #define TCG_TARGET_HAS_not_i64 1 - #define TCG_TARGET_HAS_neg_i64 0 - #define TCG_TARGET_HAS_andc_i64 1 --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0015-tcg-loongarch64-Implement-clz-ctz-ops.patch b/app-emulation/qemu/files/loongarch/v6-0015-tcg-loongarch64-Implement-clz-ctz-ops.patch deleted file mode 100644 index b7aef02..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0015-tcg-loongarch64-Implement-clz-ctz-ops.patch +++ /dev/null @@ -1,119 +0,0 @@ -From eb6d077aa10d2c65d0716ef4acf89f43fc48c4d3 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 00:30:34 +0800 -Subject: [PATCH v6 15/30] tcg/loongarch64: Implement clz/ctz ops - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target-con-set.h | 1 + - tcg/loongarch64/tcg-target.c.inc | 42 ++++++++++++++++++++++++++++ - tcg/loongarch64/tcg-target.h | 8 +++--- - 3 files changed, 47 insertions(+), 4 deletions(-) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index d958183020..2975e03127 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -18,4 +18,5 @@ C_O0_I1(r) - C_O1_I1(r, r) - C_O1_I2(r, r, rC) - C_O1_I2(r, r, rU) -+C_O1_I2(r, r, rW) - C_O1_I2(r, 0, rZ) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 9adac5b3fc..4c1c1d6182 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -412,6 +412,28 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) - tcg_out_opc_addi_w(s, ret, arg, 0); - } - -+static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, -+ TCGReg a0, TCGReg a1, TCGReg a2, -+ bool c2, bool is_32bit) -+{ -+ if (c2) { -+ /* -+ * Fast path: semantics already satisfied due to constraint and -+ * insn behavior, single instruction is enough. -+ */ -+ tcg_debug_assert(a2 == (is_32bit ? 32 : 64)); -+ /* all clz/ctz insns belong to DJ-format */ -+ tcg_out32(s, encode_dj_insn(opc, a0, a1)); -+ return; -+ } -+ -+ tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1)); -+ /* a0 = a1 ? REG_TMP0 : a2 */ -+ tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); -+ tcg_out_opc_masknez(s, a0, a2, a1); -+ tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); -+} -+ - /* - * Entry-points - */ -@@ -572,6 +594,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_opc_revb_d(s, a0, a1); - break; - -+ case INDEX_op_clz_i32: -+ tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true); -+ break; -+ case INDEX_op_clz_i64: -+ tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false); -+ break; -+ -+ case INDEX_op_ctz_i32: -+ tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true); -+ break; -+ case INDEX_op_ctz_i64: -+ tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false); -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: -@@ -632,6 +668,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - /* LoongArch reg-imm bitops have their imms ZERO-extended */ - return C_O1_I2(r, r, rU); - -+ case INDEX_op_clz_i32: -+ case INDEX_op_clz_i64: -+ case INDEX_op_ctz_i32: -+ case INDEX_op_ctz_i64: -+ return C_O1_I2(r, r, rW); -+ - case INDEX_op_deposit_i32: - case INDEX_op_deposit_i64: - /* Must deposit into the same register as input */ -diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h -index 02d17d2f6d..ef489cbc86 100644 ---- a/tcg/loongarch64/tcg-target.h -+++ b/tcg/loongarch64/tcg-target.h -@@ -120,8 +120,8 @@ typedef enum { - #define TCG_TARGET_HAS_eqv_i32 0 - #define TCG_TARGET_HAS_nand_i32 0 - #define TCG_TARGET_HAS_nor_i32 1 --#define TCG_TARGET_HAS_clz_i32 0 --#define TCG_TARGET_HAS_ctz_i32 0 -+#define TCG_TARGET_HAS_clz_i32 1 -+#define TCG_TARGET_HAS_ctz_i32 1 - #define TCG_TARGET_HAS_ctpop_i32 0 - #define TCG_TARGET_HAS_direct_jump 0 - #define TCG_TARGET_HAS_brcond2 0 -@@ -156,8 +156,8 @@ typedef enum { - #define TCG_TARGET_HAS_eqv_i64 0 - #define TCG_TARGET_HAS_nand_i64 0 - #define TCG_TARGET_HAS_nor_i64 1 --#define TCG_TARGET_HAS_clz_i64 0 --#define TCG_TARGET_HAS_ctz_i64 0 -+#define TCG_TARGET_HAS_clz_i64 1 -+#define TCG_TARGET_HAS_ctz_i64 1 - #define TCG_TARGET_HAS_ctpop_i64 0 - #define TCG_TARGET_HAS_add2_i64 0 - #define TCG_TARGET_HAS_sub2_i64 0 --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0016-tcg-loongarch64-Implement-shl-shr-sar-rotl-rotr-o.patch b/app-emulation/qemu/files/loongarch/v6-0016-tcg-loongarch64-Implement-shl-shr-sar-rotl-rotr-o.patch deleted file mode 100644 index e0fa6d7..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0016-tcg-loongarch64-Implement-shl-shr-sar-rotl-rotr-o.patch +++ /dev/null @@ -1,163 +0,0 @@ -From a4af6d29d0cd6e522364afe997ec263ed8cc1263 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 00:39:49 +0800 -Subject: [PATCH v6 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target-con-set.h | 1 + - tcg/loongarch64/tcg-target.c.inc | 91 ++++++++++++++++++++++++++++ - tcg/loongarch64/tcg-target.h | 4 +- - 3 files changed, 94 insertions(+), 2 deletions(-) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index 2975e03127..42f8e28741 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -17,6 +17,7 @@ - C_O0_I1(r) - C_O1_I1(r, r) - C_O1_I2(r, r, rC) -+C_O1_I2(r, r, ri) - C_O1_I2(r, r, rU) - C_O1_I2(r, r, rW) - C_O1_I2(r, 0, rZ) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 4c1c1d6182..d0a24cc009 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -608,6 +608,85 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false); - break; - -+ case INDEX_op_shl_i32: -+ if (c2) { -+ tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); -+ } else { -+ tcg_out_opc_sll_w(s, a0, a1, a2); -+ } -+ break; -+ case INDEX_op_shl_i64: -+ if (c2) { -+ tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); -+ } else { -+ tcg_out_opc_sll_d(s, a0, a1, a2); -+ } -+ break; -+ -+ case INDEX_op_shr_i32: -+ if (c2) { -+ tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); -+ } else { -+ tcg_out_opc_srl_w(s, a0, a1, a2); -+ } -+ break; -+ case INDEX_op_shr_i64: -+ if (c2) { -+ tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); -+ } else { -+ tcg_out_opc_srl_d(s, a0, a1, a2); -+ } -+ break; -+ -+ case INDEX_op_sar_i32: -+ if (c2) { -+ tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); -+ } else { -+ tcg_out_opc_sra_w(s, a0, a1, a2); -+ } -+ break; -+ case INDEX_op_sar_i64: -+ if (c2) { -+ tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); -+ } else { -+ tcg_out_opc_sra_d(s, a0, a1, a2); -+ } -+ break; -+ -+ case INDEX_op_rotl_i32: -+ /* transform into equivalent rotr/rotri */ -+ if (c2) { -+ tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f); -+ } else { -+ tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); -+ tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0); -+ } -+ break; -+ case INDEX_op_rotl_i64: -+ /* transform into equivalent rotr/rotri */ -+ if (c2) { -+ tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f); -+ } else { -+ tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); -+ tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0); -+ } -+ break; -+ -+ case INDEX_op_rotr_i32: -+ if (c2) { -+ tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); -+ } else { -+ tcg_out_opc_rotr_w(s, a0, a1, a2); -+ } -+ break; -+ case INDEX_op_rotr_i64: -+ if (c2) { -+ tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); -+ } else { -+ tcg_out_opc_rotr_d(s, a0, a1, a2); -+ } -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: -@@ -657,6 +736,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - */ - return C_O1_I2(r, r, rC); - -+ case INDEX_op_shl_i32: -+ case INDEX_op_shl_i64: -+ case INDEX_op_shr_i32: -+ case INDEX_op_shr_i64: -+ case INDEX_op_sar_i32: -+ case INDEX_op_sar_i64: -+ case INDEX_op_rotl_i32: -+ case INDEX_op_rotl_i64: -+ case INDEX_op_rotr_i32: -+ case INDEX_op_rotr_i64: -+ return C_O1_I2(r, r, ri); -+ - case INDEX_op_and_i32: - case INDEX_op_and_i64: - case INDEX_op_nor_i32: -diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h -index ef489cbc86..e59c2a7bec 100644 ---- a/tcg/loongarch64/tcg-target.h -+++ b/tcg/loongarch64/tcg-target.h -@@ -96,7 +96,7 @@ typedef enum { - #define TCG_TARGET_HAS_div_i32 0 - #define TCG_TARGET_HAS_rem_i32 0 - #define TCG_TARGET_HAS_div2_i32 0 --#define TCG_TARGET_HAS_rot_i32 0 -+#define TCG_TARGET_HAS_rot_i32 1 - #define TCG_TARGET_HAS_deposit_i32 1 - #define TCG_TARGET_HAS_extract_i32 1 - #define TCG_TARGET_HAS_sextract_i32 0 -@@ -133,7 +133,7 @@ typedef enum { - #define TCG_TARGET_HAS_div_i64 0 - #define TCG_TARGET_HAS_rem_i64 0 - #define TCG_TARGET_HAS_div2_i64 0 --#define TCG_TARGET_HAS_rot_i64 0 -+#define TCG_TARGET_HAS_rot_i64 1 - #define TCG_TARGET_HAS_deposit_i64 1 - #define TCG_TARGET_HAS_extract_i64 1 - #define TCG_TARGET_HAS_sextract_i64 0 --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0017-tcg-loongarch64-Implement-add-sub-ops.patch b/app-emulation/qemu/files/loongarch/v6-0017-tcg-loongarch64-Implement-add-sub-ops.patch deleted file mode 100644 index f7a4a6a..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0017-tcg-loongarch64-Implement-add-sub-ops.patch +++ /dev/null @@ -1,98 +0,0 @@ -From b06bc6a239264de8b36c1c6d0bed034cc23a180e Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 00:43:55 +0800 -Subject: [PATCH v6 17/30] tcg/loongarch64: Implement add/sub ops -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The neg_i{32,64} ops is fully expressible with sub, so omitted for -simplicity. - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target-con-set.h | 2 ++ - tcg/loongarch64/tcg-target.c.inc | 38 ++++++++++++++++++++++++++++ - 2 files changed, 40 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index 42f8e28741..4b8ce85897 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -18,6 +18,8 @@ C_O0_I1(r) - C_O1_I1(r, r) - C_O1_I2(r, r, rC) - C_O1_I2(r, r, ri) -+C_O1_I2(r, r, rI) - C_O1_I2(r, r, rU) - C_O1_I2(r, r, rW) - C_O1_I2(r, 0, rZ) -+C_O1_I2(r, rZ, rN) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index d0a24cc009..0e6b241097 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -687,6 +687,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - } - break; - -+ case INDEX_op_add_i32: -+ if (c2) { -+ tcg_out_opc_addi_w(s, a0, a1, a2); -+ } else { -+ tcg_out_opc_add_w(s, a0, a1, a2); -+ } -+ break; -+ case INDEX_op_add_i64: -+ if (c2) { -+ tcg_out_opc_addi_d(s, a0, a1, a2); -+ } else { -+ tcg_out_opc_add_d(s, a0, a1, a2); -+ } -+ break; -+ -+ case INDEX_op_sub_i32: -+ if (c2) { -+ tcg_out_opc_addi_w(s, a0, a1, -a2); -+ } else { -+ tcg_out_opc_sub_w(s, a0, a1, a2); -+ } -+ break; -+ case INDEX_op_sub_i64: -+ if (c2) { -+ tcg_out_opc_addi_d(s, a0, a1, -a2); -+ } else { -+ tcg_out_opc_sub_d(s, a0, a1, a2); -+ } -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: -@@ -748,6 +778,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_rotr_i64: - return C_O1_I2(r, r, ri); - -+ case INDEX_op_add_i32: -+ case INDEX_op_add_i64: -+ return C_O1_I2(r, r, rI); -+ - case INDEX_op_and_i32: - case INDEX_op_and_i64: - case INDEX_op_nor_i32: -@@ -770,6 +804,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - /* Must deposit into the same register as input */ - return C_O1_I2(r, 0, rZ); - -+ case INDEX_op_sub_i32: -+ case INDEX_op_sub_i64: -+ return C_O1_I2(r, rZ, rN); -+ - default: - g_assert_not_reached(); - } --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0018-tcg-loongarch64-Implement-mul-mulsh-muluh-div-div.patch b/app-emulation/qemu/files/loongarch/v6-0018-tcg-loongarch64-Implement-mul-mulsh-muluh-div-div.patch deleted file mode 100644 index cdd51ed..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0018-tcg-loongarch64-Implement-mul-mulsh-muluh-div-div.patch +++ /dev/null @@ -1,161 +0,0 @@ -From ad395d47936447e947af947c15be2bdd55431782 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 00:47:33 +0800 -Subject: [PATCH v6 18/30] tcg/loongarch64: Implement - mul/mulsh/muluh/div/divu/rem/remu ops -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target-con-set.h | 1 + - tcg/loongarch64/tcg-target.c.inc | 65 ++++++++++++++++++++++++++++ - tcg/loongarch64/tcg-target.h | 16 +++---- - 3 files changed, 74 insertions(+), 8 deletions(-) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index 4b8ce85897..fb56f3a295 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -23,3 +23,4 @@ C_O1_I2(r, r, rU) - C_O1_I2(r, r, rW) - C_O1_I2(r, 0, rZ) - C_O1_I2(r, rZ, rN) -+C_O1_I2(r, rZ, rZ) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 0e6b241097..67f07a3853 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -717,6 +717,55 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - } - break; - -+ case INDEX_op_mul_i32: -+ tcg_out_opc_mul_w(s, a0, a1, a2); -+ break; -+ case INDEX_op_mul_i64: -+ tcg_out_opc_mul_d(s, a0, a1, a2); -+ break; -+ -+ case INDEX_op_mulsh_i32: -+ tcg_out_opc_mulh_w(s, a0, a1, a2); -+ break; -+ case INDEX_op_mulsh_i64: -+ tcg_out_opc_mulh_d(s, a0, a1, a2); -+ break; -+ -+ case INDEX_op_muluh_i32: -+ tcg_out_opc_mulh_wu(s, a0, a1, a2); -+ break; -+ case INDEX_op_muluh_i64: -+ tcg_out_opc_mulh_du(s, a0, a1, a2); -+ break; -+ -+ case INDEX_op_div_i32: -+ tcg_out_opc_div_w(s, a0, a1, a2); -+ break; -+ case INDEX_op_div_i64: -+ tcg_out_opc_div_d(s, a0, a1, a2); -+ break; -+ -+ case INDEX_op_divu_i32: -+ tcg_out_opc_div_wu(s, a0, a1, a2); -+ break; -+ case INDEX_op_divu_i64: -+ tcg_out_opc_div_du(s, a0, a1, a2); -+ break; -+ -+ case INDEX_op_rem_i32: -+ tcg_out_opc_mod_w(s, a0, a1, a2); -+ break; -+ case INDEX_op_rem_i64: -+ tcg_out_opc_mod_d(s, a0, a1, a2); -+ break; -+ -+ case INDEX_op_remu_i32: -+ tcg_out_opc_mod_wu(s, a0, a1, a2); -+ break; -+ case INDEX_op_remu_i64: -+ tcg_out_opc_mod_du(s, a0, a1, a2); -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: -@@ -808,6 +857,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_sub_i64: - return C_O1_I2(r, rZ, rN); - -+ case INDEX_op_mul_i32: -+ case INDEX_op_mul_i64: -+ case INDEX_op_mulsh_i32: -+ case INDEX_op_mulsh_i64: -+ case INDEX_op_muluh_i32: -+ case INDEX_op_muluh_i64: -+ case INDEX_op_div_i32: -+ case INDEX_op_div_i64: -+ case INDEX_op_divu_i32: -+ case INDEX_op_divu_i64: -+ case INDEX_op_rem_i32: -+ case INDEX_op_rem_i64: -+ case INDEX_op_remu_i32: -+ case INDEX_op_remu_i64: -+ return C_O1_I2(r, rZ, rZ); -+ - default: - g_assert_not_reached(); - } -diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h -index e59c2a7bec..2ac2c342c7 100644 ---- a/tcg/loongarch64/tcg-target.h -+++ b/tcg/loongarch64/tcg-target.h -@@ -93,8 +93,8 @@ typedef enum { - - /* optional instructions */ - #define TCG_TARGET_HAS_movcond_i32 0 --#define TCG_TARGET_HAS_div_i32 0 --#define TCG_TARGET_HAS_rem_i32 0 -+#define TCG_TARGET_HAS_div_i32 1 -+#define TCG_TARGET_HAS_rem_i32 1 - #define TCG_TARGET_HAS_div2_i32 0 - #define TCG_TARGET_HAS_rot_i32 1 - #define TCG_TARGET_HAS_deposit_i32 1 -@@ -105,8 +105,8 @@ typedef enum { - #define TCG_TARGET_HAS_sub2_i32 0 - #define TCG_TARGET_HAS_mulu2_i32 0 - #define TCG_TARGET_HAS_muls2_i32 0 --#define TCG_TARGET_HAS_muluh_i32 0 --#define TCG_TARGET_HAS_mulsh_i32 0 -+#define TCG_TARGET_HAS_muluh_i32 1 -+#define TCG_TARGET_HAS_mulsh_i32 1 - #define TCG_TARGET_HAS_ext8s_i32 1 - #define TCG_TARGET_HAS_ext16s_i32 1 - #define TCG_TARGET_HAS_ext8u_i32 1 -@@ -130,8 +130,8 @@ typedef enum { - - /* 64-bit operations */ - #define TCG_TARGET_HAS_movcond_i64 0 --#define TCG_TARGET_HAS_div_i64 0 --#define TCG_TARGET_HAS_rem_i64 0 -+#define TCG_TARGET_HAS_div_i64 1 -+#define TCG_TARGET_HAS_rem_i64 1 - #define TCG_TARGET_HAS_div2_i64 0 - #define TCG_TARGET_HAS_rot_i64 1 - #define TCG_TARGET_HAS_deposit_i64 1 -@@ -163,8 +163,8 @@ typedef enum { - #define TCG_TARGET_HAS_sub2_i64 0 - #define TCG_TARGET_HAS_mulu2_i64 0 - #define TCG_TARGET_HAS_muls2_i64 0 --#define TCG_TARGET_HAS_muluh_i64 0 --#define TCG_TARGET_HAS_mulsh_i64 0 -+#define TCG_TARGET_HAS_muluh_i64 1 -+#define TCG_TARGET_HAS_mulsh_i64 1 - - /* not defined -- call should be eliminated at compile time */ - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0019-tcg-loongarch64-Implement-br-brcond-ops.patch b/app-emulation/qemu/files/loongarch/v6-0019-tcg-loongarch64-Implement-br-brcond-ops.patch deleted file mode 100644 index eaa5f2c..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0019-tcg-loongarch64-Implement-br-brcond-ops.patch +++ /dev/null @@ -1,109 +0,0 @@ -From de76e0fceb9d18b426cb4b404c1646bb4f90a663 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:07:38 +0800 -Subject: [PATCH v6 19/30] tcg/loongarch64: Implement br/brcond ops -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target-con-set.h | 1 + - tcg/loongarch64/tcg-target.c.inc | 53 ++++++++++++++++++++++++++++ - 2 files changed, 54 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index fb56f3a295..367689c2e2 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -15,6 +15,7 @@ - * tcg-target-con-str.h; the constraint combination is inclusive or. - */ - C_O0_I1(r) -+C_O0_I2(rZ, rZ) - C_O1_I1(r, r) - C_O1_I2(r, r, rC) - C_O1_I2(r, r, ri) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 67f07a3853..816b16f10f 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -434,6 +434,44 @@ static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, - tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); - } - -+/* -+ * Branch helpers -+ */ -+ -+static const struct { -+ LoongArchInsn op; -+ bool swap; -+} tcg_brcond_to_loongarch[] = { -+ [TCG_COND_EQ] = { OPC_BEQ, false }, -+ [TCG_COND_NE] = { OPC_BNE, false }, -+ [TCG_COND_LT] = { OPC_BGT, true }, -+ [TCG_COND_GE] = { OPC_BLE, true }, -+ [TCG_COND_LE] = { OPC_BLE, false }, -+ [TCG_COND_GT] = { OPC_BGT, false }, -+ [TCG_COND_LTU] = { OPC_BGTU, true }, -+ [TCG_COND_GEU] = { OPC_BLEU, true }, -+ [TCG_COND_LEU] = { OPC_BLEU, false }, -+ [TCG_COND_GTU] = { OPC_BGTU, false } -+}; -+ -+static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, -+ TCGReg arg2, TCGLabel *l) -+{ -+ LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; -+ -+ tcg_debug_assert(op != 0); -+ -+ if (tcg_brcond_to_loongarch[cond].swap) { -+ TCGReg t = arg1; -+ arg1 = arg2; -+ arg2 = t; -+ } -+ -+ /* all conditional branch insns belong to DJSk16-format */ -+ tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); -+ tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); -+} -+ - /* - * Entry-points - */ -@@ -456,6 +494,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); - break; - -+ case INDEX_op_br: -+ tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), -+ 0); -+ tcg_out_opc_b(s, 0); -+ break; -+ -+ case INDEX_op_brcond_i32: -+ case INDEX_op_brcond_i64: -+ tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); -+ break; -+ - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - tcg_out_ext8s(s, a0, a1); -@@ -779,6 +828,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_goto_ptr: - return C_O0_I1(r); - -+ case INDEX_op_brcond_i32: -+ case INDEX_op_brcond_i64: -+ return C_O0_I2(rZ, rZ); -+ - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - case INDEX_op_ext8u_i32: --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0020-tcg-loongarch64-Implement-setcond-ops.patch b/app-emulation/qemu/files/loongarch/v6-0020-tcg-loongarch64-Implement-setcond-ops.patch deleted file mode 100644 index 06cb63a..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0020-tcg-loongarch64-Implement-setcond-ops.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 509b3ca2c6f114f61cbd7e5fe4a45d609156e8e8 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:11:15 +0800 -Subject: [PATCH v6 20/30] tcg/loongarch64: Implement setcond ops - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target-con-set.h | 1 + - tcg/loongarch64/tcg-target.c.inc | 69 ++++++++++++++++++++++++++++ - 2 files changed, 70 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index 367689c2e2..a2ec61237e 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -22,6 +22,7 @@ C_O1_I2(r, r, ri) - C_O1_I2(r, r, rI) - C_O1_I2(r, r, rU) - C_O1_I2(r, r, rW) -+C_O1_I2(r, r, rZ) - C_O1_I2(r, 0, rZ) - C_O1_I2(r, rZ, rN) - C_O1_I2(r, rZ, rZ) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 816b16f10f..682bf76ceb 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -434,6 +434,66 @@ static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, - tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); - } - -+static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, -+ TCGReg arg1, TCGReg arg2, bool c2) -+{ -+ TCGReg tmp; -+ -+ if (c2) { -+ tcg_debug_assert(arg2 == 0); -+ } -+ -+ switch (cond) { -+ case TCG_COND_EQ: -+ if (c2) { -+ tmp = arg1; -+ } else { -+ tcg_out_opc_sub_d(s, ret, arg1, arg2); -+ tmp = ret; -+ } -+ tcg_out_opc_sltui(s, ret, tmp, 1); -+ break; -+ case TCG_COND_NE: -+ if (c2) { -+ tmp = arg1; -+ } else { -+ tcg_out_opc_sub_d(s, ret, arg1, arg2); -+ tmp = ret; -+ } -+ tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); -+ break; -+ case TCG_COND_LT: -+ tcg_out_opc_slt(s, ret, arg1, arg2); -+ break; -+ case TCG_COND_GE: -+ tcg_out_opc_slt(s, ret, arg1, arg2); -+ tcg_out_opc_xori(s, ret, ret, 1); -+ break; -+ case TCG_COND_LE: -+ tcg_out_setcond(s, TCG_COND_GE, ret, arg2, arg1, false); -+ break; -+ case TCG_COND_GT: -+ tcg_out_setcond(s, TCG_COND_LT, ret, arg2, arg1, false); -+ break; -+ case TCG_COND_LTU: -+ tcg_out_opc_sltu(s, ret, arg1, arg2); -+ break; -+ case TCG_COND_GEU: -+ tcg_out_opc_sltu(s, ret, arg1, arg2); -+ tcg_out_opc_xori(s, ret, ret, 1); -+ break; -+ case TCG_COND_LEU: -+ tcg_out_setcond(s, TCG_COND_GEU, ret, arg2, arg1, false); -+ break; -+ case TCG_COND_GTU: -+ tcg_out_setcond(s, TCG_COND_LTU, ret, arg2, arg1, false); -+ break; -+ default: -+ g_assert_not_reached(); -+ break; -+ } -+} -+ - /* - * Branch helpers - */ -@@ -815,6 +875,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_opc_mod_du(s, a0, a1, a2); - break; - -+ case INDEX_op_setcond_i32: -+ case INDEX_op_setcond_i64: -+ tcg_out_setcond(s, args[3], a0, a1, a2, c2); -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - default: -@@ -901,6 +966,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_ctz_i64: - return C_O1_I2(r, r, rW); - -+ case INDEX_op_setcond_i32: -+ case INDEX_op_setcond_i64: -+ return C_O1_I2(r, r, rZ); -+ - case INDEX_op_deposit_i32: - case INDEX_op_deposit_i64: - /* Must deposit into the same register as input */ --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0021-tcg-loongarch64-Implement-tcg_out_call.patch b/app-emulation/qemu/files/loongarch/v6-0021-tcg-loongarch64-Implement-tcg_out_call.patch deleted file mode 100644 index 19ab0bf..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0021-tcg-loongarch64-Implement-tcg_out_call.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 558a3ae3136e3af93d1171f81eeff961bdb137f4 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:16:09 +0800 -Subject: [PATCH v6 21/30] tcg/loongarch64: Implement tcg_out_call - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++ - 1 file changed, 34 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 682bf76ceb..e470d7e145 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -532,6 +532,39 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, - tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); - } - -+static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) -+{ -+ TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; -+ ptrdiff_t offset = tcg_pcrel_diff(s, arg); -+ -+ tcg_debug_assert((offset & 3) == 0); -+ if (offset == sextreg(offset, 0, 28)) { -+ /* short jump: +/- 256MiB */ -+ if (tail) { -+ tcg_out_opc_b(s, offset >> 2); -+ } else { -+ tcg_out_opc_bl(s, offset >> 2); -+ } -+ } else if (offset == sextreg(offset, 0, 38)) { -+ /* long jump: +/- 256GiB */ -+ tcg_target_long lo = sextreg(offset, 0, 18); -+ tcg_target_long hi = offset - lo; -+ tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); -+ tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); -+ } else { -+ /* far jump: 64-bit */ -+ tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); -+ tcg_target_long hi = (tcg_target_long)arg - lo; -+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); -+ tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); -+ } -+} -+ -+static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) -+{ -+ tcg_out_call_int(s, arg, false); -+} -+ - /* - * Entry-points - */ -@@ -882,6 +915,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: -+ case INDEX_op_call: /* Always emitted via tcg_out_call. */ - default: - g_assert_not_reached(); - } --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0022-tcg-loongarch64-Implement-simple-load-store-ops.patch b/app-emulation/qemu/files/loongarch/v6-0022-tcg-loongarch64-Implement-simple-load-store-ops.patch deleted file mode 100644 index 7608f30..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0022-tcg-loongarch64-Implement-simple-load-store-ops.patch +++ /dev/null @@ -1,194 +0,0 @@ -From 33fd112e4190f55c714ce6b3b16d83c54fbe3309 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:22:45 +0800 -Subject: [PATCH v6 22/30] tcg/loongarch64: Implement simple load/store ops -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - tcg/loongarch64/tcg-target-con-set.h | 1 + - tcg/loongarch64/tcg-target.c.inc | 131 +++++++++++++++++++++++++++ - 2 files changed, 132 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index a2ec61237e..e54ca9b2de 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -15,6 +15,7 @@ - * tcg-target-con-str.h; the constraint combination is inclusive or. - */ - C_O0_I1(r) -+C_O0_I2(rZ, r) - C_O0_I2(rZ, rZ) - C_O1_I1(r, r) - C_O1_I2(r, r, rC) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index e470d7e145..fec22cfaf6 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -565,6 +565,73 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) - tcg_out_call_int(s, arg, false); - } - -+/* -+ * Load/store helpers -+ */ -+ -+static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, -+ TCGReg addr, intptr_t offset) -+{ -+ intptr_t imm12 = sextreg(offset, 0, 12); -+ -+ if (offset != imm12) { -+ intptr_t diff = offset - (uintptr_t)s->code_ptr; -+ -+ if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { -+ imm12 = sextreg(diff, 0, 12); -+ tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); -+ } else { -+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); -+ if (addr != TCG_REG_ZERO) { -+ tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); -+ } -+ } -+ addr = TCG_REG_TMP2; -+ } -+ -+ switch (opc) { -+ case OPC_LD_B: -+ case OPC_LD_BU: -+ case OPC_LD_H: -+ case OPC_LD_HU: -+ case OPC_LD_W: -+ case OPC_LD_WU: -+ case OPC_LD_D: -+ case OPC_ST_B: -+ case OPC_ST_H: -+ case OPC_ST_W: -+ case OPC_ST_D: -+ tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); -+ break; -+ default: -+ g_assert_not_reached(); -+ } -+} -+ -+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, -+ TCGReg arg1, intptr_t arg2) -+{ -+ bool is_32bit = type == TCG_TYPE_I32; -+ tcg_out_ldst(s, is_32bit ? OPC_LD_W : OPC_LD_D, arg, arg1, arg2); -+} -+ -+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, -+ TCGReg arg1, intptr_t arg2) -+{ -+ bool is_32bit = type == TCG_TYPE_I32; -+ tcg_out_ldst(s, is_32bit ? OPC_ST_W : OPC_ST_D, arg, arg1, arg2); -+} -+ -+static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, -+ TCGReg base, intptr_t ofs) -+{ -+ if (val == 0) { -+ tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); -+ return true; -+ } -+ return false; -+} -+ - /* - * Entry-points - */ -@@ -913,6 +980,49 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_setcond(s, args[3], a0, a1, a2, c2); - break; - -+ case INDEX_op_ld8s_i32: -+ case INDEX_op_ld8s_i64: -+ tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); -+ break; -+ case INDEX_op_ld8u_i32: -+ case INDEX_op_ld8u_i64: -+ tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); -+ break; -+ case INDEX_op_ld16s_i32: -+ case INDEX_op_ld16s_i64: -+ tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); -+ break; -+ case INDEX_op_ld16u_i32: -+ case INDEX_op_ld16u_i64: -+ tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); -+ break; -+ case INDEX_op_ld_i32: -+ case INDEX_op_ld32s_i64: -+ tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); -+ break; -+ case INDEX_op_ld32u_i64: -+ tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); -+ break; -+ case INDEX_op_ld_i64: -+ tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); -+ break; -+ -+ case INDEX_op_st8_i32: -+ case INDEX_op_st8_i64: -+ tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); -+ break; -+ case INDEX_op_st16_i32: -+ case INDEX_op_st16_i64: -+ tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); -+ break; -+ case INDEX_op_st_i32: -+ case INDEX_op_st32_i64: -+ tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); -+ break; -+ case INDEX_op_st_i64: -+ tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ -@@ -927,6 +1037,15 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_goto_ptr: - return C_O0_I1(r); - -+ case INDEX_op_st8_i32: -+ case INDEX_op_st8_i64: -+ case INDEX_op_st16_i32: -+ case INDEX_op_st16_i64: -+ case INDEX_op_st32_i64: -+ case INDEX_op_st_i32: -+ case INDEX_op_st_i64: -+ return C_O0_I2(rZ, r); -+ - case INDEX_op_brcond_i32: - case INDEX_op_brcond_i64: - return C_O0_I2(rZ, rZ); -@@ -954,6 +1073,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_bswap32_i32: - case INDEX_op_bswap32_i64: - case INDEX_op_bswap64_i64: -+ case INDEX_op_ld8s_i32: -+ case INDEX_op_ld8s_i64: -+ case INDEX_op_ld8u_i32: -+ case INDEX_op_ld8u_i64: -+ case INDEX_op_ld16s_i32: -+ case INDEX_op_ld16s_i64: -+ case INDEX_op_ld16u_i32: -+ case INDEX_op_ld16u_i64: -+ case INDEX_op_ld32s_i64: -+ case INDEX_op_ld32u_i64: -+ case INDEX_op_ld_i32: -+ case INDEX_op_ld_i64: - return C_O1_I1(r, r); - - case INDEX_op_andc_i32: --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0023-tcg-loongarch64-Add-softmmu-load-store-helpers-im.patch b/app-emulation/qemu/files/loongarch/v6-0023-tcg-loongarch64-Add-softmmu-load-store-helpers-im.patch deleted file mode 100644 index 4411b3c..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0023-tcg-loongarch64-Add-softmmu-load-store-helpers-im.patch +++ /dev/null @@ -1,422 +0,0 @@ -From 30993dbd67ab41c71f8b81c4a81b77244df3a3f4 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:47:03 +0800 -Subject: [PATCH v6 23/30] tcg/loongarch64: Add softmmu load/store helpers, - implement qemu_ld/qemu_st ops - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target-con-set.h | 2 + - tcg/loongarch64/tcg-target.c.inc | 353 +++++++++++++++++++++++++++ - 2 files changed, 355 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h -index e54ca9b2de..349c672687 100644 ---- a/tcg/loongarch64/tcg-target-con-set.h -+++ b/tcg/loongarch64/tcg-target-con-set.h -@@ -17,7 +17,9 @@ - C_O0_I1(r) - C_O0_I2(rZ, r) - C_O0_I2(rZ, rZ) -+C_O0_I2(LZ, L) - C_O1_I1(r, r) -+C_O1_I1(r, L) - C_O1_I2(r, r, rC) - C_O1_I2(r, r, ri) - C_O1_I2(r, r, rI) -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index fec22cfaf6..ebf886ef8c 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -117,6 +117,11 @@ static const int tcg_target_call_oarg_regs[] = { - TCG_REG_A1, - }; - -+#ifndef CONFIG_SOFTMMU -+#define USE_GUEST_BASE (guest_base != 0) -+#define TCG_GUEST_BASE_REG TCG_REG_S1 -+#endif -+ - #define TCG_CT_CONST_ZERO 0x100 - #define TCG_CT_CONST_S12 0x200 - #define TCG_CT_CONST_N12 0x400 -@@ -632,6 +637,333 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - return false; - } - -+/* -+ * Load/store helpers for SoftMMU, and qemu_ld/st implementations -+ */ -+ -+#if defined(CONFIG_SOFTMMU) -+#include "../tcg-ldst.c.inc" -+ -+/* -+ * helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, -+ * TCGMemOpIdx oi, uintptr_t ra) -+ */ -+static void * const qemu_ld_helpers[4] = { -+ [MO_8] = helper_ret_ldub_mmu, -+ [MO_16] = helper_le_lduw_mmu, -+ [MO_32] = helper_le_ldul_mmu, -+ [MO_64] = helper_le_ldq_mmu, -+}; -+ -+/* -+ * helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, -+ * uintxx_t val, TCGMemOpIdx oi, -+ * uintptr_t ra) -+ */ -+static void * const qemu_st_helpers[4] = { -+ [MO_8] = helper_ret_stb_mmu, -+ [MO_16] = helper_le_stw_mmu, -+ [MO_32] = helper_le_stl_mmu, -+ [MO_64] = helper_le_stq_mmu, -+}; -+ -+/* We expect to use a 12-bit negative offset from ENV. */ -+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); -+ -+static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) -+{ -+ tcg_out_opc_b(s, 0); -+ return reloc_br_sd10k16(s->code_ptr - 1, target); -+} -+ -+/* -+ * Emits common code for TLB addend lookup, that eventually loads the -+ * addend in TCG_REG_TMP2. -+ */ -+static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGMemOpIdx oi, -+ tcg_insn_unit **label_ptr, bool is_load) -+{ -+ MemOp opc = get_memop(oi); -+ unsigned s_bits = opc & MO_SIZE; -+ unsigned a_bits = get_alignment_bits(opc); -+ tcg_target_long compare_mask; -+ int mem_index = get_mmuidx(oi); -+ int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); -+ int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); -+ int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); -+ -+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); -+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); -+ -+ tcg_out_opc_srli_d(s, TCG_REG_TMP2, addrl, -+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); -+ tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); -+ tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); -+ -+ /* Load the tlb comparator and the addend. */ -+ tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, -+ is_load ? offsetof(CPUTLBEntry, addr_read) -+ : offsetof(CPUTLBEntry, addr_write)); -+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, -+ offsetof(CPUTLBEntry, addend)); -+ -+ /* We don't support unaligned accesses. */ -+ if (a_bits < s_bits) { -+ a_bits = s_bits; -+ } -+ /* Clear the non-page, non-alignment bits from the address. */ -+ compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1); -+ tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); -+ tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl); -+ -+ /* Compare masked address with the TLB entry. */ -+ label_ptr[0] = s->code_ptr; -+ tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); -+ -+ /* TLB Hit - addend in TCG_REG_TMP2, ready for use. */ -+} -+ -+static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, -+ TCGType type, -+ TCGReg datalo, TCGReg addrlo, -+ void *raddr, tcg_insn_unit **label_ptr) -+{ -+ TCGLabelQemuLdst *label = new_ldst_label(s); -+ -+ label->is_ld = is_ld; -+ label->oi = oi; -+ label->type = type; -+ label->datalo_reg = datalo; -+ label->datahi_reg = 0; /* unused */ -+ label->addrlo_reg = addrlo; -+ label->addrhi_reg = 0; /* unused */ -+ label->raddr = tcg_splitwx_to_rx(raddr); -+ label->label_ptr[0] = label_ptr[0]; -+} -+ -+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -+{ -+ TCGMemOpIdx oi = l->oi; -+ MemOp opc = get_memop(oi); -+ MemOp size = opc & MO_SIZE; -+ TCGType type = l->type; -+ -+ /* resolve label address */ -+ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { -+ return false; -+ } -+ -+ /* call load helper */ -+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); -+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); -+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi); -+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr); -+ -+ tcg_out_call(s, qemu_ld_helpers[size]); -+ -+ switch (opc & MO_SSIZE) { -+ case MO_SB: -+ tcg_out_ext8s(s, l->datalo_reg, TCG_REG_A0); -+ break; -+ case MO_SW: -+ tcg_out_ext16s(s, l->datalo_reg, TCG_REG_A0); -+ break; -+ case MO_SL: -+ tcg_out_ext32s(s, l->datalo_reg, TCG_REG_A0); -+ break; -+ case MO_UL: -+ if (type == TCG_TYPE_I32) { -+ /* MO_UL loads of i32 should be sign-extended too */ -+ tcg_out_ext32s(s, l->datalo_reg, TCG_REG_A0); -+ break; -+ } -+ /* fallthrough */ -+ default: -+ tcg_out_mov(s, type, l->datalo_reg, TCG_REG_A0); -+ break; -+ } -+ -+ return tcg_out_goto(s, l->raddr); -+} -+ -+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -+{ -+ TCGMemOpIdx oi = l->oi; -+ MemOp opc = get_memop(oi); -+ MemOp size = opc & MO_SIZE; -+ -+ /* resolve label address */ -+ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { -+ return false; -+ } -+ -+ /* call store helper */ -+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); -+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); -+ switch (size) { -+ case MO_8: -+ tcg_out_ext8u(s, TCG_REG_A2, l->datalo_reg); -+ break; -+ case MO_16: -+ tcg_out_ext16u(s, TCG_REG_A2, l->datalo_reg); -+ break; -+ case MO_32: -+ tcg_out_ext32u(s, TCG_REG_A2, l->datalo_reg); -+ break; -+ case MO_64: -+ tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_A2, l->datalo_reg); -+ break; -+ default: -+ g_assert_not_reached(); -+ break; -+ } -+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); -+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); -+ -+ tcg_out_call(s, qemu_st_helpers[size]); -+ -+ return tcg_out_goto(s, l->raddr); -+} -+#endif /* CONFIG_SOFTMMU */ -+ -+/* -+ * `ext32u` the address register into the temp register given, -+ * if target is 32-bit, no-op otherwise. -+ * -+ * Returns the address register ready for use with TLB addend. -+ */ -+static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s, -+ TCGReg addr, TCGReg tmp) -+{ -+ if (TARGET_LONG_BITS == 32) { -+ tcg_out_ext32u(s, tmp, addr); -+ return tmp; -+ } -+ return addr; -+} -+ -+static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj, -+ TCGReg rk, MemOp opc, TCGType type) -+{ -+ /* Byte swapping is left to middle-end expansion. */ -+ tcg_debug_assert((opc & MO_BSWAP) == 0); -+ -+ switch (opc & MO_SSIZE) { -+ case MO_UB: -+ tcg_out_opc_ldx_bu(s, rd, rj, rk); -+ break; -+ case MO_SB: -+ tcg_out_opc_ldx_b(s, rd, rj, rk); -+ break; -+ case MO_UW: -+ tcg_out_opc_ldx_hu(s, rd, rj, rk); -+ break; -+ case MO_SW: -+ tcg_out_opc_ldx_h(s, rd, rj, rk); -+ break; -+ case MO_UL: -+ if (type == TCG_TYPE_I64) { -+ tcg_out_opc_ldx_wu(s, rd, rj, rk); -+ break; -+ } -+ /* fallthrough */ -+ case MO_SL: -+ tcg_out_opc_ldx_w(s, rd, rj, rk); -+ break; -+ case MO_Q: -+ tcg_out_opc_ldx_d(s, rd, rj, rk); -+ break; -+ default: -+ g_assert_not_reached(); -+ } -+} -+ -+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type) -+{ -+ TCGReg addr_regl; -+ TCGReg data_regl; -+ TCGMemOpIdx oi; -+ MemOp opc; -+#if defined(CONFIG_SOFTMMU) -+ tcg_insn_unit *label_ptr[1]; -+#endif -+ TCGReg base; -+ -+ data_regl = *args++; -+ addr_regl = *args++; -+ oi = *args++; -+ opc = get_memop(oi); -+ -+#if defined(CONFIG_SOFTMMU) -+ tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1); -+ base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); -+ tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type); -+ add_qemu_ldst_label(s, 1, oi, type, -+ data_regl, addr_regl, -+ s->code_ptr, label_ptr); -+#else -+ base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); -+ TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; -+ tcg_out_qemu_ld_indexed(s, data_regl, base, guest_base_reg, opc, type); -+#endif -+} -+ -+static void tcg_out_qemu_st_indexed(TCGContext *s, TCGReg data, -+ TCGReg rj, TCGReg rk, MemOp opc) -+{ -+ /* Byte swapping is left to middle-end expansion. */ -+ tcg_debug_assert((opc & MO_BSWAP) == 0); -+ -+ switch (opc & MO_SIZE) { -+ case MO_8: -+ tcg_out_opc_stx_b(s, data, rj, rk); -+ break; -+ case MO_16: -+ tcg_out_opc_stx_h(s, data, rj, rk); -+ break; -+ case MO_32: -+ tcg_out_opc_stx_w(s, data, rj, rk); -+ break; -+ case MO_64: -+ tcg_out_opc_stx_d(s, data, rj, rk); -+ break; -+ default: -+ g_assert_not_reached(); -+ } -+} -+ -+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args) -+{ -+ TCGReg addr_regl; -+ TCGReg data_regl; -+ TCGMemOpIdx oi; -+ MemOp opc; -+#if defined(CONFIG_SOFTMMU) -+ tcg_insn_unit *label_ptr[1]; -+#endif -+ TCGReg base; -+ -+ data_regl = *args++; -+ addr_regl = *args++; -+ oi = *args++; -+ opc = get_memop(oi); -+ -+#if defined(CONFIG_SOFTMMU) -+ tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0); -+ base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); -+ tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc); -+ add_qemu_ldst_label(s, 0, oi, -+ 0, /* type param is unused for stores */ -+ data_regl, addr_regl, -+ s->code_ptr, label_ptr); -+#else -+ base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); -+ TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; -+ tcg_out_qemu_st_indexed(s, data_regl, base, guest_base_reg, opc); -+#endif -+} -+ - /* - * Entry-points - */ -@@ -1023,6 +1355,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); - break; - -+ case INDEX_op_qemu_ld_i32: -+ tcg_out_qemu_ld(s, args, TCG_TYPE_I32); -+ break; -+ case INDEX_op_qemu_ld_i64: -+ tcg_out_qemu_ld(s, args, TCG_TYPE_I64); -+ break; -+ case INDEX_op_qemu_st_i32: -+ tcg_out_qemu_st(s, args); -+ break; -+ case INDEX_op_qemu_st_i64: -+ tcg_out_qemu_st(s, args); -+ break; -+ - case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ - case INDEX_op_mov_i64: - case INDEX_op_call: /* Always emitted via tcg_out_call. */ -@@ -1050,6 +1395,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_brcond_i64: - return C_O0_I2(rZ, rZ); - -+ case INDEX_op_qemu_st_i32: -+ case INDEX_op_qemu_st_i64: -+ return C_O0_I2(LZ, L); -+ - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - case INDEX_op_ext8u_i32: -@@ -1087,6 +1436,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - case INDEX_op_ld_i64: - return C_O1_I1(r, r); - -+ case INDEX_op_qemu_ld_i32: -+ case INDEX_op_qemu_ld_i64: -+ return C_O1_I1(r, L); -+ - case INDEX_op_andc_i32: - case INDEX_op_andc_i64: - case INDEX_op_orc_i32: --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0024-tcg-loongarch64-Implement-tcg_target_qemu_prologu.patch b/app-emulation/qemu/files/loongarch/v6-0024-tcg-loongarch64-Implement-tcg_target_qemu_prologu.patch deleted file mode 100644 index 1943283..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0024-tcg-loongarch64-Implement-tcg_target_qemu_prologu.patch +++ /dev/null @@ -1,97 +0,0 @@ -From b63dcd259799c1eb741120dcd162130a2433d004 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:51:28 +0800 -Subject: [PATCH v6 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target.c.inc | 68 ++++++++++++++++++++++++++++++++ - 1 file changed, 68 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index ebf886ef8c..207d15ed88 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -968,6 +968,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args) - * Entry-points - */ - -+static const tcg_insn_unit *tb_ret_addr; -+ - static void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) -@@ -1517,3 +1519,69 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) - g_assert_not_reached(); - } - } -+ -+static const int tcg_target_callee_save_regs[] = { -+ TCG_REG_S0, /* used for the global env (TCG_AREG0) */ -+ TCG_REG_S1, -+ TCG_REG_S2, -+ TCG_REG_S3, -+ TCG_REG_S4, -+ TCG_REG_S5, -+ TCG_REG_S6, -+ TCG_REG_S7, -+ TCG_REG_S8, -+ TCG_REG_S9, -+ TCG_REG_RA, /* should be last for ABI compliance */ -+}; -+ -+/* Stack frame parameters. */ -+#define REG_SIZE (TCG_TARGET_REG_BITS / 8) -+#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) -+#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) -+#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ -+ + TCG_TARGET_STACK_ALIGN - 1) \ -+ & -TCG_TARGET_STACK_ALIGN) -+#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) -+ -+/* We're expecting to be able to use an immediate for frame allocation. */ -+QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); -+ -+/* Generate global QEMU prologue and epilogue code */ -+static void tcg_target_qemu_prologue(TCGContext *s) -+{ -+ int i; -+ -+ tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); -+ -+ /* TB prologue */ -+ tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); -+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { -+ tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], -+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE); -+ } -+ -+#if !defined(CONFIG_SOFTMMU) -+ if (USE_GUEST_BASE) { -+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); -+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); -+ } -+#endif -+ -+ /* Call generated code */ -+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); -+ tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); -+ -+ /* Return path for goto_ptr. Set return value to 0 */ -+ tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); -+ tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); -+ -+ /* TB epilogue */ -+ tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); -+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { -+ tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], -+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE); -+ } -+ -+ tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); -+ tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); -+} --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0025-tcg-loongarch64-Implement-exit_tb-goto_tb.patch b/app-emulation/qemu/files/loongarch/v6-0025-tcg-loongarch64-Implement-exit_tb-goto_tb.patch deleted file mode 100644 index 5266c3b..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0025-tcg-loongarch64-Implement-exit_tb-goto_tb.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 25c99267018255a248bacdb66abe6777c74a3dd7 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:52:15 +0800 -Subject: [PATCH v6 25/30] tcg/loongarch64: Implement exit_tb/goto_tb - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target.c.inc | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index 207d15ed88..d0b8ac05c9 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -980,6 +980,25 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, - int c2 = const_args[2]; - - switch (opc) { -+ case INDEX_op_exit_tb: -+ /* Reuse the zeroing that exists for goto_ptr. */ -+ if (a0 == 0) { -+ tcg_out_call_int(s, tcg_code_gen_epilogue, true); -+ } else { -+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); -+ tcg_out_call_int(s, tb_ret_addr, true); -+ } -+ break; -+ -+ case INDEX_op_goto_tb: -+ assert(s->tb_jmp_insn_offset == 0); -+ /* indirect jump method */ -+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, -+ (uintptr_t)(s->tb_jmp_target_addr + a0)); -+ tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); -+ set_jmp_reset_offset(s, a0); -+ break; -+ - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0026-tcg-loongarch64-Implement-tcg_target_init.patch b/app-emulation/qemu/files/loongarch/v6-0026-tcg-loongarch64-Implement-tcg_target_init.patch deleted file mode 100644 index 08599c8..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0026-tcg-loongarch64-Implement-tcg_target_init.patch +++ /dev/null @@ -1,49 +0,0 @@ -From b13e4dd3bf5b99bb591db343fa1f3a35a5f5734c Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:57:35 +0800 -Subject: [PATCH v6 26/30] tcg/loongarch64: Implement tcg_target_init - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target.c.inc | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index d0b8ac05c9..e3c73f9fe7 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -1604,3 +1604,30 @@ static void tcg_target_qemu_prologue(TCGContext *s) - tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); - tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); - } -+ -+static void tcg_target_init(TCGContext *s) -+{ -+ tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; -+ tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; -+ -+ tcg_target_call_clobber_regs = ALL_GENERAL_REGS; -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); -+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); -+ -+ s->reserved_regs = 0; -+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); -+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); -+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); -+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); -+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); -+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); -+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); -+} --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0027-tcg-loongarch64-Register-the-JIT.patch b/app-emulation/qemu/files/loongarch/v6-0027-tcg-loongarch64-Register-the-JIT.patch deleted file mode 100644 index 43f1f15..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0027-tcg-loongarch64-Register-the-JIT.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 7427256874c5677290402ee4c9bf4fcc1237bc99 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Mon, 20 Sep 2021 01:57:52 +0800 -Subject: [PATCH v6 27/30] tcg/loongarch64: Register the JIT - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - tcg/loongarch64/tcg-target.c.inc | 44 ++++++++++++++++++++++++++++++++ - 1 file changed, 44 insertions(+) - -diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc -index e3c73f9fe7..73f230b412 100644 ---- a/tcg/loongarch64/tcg-target.c.inc -+++ b/tcg/loongarch64/tcg-target.c.inc -@@ -1631,3 +1631,47 @@ static void tcg_target_init(TCGContext *s) - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); - } -+ -+typedef struct { -+ DebugFrameHeader h; -+ uint8_t fde_def_cfa[4]; -+ uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; -+} DebugFrame; -+ -+#define ELF_HOST_MACHINE EM_LOONGARCH -+ -+static const DebugFrame debug_frame = { -+ .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ -+ .h.cie.id = -1, -+ .h.cie.version = 1, -+ .h.cie.code_align = 1, -+ .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ -+ .h.cie.return_column = TCG_REG_RA, -+ -+ /* Total FDE size does not include the "len" member. */ -+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), -+ -+ .fde_def_cfa = { -+ 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ -+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ -+ (FRAME_SIZE >> 7) -+ }, -+ .fde_reg_ofs = { -+ 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ -+ 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ -+ 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ -+ 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ -+ 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ -+ 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ -+ 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ -+ 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ -+ 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ -+ 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ -+ 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ -+ } -+}; -+ -+void tcg_register_jit(const void *buf, size_t buf_size) -+{ -+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); -+} --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0028-linux-user-Add-safe-syscall-handling-for-loongarc.patch b/app-emulation/qemu/files/loongarch/v6-0028-linux-user-Add-safe-syscall-handling-for-loongarc.patch deleted file mode 100644 index 7ccf206..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0028-linux-user-Add-safe-syscall-handling-for-loongarc.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 7960d35a1db0aa0c29b30dc63d819ccccb73e8ac Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 22:05:26 +0800 -Subject: [PATCH v6 28/30] linux-user: Add safe syscall handling for - loongarch64 hosts - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson ---- - linux-user/host/loongarch64/hostdep.h | 34 ++++++++ - .../host/loongarch64/safe-syscall.inc.S | 80 +++++++++++++++++++ - 2 files changed, 114 insertions(+) - create mode 100644 linux-user/host/loongarch64/hostdep.h - create mode 100644 linux-user/host/loongarch64/safe-syscall.inc.S - -diff --git a/linux-user/host/loongarch64/hostdep.h b/linux-user/host/loongarch64/hostdep.h -new file mode 100644 -index 0000000000..e3d5fa703f ---- /dev/null -+++ b/linux-user/host/loongarch64/hostdep.h -@@ -0,0 +1,34 @@ -+/* -+ * hostdep.h : things which are dependent on the host architecture -+ * -+ * This work is licensed under the terms of the GNU GPL, version 2 or later. -+ * See the COPYING file in the top-level directory. -+ */ -+ -+#ifndef LOONGARCH64_HOSTDEP_H -+#define LOONGARCH64_HOSTDEP_H -+ -+/* We have a safe-syscall.inc.S */ -+#define HAVE_SAFE_SYSCALL -+ -+#ifndef __ASSEMBLER__ -+ -+/* These are defined by the safe-syscall.inc.S file */ -+extern char safe_syscall_start[]; -+extern char safe_syscall_end[]; -+ -+/* Adjust the signal context to rewind out of safe-syscall if we're in it */ -+static inline void rewind_if_in_safe_syscall(void *puc) -+{ -+ ucontext_t *uc = puc; -+ unsigned long long *pcreg = &uc->uc_mcontext.__pc; -+ -+ if (*pcreg > (uintptr_t)safe_syscall_start -+ && *pcreg < (uintptr_t)safe_syscall_end) { -+ *pcreg = (uintptr_t)safe_syscall_start; -+ } -+} -+ -+#endif /* __ASSEMBLER__ */ -+ -+#endif -diff --git a/linux-user/host/loongarch64/safe-syscall.inc.S b/linux-user/host/loongarch64/safe-syscall.inc.S -new file mode 100644 -index 0000000000..bb530248b3 ---- /dev/null -+++ b/linux-user/host/loongarch64/safe-syscall.inc.S -@@ -0,0 +1,80 @@ -+/* -+ * safe-syscall.inc.S : host-specific assembly fragment -+ * to handle signals occurring at the same time as system calls. -+ * This is intended to be included by linux-user/safe-syscall.S -+ * -+ * Ported to LoongArch by WANG Xuerui -+ * -+ * Based on safe-syscall.inc.S code for every other architecture, -+ * originally written by Richard Henderson -+ * Copyright (C) 2018 Linaro, Inc. -+ * -+ * This work is licensed under the terms of the GNU GPL, version 2 or later. -+ * See the COPYING file in the top-level directory. -+ */ -+ -+ .global safe_syscall_base -+ .global safe_syscall_start -+ .global safe_syscall_end -+ .type safe_syscall_base, @function -+ .type safe_syscall_start, @function -+ .type safe_syscall_end, @function -+ -+ /* -+ * This is the entry point for making a system call. The calling -+ * convention here is that of a C varargs function with the -+ * first argument an 'int *' to the signal_pending flag, the -+ * second one the system call number (as a 'long'), and all further -+ * arguments being syscall arguments (also 'long'). -+ * We return a long which is the syscall's return value, which -+ * may be negative-errno on failure. Conversion to the -+ * -1-and-errno-set convention is done by the calling wrapper. -+ */ -+safe_syscall_base: -+ .cfi_startproc -+ /* -+ * The syscall calling convention is nearly the same as C: -+ * we enter with a0 == *signal_pending -+ * a1 == syscall number -+ * a2 ... a7 == syscall arguments -+ * and return the result in a0 -+ * and the syscall instruction needs -+ * a7 == syscall number -+ * a0 ... a5 == syscall arguments -+ * and returns the result in a0 -+ * Shuffle everything around appropriately. -+ */ -+ move $t0, $a0 /* signal_pending pointer */ -+ move $t1, $a1 /* syscall number */ -+ move $a0, $a2 /* syscall arguments */ -+ move $a1, $a3 -+ move $a2, $a4 -+ move $a3, $a5 -+ move $a4, $a6 -+ move $a5, $a7 -+ move $a7, $t1 -+ -+ /* -+ * This next sequence of code works in conjunction with the -+ * rewind_if_safe_syscall_function(). If a signal is taken -+ * and the interrupted PC is anywhere between 'safe_syscall_start' -+ * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. -+ * The code sequence must therefore be able to cope with this, and -+ * the syscall instruction must be the final one in the sequence. -+ */ -+safe_syscall_start: -+ /* If signal_pending is non-zero, don't do the call */ -+ ld.w $t1, $t0, 0 -+ bnez $t1, 0f -+ syscall 0 -+safe_syscall_end: -+ /* code path for having successfully executed the syscall */ -+ jr $ra -+ -+0: -+ /* code path when we didn't execute the syscall */ -+ li.w $a0, -TARGET_ERESTARTSYS -+ jr $ra -+ .cfi_endproc -+ -+ .size safe_syscall_base, .-safe_syscall_base --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0029-accel-tcg-user-exec-Implement-CPU-specific-signal.patch b/app-emulation/qemu/files/loongarch/v6-0029-accel-tcg-user-exec-Implement-CPU-specific-signal.patch deleted file mode 100644 index 1aa4c2e..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0029-accel-tcg-user-exec-Implement-CPU-specific-signal.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 729e2698f5d0e17e68154a8a4842addf1d90afb7 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 22:04:12 +0800 -Subject: [PATCH v6 29/30] accel/tcg/user-exec: Implement CPU-specific signal - handler for loongarch64 hosts -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - accel/tcg/user-exec.c | 73 +++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 73 insertions(+) - -diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c -index 8fed542622..38d4ad8a7d 100644 ---- a/accel/tcg/user-exec.c -+++ b/accel/tcg/user-exec.c -@@ -878,6 +878,79 @@ int cpu_signal_handler(int host_signum, void *pinfo, - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); - } - -+#elif defined(__loongarch64) -+ -+int cpu_signal_handler(int host_signum, void *pinfo, -+ void *puc) -+{ -+ siginfo_t *info = pinfo; -+ ucontext_t *uc = puc; -+ greg_t pc = uc->uc_mcontext.__pc; -+ uint32_t insn = *(uint32_t *)pc; -+ int is_write = 0; -+ -+ /* Detect store by reading the instruction at the program counter. */ -+ switch ((insn >> 26) & 0b111111) { -+ case 0b001000: /* {ll,sc}.[wd] */ -+ switch ((insn >> 24) & 0b11) { -+ case 0b01: /* sc.w */ -+ case 0b11: /* sc.d */ -+ is_write = 1; -+ break; -+ } -+ break; -+ case 0b001001: /* {ld,st}ox4.[wd] ({ld,st}ptr.[wd]) */ -+ switch ((insn >> 24) & 0b11) { -+ case 0b01: /* stox4.w (stptr.w) */ -+ case 0b11: /* stox4.d (stptr.d) */ -+ is_write = 1; -+ break; -+ } -+ break; -+ case 0b001010: /* {ld,st}.* family */ -+ switch ((insn >> 22) & 0b1111) { -+ case 0b0100: /* st.b */ -+ case 0b0101: /* st.h */ -+ case 0b0110: /* st.w */ -+ case 0b0111: /* st.d */ -+ case 0b1101: /* fst.s */ -+ case 0b1111: /* fst.d */ -+ is_write = 1; -+ break; -+ } -+ break; -+ case 0b001110: /* indexed, atomic, bounds-checking memory operations */ -+ uint32_t sel = (insn >> 15) & 0b11111111111; -+ -+ switch (sel) { -+ case 0b00000100000: /* stx.b */ -+ case 0b00000101000: /* stx.h */ -+ case 0b00000110000: /* stx.w */ -+ case 0b00000111000: /* stx.d */ -+ case 0b00001110000: /* fstx.s */ -+ case 0b00001111000: /* fstx.d */ -+ case 0b00011101100: /* fstgt.s */ -+ case 0b00011101101: /* fstgt.d */ -+ case 0b00011101110: /* fstle.s */ -+ case 0b00011101111: /* fstle.d */ -+ case 0b00011111000: /* stgt.b */ -+ case 0b00011111001: /* stgt.h */ -+ case 0b00011111010: /* stgt.w */ -+ case 0b00011111011: /* stgt.d */ -+ case 0b00011111100: /* stle.b */ -+ case 0b00011111101: /* stle.h */ -+ case 0b00011111110: /* stle.w */ -+ case 0b00011111111: /* stle.d */ -+ case 0b00011000000 ... 0b00011100011: /* am* insns */ -+ is_write = 1; -+ break; -+ } -+ break; -+ } -+ -+ return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -+} -+ - #else - - #error host CPU specific signal handler needed --- -2.33.0 - diff --git a/app-emulation/qemu/files/loongarch/v6-0030-configure-meson.build-Mark-support-for-loongarch6.patch b/app-emulation/qemu/files/loongarch/v6-0030-configure-meson.build-Mark-support-for-loongarch6.patch deleted file mode 100644 index 003efa3..0000000 --- a/app-emulation/qemu/files/loongarch/v6-0030-configure-meson.build-Mark-support-for-loongarch6.patch +++ /dev/null @@ -1,78 +0,0 @@ -From f83b92ad38e4ef1bfdcb117a886f44ab8e14b7e8 Mon Sep 17 00:00:00 2001 -From: WANG Xuerui -Date: Sun, 19 Sep 2021 21:58:01 +0800 -Subject: [PATCH v6 30/30] configure, meson.build: Mark support for loongarch64 - hosts -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Example output of `uname -a` on an initial Gentoo LA64 port, running -the upstream submission version of Linux (with some very minor patches -not influencing output here): - -> Linux 5.14.0-10342-g37a00851b145 #5 SMP PREEMPT Tue Aug 10 12:56:24 PM CST 2021 loongarch64 GNU/Linux - -And the same on the vendor-supplied Loongnix 20 system, with an early -in-house port of Linux, and using the old-world ABI: - -> Linux 4.19.167-rc5.lnd.1-loongson-3 #1 SMP Sat Apr 17 07:32:32 UTC 2021 loongarch64 loongarch64 loongarch64 GNU/Linux - -So a name of "loongarch64" matches both, fortunately. - -Signed-off-by: WANG Xuerui -Reviewed-by: Richard Henderson -Reviewed-by: Philippe Mathieu-Daudé ---- - configure | 7 ++++++- - meson.build | 2 +- - 2 files changed, 7 insertions(+), 2 deletions(-) - -diff --git a/configure b/configure -index 1043ccce4f..3a9035385d 100755 ---- a/configure -+++ b/configure -@@ -659,6 +659,8 @@ elif check_define __arm__ ; then - cpu="arm" - elif check_define __aarch64__ ; then - cpu="aarch64" -+elif check_define __loongarch64 ; then -+ cpu="loongarch64" - else - cpu=$(uname -m) - fi -@@ -667,7 +669,7 @@ ARCH= - # Normalise host CPU name and set ARCH. - # Note that this case should only have supported host CPUs, not guests. - case "$cpu" in -- ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64) -+ ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64|loongarch64) - ;; - ppc64le) - ARCH="ppc64" -@@ -4969,6 +4971,9 @@ if test "$linux" = "yes" ; then - aarch64) - linux_arch=arm64 - ;; -+ loongarch*) -+ linux_arch=loongarch -+ ;; - mips64) - linux_arch=mips - ;; -diff --git a/meson.build b/meson.build -index 15ef4d3c41..fc55712ac3 100644 ---- a/meson.build -+++ b/meson.build -@@ -57,7 +57,7 @@ python = import('python').find_installation() - - supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] - supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', -- 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] -+ 'arm', 'aarch64', 'loongarch64', 'mips', 'mips64', 'sparc', 'sparc64'] - - cpu = host_machine.cpu_family() - targetos = host_machine.system() --- -2.33.0 - diff --git a/app-emulation/qemu/files/qemu-5.2.0-cleaner-werror.patch b/app-emulation/qemu/files/qemu-5.2.0-cleaner-werror.patch deleted file mode 100644 index 33115f1..0000000 --- a/app-emulation/qemu/files/qemu-5.2.0-cleaner-werror.patch +++ /dev/null @@ -1,40 +0,0 @@ --Wall -Wextra compains about unused arguments, -causes safe-stack to be mis-detected. ---- a/configure -+++ b/configure -@@ -2293,7 +2293,7 @@ fi - cat > $TMPC << EOF - #include - #include --int main(int argc, char *argv[]) { -+int main(void) { - return printf("%zu", SIZE_MAX); - } - EOF -@@ -4911,7 +4911,7 @@ fi - - if test "$safe_stack" = "yes"; then - cat > $TMPC << EOF --int main(int argc, char *argv[]) -+int main(void) - { - #if ! __has_feature(safe_stack) - #error SafeStack Disabled -@@ -4933,7 +4933,7 @@ EOF - fi - else - cat > $TMPC << EOF --int main(int argc, char *argv[]) -+int main(void) - { - #if defined(__has_feature) - #if __has_feature(safe_stack) -@@ -5283,7 +5283,7 @@ static const int Z = 1; - #define TAUT(X) ((X) == Z) - #define PAREN(X, Y) (X == Y) - #define ID(X) (X) --int main(int argc, char *argv[]) -+int main(void) - { - int x = 0, y = 0; - x = ID(x); diff --git a/app-emulation/qemu/files/qemu-5.2.0-dce-locks.patch b/app-emulation/qemu/files/qemu-5.2.0-dce-locks.patch deleted file mode 100644 index 679a9f3..0000000 --- a/app-emulation/qemu/files/qemu-5.2.0-dce-locks.patch +++ /dev/null @@ -1,18 +0,0 @@ -Fix CFLAGS=-Og build break. -Og fails because gcc does not enable dead -code elimination (but does set __OPTIMIZE__ define). - -The fix avoids DCE reliance downstream entirely. - -Reported-by: Luke-Jr -Bug: https://bugs.gentoo.org/782364 ---- a/include/qemu/lockable.h -+++ b/include/qemu/lockable.h -@@ -28,7 +28,7 @@ struct QemuLockable { - * to QEMU_MAKE_LOCKABLE. For optimized builds, we can rely on dead-code elimination - * from the compiler, and give the errors already at link time. - */ --#if defined(__OPTIMIZE__) && !defined(__SANITIZE_ADDRESS__) -+#if defined(__OPTIMIZE__) && !defined(__SANITIZE_ADDRESS__) && defined(VALIDATE_LOCKS_VIA_DCE) - void unknown_lock_type(void *); - #else - static inline void unknown_lock_type(void *unused) diff --git a/app-emulation/qemu/files/qemu-5.2.0-strings.patch b/app-emulation/qemu/files/qemu-5.2.0-strings.patch deleted file mode 100644 index 0b3dcdc..0000000 --- a/app-emulation/qemu/files/qemu-5.2.0-strings.patch +++ /dev/null @@ -1,23 +0,0 @@ -https://bugs.gentoo.org/759310 ---- a/configure -+++ b/configure -@@ -521,6 +521,7 @@ ld="${LD-${cross_prefix}ld}" - ranlib="${RANLIB-${cross_prefix}ranlib}" - nm="${NM-${cross_prefix}nm}" - strip="${STRIP-${cross_prefix}strip}" -+strings="${STRINGS-${cross_prefix}strings}" - windres="${WINDRES-${cross_prefix}windres}" - pkg_config_exe="${PKG_CONFIG-${cross_prefix}pkg-config}" - query_pkg_config() { -@@ -2265,9 +2266,9 @@ int main(int argc, char *argv[]) { - EOF - - if compile_object ; then -- if strings -a $TMPO | grep -q BiGeNdIaN ; then -+ if $strings -a $TMPO | grep -q BiGeNdIaN ; then - bigendian="yes" -- elif strings -a $TMPO | grep -q LiTtLeEnDiAn ; then -+ elif $strings -a $TMPO | grep -q LiTtLeEnDiAn ; then - bigendian="no" - else - echo big/little test failed diff --git a/app-emulation/qemu/files/qemu-6.1.0-automagic-libbpf.patch b/app-emulation/qemu/files/qemu-6.1.0-automagic-libbpf.patch new file mode 100644 index 0000000..d067650 --- /dev/null +++ b/app-emulation/qemu/files/qemu-6.1.0-automagic-libbpf.patch @@ -0,0 +1,21 @@ +commit 080832e4f4801a28bd1170c49e61f6a0f5f05d03 +Author: Paolo Bonzini +Date: Tue Sep 7 12:45:12 2021 +0200 + + ebpf: only include in system emulators + + eBPF files are being included in user emulators, which is useless and + also breaks compilation because ebpf/trace-events is only processed + if a system emulator is included in the build. + + Resolves: https://gitlab.com/qemu-project/qemu/-/issues/566 + Signed-off-by: Paolo Bonzini + Signed-off-by: Jason Wang + +diff --git a/ebpf/meson.build b/ebpf/meson.build +index 9cd0635370..2dd0fd8948 100644 +--- a/ebpf/meson.build ++++ b/ebpf/meson.build +@@ -1 +1 @@ +-common_ss.add(when: libbpf, if_true: files('ebpf_rss.c'), if_false: files('ebpf_rss-stub.c')) ++softmmu_ss.add(when: libbpf, if_true: files('ebpf_rss.c'), if_false: files('ebpf_rss-stub.c')) diff --git a/app-emulation/qemu/files/qemu-6.1.0-data-corruption.patch b/app-emulation/qemu/files/qemu-6.1.0-data-corruption.patch new file mode 100644 index 0000000..25c7884 --- /dev/null +++ b/app-emulation/qemu/files/qemu-6.1.0-data-corruption.patch @@ -0,0 +1,114 @@ +commit cc071629539dc1f303175a7e2d4ab854c0a8b20f +Author: Paolo Bonzini +Date: Thu Sep 23 09:04:36 2021 -0400 + + block: introduce max_hw_iov for use in scsi-generic + + Linux limits the size of iovecs to 1024 (UIO_MAXIOV in the kernel + sources, IOV_MAX in POSIX). Because of this, on some host adapters + requests with many iovecs are rejected with -EINVAL by the + io_submit() or readv()/writev() system calls. + + In fact, the same limit applies to SG_IO as well. To fix both the + EINVAL and the possible performance issues from using fewer iovecs + than allowed by Linux (some HBAs have max_segments as low as 128), + introduce a separate entry in BlockLimits to hold the max_segments + value from sysfs. This new limit is used only for SG_IO and clamped + to bs->bl.max_iov anyway, just like max_hw_transfer is clamped to + bs->bl.max_transfer. + + Reported-by: Halil Pasic + Cc: Hanna Reitz + Cc: Kevin Wolf + Cc: qemu-block@nongnu.org + Cc: qemu-stable@nongnu.org + Fixes: 18473467d5 ("file-posix: try BLKSECTGET on block devices too, do not round to power of 2", 2021-06-25) + Signed-off-by: Paolo Bonzini + Message-Id: <20210923130436.1187591-1-pbonzini@redhat.com> + Signed-off-by: Kevin Wolf + +diff --git a/block/block-backend.c b/block/block-backend.c +index 6140d133e2..ba2b5ebb10 100644 +--- a/block/block-backend.c ++++ b/block/block-backend.c +@@ -1986,6 +1986,12 @@ uint32_t blk_get_max_transfer(BlockBackend *blk) + return ROUND_DOWN(max, blk_get_request_alignment(blk)); + } + ++int blk_get_max_hw_iov(BlockBackend *blk) ++{ ++ return MIN_NON_ZERO(blk->root->bs->bl.max_hw_iov, ++ blk->root->bs->bl.max_iov); ++} ++ + int blk_get_max_iov(BlockBackend *blk) + { + return blk->root->bs->bl.max_iov; +diff --git a/block/file-posix.c b/block/file-posix.c +index c62e42743d..53be0bdc1b 100644 +--- a/block/file-posix.c ++++ b/block/file-posix.c +@@ -1273,7 +1273,7 @@ static void raw_refresh_limits(BlockDriverState *bs, Error **errp) + + ret = hdev_get_max_segments(s->fd, &st); + if (ret > 0) { +- bs->bl.max_iov = ret; ++ bs->bl.max_hw_iov = ret; + } + } + } +diff --git a/block/io.c b/block/io.c +index 18d345a87a..bb0a254def 100644 +--- a/block/io.c ++++ b/block/io.c +@@ -136,6 +136,7 @@ static void bdrv_merge_limits(BlockLimits *dst, const BlockLimits *src) + dst->min_mem_alignment = MAX(dst->min_mem_alignment, + src->min_mem_alignment); + dst->max_iov = MIN_NON_ZERO(dst->max_iov, src->max_iov); ++ dst->max_hw_iov = MIN_NON_ZERO(dst->max_hw_iov, src->max_hw_iov); + } + + typedef struct BdrvRefreshLimitsState { +diff --git a/hw/scsi/scsi-generic.c b/hw/scsi/scsi-generic.c +index 665baf900e..0306ccc7b1 100644 +--- a/hw/scsi/scsi-generic.c ++++ b/hw/scsi/scsi-generic.c +@@ -180,7 +180,7 @@ static int scsi_handle_inquiry_reply(SCSIGenericReq *r, SCSIDevice *s, int len) + page = r->req.cmd.buf[2]; + if (page == 0xb0) { + uint64_t max_transfer = blk_get_max_hw_transfer(s->conf.blk); +- uint32_t max_iov = blk_get_max_iov(s->conf.blk); ++ uint32_t max_iov = blk_get_max_hw_iov(s->conf.blk); + + assert(max_transfer); + max_transfer = MIN_NON_ZERO(max_transfer, max_iov * qemu_real_host_page_size) +diff --git a/include/block/block_int.h b/include/block/block_int.h +index ffe86068d4..f4c75e8ba9 100644 +--- a/include/block/block_int.h ++++ b/include/block/block_int.h +@@ -718,6 +718,13 @@ typedef struct BlockLimits { + */ + uint64_t max_hw_transfer; + ++ /* Maximal number of scatter/gather elements allowed by the hardware. ++ * Applies whenever transfers to the device bypass the kernel I/O ++ * scheduler, for example with SG_IO. If larger than max_iov ++ * or if zero, blk_get_max_hw_iov will fall back to max_iov. ++ */ ++ int max_hw_iov; ++ + /* memory alignment, in bytes so that no bounce buffer is needed */ + size_t min_mem_alignment; + +diff --git a/include/sysemu/block-backend.h b/include/sysemu/block-backend.h +index 29d4fdbf63..82bae55161 100644 +--- a/include/sysemu/block-backend.h ++++ b/include/sysemu/block-backend.h +@@ -211,6 +211,7 @@ uint32_t blk_get_request_alignment(BlockBackend *blk); + uint32_t blk_get_max_transfer(BlockBackend *blk); + uint64_t blk_get_max_hw_transfer(BlockBackend *blk); + int blk_get_max_iov(BlockBackend *blk); ++int blk_get_max_hw_iov(BlockBackend *blk); + void blk_set_guest_block_size(BlockBackend *blk, int align); + void *blk_try_blockalign(BlockBackend *blk, size_t size); + void *blk_blockalign(BlockBackend *blk, size_t size); diff --git a/app-emulation/qemu/files/qemu-6.1.0-fix-unix-socket-copy.patch b/app-emulation/qemu/files/qemu-6.1.0-fix-unix-socket-copy.patch new file mode 100644 index 0000000..7701b26 --- /dev/null +++ b/app-emulation/qemu/files/qemu-6.1.0-fix-unix-socket-copy.patch @@ -0,0 +1,76 @@ +commit 118d527f2e4baec5fe8060b22a6212468b8e4d3f +Author: Michael Tokarev +Date: Wed Sep 1 16:16:24 2021 +0300 + + qemu-sockets: fix unix socket path copy (again) + + Commit 4cfd970ec188558daa6214f26203fe553fb1e01f added an + assert which ensures the path within an address of a unix + socket returned from the kernel is at least one byte and + does not exceed sun_path buffer. Both of this constraints + are wrong: + + A unix socket can be unnamed, in this case the path is + completely empty (not even \0) + + And some implementations (notable linux) can add extra + trailing byte (\0) _after_ the sun_path buffer if we + passed buffer larger than it (and we do). + + So remove the assertion (since it causes real-life breakage) + but at the same time fix the usage of sun_path. Namely, + we should not access sun_path[0] if kernel did not return + it at all (this is the case for unnamed sockets), + and use the returned salen when copyig actual path as an + upper constraint for the amount of bytes to copy - this + will ensure we wont exceed the information provided by + the kernel, regardless whenever there is a trailing \0 + or not. This also helps with unnamed sockets. + + Note the case of abstract socket, the sun_path is actually + a blob and can contain \0 characters, - it should not be + passed to g_strndup and the like, it should be accessed by + memcpy-like functions. + + Fixes: 4cfd970ec188558daa6214f26203fe553fb1e01f + Fixes: http://bugs.debian.org/993145 + Signed-off-by: Michael Tokarev + Reviewed-by: Daniel P. Berrangé + Reviewed-by: Marc-André Lureau + CC: qemu-stable@nongnu.org + +diff --git a/util/qemu-sockets.c b/util/qemu-sockets.c +index f2f3676d1f..c5043999e9 100644 +--- a/util/qemu-sockets.c ++++ b/util/qemu-sockets.c +@@ -1345,25 +1345,22 @@ socket_sockaddr_to_address_unix(struct sockaddr_storage *sa, + SocketAddress *addr; + struct sockaddr_un *su = (struct sockaddr_un *)sa; + +- assert(salen >= sizeof(su->sun_family) + 1 && +- salen <= sizeof(struct sockaddr_un)); +- + addr = g_new0(SocketAddress, 1); + addr->type = SOCKET_ADDRESS_TYPE_UNIX; ++ salen -= offsetof(struct sockaddr_un, sun_path); + #ifdef CONFIG_LINUX +- if (!su->sun_path[0]) { ++ if (salen > 0 && !su->sun_path[0]) { + /* Linux abstract socket */ +- addr->u.q_unix.path = g_strndup(su->sun_path + 1, +- salen - sizeof(su->sun_family) - 1); ++ addr->u.q_unix.path = g_strndup(su->sun_path + 1, salen - 1); + addr->u.q_unix.has_abstract = true; + addr->u.q_unix.abstract = true; + addr->u.q_unix.has_tight = true; +- addr->u.q_unix.tight = salen < sizeof(*su); ++ addr->u.q_unix.tight = salen < sizeof(su->sun_path); + return addr; + } + #endif + +- addr->u.q_unix.path = g_strndup(su->sun_path, sizeof(su->sun_path)); ++ addr->u.q_unix.path = g_strndup(su->sun_path, salen); + return addr; + } + #endif /* WIN32 */ diff --git a/app-emulation/qemu/metadata.xml b/app-emulation/qemu/metadata.xml index 7faebb3..d266bd0 100644 --- a/app-emulation/qemu/metadata.xml +++ b/app-emulation/qemu/metadata.xml @@ -9,6 +9,10 @@ zlogene@gentoo.org Mikle Kolyada + + ajak@gentoo.org + John Helmert III + virtualization@gentoo.org Gentoo Virtualization Project @@ -17,6 +21,7 @@ Adds support for braille displays using brltty Enables support for Linux's Async IO Enable alsa output for sound emulation + Enable eBPF support for RSS implementation. Enable disassembly support with dev-libs/capstone Support ISOs / -cdrom directives via HTTP or HTTPS. Enables firmware device tree support @@ -40,7 +45,7 @@ When the blobs are different, random corruption/bugs/crashes/etc... may be observed. Enable qemu plugin API via shared library loading. Enable pulseaudio output for sound emulation - Enable rados block device backend support, see http://ceph.newdream.net/wiki/QEMU-RBD + Enable rados block device backend support, see https://docs.ceph.com/en/mimic/rbd/qemu-rbd/ Enable the SDL-based console SDL Image support for icons Enable TCP/IP in hypervisor via net-libs/libslirp @@ -49,18 +54,16 @@ Build the User targets as static binaries Build the User and Software MMU (system) targets as well as tools as static binaries Enable SystemTAP/DTrace tracing - Enable the TCG Interpreter which can speed up or slowdown workloads depending on the host and guest CPUs being emulated. In the future it will be a runtime option but for now its - compile time. Enable jemalloc allocator support Enable jpeg image support for the VNC console server Enable png image support for the VNC console server Enable USB passthrough via dev-libs/libusb Use sys-apps/usbredir to redirect USB devices to another machine over TCP Enable VDE-based networking - Enable accelerated networking using vhost-net, see http://www.linux-kvm.org/page/VhostNet + Enable accelerated networking using vhost-net, see https://www.linux-kvm.org/page/VhostNet Enable shared file system access using the FUSE protocol carried over virtio. Enable experimental Virgil 3d (virtual software GPU) - Enable VirtFS via virtio-9p-pci / fsdev. See http://wiki.qemu.org/Documentation/9psetup + Enable VirtFS via virtio-9p-pci / fsdev. See https://wiki.qemu.org/Documentation/9psetup Enable terminal support (x11-libs/vte) in the GTK+ interface Add support for getting and setting POSIX extended attributes, through sys-apps/attr. Requisite for the virtfs backend. diff --git a/app-emulation/qemu/qemu-9999.ebuild b/app-emulation/qemu/qemu-9999.ebuild index 7a4be6c..c15115e 100644 --- a/app-emulation/qemu/qemu-9999.ebuild +++ b/app-emulation/qemu/qemu-9999.ebuild @@ -27,7 +27,7 @@ else fi DESCRIPTION="QEMU + Kernel-based Virtual Machine userland tools" -HOMEPAGE="http://www.qemu.org http://www.linux-kvm.org" +HOMEPAGE="https://www.qemu.org https://www.linux-kvm.org" LICENSE="GPL-2 LGPL-2 BSD-2" SLOT="0" @@ -179,7 +179,7 @@ SOFTMMU_TOOLS_DEPEND=" virtual/opengl media-libs/libepoxy[static-libs(+)] media-libs/mesa[static-libs(+)] - media-libs/mesa[egl,gbm] + media-libs/mesa[egl(+),gbm(+)] ) png? ( media-libs/libpng:0=[static-libs(+)] ) pulseaudio? ( media-sound/pulseaudio ) @@ -276,37 +276,6 @@ PATCHES=( "${FILESDIR}"/${PN}-5.2.0-disable-keymap.patch "${FILESDIR}"/${PN}-6.0.0-make.patch "${FILESDIR}"/${PN}-6.1.0-strings.patch - - "${FILESDIR}"/loongarch/v6-0001-elf-Add-machine-type-value-for-LoongArch.patch - "${FILESDIR}"/loongarch/v6-0002-MAINTAINERS-Add-tcg-loongarch64-entry-with-myself.patch - "${FILESDIR}"/loongarch/v6-0003-tcg-loongarch64-Add-the-tcg-target.h-file.patch - "${FILESDIR}"/loongarch/v6-0004-tcg-loongarch64-Add-generated-instruction-opcodes.patch - "${FILESDIR}"/loongarch/v6-0005-tcg-loongarch64-Add-register-names-allocation-ord.patch - "${FILESDIR}"/loongarch/v6-0006-tcg-loongarch64-Define-the-operand-constraints.patch - "${FILESDIR}"/loongarch/v6-0007-tcg-loongarch64-Implement-necessary-relocation-op.patch - "${FILESDIR}"/loongarch/v6-0008-tcg-loongarch64-Implement-the-memory-barrier-op.patch - "${FILESDIR}"/loongarch/v6-0009-tcg-loongarch64-Implement-tcg_out_mov-and-tcg_out.patch - "${FILESDIR}"/loongarch/v6-0010-tcg-loongarch64-Implement-goto_ptr.patch - "${FILESDIR}"/loongarch/v6-0011-tcg-loongarch64-Implement-sign-zero-extension-ops.patch - "${FILESDIR}"/loongarch/v6-0012-tcg-loongarch64-Implement-not-and-or-xor-nor-andc.patch - "${FILESDIR}"/loongarch/v6-0013-tcg-loongarch64-Implement-deposit-extract-ops.patch - "${FILESDIR}"/loongarch/v6-0014-tcg-loongarch64-Implement-bswap-16-32-64-ops.patch - "${FILESDIR}"/loongarch/v6-0015-tcg-loongarch64-Implement-clz-ctz-ops.patch - "${FILESDIR}"/loongarch/v6-0016-tcg-loongarch64-Implement-shl-shr-sar-rotl-rotr-o.patch - "${FILESDIR}"/loongarch/v6-0017-tcg-loongarch64-Implement-add-sub-ops.patch - "${FILESDIR}"/loongarch/v6-0018-tcg-loongarch64-Implement-mul-mulsh-muluh-div-div.patch - "${FILESDIR}"/loongarch/v6-0019-tcg-loongarch64-Implement-br-brcond-ops.patch - "${FILESDIR}"/loongarch/v6-0020-tcg-loongarch64-Implement-setcond-ops.patch - "${FILESDIR}"/loongarch/v6-0021-tcg-loongarch64-Implement-tcg_out_call.patch - "${FILESDIR}"/loongarch/v6-0022-tcg-loongarch64-Implement-simple-load-store-ops.patch - "${FILESDIR}"/loongarch/v6-0023-tcg-loongarch64-Add-softmmu-load-store-helpers-im.patch - "${FILESDIR}"/loongarch/v6-0024-tcg-loongarch64-Implement-tcg_target_qemu_prologu.patch - "${FILESDIR}"/loongarch/v6-0025-tcg-loongarch64-Implement-exit_tb-goto_tb.patch - "${FILESDIR}"/loongarch/v6-0026-tcg-loongarch64-Implement-tcg_target_init.patch - "${FILESDIR}"/loongarch/v6-0027-tcg-loongarch64-Register-the-JIT.patch - "${FILESDIR}"/loongarch/v6-0028-linux-user-Add-safe-syscall-handling-for-loongarc.patch - "${FILESDIR}"/loongarch/v6-0029-accel-tcg-user-exec-Implement-CPU-specific-signal.patch - "${FILESDIR}"/loongarch/v6-0030-configure-meson.build-Mark-support-for-loongarch6.patch ) QA_PREBUILT="