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af9033.c
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af9033.c
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/*
* Afatech AF9033 demodulator driver
*
* Copyright (C) 2008 Afatech
* Copyright (C) 2009 Antti Palosaari <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
* Thanks to TerraTec for a support received.
*/
#include "dvb_frontend.h"
#include <linux/slab.h> /* for kzalloc/kfree */
#include <linux/version.h>
#include "af9033_priv.h"
#include "af9033.h"
#include "af9033_reg.h"
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) || ((defined V4L2_VERSION) && (V4L2_VERSION >= 197120))
/* all DVB frontend drivers now work directly with the DVBv5
* structure. This warrants that all drivers will be
* getting/setting frontend parameters on a consistent way, in
* order to avoid copying data from/to the DVBv3 structs
* without need.
*/
#define V4L2_ONLY_DVB_V5
#endif
static int af9033_debug;
module_param_named(debug, af9033_debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
static int af9033_snrdb;
module_param_named(snrdb, af9033_snrdb, int, 0644);
MODULE_PARM_DESC(snrdb, "Turn on/off SNR output as dBx10 (default:off).");
struct af9033_state {
struct i2c_adapter *i2c;
struct dvb_frontend frontend;
struct af9033_config config;
u16 signal_strength;
u32 ber;
u32 ucblocks;
u16 snr;
u32 frequency;
unsigned long next_statistics_check;
};
static u8 regmask[8] = {0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff};
/* write multiple registers */
static int af9033_write_regs(struct af9033_state *state, u8 mbox, u16 reg,
u8 *val, u8 len)
{
u8 buf[3+len];
struct i2c_msg msg = {
.addr = state->config.demod_address,
.flags = 0,
.len = sizeof(buf),
.buf = buf };
buf[0] = mbox;
buf[1] = reg >> 8;
buf[2] = reg & 0xff;
memcpy(&buf[3], val, len);
if (i2c_transfer(state->i2c, &msg, 1) != 1) {
warn("I2C write failed reg:%04x len:%d", reg, len);
return -EREMOTEIO;
}
return 0;
}
/* read multiple registers */
static int af9033_read_regs(struct af9033_state *state, u8 mbox, u16 reg,
u8 *val, u8 len)
{
u8 obuf[3] = {mbox, reg >> 8, reg & 0xff};
struct i2c_msg msg[2] = {
{
.addr = state->config.demod_address,
.flags = 0,
.len = sizeof(obuf),
.buf = obuf
}, {
.addr = state->config.demod_address,
.flags = I2C_M_RD,
.len = len,
.buf = val
}
};
if (i2c_transfer(state->i2c, msg, 2) != 2) {
warn("I2C read failed reg:%04x", reg);
return -EREMOTEIO;
}
return 0;
}
/* write single register */
static int af9033_write_reg(struct af9033_state *state, u8 mbox, u16 reg,
u8 val)
{
return af9033_write_regs(state, mbox, reg, &val, 1);
}
/* read single register */
static int af9033_read_reg(struct af9033_state *state, u8 mbox, u16 reg,
u8 *val)
{
return af9033_read_regs(state, mbox, reg, val, 1);
}
/* write single register bits */
static int af9033_write_reg_bits(struct af9033_state *state, u8 mbox, u16 reg,
u8 pos, u8 len, u8 val)
{
int ret;
u8 tmp, mask;
ret = af9033_read_reg(state, mbox, reg, &tmp);
if (ret)
return ret;
mask = regmask[len - 1] << pos;
tmp = (tmp & ~mask) | ((val << pos) & mask);
return af9033_write_reg(state, mbox, reg, tmp);
}
/* read single register bits */
static int af9033_read_reg_bits(struct af9033_state *state, u8 mbox, u16 reg,
u8 pos, u8 len, u8 *val)
{
int ret;
u8 tmp;
ret = af9033_read_reg(state, mbox, reg, &tmp);
if (ret)
return ret;
*val = (tmp >> pos) & regmask[len - 1];
return 0;
}
static u32 af913_div(u32 a, u32 b, u32 x)
{
u32 r = 0, c = 0, i;
deb_info("%s: a:%d b:%d x:%d\n", __func__, a, b, x);
if (a > b) {
c = a / b;
a = a - c * b;
}
for (i = 0; i < x; i++) {
if (a >= b) {
r += 1;
a -= b;
}
a <<= 1;
r <<= 1;
}
r = (c << (u32)x) + r;
deb_info("%s: a:%d b:%d x:%d r:%d r:%x\n", __func__, a, b, x, r, r);
return r;
}
#ifdef V4L2_ONLY_DVB_V5
static int af9033_set_coeff(struct af9033_state *state, u32 bw)
#else
static int af9033_set_coeff(struct af9033_state *state, fe_bandwidth_t bw)
#endif
{
int ret = 0;
u8 tmp, i = 0;
u8 buf[36];
u32 uninitialized_var(coeff1_2048nu);
u32 uninitialized_var(coeff1_4096nu);
u32 uninitialized_var(coeff1_8191nu);
u32 uninitialized_var(coeff1_8192nu);
u32 uninitialized_var(coeff1_8193nu);
u32 uninitialized_var(coeff2_2k);
u32 uninitialized_var(coeff2_4k);
u32 uninitialized_var(coeff2_8k);
u16 uninitialized_var(bfsfcw_fftindex_ratio);
u16 uninitialized_var(fftindex_bfsfcw_ratio);
deb_info("%s: adc_clock:%d bw:%d\n", __func__,
state->config.adc_clock, bw);
#ifdef V4L2_ONLY_DVB_V5
#define BANDWIDTH_5_MHZ 5000000
#define BANDWIDTH_6_MHZ 6000000
#define BANDWIDTH_7_MHZ 7000000
#define BANDWIDTH_8_MHZ 8000000
#endif
switch (state->config.adc_clock) {
case 20156250:
switch (bw) {
#if 0 /* keep */
case BANDWIDTH_5_MHZ:
coeff1_2048nu = 0x02449b5c;
coeff1_4096nu = 0x01224dae;
coeff1_8191nu = 0x00912b60;
coeff1_8192nu = 0x009126d7;
coeff1_8193nu = 0x0091224e;
coeff2_2k = 0x01224dae;
coeff2_4k = 0x009126d7;
coeff2_8k = 0x0048936b;
bfsfcw_fftindex_ratio = 0x0387;
fftindex_bfsfcw_ratio = 0x0122;
break;
#endif
case BANDWIDTH_6_MHZ:
coeff1_2048nu = 0x02b8ba6e;
coeff1_4096nu = 0x015c5d37;
coeff1_8191nu = 0x00ae340d;
coeff1_8192nu = 0x00ae2e9b;
coeff1_8193nu = 0x00ae292a;
coeff2_2k = 0x015c5d37;
coeff2_4k = 0x00ae2e9b;
coeff2_8k = 0x0057174e;
bfsfcw_fftindex_ratio = 0x02f1;
fftindex_bfsfcw_ratio = 0x015c;
break;
case BANDWIDTH_7_MHZ:
coeff1_2048nu = 0x032cd980;
coeff1_4096nu = 0x01966cc0;
coeff1_8191nu = 0x00cb3cba;
coeff1_8192nu = 0x00cb3660;
coeff1_8193nu = 0x00cb3007;
coeff2_2k = 0x01966cc0;
coeff2_4k = 0x00cb3660;
coeff2_8k = 0x00659b30;
bfsfcw_fftindex_ratio = 0x0285;
fftindex_bfsfcw_ratio = 0x0196;
break;
case BANDWIDTH_8_MHZ:
coeff1_2048nu = 0x03a0f893;
coeff1_4096nu = 0x01d07c49;
coeff1_8191nu = 0x00e84567;
coeff1_8192nu = 0x00e83e25;
coeff1_8193nu = 0x00e836e3;
coeff2_2k = 0x01d07c49;
coeff2_4k = 0x00e83e25;
coeff2_8k = 0x00741f12;
bfsfcw_fftindex_ratio = 0x0234;
fftindex_bfsfcw_ratio = 0x01d0;
break;
default:
ret = -EINVAL;
}
break;
case 20187500:
switch (bw) {
#if 0 /* keep */
case BANDWIDTH_5_MHZ:
coeff1_2048nu = 0x0243b546;
coeff1_4096nu = 0x0121daa3;
coeff1_8191nu = 0x0090f1d9;
coeff1_8192nu = 0x0090ed51;
coeff1_8193nu = 0x0090e8ca;
coeff2_2k = 0x0121daa3;
coeff2_4k = 0x0090ed51;
coeff2_8k = 0x004876a9;
bfsfcw_fftindex_ratio = 0x0388;
fftindex_bfsfcw_ratio = 0x0122;
break;
#endif
case BANDWIDTH_6_MHZ:
coeff1_2048nu = 0x02b7a654;
coeff1_4096nu = 0x015bd32a;
coeff1_8191nu = 0x00adef04;
coeff1_8192nu = 0x00ade995;
coeff1_8193nu = 0x00ade426;
coeff2_2k = 0x015bd32a;
coeff2_4k = 0x00ade995;
coeff2_8k = 0x0056f4ca;
bfsfcw_fftindex_ratio = 0x02f2;
fftindex_bfsfcw_ratio = 0x015c;
break;
case BANDWIDTH_7_MHZ:
coeff1_2048nu = 0x032b9761;
coeff1_4096nu = 0x0195cbb1;
coeff1_8191nu = 0x00caec30;
coeff1_8192nu = 0x00cae5d8;
coeff1_8193nu = 0x00cadf81;
coeff2_2k = 0x0195cbb1;
coeff2_4k = 0x00cae5d8;
coeff2_8k = 0x006572ec;
bfsfcw_fftindex_ratio = 0x0286;
fftindex_bfsfcw_ratio = 0x0196;
break;
case BANDWIDTH_8_MHZ:
coeff1_2048nu = 0x039f886f;
coeff1_4096nu = 0x01cfc438;
coeff1_8191nu = 0x00e7e95b;
coeff1_8192nu = 0x00e7e21c;
coeff1_8193nu = 0x00e7dadd;
coeff2_2k = 0x01cfc438;
coeff2_4k = 0x00e7e21c;
coeff2_8k = 0x0073f10e;
bfsfcw_fftindex_ratio = 0x0235;
fftindex_bfsfcw_ratio = 0x01d0;
break;
default:
ret = -EINVAL;
}
break;
case 20250000:
switch (bw) {
#if 0 /* keep */
case BANDWIDTH_5_MHZ:
coeff1_2048nu = 0x0241eb3b;
coeff1_4096nu = 0x0120f59e;
coeff1_8191nu = 0x00907f53;
coeff1_8192nu = 0x00907acf;
coeff1_8193nu = 0x0090764b;
coeff2_2k = 0x0120f59e;
coeff2_4k = 0x00907acf;
coeff2_8k = 0x00483d67;
bfsfcw_fftindex_ratio = 0x038b;
fftindex_bfsfcw_ratio = 0x0121;
break;
#endif
case BANDWIDTH_6_MHZ:
coeff1_2048nu = 0x02b580ad;
coeff1_4096nu = 0x015ac057;
coeff1_8191nu = 0x00ad6597;
coeff1_8192nu = 0x00ad602b;
coeff1_8193nu = 0x00ad5ac1;
coeff2_2k = 0x015ac057;
coeff2_4k = 0x00ad602b;
coeff2_8k = 0x0056b016;
bfsfcw_fftindex_ratio = 0x02f4;
fftindex_bfsfcw_ratio = 0x015b;
break;
case BANDWIDTH_7_MHZ:
coeff1_2048nu = 0x03291620;
coeff1_4096nu = 0x01948b10;
coeff1_8191nu = 0x00ca4bda;
coeff1_8192nu = 0x00ca4588;
coeff1_8193nu = 0x00ca3f36;
coeff2_2k = 0x01948b10;
coeff2_4k = 0x00ca4588;
coeff2_8k = 0x006522c4;
bfsfcw_fftindex_ratio = 0x0288;
fftindex_bfsfcw_ratio = 0x0195;
break;
case BANDWIDTH_8_MHZ:
coeff1_2048nu = 0x039cab92;
coeff1_4096nu = 0x01ce55c9;
coeff1_8191nu = 0x00e7321e;
coeff1_8192nu = 0x00e72ae4;
coeff1_8193nu = 0x00e723ab;
coeff2_2k = 0x01ce55c9;
coeff2_4k = 0x00e72ae4;
coeff2_8k = 0x00739572;
bfsfcw_fftindex_ratio = 0x0237;
fftindex_bfsfcw_ratio = 0x01ce;
break;
default:
ret = -EINVAL;
}
break;
case 20583333:
switch (bw) {
#if 0 /* keep */
case BANDWIDTH_5_MHZ:
coeff1_2048nu = 0x02388f54;
coeff1_4096nu = 0x011c47aa;
coeff1_8191nu = 0x008e2846;
coeff1_8192nu = 0x008e23d5;
coeff1_8193nu = 0x008e1f64;
coeff2_2k = 0x011c47aa;
coeff2_4k = 0x008e23d5;
coeff2_8k = 0x004711ea;
bfsfcw_fftindex_ratio = 0x039a;
fftindex_bfsfcw_ratio = 0x011c;
break;
#endif
case BANDWIDTH_6_MHZ:
coeff1_2048nu = 0x02aa4598;
coeff1_4096nu = 0x015522cc;
coeff1_8191nu = 0x00aa96bb;
coeff1_8192nu = 0x00aa9166;
coeff1_8193nu = 0x00aa8c12;
coeff2_2k = 0x015522cc;
coeff2_4k = 0x00aa9166;
coeff2_8k = 0x005548b3;
bfsfcw_fftindex_ratio = 0x0300;
fftindex_bfsfcw_ratio = 0x0155;
break;
case BANDWIDTH_7_MHZ:
coeff1_2048nu = 0x031bfbdc;
coeff1_4096nu = 0x018dfdee;
coeff1_8191nu = 0x00c7052f;
coeff1_8192nu = 0x00c6fef7;
coeff1_8193nu = 0x00c6f8bf;
coeff2_2k = 0x018dfdee;
coeff2_4k = 0x00c6fef7;
coeff2_8k = 0x00637f7b;
bfsfcw_fftindex_ratio = 0x0293;
fftindex_bfsfcw_ratio = 0x018e;
break;
case BANDWIDTH_8_MHZ:
coeff1_2048nu = 0x038db21f;
coeff1_4096nu = 0x01c6d910;
coeff1_8191nu = 0x00e373a3;
coeff1_8192nu = 0x00e36c88;
coeff1_8193nu = 0x00e3656d;
coeff2_2k = 0x01c6d910;
coeff2_4k = 0x00e36c88;
coeff2_8k = 0x0071b644;
bfsfcw_fftindex_ratio = 0x0240;
fftindex_bfsfcw_ratio = 0x01c7;
break;
default:
ret = -EINVAL;
}
break;
case 20416667:
switch (bw) {
#if 0 /* keep */
case BANDWIDTH_5_MHZ:
coeff1_2048nu = 0x023d337f;
coeff1_4096nu = 0x011e99c0;
coeff1_8191nu = 0x008f515a;
coeff1_8192nu = 0x008f4ce0;
coeff1_8193nu = 0x008f4865;
coeff2_2k = 0x011e99c0;
coeff2_4k = 0x008f4ce0;
coeff2_8k = 0x0047a670;
bfsfcw_fftindex_ratio = 0x0393;
fftindex_bfsfcw_ratio = 0x011f;
break;
#endif
case BANDWIDTH_6_MHZ:
coeff1_2048nu = 0x02afd765;
coeff1_4096nu = 0x0157ebb3;
coeff1_8191nu = 0x00abfb39;
coeff1_8192nu = 0x00abf5d9;
coeff1_8193nu = 0x00abf07a;
coeff2_2k = 0x0157ebb3;
coeff2_4k = 0x00abf5d9;
coeff2_8k = 0x0055faed;
bfsfcw_fftindex_ratio = 0x02fa;
fftindex_bfsfcw_ratio = 0x0158;
break;
case BANDWIDTH_7_MHZ:
coeff1_2048nu = 0x03227b4b;
coeff1_4096nu = 0x01913da6;
coeff1_8191nu = 0x00c8a518;
coeff1_8192nu = 0x00c89ed3;
coeff1_8193nu = 0x00c8988e;
coeff2_2k = 0x01913da6;
coeff2_4k = 0x00c89ed3;
coeff2_8k = 0x00644f69;
bfsfcw_fftindex_ratio = 0x028d;
fftindex_bfsfcw_ratio = 0x0191;
break;
case BANDWIDTH_8_MHZ:
coeff1_2048nu = 0x03951f32;
coeff1_4096nu = 0x01ca8f99;
coeff1_8191nu = 0x00e54ef7;
coeff1_8192nu = 0x00e547cc;
coeff1_8193nu = 0x00e540a2;
coeff2_2k = 0x01ca8f99;
coeff2_4k = 0x00e547cc;
coeff2_8k = 0x0072a3e6;
bfsfcw_fftindex_ratio = 0x023c;
fftindex_bfsfcw_ratio = 0x01cb;
break;
default:
ret = -EINVAL;
}
break;
case 20480000:
switch (bw) {
#if 0 /* keep */
case BANDWIDTH_5_MHZ:
coeff1_2048nu = 0x023b6db7;
coeff1_4096nu = 0x011db6db;
coeff1_8191nu = 0x008edfe5;
coeff1_8192nu = 0x008edb6e;
coeff1_8193nu = 0x008ed6f7;
coeff2_2k = 0x011db6db;
coeff2_4k = 0x008edb6e;
coeff2_8k = 0x00476db7;
bfsfcw_fftindex_ratio = 0x0396;
fftindex_bfsfcw_ratio = 0x011e;
break;
#endif
case BANDWIDTH_6_MHZ:
coeff1_2048nu = 0x02adb6db;
coeff1_4096nu = 0x0156db6e;
coeff1_8191nu = 0x00ab7312;
coeff1_8192nu = 0x00ab6db7;
coeff1_8193nu = 0x00ab685c;
coeff2_2k = 0x0156db6e;
coeff2_4k = 0x00ab6db7;
coeff2_8k = 0x0055b6db;
bfsfcw_fftindex_ratio = 0x02fd;
fftindex_bfsfcw_ratio = 0x0157;
break;
case BANDWIDTH_7_MHZ:
coeff1_2048nu = 0x03200000;
coeff1_4096nu = 0x01900000;
coeff1_8191nu = 0x00c80640;
coeff1_8192nu = 0x00c80000;
coeff1_8193nu = 0x00c7f9c0;
coeff2_2k = 0x01900000;
coeff2_4k = 0x00c80000;
coeff2_8k = 0x00640000;
bfsfcw_fftindex_ratio = 0x028f;
fftindex_bfsfcw_ratio = 0x0190;
break;
case BANDWIDTH_8_MHZ:
coeff1_2048nu = 0x03924925;
coeff1_4096nu = 0x01c92492;
coeff1_8191nu = 0x00e4996e;
coeff1_8192nu = 0x00e49249;
coeff1_8193nu = 0x00e48b25;
coeff2_2k = 0x01c92492;
coeff2_4k = 0x00e49249;
coeff2_8k = 0x00724925;
bfsfcw_fftindex_ratio = 0x023d;
fftindex_bfsfcw_ratio = 0x01c9;
break;
default:
ret = -EINVAL;
}
break;
case 20500000:
switch (bw) {
#if 0 /* keep */
case BANDWIDTH_5_MHZ:
coeff1_2048nu = 0x023adeff;
coeff1_4096nu = 0x011d6f80;
coeff1_8191nu = 0x008ebc36;
coeff1_8192nu = 0x008eb7c0;
coeff1_8193nu = 0x008eb34a;
coeff2_2k = 0x011d6f80;
coeff2_4k = 0x008eb7c0;
coeff2_8k = 0x00475be0;
bfsfcw_fftindex_ratio = 0x0396;
fftindex_bfsfcw_ratio = 0x011d;
break;
#endif
case BANDWIDTH_6_MHZ:
coeff1_2048nu = 0x02ad0b99;
coeff1_4096nu = 0x015685cc;
coeff1_8191nu = 0x00ab4840;
coeff1_8192nu = 0x00ab42e6;
coeff1_8193nu = 0x00ab3d8c;
coeff2_2k = 0x015685cc;
coeff2_4k = 0x00ab42e6;
coeff2_8k = 0x0055a173;
bfsfcw_fftindex_ratio = 0x02fd;
fftindex_bfsfcw_ratio = 0x0157;
break;
case BANDWIDTH_7_MHZ:
coeff1_2048nu = 0x031f3832;
coeff1_4096nu = 0x018f9c19;
coeff1_8191nu = 0x00c7d44b;
coeff1_8192nu = 0x00c7ce0c;
coeff1_8193nu = 0x00c7c7ce;
coeff2_2k = 0x018f9c19;
coeff2_4k = 0x00c7ce0c;
coeff2_8k = 0x0063e706;
bfsfcw_fftindex_ratio = 0x0290;
fftindex_bfsfcw_ratio = 0x0190;
break;
case BANDWIDTH_8_MHZ:
coeff1_2048nu = 0x039164cb;
coeff1_4096nu = 0x01c8b266;
coeff1_8191nu = 0x00e46056;
coeff1_8192nu = 0x00e45933;
coeff1_8193nu = 0x00e45210;
coeff2_2k = 0x01c8b266;
coeff2_4k = 0x00e45933;
coeff2_8k = 0x00722c99;
bfsfcw_fftindex_ratio = 0x023e;
fftindex_bfsfcw_ratio = 0x01c9;
break;
default:
ret = -EINVAL;
}
break;
case 20625000:
switch (bw) {
#if 0 /* keep */
case BANDWIDTH_5_MHZ:
coeff1_2048nu = 0x02376948;
coeff1_4096nu = 0x011bb4a4;
coeff1_8191nu = 0x008ddec1;
coeff1_8192nu = 0x008dda52;
coeff1_8193nu = 0x008dd5e3;
coeff2_2k = 0x011bb4a4;
coeff2_4k = 0x008dda52;
coeff2_8k = 0x0046ed29;
bfsfcw_fftindex_ratio = 0x039c;
fftindex_bfsfcw_ratio = 0x011c;
break;
#endif
case BANDWIDTH_6_MHZ:
coeff1_2048nu = 0x02a8e4bd;
coeff1_4096nu = 0x0154725e;
coeff1_8191nu = 0x00aa3e81;
coeff1_8192nu = 0x00aa392f;
coeff1_8193nu = 0x00aa33de;
coeff2_2k = 0x0154725e;
coeff2_4k = 0x00aa392f;
coeff2_8k = 0x00551c98;
bfsfcw_fftindex_ratio = 0x0302;
fftindex_bfsfcw_ratio = 0x0154;
break;
case BANDWIDTH_7_MHZ:
coeff1_2048nu = 0x031a6032;
coeff1_4096nu = 0x018d3019;
coeff1_8191nu = 0x00c69e41;
coeff1_8192nu = 0x00c6980c;
coeff1_8193nu = 0x00c691d8;
coeff2_2k = 0x018d3019;
coeff2_4k = 0x00c6980c;
coeff2_8k = 0x00634c06;
bfsfcw_fftindex_ratio = 0x0294;
fftindex_bfsfcw_ratio = 0x018d;
break;
case BANDWIDTH_8_MHZ:
coeff1_2048nu = 0x038bdba6;
coeff1_4096nu = 0x01c5edd3;
coeff1_8191nu = 0x00e2fe02;
coeff1_8192nu = 0x00e2f6ea;
coeff1_8193nu = 0x00e2efd2;
coeff2_2k = 0x01c5edd3;
coeff2_4k = 0x00e2f6ea;
coeff2_8k = 0x00717b75;
bfsfcw_fftindex_ratio = 0x0242;
fftindex_bfsfcw_ratio = 0x01c6;
break;
default:
ret = -EINVAL;
}
break;
default:
err("invalid xtal freq");
return -EINVAL;
}
if (ret) {
err("invalid bandwidth");
return ret;
}
#ifdef V4L2_ONLY_DVB_V5
#undef BANDWIDTH_5_MHZ
#undef BANDWIDTH_6_MHZ
#undef BANDWIDTH_7_MHZ
#undef BANDWIDTH_8_MHZ
#endif
/* adc multiplier */
ret = af9033_read_reg(state, OFDM, api_adcx2, &tmp);
if (ret)
return ret;
if (tmp == 1) {
coeff1_2048nu /= 2;
coeff1_4096nu /= 2;
coeff1_8191nu /= 2;
coeff1_8192nu /= 2;
coeff1_8193nu /= 2 ;
coeff2_2k /= 2;
coeff2_4k /= 2;
coeff2_8k /= 2;
}
buf[i++] = (u8) ((coeff1_2048nu & 0x03000000) >> 24);
buf[i++] = (u8) ((coeff1_2048nu & 0x00ff0000) >> 16);
buf[i++] = (u8) ((coeff1_2048nu & 0x0000ff00) >> 8);
buf[i++] = (u8) ((coeff1_2048nu & 0x000000ff));
buf[i++] = (u8) ((coeff1_4096nu & 0x03000000) >> 24);
buf[i++] = (u8) ((coeff1_4096nu & 0x00ff0000) >> 16);
buf[i++] = (u8) ((coeff1_4096nu & 0x0000ff00) >> 8);
buf[i++] = (u8) ((coeff1_4096nu & 0x000000ff));
buf[i++] = (u8) ((coeff1_8191nu & 0x03000000) >> 24);
buf[i++] = (u8) ((coeff1_8191nu & 0x00ff0000) >> 16);
buf[i++] = (u8) ((coeff1_8191nu & 0x0000ff00) >> 8);
buf[i++] = (u8) ((coeff1_8191nu & 0x000000ff));
buf[i++] = (u8) ((coeff1_8192nu & 0x03000000) >> 24);
buf[i++] = (u8) ((coeff1_8192nu & 0x00ff0000) >> 16);
buf[i++] = (u8) ((coeff1_8192nu & 0x0000ff00) >> 8);
buf[i++] = (u8) ((coeff1_8192nu & 0x000000ff));
buf[i++] = (u8) ((coeff1_8193nu & 0x03000000) >> 24);
buf[i++] = (u8) ((coeff1_8193nu & 0x00ff0000) >> 16);
buf[i++] = (u8) ((coeff1_8193nu & 0x0000ff00) >> 8);
buf[i++] = (u8) ((coeff1_8193nu & 0x000000ff));
buf[i++] = (u8) ((coeff2_8k & 0x01000000) >> 24);
buf[i++] = (u8) ((coeff2_8k & 0x00ff0000) >> 16);
buf[i++] = (u8) ((coeff2_8k & 0x0000ff00) >> 8);
buf[i++] = (u8) ((coeff2_8k & 0x000000ff));
buf[i++] = (u8) ((coeff2_2k & 0x01000000) >> 24);
buf[i++] = (u8) ((coeff2_2k & 0x00ff0000) >> 16);
buf[i++] = (u8) ((coeff2_2k & 0x0000ff00) >> 8);
buf[i++] = (u8) ((coeff2_2k & 0x000000ff));
buf[i++] = (u8) ((coeff2_4k & 0x01000000) >> 24);
buf[i++] = (u8) ((coeff2_4k & 0x00ff0000) >> 16);
buf[i++] = (u8) ((coeff2_4k & 0x0000ff00) >> 8);
buf[i++] = (u8) ((coeff2_4k & 0x000000ff));
buf[i++] = (u8) ((bfsfcw_fftindex_ratio & 0x00ff));
buf[i++] = (u8) ((bfsfcw_fftindex_ratio & 0xff00) >> 8);
buf[i++] = (u8) ((fftindex_bfsfcw_ratio & 0x00ff));
buf[i++] = (u8) ((fftindex_bfsfcw_ratio & 0xff00) >> 8);
deb_info("%s: coeff:", __func__);
debug_dump(buf, sizeof(buf), deb_info);
/* program */
return af9033_write_regs(state, OFDM, api_cfoe_NS_2048_coeff1_25_24,
buf, sizeof(buf));
}
static int af9033_set_crystal_ctrl(struct af9033_state *state)
{
u8 buf[4];
u32 crystal_cw;
deb_info("%s: crystal_clock:%d\n", __func__,
state->config.crystal_clock);
crystal_cw = af913_div(state->config.crystal_clock, 1000000ul, 19ul);
buf[0] = (u8) ((crystal_cw & 0x000000ff));
buf[1] = (u8) ((crystal_cw & 0x0000ff00) >> 8);
buf[2] = (u8) ((crystal_cw & 0x00ff0000) >> 16);
buf[3] = (u8) ((crystal_cw & 0xff000000) >> 24);
deb_info("%s: crystal_cw:", __func__);
debug_dump(buf, sizeof(buf), deb_info);
/* program */
return af9033_write_regs(state, OFDM, api_crystal_clk_7_0, buf,
sizeof(buf));
}
static int af9033_set_adc_ctrl(struct af9033_state *state)
{
u8 buf[3];
u32 adc_cw;
deb_info("%s: adc_clock:%d\n", __func__, state->config.adc_clock);
adc_cw = af913_div(state->config.adc_clock, 1000000ul, 19ul);
buf[0] = (u8) ((adc_cw & 0x000000ff));
buf[1] = (u8) ((adc_cw & 0x0000ff00) >> 8);
buf[2] = (u8) ((adc_cw & 0x00ff0000) >> 16);
deb_info("%s: adc_cw:", __func__);
debug_dump(buf, sizeof(buf), deb_info);
/* program */
return af9033_write_regs(state, OFDM, p_reg_f_adc_7_0, buf,
sizeof(buf));
}
static int af9033_set_freq_ctrl(struct af9033_state *state)
{
int ret;
u8 buf[3], tmp;
u32 adc_freq, freq_cw;
s8 bfs_spec_inv;
int if_sample_freq;
bfs_spec_inv = state->config.rf_spec_inv ? -1 : 1;
adc_freq = state->config.adc_clock;
if_sample_freq = state->config.if_freq;
while (if_sample_freq > (adc_freq / 2))
if_sample_freq = if_sample_freq - adc_freq;
if (if_sample_freq >= 0)
bfs_spec_inv = bfs_spec_inv * (-1);
else
if_sample_freq = if_sample_freq * (-1);
freq_cw = af913_div(if_sample_freq, adc_freq, 23ul);
if (bfs_spec_inv == -1)
freq_cw *= -1;
/* adc multiplier */
ret = af9033_read_reg(state, OFDM, api_adcx2, &tmp);
if (ret)
return ret;
if (tmp == 1)
freq_cw /= 2;
buf[0] = (u8) ((freq_cw & 0x000000ff));
buf[1] = (u8) ((freq_cw & 0x0000ff00) >> 8);
buf[2] = (u8) ((freq_cw & 0x007f0000) >> 16);
deb_info("%s: freq_cw:", __func__);
debug_dump(buf, sizeof(buf), deb_info);
/* program */
return af9033_write_regs(state, OFDM, api_bfs_fcw_7_0, buf,
sizeof(buf));
}
static void af9033_release(struct dvb_frontend *fe)
{
struct af9033_state *state = fe->demodulator_priv;
kfree(state);
}
static int af9033_init(struct dvb_frontend *fe)
{
struct af9033_state *state = fe->demodulator_priv;
int ret, i, len;
u8 tmp0, tmp1;
struct regdesc *init;
deb_info("%s\n", __func__);
/* power on */
ret = af9033_write_reg_bits(state, OFDM, p_reg_afe_mem0, 3, 1, 0);
if (ret)
goto error;
ret = af9033_write_reg(state, OFDM, api_suspend_flag, 0);
if (ret)
goto error;
/* tell to the firmware type of the tuner */
ret = af9033_write_reg(state, LINK, p_reg_link_ofsm_dummy_15_8,
state->config.tuner);
if (ret)
goto error;
/* set read-update bit for constellation */
ret = af9033_write_reg_bits(state, OFDM, p_reg_feq_read_update,
reg_feq_read_update_pos, reg_feq_read_update_len, 1);
if (ret)
goto error;
/* enable FEC monitor */
ret = af9033_write_reg_bits(state, OFDM, p_fec_vtb_rsd_mon_en,
fec_vtb_rsd_mon_en_pos, fec_vtb_rsd_mon_en_len, 1);
if (ret)
goto error;
/* program crystal control */
ret = af9033_set_crystal_ctrl(state);
if (ret)
goto error;
/* program ADC control */
ret = af9033_set_adc_ctrl(state);
if (ret)
goto error;
/* enable DVB-T interrupt */
ret = af9033_write_reg_bits(state, LINK, p_reg_dvbt_inten,
reg_dvbt_inten_pos, reg_dvbt_inten_len, 1);
if (ret)
goto error;
/* enable DVB-T mode */
ret = af9033_write_reg_bits(state, LINK, p_reg_dvbt_en,
reg_dvbt_en_pos, reg_dvbt_en_len, 1);
if (ret)
goto error;
/* set dca_upper_chip */
ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_upper_chip,
reg_dca_upper_chip_pos, reg_dca_upper_chip_len, 0);
if (ret)
goto error;
ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_dca_upper,
reg_top_hostb_dca_upper_pos, reg_top_hostb_dca_upper_len, 0);
if (ret)
goto error;
ret = af9033_write_reg_bits(state, LINK, p_reg_top_hosta_dca_upper,
reg_top_hosta_dca_upper_pos, reg_top_hosta_dca_upper_len, 0);
if (ret)
goto error;
/* set dca_lower_chip */
ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_lower_chip,
reg_dca_lower_chip_pos, reg_dca_lower_chip_len, 0);
if (ret)
goto error;
ret = af9033_write_reg_bits(state, LINK, p_reg_top_hostb_dca_lower,
reg_top_hostb_dca_lower_pos, reg_top_hostb_dca_lower_len, 0);
if (ret)
goto error;
ret = af9033_write_reg_bits(state, LINK, p_reg_top_hosta_dca_lower,
reg_top_hosta_dca_lower_pos, reg_top_hosta_dca_lower_len, 0);
if (ret)
goto error;
/* set phase latch */
ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_platch,
reg_dca_platch_pos, reg_dca_platch_len, 0);
if (ret)
goto error;
/* set fpga latch */
ret = af9033_write_reg(state, OFDM, p_reg_dca_fpga_latch, 0);
if (ret)
goto error;
/* set stand alone */
ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_stand_alone,
reg_dca_stand_alone_pos, reg_dca_stand_alone_len, 1);
if (ret)
goto error;
/* set DCA enable */
ret = af9033_write_reg_bits(state, OFDM, p_reg_dca_en, reg_dca_en_pos,
reg_dca_en_len, 0);
if (ret)
goto error;
/* load OFSM settings */
deb_info("%s: load ofsm settings\n", __func__);
len = ARRAY_SIZE(ofsm_init);
init = ofsm_init;
for (i = 0; i < len; i++) {
ret = af9033_write_reg(state, OFDM, init[i].addr, init[i].val);
if (ret)
goto error;
}
/* load tuner specific settings */
deb_info("%s: load tuner specific settings\n", __func__);
switch (state->config.tuner) {
case AF9033_TUNER_TUA9001:
len = ARRAY_SIZE(tuner_init_tua9001);
init = tuner_init_tua9001;
break;
case AF9033_TUNER_MXL5007t:
len = ARRAY_SIZE(tuner_init_mxl5007t);
init = tuner_init_mxl5007t;
break;
case AF9033_TUNER_TDA18218:
len = ARRAY_SIZE(tuner_init_tda18218);
init = tuner_init_tda18218;
break;
default:
len = 0;
init = NULL;
break;
}
for (i = 0; i < len; i++) {
ret = af9033_write_reg(state, OFDM, init[i].addr, init[i].val);
if (ret)
goto error;
}
/* set H/W MPEG2 locked detection **/
ret = af9033_write_reg(state, LINK, p_reg_top_lock3_out, 1);
if (ret)
goto error;
/* set registers for driving power */
ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr2, 1);
if (ret)
goto error;
/* et registers for driving power */
ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr4, 0);
if (ret)
goto error;
/* set registers for driving power */
ret = af9033_write_reg(state, LINK, p_reg_top_padmiscdr8, 0);
if (ret)
goto error;
/* set TS mode */
deb_info("%s: setting ts mode\n", __func__);