From c3ba8f57adae385e04251189c43e173be93562d2 Mon Sep 17 00:00:00 2001 From: psndna88 Date: Sun, 4 Aug 2024 17:35:43 +0530 Subject: [PATCH] AGNi HyperOS v6.7 stable [5.4.281] --- AGNi_version.sh | 6 +- .../display/lahaina-sde-display_90hz.dtsi | 318 ------------------ arch/arm64/configs/agni_haydn_defconfig | 33 +- build_kernel_haydn_90hz.sh | 6 +- 4 files changed, 29 insertions(+), 334 deletions(-) delete mode 100644 arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display_90hz.dtsi diff --git a/AGNi_version.sh b/AGNi_version.sh index 528695f74a74..fb7d3695c972 100755 --- a/AGNi_version.sh +++ b/AGNi_version.sh @@ -4,9 +4,9 @@ KERNELDIR=`readlink -f .` export AGNI_VERSION_PREFIX="stable" -export AGNI_VERSION="v6.6" -sed -i 's/5.4.278/5.4.279/' $KERNELDIR/arch/arm64/configs/agni_* -sed -i 's/v6.5-stable/v6.6-stable/' $KERNELDIR/arch/arm64/configs/agni_* +export AGNI_VERSION="v6.7" +sed -i 's/5.4.279/5.4.281/' $KERNELDIR/arch/arm64/configs/agni_* +sed -i 's/v6.6-stable/v6.7-stable/' $KERNELDIR/arch/arm64/configs/agni_* echo " AGNi Version info loaded." diff --git a/arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display_90hz.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display_90hz.dtsi deleted file mode 100644 index 49c89143270a..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display_90hz.dtsi +++ /dev/null @@ -1,318 +0,0 @@ -#include "lahaina-sde-display-common.dtsi" -#include - -/* -&tlmm { - display_panel_avdd_default: display_panel_avdd_default { - mux { - pins = "gpio12"; - function = "gpio"; - }; - - config { - pins = "gpio12"; - drive-strength = <8>; - bias-disable = <0>; - output-high; - }; - }; -};*/ - -&soc { - display_panel_avdd: display_gpio_regulator@1 { - compatible = "qti-regulator-fixed"; - regulator-name = "display_panel_avdd"; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 12 0>; - enable-active-high; - regulator-boot-on; - proxy-supply = <&display_panel_avdd>; - qcom,proxy-consumer-enable; - pinctrl-names = "default"; - //pinctrl-0 = <&display_panel_avdd_default>; - }; - - sde_wb: qcom,wb-display@0 { - compatible = "qcom,wb-display"; - cell-index = <0>; - label = "wb_display"; - }; -}; - -&sde_dsi { - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_PCLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 SHADOW_CPHY_PCLK_SRC_1_CLK>, - /* - * Currently the dsi clock handles are under the dsi - * controller DT node. As soon as the controller probe - * finishes, the dispcc sync state can get called before - * the dsi_display probe potentially disturbing the clock - * votes for cont_splash use case. Hence we are no longer - * protected by the component model in this case against the - * disp cc sync state getting triggered after the dsi_ctrl - * probe. To protect against this incorrect sync state trigger - * add this dummy MDP clk vote handle to the dsi_display - * DT node. Since the dsi_display driver does not parse - * MDP clock nodes, no actual vote shall be added and this - * change is done just to satisfy sync state requirements. - */ - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0", - "shadow_cphybyte_clk0", "shadow_cphypixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1", - "src_byte_clk1", "src_pixel_clk1", - "shadow_byte_clk1", "shadow_pixel_clk1", - "shadow_cphybyte_clk1", "shadow_cphypixel_clk1", - "mdp_core_clk"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; - - qcom,platform-te-gpio = <&tlmm 82 0>; - qcom,panel-te-source = <0>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - avdd-supply = <&display_panel_avdd>; - lab-supply = <&ab_vreg>; - ibb-supply = <&ibb_vreg>; -}; - -&sde_dsi1 { - clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>, - <&mdss_dsi_phy0 PCLK_MUX_0_CLK>, - <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>, - <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>, - <&mdss_dsi_phy1 BYTECLK_MUX_1_CLK>, - <&mdss_dsi_phy1 PCLK_MUX_1_CLK>, - <&mdss_dsi_phy1 CPHY_BYTECLK_SRC_1_CLK>, - <&mdss_dsi_phy1 CPHY_PCLK_SRC_1_CLK>, - /* - * Currently the dsi clock handles are under the dsi - * controller DT node. As soon as the controller probe - * finishes, the dispcc sync state can get called before - * the dsi_display probe potentially disturbing the clock - * votes for cont_splash use case. Hence we are no longer - * protected by the component model in this case against the - * disp cc sync state getting triggered after the dsi_ctrl - * probe. To protect against this incorrect sync state trigger - * add this dummy MDP clk vote handle to the dsi_display - * DT node. Since the dsi_display driver does not parse - * MDP clock nodes, no actual vote shall be added and this - * change is done just to satisfy sync state requirements. - */ - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "cphy_byte_clk0", "cphy_pixel_clk0", - "mux_byte_clk1", "mux_pixel_clk1", - "cphy_byte_clk1", "cphy_pixel_clk1", - "mdp_core_clk"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; - pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; - - qcom,platform-te-gpio = <&tlmm 83 0>; - qcom,panel-te-source = <1>; - - vddio-supply = <&L12C>; - vdd-supply = <&L13C>; - avdd-supply = <&display_panel_avdd>; -}; - -&mdss_mdp { - connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_dp &sde_wb &sde_dsi - &sde_dsi1 &sde_rscc>; -}; - -&dsi_sw43404_amoled_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 180 180 180 1440 180>; - }; - }; -}; - -&dsi_r66451_amoled_cmd { - qcom,ulps-enabled; -}; - -&dsi_r66451_amoled_144hz_cmd { - qcom,ulps-enabled; -}; - -&dsi_sharp_4k_dsc_cmd { - qcom,ulps-enabled; -}; - -&dsi_sharp_1080_cmd { - qcom,ulps-enabled; -}; - -&dsi_sharp_qsync_wqhd_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { /* WQHD 60FPS CMD */ - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 8 8 8 1440 8>; - }; - timing@2 { /* FHD 60FPS CMD */ - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 8 8 8 1080 8>; - }; - timing@3 { /* WQHD 90FPS CMD */ - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 8 8 8 1440 8>; - }; - timing@4 { /* WQHD 120FPS CMD */ - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 8 8 8 1440 8>; - }; - timing@6 { /* FHD 120FPS CMD */ - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 8 8 8 1080 8>; - }; - timing@7 { /* FHD 90FPS CMD */ - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 8 8 8 1080 8>; - }; - }; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,ulps-enabled; -}; - -&dsi_nt35695b_truly_fhd_cmd { - qcom,ulps-enabled; -}; - -&dsi_sim_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { /* WQHD 60FPS cmd mode*/ - qcom,panel-roi-alignment = <720 40 720 40 720 40>; - qcom,partial-update-enabled = "single_roi"; - }; - timing@2 { /* WQHD 60FPS cmd mode*/ - qcom,panel-roi-alignment = <720 40 720 40 720 40>; - qcom,partial-update-enabled = "single_roi"; - }; - timing@3 { /* FHD 60FPS cmd mode*/ - qcom,panel-roi-alignment = <540 40 540 40 540 40>; - qcom,partial-update-enabled = "single_roi"; - }; - timing@4 { /* HD 60FPS cmd mode*/ - qcom,panel-roi-alignment = <360 40 360 40 360 40>; - qcom,partial-update-enabled = "single_roi"; - }; - }; -}; - -&dsi_sim_dsc_375_cmd { - qcom,ulps-enabled; -}; - -&dsi_sim_dsc_10b_cmd { - qcom,ulps-enabled; -}; - -&dsi_dual_sim_cmd { - qcom,ulps-enabled; -}; - -&dsi_dual_sim_dsc_375_cmd { - qcom,ulps-enabled; -}; - -&dsi_k11_38_08_0a_dsc_cmd { - //qcom,ulps-enabled; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,mdss-dsi-clk-strength = <0x65>; - qcom,mdss-dsi-display-timings { - /* 60 Hz */ - timing@0{ - qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 1A 19 09 - 0A 09 02 04 00 1E 0F]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - /* 90 Hz */ - timing@1{ - qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 1A 19 09 - 0A 09 02 04 00 1E 0F]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - /* 120 Hz */ - timing@2{ - qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 1A 19 09 - 0A 09 02 04 00 1E 0F]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - /delete-node/ timing@2; - }; -}; - -&dsi_sim_sec_hd_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,panel-roi-alignment = <720 40 720 40 720 40>; - qcom,partial-update-enabled = "single_roi"; - }; - }; -}; - -&dsi_prim_sim_vid { - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2E 33 16 - 17 14 02 04 43 1B 00]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sec_sim_vid { - qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0E 1B 01 - 01 02 02 04 00 08 06]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; diff --git a/arch/arm64/configs/agni_haydn_defconfig b/arch/arm64/configs/agni_haydn_defconfig index 37a0e611f11e..28b6d0cd6efe 100644 --- a/arch/arm64/configs/agni_haydn_defconfig +++ b/arch/arm64/configs/agni_haydn_defconfig @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.4.279 Kernel Configuration +# Linux/arm64 5.4.281 Kernel Configuration # CONFIG_CC_VERSION_TEXT="clang version 18.0.0" CONFIG_GCC_VERSION=0 @@ -21,7 +21,7 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set -CONFIG_LOCALVERSION="-AGNi_haydn_HyperOS_v6.6-stable-qgki" +CONFIG_LOCALVERSION="-AGNi_haydn_HyperOS_v6.7-stable-qgki" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" CONFIG_DEFAULT_HOSTNAME="haydn" @@ -416,10 +416,10 @@ CONFIG_PARAVIRT=y # CONFIG_QTI_QUIN_GVM is not set CONFIG_FORCE_MAX_ZONEORDER=11 # CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDEN_EL2_VECTORS=y -CONFIG_ARM64_SSBD=y -CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +# CONFIG_HARDEN_EL2_VECTORS is not set +# CONFIG_ARM64_SSBD is not set +# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set CONFIG_RODATA_FULL_DEFAULT_ENABLED=y CONFIG_ARM64_SW_TTBR0_PAN=y CONFIG_ARM64_TAGGED_ADDR_ABI=y @@ -642,7 +642,6 @@ CONFIG_VIRTUALIZATION=y CONFIG_KVM=y CONFIG_KVM_ARM_HOST=y CONFIG_KVM_ARM_PMU=y -CONFIG_KVM_INDIRECT_VECTORS=y CONFIG_VHOST_NET=y CONFIG_VHOST=y # CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set @@ -956,6 +955,7 @@ CONFIG_VMAP_LAZY_PURGING_FACTOR=32 CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_PAGE_IDLE_FLAG=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_FRAME_VECTOR=y @@ -971,6 +971,17 @@ CONFIG_LRU_GEN_ENABLED=y # CONFIG_LRU_GEN_STATS is not set CONFIG_PRIORITIZE_OOM_TASKS=y CONFIG_OOM_TASK_PRIORITY_ADJ_LIMIT=0 + +# +# Data Access Monitoring +# +CONFIG_DAMON=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_LRU_SORT=y +# end of Data Access Monitoring # end of Memory Management options # CONFIG_PROCESS_RECLAIM is not set @@ -2955,7 +2966,8 @@ CONFIG_POWER_RESET=y CONFIG_POWER_RESET_MSM=y # CONFIG_POWER_RESET_QCOM_VM is not set CONFIG_POWER_RESET_QCOM_DOWNLOAD_MODE=y -CONFIG_POWER_RESET_QCOM_DOWNLOAD_MODE_DEFAULT=y +# CONFIG_POWER_RESET_QCOM_DOWNLOAD_MODE_DEFAULT is not set +CONFIG_POWER_RESET_QCOM_DOWNLOAD_MODE_NODUMP=y # CONFIG_POWER_RESET_QCOM_PON is not set CONFIG_POWER_RESET_QCOM_REBOOT_REASON=y # CONFIG_POWER_RESET_LTC2952 is not set @@ -6338,7 +6350,9 @@ CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_ZIP=y -CONFIG_EROFS_FS_CLUSTER_PAGE_LIMIT=1 +# CONFIG_EROFS_FS_ZIP_LZMA is not set +CONFIG_EROFS_FS_PCPU_KTHREAD=y +CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI=y CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -6757,6 +6771,7 @@ CONFIG_XZ_DEC_IA64=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_DECOMPRESS_GZIP=y diff --git a/build_kernel_haydn_90hz.sh b/build_kernel_haydn_90hz.sh index b42da0b1e94d..a68a8c3e9f4c 100755 --- a/build_kernel_haydn_90hz.sh +++ b/build_kernel_haydn_90hz.sh @@ -58,8 +58,7 @@ mkdir ~/.cache/clang_thinlto-cache 2>/dev/null ln -s ~/.cache/clang_thinlto-cache $COMPILEDIR_HAYDN/.thinlto-cache 2>/dev/null # 90Hz dtsi replacement -mv arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display.dtsi arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display-ORIG.dtsi -mv arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display_90hz.dtsi arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display.dtsi +sed -i 's/\/delete-node\/ timing@1/\/delete-node\/ timing@2/' $KERNELDIR/arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display.dtsi make O=$COMPILEDIR_HAYDN $CONFIG1 make -j`nproc --ignore=2` O=$COMPILEDIR_HAYDN @@ -79,8 +78,7 @@ else fi # 90Hz dtsi UNDO -mv arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display.dtsi arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display_90hz.dtsi -mv arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display-ORIG.dtsi arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display.dtsi +sed -i 's/\/delete-node\/ timing@2/\/delete-node\/ timing@1/' $KERNELDIR/arch/arm64/boot/dts/vendor/qcom/display/lahaina-sde-display.dtsi echo ""