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lint: System Verilog sources
lint #54: Commit 5b06f43 pushed by fischeti
September 27, 2023 14:02 1m 9s no-rob-chimney
September 27, 2023 14:02 1m 9s
chimney: Fix atop bug
lint #53: Commit c63448c pushed by fischeti
September 27, 2023 13:54 1m 28s no-rob-chimney
September 27, 2023 13:54 1m 28s
nw_chimney: Don't use a reorder buffer
lint #52: Commit 681d00a pushed by fischeti
September 27, 2023 11:57 1m 5s no-rob-chimney
September 27, 2023 11:57 1m 5s
synth: Define technology specific SRAM configuration signals
lint #51: Commit 802b0e1 pushed by fischeti
September 27, 2023 08:34 1m 37s floogen
September 27, 2023 08:34 1m 37s
synth: Refactor synth wrappers
lint #50: Commit 2261738 pushed by fischeti
September 26, 2023 16:12 1m 7s floogen
September 26, 2023 16:12 1m 7s
synth: Refactor synth wrappers
lint #49: Commit 47b895f pushed by fischeti
September 26, 2023 16:02 1m 14s floogen
September 26, 2023 16:02 1m 14s
synth: Refactore nw_chimney wrapper
lint #48: Commit f1c556e pushed by fischeti
September 26, 2023 15:44 1m 21s floogen
September 26, 2023 15:44 1m 21s
synth: Refactore nw_chimney wrapper
lint #47: Commit e5ff104 pushed by fischeti
September 26, 2023 15:42 1m 15s floogen
September 26, 2023 15:42 1m 15s
nw_chimney: Fix refactoring
lint #46: Commit ca6645d pushed by fischeti
September 26, 2023 14:36 1m 4s floogen
September 26, 2023 14:36 1m 4s
test: Fix axi_xbar parameters
lint #45: Commit ac3a3a4 pushed by fischeti
September 15, 2023 08:54 1m 4s floogen
September 15, 2023 08:54 1m 4s
nw_router: Fix addr_rule parametrization
lint #44: Commit a5e6649 pushed by fischeti
September 14, 2023 14:57 1m 32s floogen
September 14, 2023 14:57 1m 32s
nw_router: Fix multiple drivers
lint #43: Commit 721d977 pushed by fischeti
September 14, 2023 09:44 1m 19s floogen
September 14, 2023 09:44 1m 19s
nw_chimney: Add ID table address map
lint #42: Commit 2ba781d pushed by fischeti
September 14, 2023 06:53 1m 26s floogen
September 14, 2023 06:53 1m 26s
nw_router: Change interface again
lint #41: Commit 914c54b pushed by fischeti
September 12, 2023 15:35 1m 5s floogen
September 12, 2023 15:35 1m 5s
test: Lower number of txns
lint #40: Commit 8aefd37 pushed by fischeti
September 12, 2023 13:33 1m 24s floogen
September 12, 2023 13:33 1m 24s
A couple of more fixes and refactoring
lint #39: Commit 88133e5 pushed by fischeti
September 12, 2023 11:51 1m 17s floogen
September 12, 2023 11:51 1m 17s
Makefile: Clean up
lint #38: Commit b437f60 pushed by fischeti
September 12, 2023 09:50 1m 0s floogen
September 12, 2023 09:50 1m 0s
Some more...
lint #37: Commit 2ba9afc pushed by fischeti
September 8, 2023 16:18 1m 27s floogen
September 8, 2023 16:18 1m 27s
Last round of refactoring, maybe?
lint #36: Commit 4b806bf pushed by fischeti
September 8, 2023 16:14 1m 11s floogen
September 8, 2023 16:14 1m 11s
Another round of refactoring
lint #35: Commit d6733ec pushed by fischeti
September 8, 2023 16:04 1m 23s floogen
September 8, 2023 16:04 1m 23s
Refactor narrow_wide_router
lint #34: Commit 9370673 pushed by fischeti
September 8, 2023 15:42 2m 3s floogen
September 8, 2023 15:42 2m 3s
lint SV sources
lint #33: Commit 9bef2f6 pushed by fischeti
September 8, 2023 15:28 1m 25s floogen
September 8, 2023 15:28 1m 25s
Update Bender.yml
lint #32: Commit 87cc17c pushed by fischeti
September 8, 2023 15:23 1m 10s floogen
September 8, 2023 15:23 1m 10s
Big refactoring
lint #31: Commit 71882d1 pushed by fischeti
September 8, 2023 15:21 1m 38s floogen
September 8, 2023 15:21 1m 38s
nw_router: Support variable number of input and output ports
lint #30: Commit 7580273 pushed by fischeti
August 18, 2023 15:15 1m 6s floogen
August 18, 2023 15:15 1m 6s