diff --git a/src/floo_narrow_wide_router.sv b/src/floo_narrow_wide_router.sv
index 68a824a6..033e7211 100644
--- a/src/floo_narrow_wide_router.sv
+++ b/src/floo_narrow_wide_router.sv
@@ -27,7 +27,7 @@ module floo_narrow_wide_router
   input  logic   rst_ni,
   input  logic   test_enable_i,
 
-  input  id_t xy_id_i,
+  input  id_t id_i,
   input  addr_rule_t [NumAddrRules-1:0] id_route_map_i,
 
   input   floo_req_t [NumInputs-1:0] floo_req_i,
@@ -95,7 +95,7 @@ module floo_narrow_wide_router
     .clk_i,
     .rst_ni,
     .test_enable_i,
-    .xy_id_i,
+    .xy_id_i(id_i),
     .id_route_map_i,
     .valid_i        ( req_valid_in  ),
     .ready_o        ( req_ready_out ),
@@ -124,7 +124,7 @@ module floo_narrow_wide_router
     .clk_i,
     .rst_ni,
     .test_enable_i,
-    .xy_id_i,
+    .xy_id_i(id_i),
     .id_route_map_i,
     .valid_i        ( rsp_valid_in  ),
     .ready_o        ( rsp_ready_out ),
@@ -152,7 +152,7 @@ module floo_narrow_wide_router
     .clk_i,
     .rst_ni,
     .test_enable_i,
-    .xy_id_i,
+    .xy_id_i(id_i),
     .id_route_map_i,
     .valid_i        ( wide_valid_in   ),
     .ready_o        ( wide_ready_out  ),
diff --git a/src/synth/floo_synth_axi_chimney.sv b/src/synth/floo_synth_axi_chimney.sv
index ba6097e8..0df21d85 100644
--- a/src/synth/floo_synth_axi_chimney.sv
+++ b/src/synth/floo_synth_axi_chimney.sv
@@ -15,7 +15,7 @@ module floo_synth_axi_chimney
   output axi_in_rsp_t  axi_in_rsp_o,
   output axi_out_req_t axi_out_req_o,
   input  axi_out_rsp_t axi_out_rsp_i,
-  input  xy_id_t    xy_id_i,
+  input  xy_id_t    id_i,
   output floo_req_t floo_req_o,
   output floo_rsp_t floo_rsp_o,
   input  floo_req_t floo_req_i,
@@ -29,7 +29,7 @@ module floo_synth_axi_chimney
     .XYAddrOffsetY      ( 32'd20              ),
     .MaxTxnsPerId       ( MaxTxnsPerId        ),
     .ReorderBufferSize  ( ReorderBufferSize   ),
-    .xy_id_t            ( xy_id_t             )
+    .id_t               ( xy_id_t             )
   ) i_floo_axi_chimney (
     .clk_i,
     .rst_ni,
@@ -39,8 +39,7 @@ module floo_synth_axi_chimney
     .axi_in_rsp_o,
     .axi_out_req_o,
     .axi_out_rsp_i,
-    .id_i('0),
-    .xy_id_i,
+    .id_i,
     .floo_req_o,
     .floo_rsp_o,
     .floo_req_i,
diff --git a/src/synth/floo_synth_endpoint.sv b/src/synth/floo_synth_endpoint.sv
index 05802a05..c6c52610 100644
--- a/src/synth/floo_synth_endpoint.sv
+++ b/src/synth/floo_synth_endpoint.sv
@@ -54,7 +54,7 @@ module floo_synth_endpoint
     .XYAddrOffsetY      ( 32'd20              ),
     .MaxTxnsPerId       ( MaxTxnsPerId        ),
     .ReorderBufferSize  ( ReorderBufferSize   ),
-    .xy_id_t            ( xy_id_t             ),
+    .id_t               ( xy_id_t             ),
     .CutAx              ( CutAx               ),
     .CutRsp             ( CutRsp              )
   ) i_floo_axi_chimney (
@@ -67,7 +67,6 @@ module floo_synth_endpoint
     .axi_out_req_o,
     .axi_out_rsp_i,
     .id_i('0),
-    .xy_id_i,
     .floo_req_o(chimney_req_out),
     .floo_rsp_o(chimney_rsp_out),
     .floo_req_i(chimney_req_in),
diff --git a/src/synth/floo_synth_narrow_wide_chimney.sv b/src/synth/floo_synth_narrow_wide_chimney.sv
index 90444c6f..edc9e0b2 100644
--- a/src/synth/floo_synth_narrow_wide_chimney.sv
+++ b/src/synth/floo_synth_narrow_wide_chimney.sv
@@ -19,7 +19,7 @@ module floo_synth_narrow_wide_chimney
   output axi_wide_in_rsp_t    axi_wide_in_rsp_o,
   output axi_wide_out_req_t     axi_wide_out_req_o,
   input  axi_wide_out_rsp_t    axi_wide_out_rsp_i,
-  input  xy_id_t        xy_id_i,
+  input  xy_id_t        id_i,
   output floo_req_t  floo_req_o,
   output floo_rsp_t  floo_rsp_o,
   input  floo_req_t  floo_req_i,
@@ -52,16 +52,15 @@ floo_narrow_wide_chimney #(
   .WideReorderBufferSize    ( WideReorderBufferSize   ),
   .CutAx                    ( CutAx                   ),
   .CutRsp                   ( CutRsp                  ),
-  .xy_id_t                  ( xy_id_t                 ),
+  .id_t                     ( xy_id_t                 ),
   .sram_cfg_t               ( sram_cfg_t              )
 ) i_floo_narrow_wide_chimney (
   .clk_i,
   .rst_ni,
   .test_enable_i(1'b0),
   .sram_cfg_i('0),
-  .id_i('0),
+  .id_i,
   .id_map_i ('0),
-  .xy_id_i,
   .axi_narrow_in_req_i,
   .axi_narrow_in_rsp_o,
   .axi_narrow_out_req_o,
diff --git a/src/synth/floo_synth_narrow_wide_router.sv b/src/synth/floo_synth_narrow_wide_router.sv
index 92dc0769..90472645 100644
--- a/src/synth/floo_synth_narrow_wide_router.sv
+++ b/src/synth/floo_synth_narrow_wide_router.sv
@@ -33,7 +33,7 @@ module floo_synth_narrow_wide_router
     .clk_i,
     .rst_ni,
     .test_enable_i,
-    .xy_id_i,
+    .id_i(xy_id_i),
     .id_route_map_i ('0),
     .floo_req_i,
     .floo_req_o,
diff --git a/test/floo_test_pkg.sv b/test/floo_test_pkg.sv
index bb3a7e1e..11138d16 100644
--- a/test/floo_test_pkg.sv
+++ b/test/floo_test_pkg.sv
@@ -41,6 +41,4 @@ package floo_test_pkg;
   localparam rob_type_e WideRoBType = NoRoB;
   localparam int unsigned WideReorderBufferSize = 32'd128;
 
-  `FLOO_NOC_TYPEDEF_XY_ID_T(xy_id_t, NumX, NumY)
-
 endpackage
diff --git a/test/tb_floo_dma_mesh.sv b/test/tb_floo_dma_mesh.sv
index 5f936dc3..a53c2b8d 100644
--- a/test/tb_floo_dma_mesh.sv
+++ b/test/tb_floo_dma_mesh.sv
@@ -386,7 +386,7 @@ module tb_floo_dma_mesh;
         .clk_i          ( clk         ),
         .rst_ni         ( rst_n       ),
         .test_enable_i  ( 1'b0        ),
-        .xy_id_i        ( current_id  ),
+        .id_i           ( current_id  ),
         .id_route_map_i ( '0          ),
         .floo_req_i     ( req_in      ),
         .floo_req_o     ( req_out     ),