From 758027314e3976a0f6d86d54e1e77bf4e9317496 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Fri, 18 Aug 2023 17:15:22 +0200 Subject: [PATCH] nw_router: Support variable number of input and output ports --- src/floo_narrow_wide_router.sv | 61 +++++++++++++++++++++------------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/src/floo_narrow_wide_router.sv b/src/floo_narrow_wide_router.sv index b0cacab9..6c6cc953 100644 --- a/src/floo_narrow_wide_router.sv +++ b/src/floo_narrow_wide_router.sv @@ -10,6 +10,8 @@ module floo_narrow_wide_router import floo_narrow_wide_flit_pkg::*; #( parameter int unsigned NumRoutes = NumDirections, + parameter int unsigned NumInputs = NumRoutes, + parameter int unsigned NumOutputs = NumRoutes, parameter int unsigned ChannelFifoDepth = 0, parameter int unsigned OutputFifoDepth = 0, parameter route_algo_e RouteAlgo = XYRouting, @@ -27,36 +29,41 @@ module floo_narrow_wide_router input id_t xy_id_i, input addr_rule_t [NumAddrRules-1:0] id_route_map_i, - input narrow_req_flit_t [NumRoutes-1:0] narrow_req_i, - input narrow_rsp_flit_t [NumRoutes-1:0] narrow_rsp_i, - output narrow_req_flit_t [NumRoutes-1:0] narrow_req_o, - output narrow_rsp_flit_t [NumRoutes-1:0] narrow_rsp_o, + input narrow_req_flit_t [NumInputs-1:0] narrow_req_i, + input narrow_rsp_flit_t [NumOutputs-1:0] narrow_rsp_i, + output narrow_req_flit_t [NumOutputs-1:0] narrow_req_o, + output narrow_rsp_flit_t [NumInputs-1:0] narrow_rsp_o, input wide_flit_t [NumRoutes-1:0] wide_i, output wide_flit_t [NumRoutes-1:0] wide_o ); - narrow_req_data_t [NumRoutes-1:0] narrow_req_in, narrow_req_out; - narrow_rsp_data_t [NumRoutes-1:0] narrow_rsp_in, narrow_rsp_out; - logic [NumRoutes-1:0] narrow_req_valid_in, narrow_req_valid_out; - logic [NumRoutes-1:0] narrow_rsp_valid_in, narrow_rsp_valid_out; - logic [NumRoutes-1:0] narrow_req_ready_in, narrow_rsp_ready_in; - logic [NumRoutes-1:0] narrow_req_ready_out, narrow_rsp_ready_out; - wide_data_t [NumRoutes-1:0] wide_in, wide_out; - logic [NumRoutes-1:0] wide_valid_in, wide_valid_out; - logic [NumRoutes-1:0] wide_ready_in, wide_ready_out; + narrow_req_data_t [NumInputs-1:0] narrow_req_in; + narrow_rsp_data_t [NumInputs-1:0] narrow_rsp_out; + narrow_req_data_t [NumOutputs-1:0] narrow_req_out; + narrow_rsp_data_t [NumOutputs-1:0] narrow_rsp_in; + logic [NumInputs-1:0] narrow_req_valid_in, narrow_req_ready_out; + logic [NumInputs-1:0] narrow_rsp_valid_out, narrow_rsp_ready_in; + logic [NumOutputs-1:0] narrow_req_valid_out, narrow_req_ready_in; + logic [NumOutputs-1:0] narrow_rsp_valid_in, narrow_rsp_ready_out; + wide_data_t [NumRoutes-1:0] wide_in, wide_out; + logic [NumRoutes-1:0] wide_valid_in, wide_valid_out; + logic [NumRoutes-1:0] wide_ready_in, wide_ready_out; - for (genvar i = 0; i < NumRoutes; i++) begin : gen_chimney_req - assign narrow_req_o[i].data = narrow_req_out[i]; + for (genvar i = 0; i < NumInputs; i++) begin : gen_chimney_req assign narrow_rsp_o[i].data = narrow_rsp_out[i]; assign narrow_req_in[i] = narrow_req_i[i].data; - assign narrow_rsp_in[i] = narrow_rsp_i[i].data; assign narrow_req_valid_in[i] = narrow_req_i[i].valid; - assign narrow_rsp_valid_in[i] = narrow_rsp_i[i].valid; - assign narrow_req_ready_in[i] = narrow_req_i[i].ready; assign narrow_rsp_ready_in[i] = narrow_rsp_i[i].ready; - assign narrow_req_o[i].valid = narrow_req_valid_out[i]; assign narrow_rsp_o[i].valid = narrow_rsp_valid_out[i]; assign narrow_req_o[i].ready = narrow_req_ready_out[i]; + end + + for (genvar i = 0; i < NumOutputs; i++) begin : gen_chimney_req + assign narrow_req_o[i].data = narrow_req_out[i]; + assign narrow_rsp_in[i] = narrow_rsp_i[i].data; + assign narrow_rsp_valid_in[i] = narrow_rsp_i[i].valid; + assign narrow_req_ready_in[i] = narrow_req_i[i].ready; + assign narrow_req_o[i].valid = narrow_req_valid_out[i]; assign narrow_rsp_o[i].ready = narrow_rsp_ready_out[i]; assign wide_o[i].data = wide_out[i]; assign wide_in[i] = wide_i[i].data; @@ -66,12 +73,20 @@ module floo_narrow_wide_router assign wide_o[i].ready = wide_ready_out[i]; end - + for (genvar i = 0; i < NumRoutes; i++) begin : gen_chimney_req + assign wide_o[i].data = wide_out[i]; + assign wide_in[i] = wide_i[i].data; + assign wide_valid_in[i] = wide_i[i].valid; + assign wide_ready_in[i] = wide_i[i].ready; + assign wide_o[i].valid = wide_valid_out[i]; + assign wide_o[i].ready = wide_ready_out[i]; + end floo_router #( .NumPhysChannels ( 1 ), .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), + .NumInputs ( NumInputs ), + .NumOutputs ( NumOutputs ), .flit_t ( narrow_req_generic_t ), .ChannelFifoDepth ( ChannelFifoDepth ), .OutputFifoDepth ( OutputFifoDepth ), @@ -97,8 +112,8 @@ module floo_narrow_wide_router floo_router #( .NumPhysChannels ( 1 ), .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), - .flit_t ( narrow_rsp_generic_t ), + .NumInputs ( NumInputs ), + .NumOutputs ( NumOutputs ), .ChannelFifoDepth ( ChannelFifoDepth ), .OutputFifoDepth ( OutputFifoDepth ), .RouteAlgo ( RouteAlgo ),