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Refactor narrow_wide_router
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@fischeti
fischeti committed Sep 8, 2023
1 parent 9bef2f6 commit 9370673
Showing 1 changed file with 82 additions and 87 deletions.
169 changes: 82 additions & 87 deletions src/floo_narrow_wide_router.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
/// Wrapper of a multi-link router for narrow and wide links
module floo_narrow_wide_router
import floo_pkg::*;
import floo_narrow_wide_flit_pkg::*;
import floo_narrow_wide_pkg::*;
#(
parameter int unsigned NumRoutes = NumDirections,
parameter int unsigned NumInputs = NumRoutes,
Expand All @@ -29,123 +29,118 @@ module floo_narrow_wide_router
input id_t xy_id_i,
input addr_rule_t [NumAddrRules-1:0] id_route_map_i,

input narrow_req_flit_t [NumInputs-1:0] narrow_req_i,
input narrow_rsp_flit_t [NumOutputs-1:0] narrow_rsp_i,
output narrow_req_flit_t [NumOutputs-1:0] narrow_req_o,
output narrow_rsp_flit_t [NumInputs-1:0] narrow_rsp_o,
input wide_flit_t [NumRoutes-1:0] wide_i,
output wide_flit_t [NumRoutes-1:0] wide_o
input floo_req_t [NumInputs-1:0] req_i,
input floo_rsp_t [NumOutputs-1:0] rsp_i,
output floo_req_t [NumOutputs-1:0] req_o,
output floo_rsp_t [NumInputs-1:0] rsp_o,
input floo_wide_t [NumRoutes-1:0] wide_i,
output floo_wide_t [NumRoutes-1:0] wide_o
);

narrow_req_data_t [NumInputs-1:0] narrow_req_in;
narrow_rsp_data_t [NumInputs-1:0] narrow_rsp_out;
narrow_req_data_t [NumOutputs-1:0] narrow_req_out;
narrow_rsp_data_t [NumOutputs-1:0] narrow_rsp_in;
logic [NumInputs-1:0] narrow_req_valid_in, narrow_req_ready_out;
logic [NumInputs-1:0] narrow_rsp_valid_out, narrow_rsp_ready_in;
logic [NumOutputs-1:0] narrow_req_valid_out, narrow_req_ready_in;
logic [NumOutputs-1:0] narrow_rsp_valid_in, narrow_rsp_ready_out;
wide_data_t [NumRoutes-1:0] wide_in, wide_out;
floo_req_t [NumInputs-1:0] req_in;
floo_rsp_t [NumInputs-1:0] rsp_in;
floo_wide_t [NumInputs-1:0] wide_in;
floo_req_t [NumOutputs-1:0] req_out;
floo_rsp_t [NumOutputs-1:0] rsp_out;
floo_wide_t [NumOutputs-1:0] wide_out;

logic [NumInputs-1:0] req_valid_in, req_ready_out;
logic [NumInputs-1:0] rsp_valid_out, rsp_ready_in;
logic [NumOutputs-1:0] req_valid_out, req_ready_in;
logic [NumOutputs-1:0] rsp_valid_in, rsp_ready_out;
logic [NumRoutes-1:0] wide_valid_in, wide_valid_out;
logic [NumRoutes-1:0] wide_ready_in, wide_ready_out;

for (genvar i = 0; i < NumInputs; i++) begin : gen_chimney_req
assign narrow_rsp_o[i].data = narrow_rsp_out[i];
assign narrow_req_in[i] = narrow_req_i[i].data;
assign narrow_req_valid_in[i] = narrow_req_i[i].valid;
assign narrow_rsp_ready_in[i] = narrow_rsp_i[i].ready;
assign narrow_rsp_o[i].valid = narrow_rsp_valid_out[i];
assign narrow_req_o[i].ready = narrow_req_ready_out[i];
assign req_valid_in[i] = req_i[i].generic.valid;
assign rsp_ready_in[i] = rsp_i[i].generic.ready;
assign rsp_o[i].generic.valid = rsp_valid_out[i];
assign req_o[i].generic.ready = req_ready_out[i];
end

for (genvar i = 0; i < NumOutputs; i++) begin : gen_chimney_req
assign narrow_req_o[i].data = narrow_req_out[i];
assign narrow_rsp_in[i] = narrow_rsp_i[i].data;
assign narrow_rsp_valid_in[i] = narrow_rsp_i[i].valid;
assign narrow_req_ready_in[i] = narrow_req_i[i].ready;
assign narrow_req_o[i].valid = narrow_req_valid_out[i];
assign narrow_rsp_o[i].ready = narrow_rsp_ready_out[i];
assign wide_o[i].data = wide_out[i];
assign wide_in[i] = wide_i[i].data;
assign wide_valid_in[i] = wide_i[i].valid;
assign wide_ready_in[i] = wide_i[i].ready;
assign wide_o[i].valid = wide_valid_out[i];
assign wide_o[i].ready = wide_ready_out[i];
for (genvar i = 0; i < NumOutputs; i++) begin : gen_chimney_rsp
assign rsp_valid_in[i] = rsp_i[i].generic.valid;
assign req_ready_in[i] = req_i[i].generic.ready;
assign req_o[i].generic.valid = req_valid_out[i];
assign rsp_o[i].generic.ready = rsp_ready_out[i];
assign wide_valid_in[i] = wide_i[i].generic.valid;
assign wide_ready_in[i] = wide_i[i].generic.ready;
assign wide_o[i].generic.valid = wide_valid_out[i];
assign wide_o[i].generic.ready = wide_ready_out[i];
end

for (genvar i = 0; i < NumRoutes; i++) begin : gen_chimney_req
assign wide_o[i].data = wide_out[i];
assign wide_in[i] = wide_i[i].data;
assign wide_valid_in[i] = wide_i[i].valid;
assign wide_ready_in[i] = wide_i[i].ready;
assign wide_o[i].valid = wide_valid_out[i];
assign wide_o[i].ready = wide_ready_out[i];
for (genvar i = 0; i < NumRoutes; i++) begin : gen_chimney_wide
assign wide_valid_in[i] = wide_i[i].generic.valid;
assign wide_ready_in[i] = wide_i[i].generic.ready;
assign wide_o[i].generic.valid = wide_valid_out[i];
assign wide_o[i].generic.ready = wide_ready_out[i];
end

floo_router #(
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumInputs ( NumInputs ),
.NumOutputs ( NumOutputs ),
.flit_t ( narrow_req_generic_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.IdWidth ( IdWidth ),
.id_t ( id_t ),
.NumAddrRules ( NumAddrRules )
) i_narrow_req_floo_router (
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumInput ( NumInputs ),
.NumOutput ( NumOutputs ),
.flit_t ( floo_req_generic_flit_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.IdWidth ( IdWidth ),
.id_t ( id_t ),
.NumAddrRules ( NumAddrRules )
) i_req_floo_router (
.clk_i,
.rst_ni,
.test_enable_i,
.xy_id_i,
.id_route_map_i,
.valid_i ( narrow_req_valid_in ),
.ready_o ( narrow_req_ready_out ),
.data_i ( narrow_req_in ),
.valid_o ( narrow_req_valid_out ),
.ready_i ( narrow_req_ready_in ),
.data_o ( narrow_req_out )
.valid_i ( req_valid_in ),
.ready_o ( req_ready_out ),
.data_i ( req_in ),
.valid_o ( req_valid_out ),
.ready_i ( req_ready_in ),
.data_o ( req_out )
);


floo_router #(
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumInputs ( NumInputs ),
.NumOutputs ( NumOutputs ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.IdWidth ( IdWidth ),
.id_t ( id_t ),
.NumAddrRules ( NumAddrRules )
) i_narrow_rsp_floo_router (
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumInput ( NumInputs ),
.NumOutput ( NumOutputs ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.IdWidth ( IdWidth ),
.flit_t ( floo_rsp_generic_flit_t ),
.id_t ( id_t ),
.NumAddrRules ( NumAddrRules )
) i_rsp_floo_router (
.clk_i,
.rst_ni,
.test_enable_i,
.xy_id_i,
.id_route_map_i,
.valid_i ( narrow_rsp_valid_in ),
.ready_o ( narrow_rsp_ready_out ),
.data_i ( narrow_rsp_in ),
.valid_o ( narrow_rsp_valid_out ),
.ready_i ( narrow_rsp_ready_in ),
.data_o ( narrow_rsp_out )
.valid_i ( rsp_valid_in ),
.ready_o ( rsp_ready_out ),
.data_i ( rsp_in ),
.valid_o ( rsp_valid_out ),
.ready_i ( rsp_ready_in ),
.data_o ( rsp_out )
);


floo_router #(
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumRoutes ( NumRoutes ),
.flit_t ( wide_generic_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.IdWidth ( IdWidth ),
.id_t ( id_t ),
.NumAddrRules ( NumAddrRules )
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumRoutes ( NumRoutes ),
.flit_t ( floo_wide_generic_flit_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.IdWidth ( IdWidth ),
.id_t ( id_t ),
.NumAddrRules ( NumAddrRules )
) i_wide_req_floo_router (
.clk_i,
.rst_ni,
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