ci: Don't format generated sources with verible

pulp-platform · Sep 18, 2024 · 996f715 · 996f715
1 parent e770636
commit 996f715
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -76,7 +76,7 @@ run-traffic:
     - $PYTHON -m venv .venv
     - source .venv/bin/activate
     - pip install .
-    - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated
+    - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format
     - make compile-sim BENDER_FLAGS="-t ${DUT}"
     - make jobs
     - make run-sim-batch VSIM_TB_DUT=${tb_floo_${DUT}} | tee vsim.log 2>&1