From 996f715831d9c347c019fa7d1345da7f94a6a9f9 Mon Sep 17 00:00:00 2001
From: Tim Fischer <fischeti@iis.ee.ethz.ch>
Date: Wed, 18 Sep 2024 10:51:57 +0200
Subject: [PATCH] ci: Don't format generated sources with verible

---
 .gitlab-ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index b574ff81..9f1037ce 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -76,7 +76,7 @@ run-traffic:
     - $PYTHON -m venv .venv
     - source .venv/bin/activate
     - pip install .
-    - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated
+    - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format
     - make compile-sim BENDER_FLAGS="-t ${DUT}"
     - make jobs
     - make run-sim-batch VSIM_TB_DUT=${tb_floo_${DUT}} | tee vsim.log 2>&1