lint: Line lengths

pulp-platform · Oct 31, 2023 · b4a54f6 · b4a54f6
1 parent c04d055
commit b4a54f6
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Showing 2 changed files with 34 additions and 17 deletions.
diff --git a/src/floo_axi_chimney.sv b/src/floo_axi_chimney.sv
@@ -531,8 +531,10 @@ module floo_axi_chimney
   assign axi_valid_in[AxiAw] = floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAw);
   assign axi_valid_in[AxiW]  = floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiW);
   assign axi_valid_in[AxiAr] = floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAr);
-  assign axi_valid_in[AxiB]  = EnSbrPort && floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiB);
-  assign axi_valid_in[AxiR]  = EnSbrPort && floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiR);
+  assign axi_valid_in[AxiB]  = EnSbrPort && floo_rsp_in_valid &&
+                               (unpack_rsp_generic.hdr.axi_ch == AxiB);
+  assign axi_valid_in[AxiR]  = EnSbrPort && floo_rsp_in_valid &&
+                               (unpack_rsp_generic.hdr.axi_ch == AxiR);
 
   assign axi_ready_out[AxiAw] = axi_meta_buf_rsp_out.aw_ready;
   assign axi_ready_out[AxiW]  = axi_meta_buf_rsp_out.w_ready;
@@ -645,11 +647,16 @@ module floo_axi_chimney
   `ASSERT_INIT(NoSbrPortRobType, EnSbrPort || (RoBType == NoRoB))
 
   // Network Interface cannot accept any B and R responses if `EnSbrPort` is not set
-  `ASSERT(NoSbrPortBResponse, EnSbrPort || !(floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiB)))
-  `ASSERT(NoSbrPortRResponse, EnSbrPort || !(floo_rsp_in_valid && (unpack_rsp_generic.hdr.axi_ch == AxiR)))
+  `ASSERT(NoSbrPortBResponse, EnSbrPort || !(floo_rsp_in_valid &&
+                                             (unpack_rsp_generic.hdr.axi_ch == AxiB)))
+  `ASSERT(NoSbrPortRResponse, EnSbrPort || !(floo_rsp_in_valid &&
+                                             (unpack_rsp_generic.hdr.axi_ch == AxiR)))
   // Network Interface cannot accept any AW, AR and W requests if `EnMgrPort` is not set
-  `ASSERT(NoMgrPortAwRequest, EnMgrPort || !(floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAw)))
-  `ASSERT(NoMgrPortArRequest, EnMgrPort || !(floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiAr)))
-  `ASSERT(NoMgrPortWRequest,  EnMgrPort || !(floo_req_in_valid && (unpack_req_generic.hdr.axi_ch == AxiW)))
+  `ASSERT(NoMgrPortAwRequest, EnMgrPort || !(floo_req_in_valid &&
+                                             (unpack_req_generic.hdr.axi_ch == AxiAw)))
+  `ASSERT(NoMgrPortArRequest, EnMgrPort || !(floo_req_in_valid &&
+                                             (unpack_req_generic.hdr.axi_ch == AxiAr)))
+  `ASSERT(NoMgrPortWRequest,  EnMgrPort || !(floo_req_in_valid &&
+                                             (unpack_req_generic.hdr.axi_ch == AxiW)))
 
 endmodule
diff --git a/src/floo_narrow_wide_chimney.sv b/src/floo_narrow_wide_chimney.sv
@@ -1175,16 +1175,26 @@ module floo_narrow_wide_chimney
                            !floo_wide_o.ready |=> floo_wide_i.valid)
 
   // Network Interface cannot accept any B and R responses if `En*SbrPort` are not set
-  `ASSERT(NoNarrowSbrPortBResponse, EnNarrowSbrPort || !(floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowB)))
-  `ASSERT(NoNarrowSbrPortRResponse, EnNarrowSbrPort || !(floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == NarrowR)))
-  `ASSERT(NoWideSbrPortBResponse, EnWideSbrPort || !(floo_rsp_in_valid && (floo_rsp_unpack_generic.hdr.axi_ch == WideB)))
-  `ASSERT(NoWideSbrPortRResponse, EnWideSbrPort || !(floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideR)))
+  `ASSERT(NoNarrowSbrPortBResponse, EnNarrowSbrPort || !(floo_rsp_in_valid &&
+                           (floo_rsp_unpack_generic.hdr.axi_ch == NarrowB)))
+  `ASSERT(NoNarrowSbrPortRResponse, EnNarrowSbrPort || !(floo_rsp_in_valid &&
+                           (floo_rsp_unpack_generic.hdr.axi_ch == NarrowR)))
+  `ASSERT(NoWideSbrPortBResponse, EnWideSbrPort || !(floo_rsp_in_valid &&
+                           (floo_rsp_unpack_generic.hdr.axi_ch == WideB)))
+  `ASSERT(NoWideSbrPortRResponse, EnWideSbrPort || !(floo_wide_in_valid &&
+                           (floo_wide_unpack_generic.hdr.axi_ch == WideR)))
   // Network Interface cannot accept any AW, AR and W requests if `En*MgrPort` is not set
-  `ASSERT(NoNarrowMgrPortAwRequest, EnNarrowMgrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == NarrowAw)))
-  `ASSERT(NoNarrowMgrPortArRequest, EnNarrowMgrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == NarrowAr)))
-  `ASSERT(NoNarrowMgrPortWRequest,  EnNarrowMgrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == NarrowW)))
-  `ASSERT(NoWideMgrPortAwRequest, EnWideMgrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == WideAw)))
-  `ASSERT(NoWideMgrPortArRequest, EnWideMgrPort || !(floo_req_in_valid && (floo_req_unpack_generic.hdr.axi_ch == WideAr)))
-  `ASSERT(NoWideMgrPortWRequest,  EnWideMgrPort || !(floo_wide_in_valid && (floo_wide_unpack_generic.hdr.axi_ch == WideW)))
+  `ASSERT(NoNarrowMgrPortAwRequest, EnNarrowMgrPort || !(floo_req_in_valid &&
+                           (floo_req_unpack_generic.hdr.axi_ch == NarrowAw)))
+  `ASSERT(NoNarrowMgrPortArRequest, EnNarrowMgrPort || !(floo_req_in_valid &&
+                           (floo_req_unpack_generic.hdr.axi_ch == NarrowAr)))
+  `ASSERT(NoNarrowMgrPortWRequest,  EnNarrowMgrPort || !(floo_req_in_valid &&
+                           (floo_req_unpack_generic.hdr.axi_ch == NarrowW)))
+  `ASSERT(NoWideMgrPortAwRequest, EnWideMgrPort || !(floo_req_in_valid &&
+                           (floo_req_unpack_generic.hdr.axi_ch == WideAw)))
+  `ASSERT(NoWideMgrPortArRequest, EnWideMgrPort || !(floo_req_in_valid &&
+                           (floo_req_unpack_generic.hdr.axi_ch == WideAr)))
+  `ASSERT(NoWideMgrPortWRequest,  EnWideMgrPort || !(floo_wide_in_valid &&
+                           (floo_wide_unpack_generic.hdr.axi_ch == WideW)))
 
 endmodule