diff --git a/test/tb_floo_dma_chimney.sv b/test/tb_floo_dma_chimney.sv index 94b6fbed..f81ed516 100644 --- a/test/tb_floo_dma_chimney.sv +++ b/test/tb_floo_dma_chimney.sv @@ -11,7 +11,7 @@ module tb_floo_dma_chimney; import floo_pkg::*; - import floo_axi_flit_pkg::*; + import floo_axi_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 0ns; @@ -26,21 +26,21 @@ module tb_floo_dma_chimney; logic clk, rst_n; axi_in_req_t [NumTargets-1:0] node_man_req; - axi_in_resp_t [NumTargets-1:0] node_man_rsp; + axi_in_rsp_t [NumTargets-1:0] node_man_rsp; axi_in_req_t [NumTargets-1:0] node_sub_req; - axi_in_resp_t [NumTargets-1:0] node_sub_rsp; + axi_in_rsp_t [NumTargets-1:0] node_sub_rsp; axi_in_req_t [NumTargets-1:0] sub_req_id_mapped; - axi_in_resp_t [NumTargets-1:0] sub_rsp_id_mapped; + axi_in_rsp_t [NumTargets-1:0] sub_rsp_id_mapped; for (genvar i = 0; i < NumTargets; i++) begin : gen_axi_assign `AXI_ASSIGN_REQ_STRUCT(sub_req_id_mapped[i], node_sub_req[i]) `AXI_ASSIGN_RESP_STRUCT(sub_rsp_id_mapped[i], node_sub_rsp[i]) end - req_flit_t [NumTargets-1:0] chimney_req; - rsp_flit_t [NumTargets-1:0] chimney_rsp; + floo_req_t [NumTargets-1:0] chimney_req; + floo_rsp_t [NumTargets-1:0] chimney_rsp; logic [NumTargets-1:0] end_of_sim; @@ -71,7 +71,7 @@ module tb_floo_dma_chimney; .MemBaseAddr ( MemBaseAddr ), .MemSize ( MemSize ), .axi_req_t ( axi_in_req_t ), - .axi_rsp_t ( axi_in_resp_t ), + .axi_rsp_t ( axi_in_rsp_t ), .JobId ( 0 ) ) i_floo_dma_test_node_0 ( .clk_i ( clk ), @@ -90,7 +90,7 @@ module tb_floo_dma_chimney; .ar_chan_t ( axi_in_ar_chan_t ), .r_chan_t ( axi_in_r_chan_t ), .req_t ( axi_in_req_t ), - .resp_t ( axi_in_resp_t ) + .resp_t ( axi_in_rsp_t ) ) i_axi_channel_compare_0 ( .clk_i ( clk ), .axi_a_req ( node_man_req[0] ), @@ -115,10 +115,10 @@ module tb_floo_dma_chimney; .axi_out_rsp_i ( node_sub_rsp[0] ), .xy_id_i ( '0 ), .id_i ( '0 ), - .req_o ( chimney_req[0] ), - .rsp_o ( chimney_rsp[0] ), - .req_i ( chimney_req[1] ), - .rsp_i ( chimney_rsp[1] ) + .floo_req_o ( chimney_req[0] ), + .floo_rsp_o ( chimney_rsp[0] ), + .floo_req_i ( chimney_req[1] ), + .floo_rsp_i ( chimney_rsp[1] ) ); floo_axi_chimney #( @@ -137,10 +137,10 @@ module tb_floo_dma_chimney; .axi_out_rsp_i ( node_sub_rsp[1] ), .xy_id_i ( '0 ), .id_i ( '0 ), - .req_o ( chimney_req[1] ), - .rsp_o ( chimney_rsp[1] ), - .req_i ( chimney_req[0] ), - .rsp_i ( chimney_rsp[0] ) + .floo_req_o ( chimney_req[1] ), + .floo_rsp_o ( chimney_rsp[1] ), + .floo_req_i ( chimney_req[0] ), + .floo_rsp_i ( chimney_rsp[0] ) ); axi_channel_compare #( @@ -150,7 +150,7 @@ module tb_floo_dma_chimney; .ar_chan_t ( axi_in_ar_chan_t ), .r_chan_t ( axi_in_r_chan_t ), .req_t ( axi_in_req_t ), - .resp_t ( axi_in_resp_t ) + .resp_t ( axi_in_rsp_t ) ) i_axi_channel_compare_1 ( .clk_i(clk), .axi_a_req ( node_man_req[1] ), @@ -170,7 +170,7 @@ module tb_floo_dma_chimney; .MemBaseAddr ( MemBaseAddr ), .MemSize ( MemSize ), .axi_req_t ( axi_in_req_t ), - .axi_rsp_t ( axi_in_resp_t ), + .axi_rsp_t ( axi_in_rsp_t ), .JobId ( 1 ) ) i_floo_dma_test_node_1 ( .clk_i ( clk ), @@ -184,7 +184,7 @@ module tb_floo_dma_chimney; axi_bw_monitor #( .req_t ( axi_in_req_t ), - .rsp_t ( axi_in_resp_t ), + .rsp_t ( axi_in_rsp_t ), .AxiIdWidth ( AxiInIdWidth ) ) i_axi_bw_monitor ( .clk_i ( clk ), diff --git a/test/tb_floo_dma_nw_chimney.sv b/test/tb_floo_dma_nw_chimney.sv index be16e9ec..6dc6d09f 100644 --- a/test/tb_floo_dma_nw_chimney.sv +++ b/test/tb_floo_dma_nw_chimney.sv @@ -11,7 +11,7 @@ module tb_floo_dma_nw_chimney; import floo_pkg::*; - import floo_narrow_wide_flit_pkg::*; + import floo_narrow_wide_pkg::*; localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; @@ -25,20 +25,20 @@ module tb_floo_dma_nw_chimney; logic clk, rst_n; - narrow_in_req_t [NumTargets-1:0] narrow_man_req; - narrow_in_resp_t [NumTargets-1:0] narrow_man_rsp; - wide_in_req_t [NumTargets-1:0] wide_man_req; - wide_in_resp_t [NumTargets-1:0] wide_man_rsp; + axi_narrow_in_req_t [NumTargets-1:0] narrow_man_req; + axi_narrow_in_rsp_t [NumTargets-1:0] narrow_man_rsp; + axi_wide_in_req_t [NumTargets-1:0] wide_man_req; + axi_wide_in_rsp_t [NumTargets-1:0] wide_man_rsp; - narrow_out_req_t [NumTargets-1:0] narrow_sub_req; - narrow_out_resp_t [NumTargets-1:0] narrow_sub_rsp; - wide_out_req_t [NumTargets-1:0] wide_sub_req; - wide_out_resp_t [NumTargets-1:0] wide_sub_rsp; + axi_narrow_out_req_t [NumTargets-1:0] narrow_sub_req; + axi_narrow_out_rsp_t [NumTargets-1:0] narrow_sub_rsp; + axi_wide_out_req_t [NumTargets-1:0] wide_sub_req; + axi_wide_out_rsp_t [NumTargets-1:0] wide_sub_rsp; - narrow_in_req_t [NumTargets-1:0] narrow_sub_req_id_mapped; - narrow_in_resp_t [NumTargets-1:0] narrow_sub_rsp_id_mapped; - wide_in_req_t [NumTargets-1:0] wide_sub_req_id_mapped; - wide_in_resp_t [NumTargets-1:0] wide_sub_rsp_id_mapped; + axi_narrow_in_req_t [NumTargets-1:0] narrow_sub_req_id_mapped; + axi_narrow_in_rsp_t [NumTargets-1:0] narrow_sub_rsp_id_mapped; + axi_wide_in_req_t [NumTargets-1:0] wide_sub_req_id_mapped; + axi_wide_in_rsp_t [NumTargets-1:0] wide_sub_rsp_id_mapped; for (genvar i = 0; i < NumDirections; i++) begin : gen_dir `AXI_ASSIGN_REQ_STRUCT(narrow_sub_req_id_mapped[i], narrow_sub_req[i]) @@ -47,9 +47,9 @@ module tb_floo_dma_nw_chimney; `AXI_ASSIGN_RESP_STRUCT(wide_sub_rsp_id_mapped[i], wide_sub_rsp[i]) end - narrow_req_flit_t [NumTargets-1:0] narrow_chimney_req, narrow_chimney_req_cut; - narrow_rsp_flit_t [NumTargets-1:0] narrow_chimney_rsp, narrow_chimney_rsp_cut; - wide_flit_t [NumTargets-1:0] wide_chimney, wide_chimney_cut; + floo_req_t [NumTargets-1:0] chimney_req, chimney_req_cut; + floo_rsp_t [NumTargets-1:0] chimney_rsp, chimney_rsp_cut; + floo_wide_t [NumTargets-1:0] chimney_wide, chimney_wide_cut; logic [NumTargets*2-1:0] end_of_sim; @@ -70,21 +70,21 @@ module tb_floo_dma_nw_chimney; localparam int unsigned MemSize = 32'h0001_0000; floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .DataWidth ( NarrowInDataWidth ), - .AddrWidth ( NarrowInAddrWidth ), - .UserWidth ( NarrowInUserWidth ), - .AxiIdInWidth ( NarrowOutIdWidth ), - .AxiIdOutWidth ( NarrowInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( narrow_out_req_t ), - .axi_in_rsp_t ( narrow_out_resp_t ), - .axi_out_req_t ( narrow_in_req_t ), - .axi_out_rsp_t ( narrow_in_resp_t ), - .JobId ( 100 ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .DataWidth ( NarrowInDataWidth ), + .AddrWidth ( NarrowInAddrWidth ), + .UserWidth ( NarrowInUserWidth ), + .AxiIdInWidth ( NarrowOutIdWidth ), + .AxiIdOutWidth ( NarrowInIdWidth ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .axi_in_req_t ( axi_narrow_out_req_t ), + .axi_in_rsp_t ( axi_narrow_out_rsp_t ), + .axi_out_req_t ( axi_narrow_in_req_t ), + .axi_out_rsp_t ( axi_narrow_in_rsp_t ), + .JobId ( 100 ) ) i_narrow_dma_node_0 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -96,21 +96,21 @@ module tb_floo_dma_nw_chimney; ); floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .DataWidth ( WideInDataWidth ), - .AddrWidth ( WideInAddrWidth ), - .UserWidth ( WideInUserWidth ), - .AxiIdInWidth ( WideOutIdWidth ), - .AxiIdOutWidth ( WideInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( wide_out_req_t ), - .axi_in_rsp_t ( wide_out_resp_t ), - .axi_out_req_t ( wide_in_req_t ), - .axi_out_rsp_t ( wide_in_resp_t ), - .JobId ( 0 ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .DataWidth ( WideInDataWidth ), + .AddrWidth ( WideInAddrWidth ), + .UserWidth ( WideInUserWidth ), + .AxiIdInWidth ( WideOutIdWidth ), + .AxiIdOutWidth ( WideInIdWidth ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .axi_in_req_t ( axi_wide_out_req_t ), + .axi_in_rsp_t ( axi_wide_out_rsp_t ), + .axi_out_req_t ( axi_wide_in_req_t ), + .axi_out_rsp_t ( axi_wide_in_rsp_t ), + .JobId ( 0 ) ) i_wide_dma_node_0 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -122,13 +122,13 @@ module tb_floo_dma_nw_chimney; ); axi_channel_compare #( - .aw_chan_t ( narrow_in_aw_chan_t ), - .w_chan_t ( narrow_in_w_chan_t ), - .b_chan_t ( narrow_in_b_chan_t ), - .ar_chan_t ( narrow_in_ar_chan_t ), - .r_chan_t ( narrow_in_r_chan_t ), - .req_t ( narrow_in_req_t ), - .resp_t ( narrow_in_resp_t ) + .aw_chan_t ( axi_narrow_in_aw_chan_t ), + .w_chan_t ( axi_narrow_in_w_chan_t ), + .b_chan_t ( axi_narrow_in_b_chan_t ), + .ar_chan_t ( axi_narrow_in_ar_chan_t ), + .r_chan_t ( axi_narrow_in_r_chan_t ), + .req_t ( axi_narrow_in_req_t ), + .resp_t ( axi_narrow_in_rsp_t ) ) i_narrow_channel_compare_0 ( .clk_i ( clk ), .axi_a_req ( narrow_man_req[0] ), @@ -138,13 +138,13 @@ module tb_floo_dma_nw_chimney; ); axi_channel_compare #( - .aw_chan_t ( wide_in_aw_chan_t ), - .w_chan_t ( wide_in_w_chan_t ), - .b_chan_t ( wide_in_b_chan_t ), - .ar_chan_t ( wide_in_ar_chan_t ), - .r_chan_t ( wide_in_r_chan_t ), - .req_t ( wide_in_req_t ), - .resp_t ( wide_in_resp_t ) + .aw_chan_t ( axi_wide_in_aw_chan_t ), + .w_chan_t ( axi_wide_in_w_chan_t ), + .b_chan_t ( axi_wide_in_b_chan_t ), + .ar_chan_t ( axi_wide_in_ar_chan_t ), + .r_chan_t ( axi_wide_in_r_chan_t ), + .req_t ( axi_wide_in_req_t ), + .resp_t ( axi_wide_in_rsp_t ) ) i_wide_channel_compare_0 ( .clk_i ( clk ), .axi_a_req ( wide_man_req[0] ), @@ -162,71 +162,71 @@ module tb_floo_dma_nw_chimney; .WideMaxTxnsPerId ( MaxTxnsPerId ), .WideReorderBufferSize ( ReorderBufferSize ) ) i_floo_narrow_wide_chimney_0 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .narrow_in_req_i ( narrow_man_req[0] ), - .narrow_in_rsp_o ( narrow_man_rsp[0] ), - .narrow_out_req_o ( narrow_sub_req[0] ), - .narrow_out_rsp_i ( narrow_sub_rsp[0] ), - .wide_in_req_i ( wide_man_req[0] ), - .wide_in_rsp_o ( wide_man_rsp[0] ), - .wide_out_req_o ( wide_sub_req[0] ), - .wide_out_rsp_i ( wide_sub_rsp[0] ), - .xy_id_i ( '0 ), - .id_i ( '0 ), - .narrow_req_o ( narrow_chimney_req[0] ), - .narrow_rsp_o ( narrow_chimney_rsp[0] ), - .wide_o ( wide_chimney[0] ), - .narrow_req_i ( narrow_chimney_req_cut[1] ), - .narrow_rsp_i ( narrow_chimney_rsp_cut[1] ), - .wide_i ( wide_chimney_cut[1] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_narrow_in_req_i ( narrow_man_req[0] ), + .axi_narrow_in_rsp_o ( narrow_man_rsp[0] ), + .axi_narrow_out_req_o ( narrow_sub_req[0] ), + .axi_narrow_out_rsp_i ( narrow_sub_rsp[0] ), + .axi_wide_in_req_i ( wide_man_req[0] ), + .axi_wide_in_rsp_o ( wide_man_rsp[0] ), + .axi_wide_out_req_o ( wide_sub_req[0] ), + .axi_wide_out_rsp_i ( wide_sub_rsp[0] ), + .xy_id_i ( '0 ), + .id_i ( '0 ), + .floo_req_o ( chimney_req[0] ), + .floo_rsp_o ( chimney_rsp[0] ), + .floo_wide_o ( chimney_wide[0] ), + .floo_req_i ( chimney_req_cut[1] ), + .floo_rsp_i ( chimney_rsp_cut[1] ), + .floo_wide_i ( chimney_wide_cut[1] ) ); floo_cut #( - .NumChannels ( 2 ), - .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers - .flit_t ( narrow_req_data_t ) + .NumChannels ( 2 ), + .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers + .flit_t ( floo_req_t ) ) i_floo_req_cut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .valid_i ( {narrow_chimney_req[1].valid, narrow_chimney_req[0].valid} ), - .ready_o ( {narrow_chimney_req_cut[1].ready, narrow_chimney_req_cut[0].ready} ), - .data_i ( {narrow_chimney_req[1].data, narrow_chimney_req[0].data} ), - .valid_o ( {narrow_chimney_req_cut[1].valid, narrow_chimney_req_cut[0].valid} ), - .ready_i ( {narrow_chimney_req[1].ready, narrow_chimney_req[0].ready} ), - .data_o ( {narrow_chimney_req_cut[1].data, narrow_chimney_req_cut[0].data} ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .valid_i ( {chimney_req[1].generic.valid, chimney_req[0].generic.valid} ), + .ready_o ( {chimney_req_cut[1].generic.ready, chimney_req_cut[0].generic.ready} ), + .data_i ( {chimney_req[1].generic, chimney_req[0]} ), + .valid_o ( {chimney_req_cut[1].generic.valid, chimney_req_cut[0].generic.valid} ), + .ready_i ( {chimney_req[1].generic.ready, chimney_req[0].generic.ready} ), + .data_o ( {chimney_req_cut[1].generic, chimney_req_cut[0]} ) ); floo_cut #( - .NumChannels ( 2 ), - .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers - .flit_t ( narrow_rsp_data_t ) + .NumChannels ( 2 ), + .NumCuts ( 32'd7 ), // should simulate a hop with 2 routers + .flit_t ( floo_rsp_t ) ) i_floo_rsp_cut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .valid_i ( {narrow_chimney_rsp[1].valid, narrow_chimney_rsp[0].valid} ), - .ready_o ( {narrow_chimney_rsp_cut[1].ready, narrow_chimney_rsp_cut[0].ready} ), - .data_i ( {narrow_chimney_rsp[1].data, narrow_chimney_rsp[0].data} ), - .valid_o ( {narrow_chimney_rsp_cut[1].valid, narrow_chimney_rsp_cut[0].valid} ), - .ready_i ( {narrow_chimney_rsp[1].ready, narrow_chimney_rsp[0].ready} ), - .data_o ( {narrow_chimney_rsp_cut[1].data, narrow_chimney_rsp_cut[0].data} ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .valid_i ( {chimney_rsp[1].generic.valid, chimney_rsp[0].generic.valid} ), + .ready_o ( {chimney_rsp_cut[1].generic.ready, chimney_rsp_cut[0].generic.ready} ), + .data_i ( {chimney_rsp[1], chimney_rsp[0]} ), + .valid_o ( {chimney_rsp_cut[1].generic.valid, chimney_rsp_cut[0].generic.valid} ), + .ready_i ( {chimney_rsp[1].generic.ready, chimney_rsp[0].generic.ready} ), + .data_o ( {chimney_rsp_cut[1], chimney_rsp_cut[0]} ) ); floo_cut #( .NumChannels ( 2 ), .NumCuts ( 32'd4 ), // should simulate a hop with 2 routers - .flit_t ( wide_data_t ) + .flit_t ( floo_wide_t ) ) i_floo_wide_cut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .valid_i ( {wide_chimney[1].valid, wide_chimney[0].valid} ), - .ready_o ( {wide_chimney_cut[1].ready, wide_chimney_cut[0].ready} ), - .data_i ( {wide_chimney[1].data, wide_chimney[0].data} ), - .valid_o ( {wide_chimney_cut[1].valid, wide_chimney_cut[0].valid} ), - .ready_i ( {wide_chimney[1].ready, wide_chimney[0].ready} ), - .data_o ( {wide_chimney_cut[1].data, wide_chimney_cut[0].data} ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .valid_i ( {chimney_wide[1].generic.valid, chimney_wide[0].generic.valid} ), + .ready_o ( {chimney_wide_cut[1].generic.ready, chimney_wide_cut[0].generic.ready} ), + .data_i ( {chimney_wide[1], chimney_wide[0]} ), + .valid_o ( {chimney_wide_cut[1].generic.valid, chimney_wide_cut[0].generic.valid} ), + .ready_i ( {chimney_wide[1].generic.ready, chimney_wide[0].generic.ready} ), + .data_o ( {chimney_wide_cut[1], chimney_wide_cut[0]} ) ); floo_narrow_wide_chimney #( @@ -238,76 +238,76 @@ module tb_floo_dma_nw_chimney; .WideMaxTxnsPerId ( MaxTxnsPerId ), .WideReorderBufferSize ( ReorderBufferSize ) ) i_floo_narrow_wide_chimney_1 ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .sram_cfg_i ( '0 ), - .test_enable_i ( 1'b0 ), - .narrow_in_req_i ( narrow_man_req[1] ), - .narrow_in_rsp_o ( narrow_man_rsp[1] ), - .narrow_out_req_o ( narrow_sub_req[1] ), - .narrow_out_rsp_i ( narrow_sub_rsp[1] ), - .wide_in_req_i ( wide_man_req[1] ), - .wide_in_rsp_o ( wide_man_rsp[1] ), - .wide_out_req_o ( wide_sub_req[1] ), - .wide_out_rsp_i ( wide_sub_rsp[1] ), - .xy_id_i ( '0 ), - .id_i ( '0 ), - .narrow_req_o ( narrow_chimney_req[1] ), - .narrow_rsp_o ( narrow_chimney_rsp[1] ), - .wide_o ( wide_chimney[1] ), - .narrow_req_i ( narrow_chimney_req_cut[0] ), - .narrow_rsp_i ( narrow_chimney_rsp_cut[0] ), - .wide_i ( wide_chimney_cut[0] ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_narrow_in_req_i ( narrow_man_req[1] ), + .axi_narrow_in_rsp_o ( narrow_man_rsp[1] ), + .axi_narrow_out_req_o ( narrow_sub_req[1] ), + .axi_narrow_out_rsp_i ( narrow_sub_rsp[1] ), + .axi_wide_in_req_i ( wide_man_req[1] ), + .axi_wide_in_rsp_o ( wide_man_rsp[1] ), + .axi_wide_out_req_o ( wide_sub_req[1] ), + .axi_wide_out_rsp_i ( wide_sub_rsp[1] ), + .xy_id_i ( '0 ), + .id_i ( '0 ), + .floo_req_o ( chimney_req[1] ), + .floo_rsp_o ( chimney_rsp[1] ), + .floo_wide_o ( chimney_wide[1] ), + .floo_req_i ( chimney_req_cut[0] ), + .floo_rsp_i ( chimney_rsp_cut[0] ), + .floo_wide_i ( chimney_wide_cut[0] ) ); axi_channel_compare #( - .aw_chan_t ( narrow_in_aw_chan_t ), - .w_chan_t ( narrow_in_w_chan_t ), - .b_chan_t ( narrow_in_b_chan_t ), - .ar_chan_t ( narrow_in_ar_chan_t ), - .r_chan_t ( narrow_in_r_chan_t ), - .req_t ( narrow_in_req_t ), - .resp_t ( narrow_in_resp_t ) + .aw_chan_t ( axi_narrow_in_aw_chan_t ), + .w_chan_t ( axi_narrow_in_w_chan_t ), + .b_chan_t ( axi_narrow_in_b_chan_t ), + .ar_chan_t ( axi_narrow_in_ar_chan_t ), + .r_chan_t ( axi_narrow_in_r_chan_t ), + .req_t ( axi_narrow_in_req_t ), + .resp_t ( axi_narrow_in_rsp_t ) ) i_narrow_channel_compare_1 ( - .clk_i ( clk ), - .axi_a_req ( narrow_man_req[1] ), - .axi_a_res ( narrow_man_rsp[1] ), + .clk_i ( clk ), + .axi_a_req ( narrow_man_req[1] ), + .axi_a_res ( narrow_man_rsp[1] ), .axi_b_req ( narrow_sub_req_id_mapped[0] ), .axi_b_res ( narrow_sub_rsp_id_mapped[0] ) ); axi_channel_compare #( - .aw_chan_t ( wide_in_aw_chan_t ), - .w_chan_t ( wide_in_w_chan_t ), - .b_chan_t ( wide_in_b_chan_t ), - .ar_chan_t ( wide_in_ar_chan_t ), - .r_chan_t ( wide_in_r_chan_t ), - .req_t ( wide_in_req_t ), - .resp_t ( wide_in_resp_t ) + .aw_chan_t ( axi_wide_in_aw_chan_t ), + .w_chan_t ( axi_wide_in_w_chan_t ), + .b_chan_t ( axi_wide_in_b_chan_t ), + .ar_chan_t ( axi_wide_in_ar_chan_t ), + .r_chan_t ( axi_wide_in_r_chan_t ), + .req_t ( axi_wide_in_req_t ), + .resp_t ( axi_wide_in_rsp_t ) ) i_wide_channel_compare_1 ( - .clk_i ( clk ), - .axi_a_req ( wide_man_req[1] ), - .axi_a_res ( wide_man_rsp[1] ), + .clk_i ( clk ), + .axi_a_req ( wide_man_req[1] ), + .axi_a_res ( wide_man_rsp[1] ), .axi_b_req ( wide_sub_req_id_mapped[0] ), .axi_b_res ( wide_sub_rsp_id_mapped[0] ) ); floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .DataWidth ( NarrowInDataWidth ), - .AddrWidth ( NarrowInAddrWidth ), - .UserWidth ( NarrowInUserWidth ), - .AxiIdInWidth ( NarrowOutIdWidth ), - .AxiIdOutWidth ( NarrowInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( narrow_out_req_t ), - .axi_in_rsp_t ( narrow_out_resp_t ), - .axi_out_req_t ( narrow_in_req_t ), - .axi_out_rsp_t ( narrow_in_resp_t ), - .JobId ( 101 ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .DataWidth ( NarrowInDataWidth ), + .AddrWidth ( NarrowInAddrWidth ), + .UserWidth ( NarrowInUserWidth ), + .AxiIdInWidth ( NarrowOutIdWidth ), + .AxiIdOutWidth ( NarrowInIdWidth ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .axi_in_req_t ( axi_narrow_out_req_t ), + .axi_in_rsp_t ( axi_narrow_out_rsp_t ), + .axi_out_req_t ( axi_narrow_in_req_t ), + .axi_out_rsp_t ( axi_narrow_in_rsp_t ), + .JobId ( 101 ) ) i_narrow_dma_node_1 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -319,21 +319,21 @@ module tb_floo_dma_nw_chimney; ); floo_dma_test_node #( - .TA ( ApplTime ), - .TT ( TestTime ), - .TCK ( CyclTime ), - .DataWidth ( WideInDataWidth ), - .AddrWidth ( WideInAddrWidth ), - .UserWidth ( WideInUserWidth ), - .AxiIdInWidth ( WideOutIdWidth ), - .AxiIdOutWidth ( WideInIdWidth ), - .MemBaseAddr ( MemBaseAddr ), - .MemSize ( MemSize ), - .axi_in_req_t ( wide_out_req_t ), - .axi_in_rsp_t ( wide_out_resp_t ), - .axi_out_req_t ( wide_in_req_t ), - .axi_out_rsp_t ( wide_in_resp_t ), - .JobId ( 1 ) + .TA ( ApplTime ), + .TT ( TestTime ), + .TCK ( CyclTime ), + .DataWidth ( WideInDataWidth ), + .AddrWidth ( WideInAddrWidth ), + .UserWidth ( WideInUserWidth ), + .AxiIdInWidth ( WideOutIdWidth ), + .AxiIdOutWidth ( WideInIdWidth ), + .MemBaseAddr ( MemBaseAddr ), + .MemSize ( MemSize ), + .axi_in_req_t ( axi_wide_out_req_t ), + .axi_in_rsp_t ( axi_wide_out_rsp_t ), + .axi_out_req_t ( axi_wide_in_req_t ), + .axi_out_rsp_t ( axi_wide_in_rsp_t ), + .JobId ( 1 ) ) i_wide_dma_node_1 ( .clk_i ( clk ), .rst_ni ( rst_n ), @@ -345,10 +345,10 @@ module tb_floo_dma_nw_chimney; ); axi_bw_monitor #( - .req_t ( narrow_in_req_t ), - .rsp_t ( narrow_in_resp_t ), - .AxiIdWidth ( NarrowInIdWidth ), - .name ( "narrow 0" ) + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ), + .AxiIdWidth ( NarrowInIdWidth ), + .name ( "narrow 0" ) ) i_axi_narrow_bw_monitor_0 ( .clk_i ( clk ), .en_i ( rst_n ), @@ -358,10 +358,10 @@ module tb_floo_dma_nw_chimney; ); axi_bw_monitor #( - .req_t ( narrow_in_req_t ), - .rsp_t ( narrow_in_resp_t ), - .AxiIdWidth ( NarrowInIdWidth ), - .name ( "narrow 1" ) + .req_t ( axi_narrow_in_req_t ), + .rsp_t ( axi_narrow_in_rsp_t ), + .AxiIdWidth ( NarrowInIdWidth ), + .name ( "narrow 1" ) ) i_axi_narrow_bw_monitor_1 ( .clk_i ( clk ), .en_i ( rst_n ), @@ -371,10 +371,10 @@ module tb_floo_dma_nw_chimney; ); axi_bw_monitor #( - .req_t ( wide_in_req_t ), - .rsp_t ( wide_in_resp_t ), - .AxiIdWidth ( WideInIdWidth ), - .name ( "wide 0" ) + .req_t ( axi_wide_in_req_t ), + .rsp_t ( axi_wide_in_rsp_t ), + .AxiIdWidth ( WideInIdWidth ), + .name ( "wide 0" ) ) i_axi_wide_bw_monitor_0 ( .clk_i ( clk ), .en_i ( rst_n ), @@ -384,10 +384,10 @@ module tb_floo_dma_nw_chimney; ); axi_bw_monitor #( - .req_t ( wide_in_req_t ), - .rsp_t ( wide_in_resp_t ), - .AxiIdWidth ( WideInIdWidth ), - .name ( "wide 1" ) + .req_t ( axi_wide_in_req_t ), + .rsp_t ( axi_wide_in_rsp_t ), + .AxiIdWidth ( WideInIdWidth ), + .name ( "wide 1" ) ) i_axi_wide_bw_monitor_1 ( .clk_i ( clk ), .en_i ( rst_n ),