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tests: Add generated mesh traffic tests #72

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Sep 18, 2024
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4297b40
hw(nw_join): Use axi configs for `nw_join`
fischeti Sep 18, 2024
ac806e1
sim: Don't show loading messages in vsim
fischeti Sep 18, 2024
4b69104
tb: Add `nw_mesh` testbench with generated NoC
fischeti Sep 18, 2024
b1584e4
floogen(router): Add global id offset to router
fischeti Sep 18, 2024
44c33ca
util(jobs): Start mesh index at (0,0)
fischeti Sep 18, 2024
a6c411d
ci: Try to generate with floogen and run traffic on `nw_mesh`
fischeti Sep 18, 2024
e770636
ci: Try with venv
fischeti Sep 18, 2024
996f715
ci: Don't format generated sources with verible
fischeti Sep 18, 2024
6af9e0d
ci: Small fix
fischeti Sep 18, 2024
f08fbb1
make: Use `EXTRA_BENDER_FLAGS` to add additional bender targets from …
fischeti Sep 18, 2024
10f5636
util(jobs): Fix `random` coordinate range
fischeti Sep 18, 2024
40debc6
ci: Install FlooGen in earlier stage
fischeti Sep 18, 2024
7a44afa
ci: Remove `noci` rule
fischeti Sep 18, 2024
9a90fa2
ci: Debug
fischeti Sep 18, 2024
c558b2b
floogen(pkg): Also print endpoint enum for XY routing and sort system…
fischeti Sep 18, 2024
9f1a90e
test: Use correct x,y increments
fischeti Sep 18, 2024
e7e5e08
tb: Index directly into system address map
fischeti Sep 18, 2024
9970724
ci: Add `src` and `id` test for `nw_mesh`
fischeti Sep 18, 2024
47aa75e
floogen(examples): Align `axi_mesh` exampels
fischeti Sep 18, 2024
372f168
floogen(routing): Use correct `axi_ch` type for single-AXI networks
fischeti Sep 18, 2024
00650ef
floogen(tpl): Fix xy id offset in `axi_router`
fischeti Sep 18, 2024
d7f8f47
waves: Rename `narrow_wide` to `nw` in wave scripts
fischeti Sep 18, 2024
04bf743
test: Add `axi_mesh` testbench
fischeti Sep 18, 2024
7f43d43
ci: Add `axi_mesh` to CI
fischeti Sep 18, 2024
bbd9025
make: Specify work folder
fischeti Sep 18, 2024
94d3d77
ci: Improve stages in CI
fischeti Sep 18, 2024
fefde2e
lint: SV sources
fischeti Sep 18, 2024
08d402c
lint: python sources
fischeti Sep 18, 2024
b65e5bd
ci: Remove FlooGen generation from GitHub CI
fischeti Sep 18, 2024
c8e3955
tb: Remove deprecated `dma_mesh` and `dma_vc_mesh`
fischeti Sep 18, 2024
58c511b
bender: Remove special target for `vc_router`
fischeti Sep 18, 2024
c1da366
docs: Update README
fischeti Sep 18, 2024
933aeb3
docs: Update CHANGELOG
fischeti Sep 18, 2024
f2a3888
bender: Remove `vc_router` target
fischeti Sep 18, 2024
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55 changes: 0 additions & 55 deletions .github/workflows/floogen.yml
Original file line number Diff line number Diff line change
Expand Up @@ -29,58 +29,3 @@ jobs:
- name: Run unit tests
run: |
python -m pytest -v

#####################
# Generate SV files #
#####################
gen-nocs:
runs-on: ubuntu-latest
strategy:
matrix:
examples: ["single_cluster", "occamy_mesh_xy", "occamy_tree", "occamy_mesh_src", "terapool"]
steps:
- uses: actions/checkout@v4
- name: Set up Python
uses: actions/setup-python@v5
with:
python-version: '3.10'
- name: Install dependencies
run: |
python -m pip install --upgrade pip
- name: Install floogen
run: |
python -m pip install .
- name: Install Verible
uses: chipsalliance/verible-actions-common/install-verible@main
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
- name: Generate NoCs
run: |
floogen -c floogen/examples/${{ matrix.examples }}.yml -o generated
- name: Upload artifact
uses: actions/upload-artifact@v4
with:
name: ${{ matrix.examples }}
path: generated/floo_${{ matrix.examples }}_noc.sv
if-no-files-found: error
retention-days: 1

#################
# Lint SV files #
#################
lint-nocs:
runs-on: ubuntu-latest
needs: gen-nocs
steps:
- uses: actions/checkout@v4
- name: Download artifact
uses: actions/download-artifact@v4
with:
path: generated
- name: Lint SV files
uses: chipsalliance/verible-linter-action@main
with:
config_file: ''
paths:
./generated
github_token: ${{ secrets.GITHUB_TOKEN }}
64 changes: 42 additions & 22 deletions .gitlab-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
variables:
VSIM: questa-2023.4 vsim
BENDER: bender
PYTHON: /usr/local/anaconda3/bin/python

stages:
- init
Expand All @@ -24,25 +25,44 @@ collect-bender-sources:

compile-vsim:
stage: build
script:
- make compile-sim VC=true | tee compile.log 2>&1
- '! grep "\*\* Error" compile.log'
needs:
- collect-bender-sources
script:
- make compile-sim | tee compile.log 2>&1
- '! grep "\*\* Error" compile.log'
artifacts:
paths:
- scripts/
- work/
- modelsim.ini

run-vsim:
stage: run
compile-meshes:
stage: build
needs:
- collect-bender-sources
parallel:
matrix:
- DUT: [axi_mesh, nw_mesh]
ROUTE_ALGO: [xy, src, id]
script:
- make run-sim-batch | tee vsim.log 2>&1
- 'grep "Errors: 0," vsim.log'
# Install `floogen`
- $PYTHON -m venv .venv
- source .venv/bin/activate
- pip install .
# Generate sources
- floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format
# Compile the network
- make compile-sim EXTRA_BENDER_FLAGS="-t ${DUT}" WORK="work_${DUT}_${ROUTE_ALGO}" | tee compile.log 2>&1
- '! grep "\*\* Error" compile.log'
artifacts:
paths:
- vsim.log
- work_*/

run-vsim:
stage: run
needs:
- collect-bender-sources
- compile-vsim
parallel:
matrix:
- VSIM_TB_DUT:
Expand All @@ -51,35 +71,35 @@ run-vsim:
- tb_floo_axi_chimney
- tb_floo_nw_chimney
- tb_floo_rob
needs:
- collect-bender-sources
- compile-vsim
rules:
- if: '$CI_COMMIT_REF_NAME =~ /noci$/'
when: manual
- when: always
script:
- make run-sim-batch | tee vsim.log 2>&1
- 'grep "Errors: 0," vsim.log'
artifacts:
paths:
- vsim.log

run-traffic:
stage: run
needs:
- collect-bender-sources
- compile-meshes
variables:
JOB_NAME: mesh
parallel:
matrix:
- VSIM_TB_DUT: [tb_floo_dma_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses
- DUT: [axi_mesh, nw_mesh]
ROUTE_ALGO: [xy, src, id]
TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center]
TRAFFIC_RW: [read, write]
needs:
- collect-bender-sources
- compile-vsim
script:
- make jobs
- make run-sim-batch | tee vsim.log 2>&1
- make run-sim-batch VSIM_TB_DUT=tb_floo_${DUT} WORK=work_${DUT}_${ROUTE_ALGO} | tee vsim.log 2>&1
- 'grep "Errors: 0," vsim.log'

morty:
stage: build
needs:
- collect-bender-sources
script:
- $BENDER sources -f > source_list.txt
- morty -f source_list.txt
needs:
- collect-bender-sources
49 changes: 27 additions & 22 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -42,24 +42,22 @@ sources:
- hw/floo_axi_router.sv
- hw/floo_nw_router.sv

- target: vc_router
files:
# Level 1
- hw/vc_router_util/floo_credit_counter.sv
- hw/vc_router_util/floo_input_fifo.sv
- hw/vc_router_util/floo_input_port.sv
- hw/vc_router_util/floo_look_ahead_routing.sv
- hw/vc_router_util/floo_mux.sv
- hw/vc_router_util/floo_rr_arbiter.sv
- hw/vc_router_util/floo_sa_global.sv
- hw/vc_router_util/floo_sa_local.sv
- hw/vc_router_util/floo_vc_assignment.sv
- hw/vc_router_util/floo_vc_router_switch.sv
- hw/vc_router_util/floo_vc_selection.sv
# Level 2
- hw/floo_vc_router.sv
- hw/floo_nw_vc_chimney.sv
- hw/floo_nw_vc_router.sv
# VC Router (Level 1)
- hw/vc_router_util/floo_credit_counter.sv
- hw/vc_router_util/floo_input_fifo.sv
- hw/vc_router_util/floo_input_port.sv
- hw/vc_router_util/floo_look_ahead_routing.sv
- hw/vc_router_util/floo_mux.sv
- hw/vc_router_util/floo_rr_arbiter.sv
- hw/vc_router_util/floo_sa_global.sv
- hw/vc_router_util/floo_sa_local.sv
- hw/vc_router_util/floo_vc_assignment.sv
- hw/vc_router_util/floo_vc_router_switch.sv
- hw/vc_router_util/floo_vc_selection.sv
# Level 2
- hw/floo_vc_router.sv
- hw/floo_nw_vc_chimney.sv
- hw/floo_nw_vc_router.sv

- target: test
include_dirs:
Expand All @@ -80,11 +78,18 @@ sources:
- hw/tb/tb_floo_nw_chimney.sv
- hw/tb/tb_floo_router.sv
- hw/tb/tb_floo_rob.sv
- hw/tb/tb_floo_dma_mesh.sv
- hw/tb/tb_floo_vc_router.sv

- target: all(test, vc_router)
- target: all(test, axi_mesh)
include_dirs:
- hw/test/include
files:
- hw/tb/tb_floo_vc_router.sv
- hw/tb/tb_floo_vc_dma_mesh.sv
- generated/floo_axi_mesh_noc.sv
- hw/tb/tb_floo_axi_mesh.sv

- target: all(test, nw_mesh)
include_dirs:
- hw/test/include
files:
- generated/floo_nw_mesh_noc.sv
- hw/tb/tb_floo_nw_mesh.sv
3 changes: 3 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -45,10 +45,12 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
- The `name` field must be unique now, since it is used by `mgr_port_protocol` and `sbr_port_protocol` to reference the exact protocol.
- All examples were adapted to reflect those changes.
- A FlooGen configuration file now requires a `network_type` field, to determine the type of network to generate. The options are `axi` for single-AXI networks and `narrow-wide` for the narrow-wide AXI configurations.
- The system address map `Sam` is now sorted correctly and can be indexed with `ep_id_e` values.

### Fixed

- A bug in the calcuation of the RoB offset in `floo_rob` was fixed. Previously, the allocation and the write process used the same counter in bursts for offset calculation, which resulted in wrong offsets.
- Routers with `XYRouting` do now use the global `id_offset`, which was previously not accounted for (or had to be specified manually).

### Removed

Expand All @@ -57,6 +59,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
- As the flit type definitions were moved to `typedef.svh`, the auto-generated `floo_*_pkg` packages were removed from the repository. Furthermore, all the (global) imports of those packages in the modules were replaced by parameters.
- The testbench `tb_floo_nw_chimney` was removed since it was neither used nor maintained anymore.
- The `IdIsPort` routing algorithm was removed since it can only be used for routes over a single router. The same functionality can be achieved with the `SourceRouting` algorithm.
- The `dma_mesh` testbench was removed in favor of `nw_mesh` and `axi_mesh` which use generated networks with _FlooGen_.

#### FlooGen
- The package generation was removed from _FlooGen_ since it is now handled by the `typedef.svh` file. Further, the `--only-pkg` and `--pkg-outdir` flags were removed from the _FlooGen_ CLI.
Expand Down
9 changes: 6 additions & 3 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -33,20 +33,23 @@ BENDER_FLAGS += -t rtl
BENDER_FLAGS += -t test
BENDER_FLAGS += -t snitch_cluster
BENDER_FLAGS += -t idma_test
ifdef VC
BENDER_FLAGS += -t vc_router
endif
BENDER_FLAGS := $(BENDER_FLAGS) $(EXTRA_BENDER_FLAGS)

WORK ?= work

VLOG_ARGS += -suppress vlog-2583
VLOG_ARGS += -suppress vlog-13314
VLOG_ARGS += -suppress vlog-13233
VLOG_ARGS += -timescale \"1 ns / 1 ps\"
VLOG_ARGS += -work $(WORK)

VSIM_TB_DUT ?= floo_noc_router_test

VSIM_FLAGS += -64
VSIM_FLAGS += -t 1ps
VSIM_FLAGS += -sv_seed 0
VSIM_FLAGS += -quiet
VSIM_FLAGS += -work $(WORK)

# Set the job name and directory if specified
ifdef JOB_NAME
Expand Down
6 changes: 3 additions & 3 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -104,13 +104,13 @@ This repository includes the following NoC IPs:
| Name | Description | Doc |
| --- | --- | --- |
| [floo_router](hw/floo_router.sv) | A simple router with configurable number of ports, physical and virtual channels, and input/output buffers | |
| [floo_narrow_wide_router](hw/floo_narrow_wide_router.sv) | Wrapper of a multi-link router for narrow and wide links | |
| [floo_nw_router](hw/floo_nw_router.sv) | Wrapper of a multi-link router for narrow and wide links | |

### Network Interfaces
| Name | Description | Doc |
| --- | --- | --- |
| [floo_axi_chimney](hw/floo_axi_chimney.sv) | A bidirectional network interface for connecting AXI4 Buses to the NoC | |
| [floo_narrow_wide_chimney](hw/floo_narrow_wide_chimney.sv) | A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC | |
| [floo_nw_chimney](hw/floo_nw_chimney.sv) | A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC | |

### Common IPs
| Name | Description | Doc |
Expand All @@ -124,7 +124,7 @@ This repository includes the following NoC IPs:
| [floo_rob](hw/floo_rob.sv) | A table-based Reorder Buffer | |
| [floo_simple_rob](hw/floo_simple_rob.sv) | A simplistic low-complexity Reorder Buffer | |
| [floo_rob_wrapper](hw/floo_simple_rob.sv) | A wrapper of all available types of RoBs including RoB-less version | |
| [floo_narrow_wide_join](hw/floo_narrow_wide_join.sv) | A mux for joining a narrow and wide AXI bus a single wide bus | |
| [floo_nw_join](hw/floo_nw_join.sv) | A mux for joining a narrow and wide AXI bus a single wide bus | |

### Verification IPs
| Name | Description | Doc |
Expand Down
20 changes: 4 additions & 16 deletions floogen/examples/axi_mesh_id.yml
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
# SPDX-License-Identifier: Apache-2.0

name: axi_mesh
description: "AXI mesh configuration for FlooGen"
description: "AXI mesh configuration with table-based routing for FlooGen"
network_type: "axi"

routing:
Expand All @@ -30,8 +30,8 @@ endpoints:
- name: "cluster"
array: [4, 4]
addr_range:
base: 0x0000_1000_0000
size: 0x0000_0004_0000
base: 0x0000_0000_0000
size: 0x0000_0001_0000
mgr_port_protocol:
- "axi_in"
sbr_port_protocol:
Expand All @@ -40,15 +40,7 @@ endpoints:
array: [4]
addr_range:
base: 0x0000_8000_0000
size: 0x0000_4000_0000
sbr_port_protocol:
- "axi_out"
- name: "peripherals"
addr_range:
start: 0x0000_0000_0000
end: 0x0000_0fff_ffff
mgr_port_protocol:
- "axi_in"
size: 0x0000_0001_0000
sbr_port_protocol:
- "axi_out"

Expand All @@ -75,7 +67,3 @@ connections:
- [0, 0]
- [0, 3]
dst_dir: "West"
- src: "peripherals"
dst: "router"
dst_idx: [1, 3]
dst_dir: "North"
20 changes: 4 additions & 16 deletions floogen/examples/axi_mesh_src.yml
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
# SPDX-License-Identifier: Apache-2.0

name: axi_mesh
description: "AXI mesh configuration for FlooGen"
description: "AXI mesh configuration with source-based routing for FlooGen"
network_type: "axi"

routing:
Expand All @@ -30,8 +30,8 @@ endpoints:
- name: "cluster"
array: [4, 4]
addr_range:
base: 0x0000_1000_0000
size: 0x0000_0004_0000
base: 0x0000_0000_0000
size: 0x0000_0001_0000
mgr_port_protocol:
- "axi_in"
sbr_port_protocol:
Expand All @@ -40,15 +40,7 @@ endpoints:
array: [4]
addr_range:
base: 0x0000_8000_0000
size: 0x0000_4000_0000
sbr_port_protocol:
- "axi_out"
- name: "peripherals"
addr_range:
start: 0x0000_0000_0000
end: 0x0000_0fff_ffff
mgr_port_protocol:
- "axi_in"
size: 0x0000_0001_0000
sbr_port_protocol:
- "axi_out"

Expand All @@ -75,7 +67,3 @@ connections:
- [0, 0]
- [0, 3]
dst_dir: "West"
- src: "peripherals"
dst: "router"
dst_idx: [1, 3]
dst_dir: "North"
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