From 5e3f6a32749ffee457220cc607abb9fa62bcc72e Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Tue, 14 Jan 2025 17:19:28 +0100 Subject: [PATCH] [CHANGELOG] Update Changelog --- CHANGELOG.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index ff7c14f70..dfe8d0da6 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -30,6 +30,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Remove a couple of latches - Fix dispatcher state change upon vector CSR instruction - Force a reshuffle when `vl == vlmax && vstart > 0` + - Align g++ version with cheshire's if simulating with it (for QuestaSim) + - Don't compile the first-pass-decoder in CVA6 (need for a specific bender target) + - Solve type-conversion warnings about type conversions ### Added @@ -50,6 +53,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Add Cheshire bare-metal FPGA flow for vcu128 and vcu118 - Add cva6-sdk submodule - Add Cheshire Linux FPGA flow for vcu128 and vcu118 + - Add RVV tests to be used with Cheshire's stub and specific debug environment. ### Changed