diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 80455f8c..0c4ed815 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -518,7 +518,9 @@ package cheshire_pkg; RefillWrite = 4, RefillRead = 5, EvictWrite = 6, - EvictRead = 7 + EvictRead = 7, + WAccess = 8, + RAccess = 9 } llc_evts_e; //////////////// diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index a231ce54..bb7d96c6 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -440,7 +440,7 @@ module cheshire_soc import cheshire_pkg::*; #( axi_llc_pkg::events_t axi_llc_evts_all; // Selected LLC events - localparam int unsigned LlcNumEvts = 8; + localparam int unsigned LlcNumEvts = 10; localparam int unsigned LlcEvtCntWidth = 32; logic [LlcNumEvts-1:0] llc_evts; @@ -451,7 +451,7 @@ module cheshire_soc import cheshire_pkg::*; #( logic [LlcEvtCntWidth-1:0] read; } llc_cnt_t; - llc_cnt_t llc_hit_cnt_cache, llc_miss_cnt_cache, llc_refill_cnt, llc_evict_cnt; + llc_cnt_t llc_hit_cnt_cache, llc_miss_cnt_cache, llc_refill_cnt, llc_evict_cnt, llc_access_cnt_cache; if (Cfg.LlcOutConnect) begin : gen_llc_atomics @@ -556,15 +556,18 @@ module cheshire_soc import cheshire_pkg::*; #( .axi_llc_events_o ( axi_llc_evts_all ) ); - // LLC events array comprises 24 17-bit `event_num_bytes_t` data structures and 4 1-bit event - // signals. The 24 structs track, for various events, (i) a level-sensitive signal corresponding - // to a handshake (1-bit `active` field), and (ii) the number of transferred bytes (16-bits - // `num_bytes` field) during the handshake. The 4 remaining 1-bit signals perform high-level - // tracking of evict, refill, write and read requests. We filter all this information and extract - // the `active` events for hit (w/r), miss (w/r), refill (w/r) and evict (w/r) to count how - // frequently an event happened, and collect this number in a register. - - assign llc_evts = { axi_llc_evts_all.evict_read.active, axi_llc_evts_all.evict_write.active, + // LLC events array comprises 24 17-bit `event_num_bytes_t` data structures + // and 4 1-bit event signals. The 24 structs track, for various events, (i) a + // level-sensitive signal corresponding to a handshake (1-bit `active` field), + // and (ii) the number of transferred bytes (16-bits `num_bytes` field) during + // the handshake. The 4 remaining 1-bit signals perform high-level tracking of + // evict, refill, write and read requests. We filter all this information and + // extract the `active` events for accesses to the LLC (w/r), hits (w/r), + // misses (w/r), refills (w/r) and evictions (w/r) to count how frequently an + // event happened, and collect this number in a register. + + assign llc_evts = { axi_llc_evts_all.ar_desc_cache.active, axi_llc_evts_all.aw_desc_cache.active, + axi_llc_evts_all.evict_read.active, axi_llc_evts_all.evict_write.active, axi_llc_evts_all.refill_read.active, axi_llc_evts_all.refill_write.active, axi_llc_evts_all.miss_read_cache.active, axi_llc_evts_all.miss_write_cache.active, axi_llc_evts_all.hit_read_cache.active, axi_llc_evts_all.hit_write_cache.active @@ -578,6 +581,8 @@ module cheshire_soc import cheshire_pkg::*; #( assign llc_refill_cnt.read = llc_evt_cnts[RefillRead]; assign llc_evict_cnt.write = llc_evt_cnts[EvictWrite]; assign llc_evict_cnt.read = llc_evt_cnts[EvictRead]; + assign llc_access_cnt_cache.write = llc_evt_cnts[WAccess]; + assign llc_access_cnt_cache.read = llc_evt_cnts[RAccess]; for (genvar i=0; i < LlcNumEvts; i++) begin : gen_llc_evt_cntrs counter #( @@ -1118,6 +1123,8 @@ module cheshire_soc import cheshire_pkg::*; #( llc_refill_cnt_read : llc_refill_cnt.read, llc_evict_cnt_write : llc_evict_cnt.write, llc_evict_cnt_read : llc_evict_cnt.read, + llc_access_cnt_write_cache : llc_access_cnt_cache.write, + llc_access_cnt_read_cache : llc_access_cnt_cache.read, vga_params : '{ red_width : Cfg.VgaRedWidth, green_width : Cfg.VgaGreenWidth, diff --git a/hw/regs/cheshire_reg_pkg.sv b/hw/regs/cheshire_reg_pkg.sv index 488866ab..f21f0873 100644 --- a/hw/regs/cheshire_reg_pkg.sv +++ b/hw/regs/cheshire_reg_pkg.sv @@ -7,7 +7,7 @@ package cheshire_reg_pkg; // Address widths within the block - parameter int BlockAw = 7; + parameter int BlockAw = 8; //////////////////////////// // Typedefs for registers // @@ -107,6 +107,14 @@ package cheshire_reg_pkg; logic [31:0] d; } cheshire_hw2reg_llc_evict_cnt_read_reg_t; + typedef struct packed { + logic [31:0] d; + } cheshire_hw2reg_llc_access_cnt_write_cache_reg_t; + + typedef struct packed { + logic [31:0] d; + } cheshire_hw2reg_llc_access_cnt_read_cache_reg_t; + typedef struct packed { struct packed { logic [7:0] d; @@ -121,55 +129,59 @@ package cheshire_reg_pkg; // HW -> register type typedef struct packed { - cheshire_hw2reg_boot_mode_reg_t boot_mode; // [422:421] - cheshire_hw2reg_rtc_freq_reg_t rtc_freq; // [420:389] - cheshire_hw2reg_platform_rom_reg_t platform_rom; // [388:357] - cheshire_hw2reg_num_int_harts_reg_t num_int_harts; // [356:325] - cheshire_hw2reg_hw_features_reg_t hw_features; // [324:312] - cheshire_hw2reg_llc_size_reg_t llc_size; // [311:280] - cheshire_hw2reg_llc_hit_cnt_write_cache_reg_t llc_hit_cnt_write_cache; // [279:248] - cheshire_hw2reg_llc_hit_cnt_read_cache_reg_t llc_hit_cnt_read_cache; // [247:216] - cheshire_hw2reg_llc_miss_cnt_write_cache_reg_t llc_miss_cnt_write_cache; // [215:184] - cheshire_hw2reg_llc_miss_cnt_read_cache_reg_t llc_miss_cnt_read_cache; // [183:152] - cheshire_hw2reg_llc_refill_cnt_write_reg_t llc_refill_cnt_write; // [151:120] - cheshire_hw2reg_llc_refill_cnt_read_reg_t llc_refill_cnt_read; // [119:88] - cheshire_hw2reg_llc_evict_cnt_write_reg_t llc_evict_cnt_write; // [87:56] - cheshire_hw2reg_llc_evict_cnt_read_reg_t llc_evict_cnt_read; // [55:24] + cheshire_hw2reg_boot_mode_reg_t boot_mode; // [486:485] + cheshire_hw2reg_rtc_freq_reg_t rtc_freq; // [484:453] + cheshire_hw2reg_platform_rom_reg_t platform_rom; // [452:421] + cheshire_hw2reg_num_int_harts_reg_t num_int_harts; // [420:389] + cheshire_hw2reg_hw_features_reg_t hw_features; // [388:376] + cheshire_hw2reg_llc_size_reg_t llc_size; // [375:344] + cheshire_hw2reg_llc_hit_cnt_write_cache_reg_t llc_hit_cnt_write_cache; // [343:312] + cheshire_hw2reg_llc_hit_cnt_read_cache_reg_t llc_hit_cnt_read_cache; // [311:280] + cheshire_hw2reg_llc_miss_cnt_write_cache_reg_t llc_miss_cnt_write_cache; // [279:248] + cheshire_hw2reg_llc_miss_cnt_read_cache_reg_t llc_miss_cnt_read_cache; // [247:216] + cheshire_hw2reg_llc_refill_cnt_write_reg_t llc_refill_cnt_write; // [215:184] + cheshire_hw2reg_llc_refill_cnt_read_reg_t llc_refill_cnt_read; // [183:152] + cheshire_hw2reg_llc_evict_cnt_write_reg_t llc_evict_cnt_write; // [151:120] + cheshire_hw2reg_llc_evict_cnt_read_reg_t llc_evict_cnt_read; // [119:88] + cheshire_hw2reg_llc_access_cnt_write_cache_reg_t llc_access_cnt_write_cache; // [87:56] + cheshire_hw2reg_llc_access_cnt_read_cache_reg_t llc_access_cnt_read_cache; // [55:24] cheshire_hw2reg_vga_params_reg_t vga_params; // [23:0] } cheshire_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_0_OFFSET = 7'h 0; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_1_OFFSET = 7'h 4; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_2_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_3_OFFSET = 7'h c; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_4_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_5_OFFSET = 7'h 14; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_6_OFFSET = 7'h 18; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_7_OFFSET = 7'h 1c; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_8_OFFSET = 7'h 20; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_9_OFFSET = 7'h 24; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_10_OFFSET = 7'h 28; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_11_OFFSET = 7'h 2c; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_12_OFFSET = 7'h 30; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_13_OFFSET = 7'h 34; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_14_OFFSET = 7'h 38; - parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_15_OFFSET = 7'h 3c; - parameter logic [BlockAw-1:0] CHESHIRE_BOOT_MODE_OFFSET = 7'h 40; - parameter logic [BlockAw-1:0] CHESHIRE_RTC_FREQ_OFFSET = 7'h 44; - parameter logic [BlockAw-1:0] CHESHIRE_PLATFORM_ROM_OFFSET = 7'h 48; - parameter logic [BlockAw-1:0] CHESHIRE_NUM_INT_HARTS_OFFSET = 7'h 4c; - parameter logic [BlockAw-1:0] CHESHIRE_HW_FEATURES_OFFSET = 7'h 50; - parameter logic [BlockAw-1:0] CHESHIRE_LLC_SIZE_OFFSET = 7'h 54; - parameter logic [BlockAw-1:0] CHESHIRE_LLC_HIT_CNT_WRITE_CACHE_OFFSET = 7'h 58; - parameter logic [BlockAw-1:0] CHESHIRE_LLC_HIT_CNT_READ_CACHE_OFFSET = 7'h 5c; - parameter logic [BlockAw-1:0] CHESHIRE_LLC_MISS_CNT_WRITE_CACHE_OFFSET = 7'h 60; - parameter logic [BlockAw-1:0] CHESHIRE_LLC_MISS_CNT_READ_CACHE_OFFSET = 7'h 64; - parameter logic [BlockAw-1:0] CHESHIRE_LLC_REFILL_CNT_WRITE_OFFSET = 7'h 68; - parameter logic [BlockAw-1:0] CHESHIRE_LLC_REFILL_CNT_READ_OFFSET = 7'h 6c; - parameter logic [BlockAw-1:0] CHESHIRE_LLC_EVICT_CNT_WRITE_OFFSET = 7'h 70; - parameter logic [BlockAw-1:0] CHESHIRE_LLC_EVICT_CNT_READ_OFFSET = 7'h 74; - parameter logic [BlockAw-1:0] CHESHIRE_VGA_PARAMS_OFFSET = 7'h 78; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_0_OFFSET = 8'h 0; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_1_OFFSET = 8'h 4; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_2_OFFSET = 8'h 8; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_3_OFFSET = 8'h c; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_4_OFFSET = 8'h 10; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_5_OFFSET = 8'h 14; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_6_OFFSET = 8'h 18; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_7_OFFSET = 8'h 1c; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_8_OFFSET = 8'h 20; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_9_OFFSET = 8'h 24; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_10_OFFSET = 8'h 28; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_11_OFFSET = 8'h 2c; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_12_OFFSET = 8'h 30; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_13_OFFSET = 8'h 34; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_14_OFFSET = 8'h 38; + parameter logic [BlockAw-1:0] CHESHIRE_SCRATCH_15_OFFSET = 8'h 3c; + parameter logic [BlockAw-1:0] CHESHIRE_BOOT_MODE_OFFSET = 8'h 40; + parameter logic [BlockAw-1:0] CHESHIRE_RTC_FREQ_OFFSET = 8'h 44; + parameter logic [BlockAw-1:0] CHESHIRE_PLATFORM_ROM_OFFSET = 8'h 48; + parameter logic [BlockAw-1:0] CHESHIRE_NUM_INT_HARTS_OFFSET = 8'h 4c; + parameter logic [BlockAw-1:0] CHESHIRE_HW_FEATURES_OFFSET = 8'h 50; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_SIZE_OFFSET = 8'h 54; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_HIT_CNT_WRITE_CACHE_OFFSET = 8'h 58; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_HIT_CNT_READ_CACHE_OFFSET = 8'h 5c; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_MISS_CNT_WRITE_CACHE_OFFSET = 8'h 60; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_MISS_CNT_READ_CACHE_OFFSET = 8'h 64; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_REFILL_CNT_WRITE_OFFSET = 8'h 68; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_REFILL_CNT_READ_OFFSET = 8'h 6c; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_EVICT_CNT_WRITE_OFFSET = 8'h 70; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_EVICT_CNT_READ_OFFSET = 8'h 74; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE_OFFSET = 8'h 78; + parameter logic [BlockAw-1:0] CHESHIRE_LLC_ACCESS_CNT_READ_CACHE_OFFSET = 8'h 7c; + parameter logic [BlockAw-1:0] CHESHIRE_VGA_PARAMS_OFFSET = 8'h 80; // Reset values for hwext registers and their fields parameter logic [1:0] CHESHIRE_BOOT_MODE_RESVAL = 2'h 0; @@ -186,6 +198,8 @@ package cheshire_reg_pkg; parameter logic [31:0] CHESHIRE_LLC_REFILL_CNT_READ_RESVAL = 32'h 0; parameter logic [31:0] CHESHIRE_LLC_EVICT_CNT_WRITE_RESVAL = 32'h 0; parameter logic [31:0] CHESHIRE_LLC_EVICT_CNT_READ_RESVAL = 32'h 0; + parameter logic [31:0] CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE_RESVAL = 32'h 0; + parameter logic [31:0] CHESHIRE_LLC_ACCESS_CNT_READ_CACHE_RESVAL = 32'h 0; parameter logic [23:0] CHESHIRE_VGA_PARAMS_RESVAL = 24'h 0; // Register index @@ -220,11 +234,13 @@ package cheshire_reg_pkg; CHESHIRE_LLC_REFILL_CNT_READ, CHESHIRE_LLC_EVICT_CNT_WRITE, CHESHIRE_LLC_EVICT_CNT_READ, + CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE, + CHESHIRE_LLC_ACCESS_CNT_READ_CACHE, CHESHIRE_VGA_PARAMS } cheshire_id_e; // Register width information to check illegal writes - parameter logic [3:0] CHESHIRE_PERMIT [31] = '{ + parameter logic [3:0] CHESHIRE_PERMIT [33] = '{ 4'b 1111, // index[ 0] CHESHIRE_SCRATCH_0 4'b 1111, // index[ 1] CHESHIRE_SCRATCH_1 4'b 1111, // index[ 2] CHESHIRE_SCRATCH_2 @@ -255,7 +271,9 @@ package cheshire_reg_pkg; 4'b 1111, // index[27] CHESHIRE_LLC_REFILL_CNT_READ 4'b 1111, // index[28] CHESHIRE_LLC_EVICT_CNT_WRITE 4'b 1111, // index[29] CHESHIRE_LLC_EVICT_CNT_READ - 4'b 0111 // index[30] CHESHIRE_VGA_PARAMS + 4'b 1111, // index[30] CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE + 4'b 1111, // index[31] CHESHIRE_LLC_ACCESS_CNT_READ_CACHE + 4'b 0111 // index[32] CHESHIRE_VGA_PARAMS }; endpackage diff --git a/hw/regs/cheshire_reg_top.sv b/hw/regs/cheshire_reg_top.sv index 6e4e6605..cc7603c6 100644 --- a/hw/regs/cheshire_reg_top.sv +++ b/hw/regs/cheshire_reg_top.sv @@ -10,7 +10,7 @@ module cheshire_reg_top #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter int AW = 7 + parameter int AW = 8 ) ( input logic clk_i, input logic rst_ni, @@ -167,6 +167,10 @@ module cheshire_reg_top #( logic llc_evict_cnt_write_re; logic [31:0] llc_evict_cnt_read_qs; logic llc_evict_cnt_read_re; + logic [31:0] llc_access_cnt_write_cache_qs; + logic llc_access_cnt_write_cache_re; + logic [31:0] llc_access_cnt_read_cache_qs; + logic llc_access_cnt_read_cache_re; logic [7:0] vga_params_red_width_qs; logic vga_params_red_width_re; logic [7:0] vga_params_green_width_qs; @@ -1014,6 +1018,38 @@ module cheshire_reg_top #( ); + // R[llc_access_cnt_write_cache]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_llc_access_cnt_write_cache ( + .re (llc_access_cnt_write_cache_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.llc_access_cnt_write_cache.d), + .qre (), + .qe (), + .q (), + .qs (llc_access_cnt_write_cache_qs) + ); + + + // R[llc_access_cnt_read_cache]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_llc_access_cnt_read_cache ( + .re (llc_access_cnt_read_cache_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.llc_access_cnt_read_cache.d), + .qre (), + .qe (), + .q (), + .qs (llc_access_cnt_read_cache_qs) + ); + + // R[vga_params]: V(True) // F[red_width]: 7:0 @@ -1063,7 +1099,7 @@ module cheshire_reg_top #( - logic [30:0] addr_hit; + logic [32:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CHESHIRE_SCRATCH_0_OFFSET); @@ -1096,7 +1132,9 @@ module cheshire_reg_top #( addr_hit[27] = (reg_addr == CHESHIRE_LLC_REFILL_CNT_READ_OFFSET); addr_hit[28] = (reg_addr == CHESHIRE_LLC_EVICT_CNT_WRITE_OFFSET); addr_hit[29] = (reg_addr == CHESHIRE_LLC_EVICT_CNT_READ_OFFSET); - addr_hit[30] = (reg_addr == CHESHIRE_VGA_PARAMS_OFFSET); + addr_hit[30] = (reg_addr == CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE_OFFSET); + addr_hit[31] = (reg_addr == CHESHIRE_LLC_ACCESS_CNT_READ_CACHE_OFFSET); + addr_hit[32] = (reg_addr == CHESHIRE_VGA_PARAMS_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1134,7 +1172,9 @@ module cheshire_reg_top #( (addr_hit[27] & (|(CHESHIRE_PERMIT[27] & ~reg_be))) | (addr_hit[28] & (|(CHESHIRE_PERMIT[28] & ~reg_be))) | (addr_hit[29] & (|(CHESHIRE_PERMIT[29] & ~reg_be))) | - (addr_hit[30] & (|(CHESHIRE_PERMIT[30] & ~reg_be))))); + (addr_hit[30] & (|(CHESHIRE_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(CHESHIRE_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(CHESHIRE_PERMIT[32] & ~reg_be))))); end assign scratch_0_we = addr_hit[0] & reg_we & !reg_error; @@ -1237,11 +1277,15 @@ module cheshire_reg_top #( assign llc_evict_cnt_read_re = addr_hit[29] & reg_re & !reg_error; - assign vga_params_red_width_re = addr_hit[30] & reg_re & !reg_error; + assign llc_access_cnt_write_cache_re = addr_hit[30] & reg_re & !reg_error; + + assign llc_access_cnt_read_cache_re = addr_hit[31] & reg_re & !reg_error; - assign vga_params_green_width_re = addr_hit[30] & reg_re & !reg_error; + assign vga_params_red_width_re = addr_hit[32] & reg_re & !reg_error; - assign vga_params_blue_width_re = addr_hit[30] & reg_re & !reg_error; + assign vga_params_green_width_re = addr_hit[32] & reg_re & !reg_error; + + assign vga_params_blue_width_re = addr_hit[32] & reg_re & !reg_error; // Read data return always_comb begin @@ -1380,6 +1424,14 @@ module cheshire_reg_top #( end addr_hit[30]: begin + reg_rdata_next[31:0] = llc_access_cnt_write_cache_qs; + end + + addr_hit[31]: begin + reg_rdata_next[31:0] = llc_access_cnt_read_cache_qs; + end + + addr_hit[32]: begin reg_rdata_next[7:0] = vga_params_red_width_qs; reg_rdata_next[15:8] = vga_params_green_width_qs; reg_rdata_next[23:16] = vga_params_blue_width_qs; @@ -1407,7 +1459,7 @@ endmodule module cheshire_reg_top_intf #( - parameter int AW = 7, + parameter int AW = 8, localparam int DW = 32 ) ( input logic clk_i, diff --git a/hw/regs/cheshire_regs.hjson b/hw/regs/cheshire_regs.hjson index fe83c978..1a194ac3 100644 --- a/hw/regs/cheshire_regs.hjson +++ b/hw/regs/cheshire_regs.hjson @@ -205,6 +205,28 @@ ] } + { name: "llc_access_cnt_write_cache" + desc: "Performance counter for LLC accesses on the write path" + swaccess: "ro" + hwaccess: "hwo" + hwqe: "true" + hwext: "true" + fields: [ + { bits: "31:0", name: "llc_access_cnt_write_cache", desc: "Performance counter for LLC accesses on the write path" } + ] + } + + { name: "llc_access_cnt_read_cache" + desc: "Performance counter for LLC accesses on the read path" + swaccess: "ro" + hwaccess: "hwo" + hwqe: "true" + hwext: "true" + fields: [ + { bits: "31:0", name: "llc_access_cnt_read_cache", desc: "Performance counter for LLC accesses on the read path" } + ] + } + { name: "vga_params" desc: "VGA hardware parameters" swaccess: "ro" diff --git a/sw/include/regs/cheshire.h b/sw/include/regs/cheshire.h index 3d1b2ac2..a8a13282 100644 --- a/sw/include/regs/cheshire.h +++ b/sw/include/regs/cheshire.h @@ -132,8 +132,14 @@ extern "C" { // Performance counter for LLC evictions on the read path #define CHESHIRE_LLC_EVICT_CNT_READ_REG_OFFSET 0x74 +// Performance counter for LLC accesses on the write path +#define CHESHIRE_LLC_ACCESS_CNT_WRITE_CACHE_REG_OFFSET 0x78 + +// Performance counter for LLC accesses on the read path +#define CHESHIRE_LLC_ACCESS_CNT_READ_CACHE_REG_OFFSET 0x7c + // VGA hardware parameters -#define CHESHIRE_VGA_PARAMS_REG_OFFSET 0x78 +#define CHESHIRE_VGA_PARAMS_REG_OFFSET 0x80 #define CHESHIRE_VGA_PARAMS_RED_WIDTH_MASK 0xff #define CHESHIRE_VGA_PARAMS_RED_WIDTH_OFFSET 0 #define CHESHIRE_VGA_PARAMS_RED_WIDTH_FIELD \