diff --git a/core/axi_shim.sv b/core/axi_shim.sv
index d306278427..128470d009 100644
--- a/core/axi_shim.sv
+++ b/core/axi_shim.sv
@@ -286,7 +286,7 @@ module axi_shim #(
   // Registers
   // ----------------
   `FFARNC(wr_state_q, wr_state_d, clear_i, IDLE, clk_i, rst_ni)
-  `FFARNC(wr_cnt_q  , wr_cnt_d  , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(wr_cnt_q, wr_cnt_d, clear_i, '0, clk_i, rst_ni)
 
   // ----------------
   // Assertions
diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv
index 4f1f7ada69..dde4375b31 100644
--- a/core/cache_subsystem/axi_adapter.sv
+++ b/core/cache_subsystem/axi_adapter.sv
@@ -463,14 +463,14 @@ module axi_adapter #(
   // ----------------
   // Registers
   // ----------------
-  `FFARNC(state_q              , state_d             , 1'b0, IDLE                , clk_i, rst_ni)
-  `FFARNC(cnt_q                , cnt_d               , 1'b0, '0                  , clk_i, rst_ni)
-  `FFARNC(cache_line_q         , cache_line_d        , 1'b0, '0                  , clk_i, rst_ni)
-  `FFARNC(addr_offset_q        , addr_offset_d       , 1'b0, '0                  , clk_i, rst_ni)
-  `FFARNC(id_q                 , id_d                , 1'b0, '0                  , clk_i, rst_ni)
-  `FFARNC(amo_q                , amo_d               , 1'b0, ariane_pkg::AMO_NONE, clk_i, rst_ni)
-  `FFARNC(size_q               , size_d              , 1'b0, '0                  , clk_i, rst_ni)
-  `FFARNC(outstanding_aw_cnt_q , outstanding_aw_cnt_d, 1'b0, '0                  , clk_i, rst_ni)
+  `FFARNC(state_q, state_d, 1'b0, IDLE, clk_i, rst_ni)
+  `FFARNC(cnt_q, cnt_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(cache_line_q, cache_line_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(addr_offset_q, addr_offset_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(id_q, id_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(amo_q, amo_d, 1'b0, ariane_pkg::AMO_NONE, clk_i, rst_ni)
+  `FFARNC(size_q, size_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(outstanding_aw_cnt_q, outstanding_aw_cnt_d, 1'b0, '0, clk_i, rst_ni)
 
   function automatic axi_pkg::atop_t atop_from_amo(ariane_pkg::amo_t amo);
     axi_pkg::atop_t result = 6'b000000;
diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv
index 0f2a713e62..0e88262c9a 100644
--- a/core/cache_subsystem/cache_ctrl.sv
+++ b/core/cache_subsystem/cache_ctrl.sv
@@ -444,9 +444,9 @@ module cache_ctrl
   // --------------
   // Registers
   // --------------
-  `FFARNC(state_q   , state_d  , clear_i, IDLE, clk_i, rst_ni)
-  `FFARNC(mem_req_q , mem_req_d, clear_i, '0, clk_i, rst_ni)
-  `FFARNC(hit_way_q , hit_way_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(state_q, state_d, clear_i, IDLE, clk_i, rst_ni)
+  `FFARNC(mem_req_q, mem_req_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(hit_way_q, hit_way_d, clear_i, '0, clk_i, rst_ni)
 
   //pragma translate_off
 `ifndef VERILATOR
diff --git a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv
index 4acc7bc7fa..ac9a613314 100644
--- a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv
+++ b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv
@@ -111,7 +111,7 @@ module cva6_hpdcache_if_adapter
       logic             [ 7:0] amo_data_be;
       hpdcache_req_op_t        amo_op;
       logic             [31:0] amo_resp_word;
-      logic                    amo_pending_q, amo_pending_n;
+      logic amo_pending_q, amo_pending_n;
 
       //  AMO logic
       //  {{{
diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv
index f8efd70ffe..8772ea65ca 100644
--- a/core/cache_subsystem/miss_handler.sv
+++ b/core/cache_subsystem/miss_handler.sv
@@ -507,12 +507,12 @@ module miss_handler
   // --------------------
   // Sequential Process
   // --------------------
-  `FFARNC(mshr_q      , mshr_d     , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(state_q     , state_d    , 1'b0, INIT, clk_i, rst_ni)
-  `FFARNC(cnt_q       , cnt_d      , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(evict_way_q , evict_way_d, 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(evict_cl_q  , evict_cl_d , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(serve_amo_q , serve_amo_d, 1'b0, '0  , clk_i, rst_ni)
+  `FFARNC(mshr_q, mshr_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(state_q, state_d, 1'b0, INIT, clk_i, rst_ni)
+  `FFARNC(cnt_q, cnt_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(evict_way_q, evict_way_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(evict_cl_q, evict_cl_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(serve_amo_q, serve_amo_d, 1'b0, '0, clk_i, rst_ni)
 
   //pragma translate_off
 `ifndef VERILATOR
@@ -789,10 +789,10 @@ module axi_adapter_arbiter #(
     endcase
   end
 
-  `FFARNC(state_q           , state_d          , 1'b0, IDLE, clk_i, rst_ni)
-  `FFARNC(sel_q             , sel_d            , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(req_q             , req_d            , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(outstanding_cnt_q , outstanding_cnt_d, 1'b0, '0  , clk_i, rst_ni)
+  `FFARNC(state_q, state_d, 1'b0, IDLE, clk_i, rst_ni)
+  `FFARNC(sel_q, sel_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(req_q, req_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(outstanding_cnt_q, outstanding_cnt_d, 1'b0, '0, clk_i, rst_ni)
 
   // ------------
   // Assertions
diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv
index 39c7a914d7..8d22124bc4 100644
--- a/core/cache_subsystem/wt_axi_adapter.sv
+++ b/core/cache_subsystem/wt_axi_adapter.sv
@@ -61,6 +61,7 @@ module wt_axi_adapter
   localparam MaxNumWords = $clog2(CVA6Cfg.AxiDataWidth / 8);
   localparam AxiRdBlenIcache = ariane_pkg::ICACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
   localparam AxiRdBlenDcache = ariane_pkg::DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
+  localparam DcacheReturnTypeRstVal = wt_cache_pkg::DCACHE_LOAD_ACK;
 
   ///////////////////////////////////////////////////////
   // request path
@@ -621,20 +622,20 @@ module wt_axi_adapter
   // assign dcache_rtrn_o.inv.vld  = '0;
   // assign dcache_rtrn_o.inv.all  = '0;
 
-  `FFARNC(icache_first_q         , icache_first_d        , clear_i, 1'b1                         , clk_i, rst_ni)
-  `FFARNC(dcache_first_q         , dcache_first_d        , clear_i, 1'b1                         , clk_i, rst_ni)
-  `FFARNC(icache_rd_shift_q      , icache_rd_shift_d     , clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(icache_rd_shift_user_q , icache_rd_shift_user_d, clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(dcache_rd_shift_q      , dcache_rd_shift_d     , clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(dcache_rd_shift_user_q , dcache_rd_shift_user_d, clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(icache_rtrn_vld_q      , icache_rtrn_vld_d     , clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(dcache_rtrn_vld_q      , dcache_rtrn_vld_d     , clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(icache_rtrn_tid_q      , icache_rtrn_tid_d     , clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(dcache_rtrn_tid_q      , dcache_rtrn_tid_d     , clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(dcache_rtrn_type_q     , dcache_rtrn_type_d    , clear_i, wt_cache_pkg::DCACHE_LOAD_ACK, clk_i, rst_ni)
-  `FFARNC(dcache_rtrn_inv_q      , dcache_rtrn_inv_d     , clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(amo_off_q              , amo_off_d             , clear_i, '0                           , clk_i, rst_ni)
-  `FFARNC(amo_gen_r_q            , amo_gen_r_d           , clear_i, '0                           , clk_i, rst_ni)
+  `FFARNC(icache_first_q, icache_first_d, clear_i, 1'b1, clk_i, rst_ni)
+  `FFARNC(dcache_first_q, dcache_first_d, clear_i, 1'b1, clk_i, rst_ni)
+  `FFARNC(icache_rd_shift_q, icache_rd_shift_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(icache_rd_shift_user_q, icache_rd_shift_user_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dcache_rd_shift_q, dcache_rd_shift_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dcache_rd_shift_user_q, dcache_rd_shift_user_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(icache_rtrn_vld_q, icache_rtrn_vld_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dcache_rtrn_vld_q, dcache_rtrn_vld_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(icache_rtrn_tid_q, icache_rtrn_tid_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dcache_rtrn_tid_q, dcache_rtrn_tid_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dcache_rtrn_type_q, dcache_rtrn_type_d, clear_i, DcacheReturnTypeRstVal, clk_i, rst_ni)
+  `FFARNC(dcache_rtrn_inv_q, dcache_rtrn_inv_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(amo_off_q, amo_off_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(amo_gen_r_q, amo_gen_r_d, clear_i, '0, clk_i, rst_ni)
 
 
   ///////////////////////////////////////////////////////
diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv
index 8bf34ff57e..e0ee9cd02a 100644
--- a/core/cache_subsystem/wt_dcache.sv
+++ b/core/cache_subsystem/wt_dcache.sv
@@ -24,9 +24,8 @@ module wt_dcache
     parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1
 ) (
     input logic clk_i,  // Clock
-    input logic rst_ni, // Asynchronous reset active low
-    input logic clear_i, // Synchronous clear active high
-
+    input logic rst_ni,  // Asynchronous reset active low
+    input logic clear_i,  // Synchronous clear active high
     // Cache management
     input logic enable_i,  // from CSR
     input logic flush_i,  // high until acknowledged
diff --git a/core/cache_subsystem/wt_dcache_mem.sv b/core/cache_subsystem/wt_dcache_mem.sv
index 40479e9191..8810c54b0e 100644
--- a/core/cache_subsystem/wt_dcache_mem.sv
+++ b/core/cache_subsystem/wt_dcache_mem.sv
@@ -342,10 +342,10 @@ module wt_dcache_mem
     );
   end
 
-  `FFARNC(bank_idx_q , bank_idx_d, 1'b0, '0, clk_i, rst_ni)
-  `FFARNC(bank_off_q , bank_off_d, 1'b0, '0, clk_i, rst_ni)
-  `FFARNC(vld_sel_q  , vld_sel_d , 1'b0, '0, clk_i, rst_ni)
-  `FFARNC(cmp_en_q   , cmp_en_d  , 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(bank_idx_q, bank_idx_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(bank_off_q, bank_off_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(vld_sel_q, vld_sel_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(cmp_en_q, cmp_en_d, 1'b0, '0, clk_i, rst_ni)
 
   ///////////////////////////////////////////////////////
   // assertions
@@ -395,8 +395,8 @@ module wt_dcache_mem
   logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] load_enable;
   for (genvar i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin : gen_p_mirror_registers
     assign load_enable[i] = (vld_req[i] & vld_we) ? 1'b1 : 1'b0;
-    `FFLARNC(vld_mirror[vld_addr][i], vld_wdata[i], load_enable[i], clear_i, '{default: '0}, clk_i, rst_ni)
-    `FFLARNC(tag_mirror[vld_addr][i], wr_cl_tag_i, load_enable[i], clear_i, '{default: '0}, clk_i, rst_ni)
+    `FFLARNC(vld_mirror[vld_addr][i], vld_wdata[i], load_enable[i], clear_i, '0, clk_i, rst_ni)
+    `FFLARNC(tag_mirror[vld_addr][i], wr_cl_tag_i, load_enable[i], clear_i, '0, clk_i, rst_ni)
   end
 
   for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin : gen_tag_dubl_test
diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv
index 3c982fdb36..08c4b61702 100644
--- a/core/cache_subsystem/wt_dcache_wbuffer.sv
+++ b/core/cache_subsystem/wt_dcache_wbuffer.sv
@@ -57,9 +57,8 @@ module wt_dcache_wbuffer
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
 ) (
     input logic clk_i,  // Clock
-    input logic rst_ni, // Asynchronous reset active low
-    input logic clear_i, // Synchronous clear active high
-
+    input logic rst_ni,  // Asynchronous reset active low
+    input logic clear_i,  // Synchronous clear active high
     input logic cache_en_i,  // writes are treated as NC if disabled
     output logic empty_o,  // asserted if no data is present in write buffer
     output logic not_ni_o,  // asserted if no ni data is present in write buffer
diff --git a/core/cvxif_fu.sv b/core/cvxif_fu.sv
index 30721793fd..2ce49a8ef1 100644
--- a/core/cvxif_fu.sv
+++ b/core/cvxif_fu.sv
@@ -117,8 +117,8 @@ module cvxif_fu
     end
   end
 
-  `FFARNC(illegal_q      , illegal_n      , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(illegal_id_q   , illegal_id_n   , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(illegal_q, illegal_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(illegal_id_q, illegal_id_n, clear_i, '0, clk_i, rst_ni)
   `FFARNC(illegal_instr_q, illegal_instr_n, clear_i, '0, clk_i, rst_ni)
 
 endmodule
diff --git a/core/ex_stage.sv b/core/ex_stage.sv
index d0009c6a7e..5a33a8e4fa 100644
--- a/core/ex_stage.sv
+++ b/core/ex_stage.sv
@@ -259,6 +259,11 @@ module ex_stage
   logic [TRANS_ID_BITS-1:0] mult_trans_id;
   logic mult_valid;
 
+  // for reset values in flip flops
+  logic [ASID_WIDTH-1:0] asid_rs2_forwarding;
+  logic [VMID_WIDTH-1:0] vmid_rs2_forwarding;
+  logic [riscv::GPLEN-1:0] gpaddr_flush;
+
   // 1. ALU (combinatorial)
   // data silence operation
   fu_data_t alu_data;
@@ -348,7 +353,7 @@ module ex_stage
   ) i_mult (
       .clk_i,
       .rst_ni,
-      .clear_i(clear_i),
+      .clear_i,
       .flush_i,
       .mult_valid_i,
       .fu_data_i      (mult_data),
@@ -510,26 +515,30 @@ module ex_stage
 
   if (CVA6Cfg.RVS) begin
     if (CVA6Cfg.RVH) begin
-      `FFLARNC(current_instruction_is_sfence_vma , 1'b1, load_enable[0], clear_i, 1'b0, clk_i, rst_ni)
-      `FFLARNC(current_instruction_is_hfence_vvma, 1'b1, load_enable[1], clear_i, 1'b0, clk_i, rst_ni)
-      `FFLARNC(current_instruction_is_hfence_gvma, 1'b1, load_enable[2], clear_i, 1'b0, clk_i, rst_ni)
+      `FFLARNC(current_instruction_is_sfence_vma, '1, load_enable[0], clear_i, '0, clk_i, rst_ni)
+      `FFLARNC(current_instruction_is_hfence_vvma, '1, load_enable[1], clear_i, '0, clk_i, rst_ni)
+      `FFLARNC(current_instruction_is_hfence_gvma, '1, load_enable[2], clear_i, '0, clk_i, rst_ni)
     end else begin
       assign current_instruction_is_hfence_vvma = 1'b0;
       assign current_instruction_is_hfence_gvma = 1'b0;
-      `FFLARNC(current_instruction_is_sfence_vma, 1'b1, load_enable[3], clear_i, 1'b0, clk_i, rst_ni)
+      `FFLARNC(current_instruction_is_sfence_vma, '1, load_enable[3], clear_i, '0, clk_i, rst_ni)
     end
     if (CVA6Cfg.RVH) begin
+      assign asid_rs2_forwarding = rs2_forwarding_i[ASID_WIDTH-1:0];
+      assign vmid_rs2_forwarding = rs2_forwarding_i[VMID_WIDTH-1:0];
+      assign gpaddr_flush = rs1_forwarding_i >> 2;
       // This process stores the rs1 and rs2 parameters of a SFENCE_VMA instruction.
-      `FFLARNC(vaddr_to_be_flushed , rs1_forwarding_i                , load_enable[4], clear_i, '0, clk_i, rst_ni)
-      `FFLARNC(gpaddr_to_be_flushed, rs1_forwarding_i >> 2           , load_enable[4], clear_i, '0, clk_i, rst_ni)
-      `FFLARNC(asid_to_be_flushed  , rs2_forwarding_i[ASID_WIDTH-1:0], load_enable[4], clear_i, '0, clk_i, rst_ni)
-      `FFLARNC(vmid_to_be_flushed  , rs2_forwarding_i[VMID_WIDTH-1:0], load_enable[4], clear_i, '0, clk_i, rst_ni)
+      `FFLARNC(vaddr_to_be_flushed, rs1_forwarding_i, load_enable[4], clear_i, '0, clk_i, rst_ni)
+      `FFLARNC(gpaddr_to_be_flushed, gpaddr_flush, load_enable[4], clear_i, '0, clk_i, rst_ni)
+      `FFLARNC(asid_to_be_flushed, asid_rs2_forwarding, load_enable[4], clear_i, '0, clk_i, rst_ni)
+      `FFLARNC(vmid_to_be_flushed, vmid_rs2_forwarding, load_enable[4], clear_i, '0, clk_i, rst_ni)
     end else begin
       assign vmid_to_be_flushed   = '0;
       assign gpaddr_to_be_flushed = '0;
+      assign asid_rs2_forwarding = rs2_forwarding_i[ASID_WIDTH-1:0];
       // This process stores the rs1 and rs2 parameters of a SFENCE_VMA instruction.
-      `FFLARNC(vaddr_to_be_flushed, rs1_forwarding_i                , load_enable[5], clear_i, '0, clk_i, rst_ni)
-      `FFLARNC(asid_to_be_flushed , rs2_forwarding_i[ASID_WIDTH-1:0], load_enable[5], clear_i, '0, clk_i, rst_ni)
+      `FFLARNC(vaddr_to_be_flushed, rs1_forwarding_i, load_enable[5], clear_i, '0, clk_i, rst_ni)
+      `FFLARNC(asid_to_be_flushed, asid_rs2_forwarding, load_enable[5], clear_i, '0, clk_i, rst_ni)
     end
   end else begin
     assign current_instruction_is_sfence_vma  = 1'b0;
diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv
index 12a9c08c42..0d6ff85a69 100644
--- a/core/frontend/frontend.sv
+++ b/core/frontend/frontend.sv
@@ -461,7 +461,7 @@ module frontend
     ) i_ras (
         .clk_i,
         .rst_ni,
-        .clear_i (clear_i),
+        .clear_i,
         .flush_i(flush_bp_i),
         .push_i (ras_push),
         .pop_i  (ras_pop),
diff --git a/core/issue_stage.sv b/core/issue_stage.sv
index 4317b19d0e..43bda3e00c 100644
--- a/core/issue_stage.sv
+++ b/core/issue_stage.sv
@@ -166,7 +166,6 @@ module issue_stage
       .CVA6Cfg  (CVA6Cfg),
       .rs3_len_t(rs3_len_t)
   ) i_scoreboard (
-      .clear_i(clear_i),
       .rst_ni(rst_uarch_ni),
 
       .sb_full_o          (sb_full_o),
diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv
index adc34fb4af..b9252beb75 100644
--- a/core/load_store_unit.sv
+++ b/core/load_store_unit.sv
@@ -331,9 +331,9 @@ module load_store_unit
     assign dtlb_ppn                            = mmu_vaddr_plen[riscv::PLEN-1:12];
     assign dtlb_hit                            = 1'b1;
 
-    `FFARNC(mmu_paddr        , mmu_vaddr_plen      , clear_i, '0, clk_i, rst_ni)
-    `FFARNC(translation_valid, translation_req     , clear_i, '0, clk_i, rst_ni)
-    `FFARNC(mmu_exception    , misaligned_exception, clear_i, '0, clk_i, rst_ni)
+    `FFARNC(mmu_paddr, mmu_vaddr_plen, clear_i, '0, clk_i, rst_ni)
+    `FFARNC(translation_valid, translation_req, clear_i, '0, clk_i, rst_ni)
+    `FFARNC(mmu_exception, misaligned_exception, clear_i, '0, clk_i, rst_ni)
   end
 
 
diff --git a/core/lsu_bypass.sv b/core/lsu_bypass.sv
index dc5fc19604..22749893b9 100644
--- a/core/lsu_bypass.sv
+++ b/core/lsu_bypass.sv
@@ -117,9 +117,9 @@ module lsu_bypass
   end
 
   // registers
-  `FFARNC(mem_q           , mem_n          , 1'b0, '0, clk_i, rst_ni)
-  `FFARNC(status_cnt_q    , status_cnt_n   , 1'b0, '0, clk_i, rst_ni)
-  `FFARNC(write_pointer_q , write_pointer_n, 1'b0, '0, clk_i, rst_ni)
-  `FFARNC(read_pointer_q  , read_pointer_n , 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(mem_q, mem_n, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(status_cnt_q, status_cnt_n, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(write_pointer_q, write_pointer_n, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(read_pointer_q, read_pointer_n, 1'b0, '0, clk_i, rst_ni)
 endmodule
 
diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv
index 9495cae743..2415fb84da 100644
--- a/core/mmu_sv32/cva6_mmu_sv32.sv
+++ b/core/mmu_sv32/cva6_mmu_sv32.sv
@@ -122,7 +122,7 @@ module cva6_mmu_sv32
   ) i_itlb (
       .clk_i  (clk_i),
       .rst_ni (rst_ni),
-      .clear_i (clear_i),
+      .clear_i(clear_i),
       .flush_i(flush_tlb_i),
 
       .update_i(update_itlb),
@@ -571,11 +571,11 @@ module cva6_mmu_sv32
   // ----------
   // Registers
   // ----------
-  `FFARNC(lsu_vaddr_q     ,lsu_vaddr_n    , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(lsu_req_q       ,lsu_req_n      , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(misaligned_ex_q ,misaligned_ex_n, clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_pte_q      ,dtlb_pte_n     , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_hit_q      ,dtlb_hit_n     , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(lsu_is_store_q  ,lsu_is_store_n , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_is_4M_q    ,dtlb_is_4M_n   , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_vaddr_q, lsu_vaddr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_req_q, lsu_req_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(misaligned_ex_q, misaligned_ex_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_pte_q, dtlb_pte_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_hit_q, dtlb_hit_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_is_store_q, lsu_is_store_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_is_4M_q, dtlb_is_4M_n, clear_i, '0, clk_i, rst_ni)
 endmodule
diff --git a/core/mmu_sv32/cva6_ptw_sv32.sv b/core/mmu_sv32/cva6_ptw_sv32.sv
index bc541c4398..32b4f292f8 100644
--- a/core/mmu_sv32/cva6_ptw_sv32.sv
+++ b/core/mmu_sv32/cva6_ptw_sv32.sv
@@ -373,16 +373,16 @@ module cva6_ptw_sv32
   end
 
   // sequential process
-  `FFARNC(state_q           , state_d               , clear_i, IDLE, clk_i, rst_ni)
-  `FFARNC(ptw_pptr_q        , ptw_pptr_n            , clear_i, '0  , clk_i, rst_ni)
-  `FFARNC(is_instr_ptw_q    , is_instr_ptw_n        , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(ptw_lvl_q         , ptw_lvl_n             , clear_i, LVL1, clk_i, rst_ni)
-  `FFARNC(tag_valid_q       , tag_valid_n           , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(tlb_update_asid_q , tlb_update_asid_n     , clear_i, '0  , clk_i, rst_ni)
-  `FFARNC(vaddr_q           , vaddr_n               , clear_i, '0  , clk_i, rst_ni)
-  `FFARNC(global_mapping_q  , global_mapping_n      , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(data_rdata_q      , req_port_i.data_rdata , clear_i, '0  , clk_i, rst_ni)
-  `FFARNC(data_rvalid_q     , req_port_i.data_rvalid, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(state_q, state_d, clear_i, IDLE, clk_i, rst_ni)
+  `FFARNC(ptw_pptr_q, ptw_pptr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(is_instr_ptw_q, is_instr_ptw_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(ptw_lvl_q, ptw_lvl_n, clear_i, LVL1, clk_i, rst_ni)
+  `FFARNC(tag_valid_q, tag_valid_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(tlb_update_asid_q, tlb_update_asid_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(vaddr_q, vaddr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(global_mapping_q, global_mapping_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(data_rdata_q, req_port_i.data_rdata, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(data_rvalid_q, req_port_i.data_rvalid, clear_i, 1'b0, clk_i, rst_ni)
 
 endmodule
 /* verilator lint_on WIDTH */
diff --git a/core/mmu_sv32/cva6_shared_tlb_sv32.sv b/core/mmu_sv32/cva6_shared_tlb_sv32.sv
index 1fbaf30cff..076fd6fe2e 100644
--- a/core/mmu_sv32/cva6_shared_tlb_sv32.sv
+++ b/core/mmu_sv32/cva6_shared_tlb_sv32.sv
@@ -27,9 +27,9 @@ module cva6_shared_tlb_sv32
     parameter int SHARED_TLB_WAYS = 2,
     parameter int ASID_WIDTH = 1
 ) (
-    input logic clk_i,   // Clock
+    input logic clk_i,  // Clock
     input logic rst_ni,  // Asynchronous reset active low
-    input logic clear_i,
+    input logic clear_i,  // Synchronous clear active high
     input logic flush_i,
 
     input logic enable_translation_i,   // CSRs indicate to enable SV32
@@ -232,17 +232,17 @@ module cva6_shared_tlb_sv32
   end  //tag_comparison
 
   // sequential process
-  `FFARNC(itlb_vpn_q          , itlb_vaddr_i[riscv::SV-1:12]   , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_vpn_q          , dtlb_vaddr_i[riscv::SV-1:12]   , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(tlb_update_asid_q   , tlb_update_asid_d              , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(shared_tlb_access_q , shared_tlb_access_d            , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(shared_tlb_vaddr_q  , shared_tlb_vaddr_d             , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(shared_tag_valid_q  , shared_tag_valid_d             , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(vpn0_q              , vpn0_d                         , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(vpn1_q              , vpn1_d                         , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(itlb_req_q          , itlb_req_d                     , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_req_q          , dtlb_req_d                     , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(shared_tag_valid    , shared_tag_valid_q[tag_rd_addr], clear_i, '0, clk_i, rst_ni)
+  `FFARNC(itlb_vpn_q, itlb_vaddr_i[riscv::SV-1:12], clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_vpn_q, dtlb_vaddr_i[riscv::SV-1:12], clear_i, '0, clk_i, rst_ni)
+  `FFARNC(tlb_update_asid_q, tlb_update_asid_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(shared_tlb_access_q, shared_tlb_access_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(shared_tlb_vaddr_q, shared_tlb_vaddr_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(shared_tag_valid_q, shared_tag_valid_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(vpn0_q, vpn0_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(vpn1_q, vpn1_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(itlb_req_q, itlb_req_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_req_q, dtlb_req_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(shared_tag_valid, shared_tag_valid_q[tag_rd_addr], clear_i, '0, clk_i, rst_ni)
 
   // ------------------
   // Update and Flush
diff --git a/core/mmu_sv32/cva6_tlb_sv32.sv b/core/mmu_sv32/cva6_tlb_sv32.sv
index 9d2491d434..8bb10ba05b 100644
--- a/core/mmu_sv32/cva6_tlb_sv32.sv
+++ b/core/mmu_sv32/cva6_tlb_sv32.sv
@@ -227,11 +227,11 @@ module cva6_tlb_sv32
   end
 
   // sequential process
-  `FFARNC(tags_q      ,tags_n     , clear_i, '{defautl: 0}, clk_i, rst_ni)
-  `FFARNC(content_q   ,content_n  , clear_i, '{defautl: 0}, clk_i, rst_ni)
-  `FFARNC(plru_tree_q ,plru_tree_n, clear_i, '{defautl: 0}, clk_i, rst_ni)
+  `FFARNC(tags_q, tags_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(content_q, content_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(plru_tree_q, plru_tree_n, clear_i, '0, clk_i, rst_ni)
 
- //--------------
+  //--------------
   // Sanity checks
   //--------------
 
diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv
index 2bd281aeb1..eb410cd29a 100644
--- a/core/mmu_sv39/mmu.sv
+++ b/core/mmu_sv39/mmu.sv
@@ -106,7 +106,7 @@ module mmu
   ) i_itlb (
       .clk_i  (clk_i),
       .rst_ni (rst_ni),
-      .clear_i (clear_i),
+      .clear_i(clear_i),
       .flush_i(flush_tlb_i),
 
       .update_i(update_ptw_itlb),
@@ -515,12 +515,12 @@ module mmu
   // ----------
   // Registers
   // ----------
-  `FFARNC(lsu_vaddr_q    , lsu_vaddr_n    , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(lsu_req_q      , lsu_req_n      , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_vaddr_q, lsu_vaddr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_req_q, lsu_req_n, clear_i, '0, clk_i, rst_ni)
   `FFARNC(misaligned_ex_q, misaligned_ex_n, clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_pte_q     , dtlb_pte_n     , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_hit_q     , dtlb_hit_n     , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(lsu_is_store_q , lsu_is_store_n , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_is_2M_q   , dtlb_is_2M_n   , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_is_1G_q   , dtlb_is_1G_n   , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_pte_q, dtlb_pte_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_hit_q, dtlb_hit_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_is_store_q, lsu_is_store_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_is_2M_q, dtlb_is_2M_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_is_1G_q, dtlb_is_1G_n, clear_i, '0, clk_i, rst_ni)
 endmodule
diff --git a/core/mmu_sv39/ptw.sv b/core/mmu_sv39/ptw.sv
index 09e4aefcad..1d290eed76 100644
--- a/core/mmu_sv39/ptw.sv
+++ b/core/mmu_sv39/ptw.sv
@@ -382,16 +382,16 @@ module ptw
   end
 
   // sequential process
-  `FFARNC(state_q          , state_d               , clear_i, IDLE, clk_i, rst_ni)
-  `FFARNC(ptw_pptr_q       , ptw_pptr_n            , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(is_instr_ptw_q   , is_instr_ptw_n        , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(ptw_lvl_q        , ptw_lvl_n             , clear_i, LVL1, clk_i, rst_ni)
-  `FFARNC(tag_valid_q      , tag_valid_n           , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(tlb_update_asid_q, tlb_update_asid_n     , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(vaddr_q          , vaddr_n               , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(global_mapping_q , global_mapping_n      , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(data_rdata_q     , req_port_i.data_rdata , clear_i, 1'b0, clk_i, rst_ni)
-  `FFARNC(data_rvalid_q    , req_port_i.data_rvalid, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(state_q, state_d, clear_i, IDLE, clk_i, rst_ni)
+  `FFARNC(ptw_pptr_q, ptw_pptr_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(is_instr_ptw_q, is_instr_ptw_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(ptw_lvl_q, ptw_lvl_n, clear_i, LVL1, clk_i, rst_ni)
+  `FFARNC(tag_valid_q, tag_valid_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(tlb_update_asid_q, tlb_update_asid_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(vaddr_q, vaddr_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(global_mapping_q, global_mapping_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(data_rdata_q, req_port_i.data_rdata, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(data_rvalid_q, req_port_i.data_rvalid, clear_i, 1'b0, clk_i, rst_ni)
 
 endmodule
 /* verilator lint_on WIDTH */
diff --git a/core/mmu_sv39/tlb.sv b/core/mmu_sv39/tlb.sv
index 802852c994..cb4d130aaa 100644
--- a/core/mmu_sv39/tlb.sv
+++ b/core/mmu_sv39/tlb.sv
@@ -235,8 +235,8 @@ module tlb
   end
 
   // sequential process
-  `FFARNC(tags_q     , tags_n     , clear_i, '{default: 0}, clk_i, rst_ni)
-  `FFARNC(content_q  , content_n  , clear_i, '{default: 0}, clk_i, rst_ni)
+  `FFARNC(tags_q, tags_n, clear_i, '{default: 0}, clk_i, rst_ni)
+  `FFARNC(content_q, content_n, clear_i, '{default: 0}, clk_i, rst_ni)
   `FFARNC(plru_tree_q, plru_tree_n, clear_i, '{default: 0}, clk_i, rst_ni)
   //--------------
   // Sanity checks
diff --git a/core/mmu_sv39x4/cva6_mmu_sv39x4.sv b/core/mmu_sv39x4/cva6_mmu_sv39x4.sv
index e67e251b05..19eabe6c6c 100644
--- a/core/mmu_sv39x4/cva6_mmu_sv39x4.sv
+++ b/core/mmu_sv39x4/cva6_mmu_sv39x4.sv
@@ -687,16 +687,16 @@ module cva6_mmu_sv39x4
   // ----------
   // Registers
   // ----------
-  `FFARNC(lsu_vaddr_q     ,lsu_vaddr_n    , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(lsu_gpaddr_q    ,lsu_gpaddr_n   , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(lsu_tinst_q     ,lsu_tinst_n    , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(hs_ld_st_inst_q ,hs_ld_st_inst_n, clear_i, '0, clk_i, rst_ni)
-  `FFARNC(lsu_req_q       ,lsu_req_n      , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(misaligned_ex_q ,misaligned_ex_n, clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_pte_q      ,dtlb_pte_n     , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_gpte_q     ,dtlb_gpte_n    , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_hit_q      ,dtlb_hit_n     , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(lsu_is_store_q  ,lsu_is_store_n , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_is_2M_q    ,dtlb_is_2M_n   , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(dtlb_is_1G_q    ,dtlb_is_1G_n   , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_vaddr_q, lsu_vaddr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_gpaddr_q, lsu_gpaddr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_tinst_q, lsu_tinst_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(hs_ld_st_inst_q, hs_ld_st_inst_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_req_q, lsu_req_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(misaligned_ex_q, misaligned_ex_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_pte_q, dtlb_pte_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_gpte_q, dtlb_gpte_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_hit_q, dtlb_hit_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(lsu_is_store_q, lsu_is_store_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_is_2M_q, dtlb_is_2M_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(dtlb_is_1G_q, dtlb_is_1G_n, clear_i, '0, clk_i, rst_ni)
 endmodule
diff --git a/core/mmu_sv39x4/cva6_ptw_sv39x4.sv b/core/mmu_sv39x4/cva6_ptw_sv39x4.sv
index 9a4de9a2e6..8662106649 100644
--- a/core/mmu_sv39x4/cva6_ptw_sv39x4.sv
+++ b/core/mmu_sv39x4/cva6_ptw_sv39x4.sv
@@ -599,22 +599,22 @@ module cva6_ptw_sv39x4
   end
 
   // sequential process
-  `FFARNC(state_q           , state_d               , clear_i, IDLE   , clk_i, rst_ni)
-  `FFARNC(ptw_stage_q       , ptw_stage_d           , clear_i, S_STAGE, clk_i, rst_ni)
-  `FFARNC(is_instr_ptw_q    , is_instr_ptw_n        , clear_i, 1'b0   , clk_i, rst_ni)
-  `FFARNC(ptw_lvl_q         , ptw_lvl_n             , clear_i, LVL1   , clk_i, rst_ni)
-  `FFARNC(gptw_lvl_q        , gptw_lvl_n            , clear_i, LVL1   , clk_i, rst_ni)
-  `FFARNC(tag_valid_q       , tag_valid_n           , clear_i, 1'b0   , clk_i, rst_ni)
-  `FFARNC(tlb_update_asid_q , tlb_update_asid_n     , clear_i, '0     , clk_i, rst_ni)
-  `FFARNC(tlb_update_vmid_q , tlb_update_vmid_n     , clear_i, '0     , clk_i, rst_ni)
-  `FFARNC(vaddr_q           , vaddr_n               , clear_i, '0     , clk_i, rst_ni)
-  `FFARNC(gpaddr_q          , gpaddr_n              , clear_i, '0     , clk_i, rst_ni)
-  `FFARNC(ptw_pptr_q        , ptw_pptr_n            , clear_i, '0     , clk_i, rst_ni)
-  `FFARNC(gptw_pptr_q       , gptw_pptr_n           , clear_i, '0     , clk_i, rst_ni)
-  `FFARNC(global_mapping_q  , global_mapping_n      , clear_i, 1'b0   , clk_i, rst_ni)
-  `FFARNC(data_rdata_q      , req_port_i.data_rdata , clear_i, '0     , clk_i, rst_ni)
-  `FFARNC(gpte_q            , gpte_d                , clear_i, '0     , clk_i, rst_ni)
-  `FFARNC(data_rvalid_q     , req_port_i.data_rvalid, clear_i, 1'b0   , clk_i, rst_ni)
+  `FFARNC(state_q, state_d, clear_i, IDLE, clk_i, rst_ni)
+  `FFARNC(ptw_stage_q, ptw_stage_d, clear_i, S_STAGE, clk_i, rst_ni)
+  `FFARNC(is_instr_ptw_q, is_instr_ptw_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(ptw_lvl_q, ptw_lvl_n, clear_i, LVL1, clk_i, rst_ni)
+  `FFARNC(gptw_lvl_q, gptw_lvl_n, clear_i, LVL1, clk_i, rst_ni)
+  `FFARNC(tag_valid_q, tag_valid_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(tlb_update_asid_q, tlb_update_asid_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(tlb_update_vmid_q, tlb_update_vmid_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(vaddr_q, vaddr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(gpaddr_q, gpaddr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(ptw_pptr_q, ptw_pptr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(gptw_pptr_q, gptw_pptr_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(global_mapping_q, global_mapping_n, clear_i, 1'b0, clk_i, rst_ni)
+  `FFARNC(data_rdata_q, req_port_i.data_rdata, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(gpte_q, gpte_d, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(data_rvalid_q, req_port_i.data_rvalid, clear_i, 1'b0, clk_i, rst_ni)
 
 endmodule
 /* verilator lint_on WIDTH */
diff --git a/core/mmu_sv39x4/cva6_tlb_sv39x4.sv b/core/mmu_sv39x4/cva6_tlb_sv39x4.sv
index 3362673cce..c12a5104ee 100644
--- a/core/mmu_sv39x4/cva6_tlb_sv39x4.sv
+++ b/core/mmu_sv39x4/cva6_tlb_sv39x4.sv
@@ -359,8 +359,8 @@ module cva6_tlb_sv39x4
   end
 
   // sequential process
-  `FFARNC(tags_q     , tags_n     , clear_i, '{default: 0}, clk_i, rst_ni)
-  `FFARNC(content_q  , content_n  , clear_i, '{default: 0}, clk_i, rst_ni)
+  `FFARNC(tags_q, tags_n, clear_i, '{default: 0}, clk_i, rst_ni)
+  `FFARNC(content_q, content_n, clear_i, '{default: 0}, clk_i, rst_ni)
   `FFARNC(plru_tree_q, plru_tree_n, clear_i, '{default: 0}, clk_i, rst_ni)
 
   //--------------
diff --git a/core/perf_counters.sv b/core/perf_counters.sv
index befa83b4f9..a9fc5c539a 100644
--- a/core/perf_counters.sv
+++ b/core/perf_counters.sv
@@ -235,6 +235,6 @@ module perf_counters
 
   //Registers
   `FFARNC(generic_counter_q, generic_counter_d, clear_i, '{default: 0}, clk_i, rst_ni)
-  `FFARNC(mhpmevent_q      , mhpmevent_d      , clear_i, '{default: 0}, clk_i, rst_ni)
+  `FFARNC(mhpmevent_q, mhpmevent_d, clear_i, '{default: 0}, clk_i, rst_ni)
 
 endmodule
diff --git a/core/scoreboard.sv b/core/scoreboard.sv
index 5b44acc9ec..3ce3310b63 100644
--- a/core/scoreboard.sv
+++ b/core/scoreboard.sv
@@ -433,9 +433,9 @@ module scoreboard #(
 
 
   // sequential process
-  `FFARNC(issue_cnt_q     , issue_cnt_n     , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(issue_pointer_q , issue_pointer_n , clear_i, '0, clk_i, rst_ni)
-  `FFARNC(mem_q           , mem_n           , clear_i, '{default: sb_mem_t'(0)}, clk_i, rst_ni)
+  `FFARNC(issue_cnt_q, issue_cnt_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(issue_pointer_q, issue_pointer_n, clear_i, '0, clk_i, rst_ni)
+  `FFARNC(mem_q, mem_n, clear_i, '{default: sb_mem_t'(0)}, clk_i, rst_ni)
   `FFARNC(commit_pointer_q, commit_pointer_n, clear_i, '0, clk_i, rst_ni)
 
   //RVFI
diff --git a/core/serdiv.sv b/core/serdiv.sv
index ae08c763e2..bb14115220 100644
--- a/core/serdiv.sv
+++ b/core/serdiv.sv
@@ -247,17 +247,17 @@ module serdiv
   assign op_b_d = (b_reg_en) ? b_mux : op_b_q;
   assign res_d = (load_en) ? '0 : (res_reg_en) ? {res_q[$high(res_q)-1:0], ab_comp} : res_q;
 
-  `FFARNC(state_q        , state_d       , 1'b0, IDLE, clk_i, rst_ni)
-  `FFARNC(op_a_q         , op_a_d        , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(op_b_q         , op_b_d        , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(res_q          , res_d         , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(cnt_q          , cnt_d         , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(id_q           , id_d          , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(rem_sel_q      , rem_sel_d     , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(comp_inv_q     , comp_inv_d    , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(res_inv_q      , res_inv_d     , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(op_b_zero_q    , op_b_zero_d   , 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(op_b_neg_one_q , op_b_neg_one_d, 1'b0, '0  , clk_i, rst_ni)
-  `FFARNC(div_res_zero_q , div_res_zero_d, 1'b0, '0  , clk_i, rst_ni)
+  `FFARNC(state_q, state_d, 1'b0, IDLE, clk_i, rst_ni)
+  `FFARNC(op_a_q, op_a_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(op_b_q, op_b_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(res_q, res_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(cnt_q, cnt_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(id_q, id_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(rem_sel_q, rem_sel_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(comp_inv_q, comp_inv_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(res_inv_q, res_inv_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(op_b_zero_q, op_b_zero_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(op_b_neg_one_q, op_b_neg_one_d, 1'b0, '0, clk_i, rst_ni)
+  `FFARNC(div_res_zero_q, div_res_zero_d, 1'b0, '0, clk_i, rst_ni)
 
 endmodule
diff --git a/core/store_buffer.sv b/core/store_buffer.sv
index 6dbacb02f2..8e82d385d4 100644
--- a/core/store_buffer.sv
+++ b/core/store_buffer.sv
@@ -234,15 +234,15 @@ module store_buffer
 
 
   // registers
-  `FFARNC(speculative_queue_q        , speculative_queue_n        , clear_i, '{default: 0}, clk_i, rst_ni)
-  `FFARNC(speculative_read_pointer_q , speculative_read_pointer_n , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(speculative_queue_q, speculative_queue_n, clear_i, '{default: 0}, clk_i, rst_ni)
+  `FFARNC(speculative_read_pointer_q, speculative_read_pointer_n, clear_i, '0, clk_i, rst_ni)
   `FFARNC(speculative_write_pointer_q, speculative_write_pointer_n, clear_i, '0, clk_i, rst_ni)
-  `FFARNC(speculative_status_cnt_q   , speculative_status_cnt_n   , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(speculative_status_cnt_q, speculative_status_cnt_n, clear_i, '0, clk_i, rst_ni)
 
-  `FFARNC(commit_queue_q        , commit_queue_n        , clear_i, '{default: 0}, clk_i, rst_ni)
-  `FFARNC(commit_read_pointer_q , commit_read_pointer_n , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(commit_queue_q, commit_queue_n, clear_i, '{default: 0}, clk_i, rst_ni)
+  `FFARNC(commit_read_pointer_q, commit_read_pointer_n, clear_i, '0, clk_i, rst_ni)
   `FFARNC(commit_write_pointer_q, commit_write_pointer_n, clear_i, '0, clk_i, rst_ni)
-  `FFARNC(commit_status_cnt_q   , commit_status_cnt_n   , clear_i, '0, clk_i, rst_ni)
+  `FFARNC(commit_status_cnt_q, commit_status_cnt_n, clear_i, '0, clk_i, rst_ni)
 
   ///////////////////////////////////////////////////////
   // assertions