From 0a3f0aae5b4c39eafc9bcdb7030582cd75268274 Mon Sep 17 00:00:00 2001 From: Paul Scheffler Date: Thu, 24 Oct 2024 16:43:33 +0200 Subject: [PATCH] wt_axi_adapter: Remove redundant, parameterization-breaking zero extensions --- core/cache_subsystem/wt_axi_adapter.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 14dade2b58..0aae2aee4a 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -141,7 +141,7 @@ module wt_axi_adapter axi_wr_data[0] = {(CVA6Cfg.AxiDataWidth/CVA6Cfg.XLEN){dcache_data.data}}; axi_wr_user[0] = dcache_data.user; // Cast to AXI address width - axi_wr_addr = {{CVA6Cfg.AxiAddrWidth-CVA6Cfg.PLEN{1'b0}}, dcache_data.paddr}; + axi_wr_addr = dcache_data.paddr; axi_wr_size = dcache_data.size; axi_wr_req = 1'b0; axi_wr_blen = '0;// single word writes @@ -166,7 +166,7 @@ module wt_axi_adapter // arbiter mux if (arb_idx) begin // Cast to AXI address width - axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, dcache_data.paddr}; + axi_rd_addr = dcache_data.paddr; // If dcache_data.size MSB is set, we want to read as much as possible axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size; if (dcache_data.size[2]) begin @@ -174,7 +174,7 @@ module wt_axi_adapter end end else begin // Cast to AXI address width - axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, icache_data.paddr}; + axi_rd_addr = icache_data.paddr; axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill if (!icache_data.nc) begin axi_rd_blen = AxiRdBlenIcache[$clog2(AxiNumWords)-1:0];