From 206396479010ee0473749c5409db4476edc33eae Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 12 May 2024 21:56:01 +0200 Subject: [PATCH] Try fix verible-verilog-format. --- core/cache_subsystem/axi_adapter.sv | 5 ++--- core/cache_subsystem/miss_handler.sv | 4 ++-- core/ex_stage.sv | 12 +++++++----- core/mmu_sv32/cva6_shared_tlb_sv32.sv | 4 ++-- 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv index b63c59f918..945eea0942 100644 --- a/core/cache_subsystem/axi_adapter.sv +++ b/core/cache_subsystem/axi_adapter.sv @@ -26,10 +26,9 @@ module axi_adapter #( parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, + input logic rst_ni, input logic clear_i, - output logic busy_o, input logic req_i, input ariane_pkg::ad_req_t type_i, diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv index 067aa9231d..493fcf2b83 100644 --- a/core/cache_subsystem/miss_handler.sv +++ b/core/cache_subsystem/miss_handler.sv @@ -560,7 +560,7 @@ module miss_handler .req_t (bypass_req_t), .rsp_t (bypass_rsp_t) ) i_bypass_arbiter ( - .clk_i (clk_i), + .clk_i(clk_i), .rst_ni(rst_ni), .clear_i(clear_i), // Master Side @@ -689,7 +689,7 @@ module axi_adapter_arbiter #( parameter type req_t = std_cache_pkg::bypass_req_t, parameter type rsp_t = std_cache_pkg::bypass_rsp_t ) ( - input logic clk_i, // Clock + input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic clear_i, // Master ports diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 53b0ac5f41..121c771a63 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -241,6 +241,8 @@ module ex_stage // instructions. + logic clear; + logic [5:0] load_enable; logic current_instruction_is_sfence_vma; logic current_instruction_is_hfence_vvma; logic current_instruction_is_hfence_gvma; @@ -505,7 +507,7 @@ module ex_stage assign x_valid_o = '0; end - logic [5:0] load_enable; + assign clear = flush_i | clear_i; assign load_enable[0] = ((fu_data_i.operation == SFENCE_VMA && !v_i) && csr_valid_i) ? 1'b1 : 1'b0; assign load_enable[1] = (((fu_data_i.operation == SFENCE_VMA && v_i) || fu_data_i.operation == HFENCE_VVMA) && csr_valid_i) ? 1'b1 : 1'b0; assign load_enable[2] = ((fu_data_i.operation == HFENCE_GVMA) && csr_valid_i) ? 1'b1 : 1'b0; @@ -515,13 +517,13 @@ module ex_stage if (CVA6Cfg.RVS) begin if (CVA6Cfg.RVH) begin - `FFLARNC(current_instruction_is_sfence_vma, '1, load_enable[0], (flush_i | clear_i), '0, clk_i, rst_ni) - `FFLARNC(current_instruction_is_hfence_vvma, '1, load_enable[1], (flush_i | clear_i), '0, clk_i, rst_ni) - `FFLARNC(current_instruction_is_hfence_gvma, '1, load_enable[2], (flush_i | clear_i), '0, clk_i, rst_ni) + `FFLARNC(current_instruction_is_sfence_vma, '1, load_enable[0], clear, '0, clk_i, rst_ni) + `FFLARNC(current_instruction_is_hfence_vvma, '1, load_enable[1], clear, '0, clk_i, rst_ni) + `FFLARNC(current_instruction_is_hfence_gvma, '1, load_enable[2], clear, '0, clk_i, rst_ni) end else begin assign current_instruction_is_hfence_vvma = 1'b0; assign current_instruction_is_hfence_gvma = 1'b0; - `FFLARNC(current_instruction_is_sfence_vma, '1, load_enable[3], (flush_i | clear_i), '0, clk_i, rst_ni) + `FFLARNC(current_instruction_is_sfence_vma, '1, load_enable[3], clear, '0, clk_i, rst_ni) end if (CVA6Cfg.RVH) begin assign asid_rs2_forwarding = rs2_forwarding_i[ASID_WIDTH-1:0]; diff --git a/core/mmu_sv32/cva6_shared_tlb_sv32.sv b/core/mmu_sv32/cva6_shared_tlb_sv32.sv index 12faf97ce6..d457edf461 100644 --- a/core/mmu_sv32/cva6_shared_tlb_sv32.sv +++ b/core/mmu_sv32/cva6_shared_tlb_sv32.sv @@ -27,8 +27,8 @@ module cva6_shared_tlb_sv32 parameter int SHARED_TLB_WAYS = 2, parameter int ASID_WIDTH = 1 ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, + input logic rst_ni, input logic flush_i, input logic clear_i,