From 77c2d6808706b156ebb5840ad3a58ae7a50dd3a6 Mon Sep 17 00:00:00 2001
From: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Date: Fri, 8 Nov 2024 18:03:23 +1100
Subject: [PATCH] csr_regfile: Fix S-mode traps when H extension is enabled

If Hypervisor extension is enabled, the logic required to properly trap
to S mode is currently excluded. Fix this by adjusting the if block.

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
---
 core/csr_regfile.sv | 36 +++++++++++++++++-------------------
 1 file changed, 17 insertions(+), 19 deletions(-)

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
index 8f6fe1132d..c4ae777813 100644
--- a/core/csr_regfile.sv
+++ b/core/csr_regfile.sv
@@ -2001,25 +2001,23 @@ module csr_regfile
 
       // trap to supervisor mode
       if (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S) begin
-        if (CVA6Cfg.RVH) begin
-          if (trap_to_v) begin
-            // update sstatus
-            vsstatus_d.sie = 1'b0;
-            vsstatus_d.spie = vsstatus_q.sie;
-            // this can either be user or supervisor mode
-            vsstatus_d.spp = priv_lvl_q[0];
-            // set cause
-            vscause_d = ex_i.cause[CVA6Cfg.XLEN-1] ? {ex_i.cause[CVA6Cfg.XLEN-1:2], 2'b01} : ex_i.cause;
-            // set epc
-            vsepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
-            // set vstval
-            vstval_d        = (ariane_pkg::ZERO_TVAL
-                                        && (ex_i.cause inside {
-                                          riscv::ILLEGAL_INSTR,
-                                          riscv::BREAKPOINT,
-                                          riscv::ENV_CALL_UMODE
-                                        } || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : ex_i.tval;
-          end
+        if (CVA6Cfg.RVH && trap_to_v) begin
+          // update sstatus
+          vsstatus_d.sie = 1'b0;
+          vsstatus_d.spie = vsstatus_q.sie;
+          // this can either be user or supervisor mode
+          vsstatus_d.spp = priv_lvl_q[0];
+          // set cause
+          vscause_d = ex_i.cause[CVA6Cfg.XLEN-1] ? {ex_i.cause[CVA6Cfg.XLEN-1:2], 2'b01} : ex_i.cause;
+          // set epc
+          vsepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i};
+          // set vstval
+          vstval_d        = (ariane_pkg::ZERO_TVAL
+                             && (ex_i.cause inside {
+                             riscv::ILLEGAL_INSTR,
+                             riscv::BREAKPOINT,
+                             riscv::ENV_CALL_UMODE
+                             } || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : ex_i.tval;
         end else begin
           // update sstatus
           mstatus_d.sie = 1'b0;