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[WIP - 4] - Cleaning up synchronous clear integration.
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Yvan Tortorella committed May 8, 2024
1 parent c7bcacf commit 7cc4d69
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Showing 7 changed files with 134 additions and 131 deletions.
10 changes: 3 additions & 7 deletions core/cva6.sv
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Expand Up @@ -12,6 +12,7 @@
// Date: 19.03.2017
// Description: CVA6 Top-level module

`include "common_cells/registers.svh"

module cva6
import ariane_pkg::*;
Expand Down Expand Up @@ -518,13 +519,7 @@ module cva6
logic inval_valid;
logic inval_ready;

always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
rst_uarch_n <= 1'b0;
end else begin
rst_uarch_n <= rst_uarch_controller_n & ~clear_i;
end
end
`FFARN(rst_uarch_n, rst_uarch_controller_n, 1'b0, clk_i, rst_ni)

// ----------------------
// CLIC Controller <-> ID
Expand Down Expand Up @@ -1367,6 +1362,7 @@ module cva6
) i_clic_controller (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (clear_i),
// from CSR file
.priv_lvl_i (priv_lvl),
.irq_ctrl_i (irq_ctrl_csr_id),
Expand Down
11 changes: 4 additions & 7 deletions core/cva6_clic_controller.sv
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Expand Up @@ -4,11 +4,14 @@
//
// Author: Nils Wistoff <[email protected]>

`include "common_cells/registers.svh"

module cva6_clic_controller #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,
input logic clear_i,
// from CSR file
input riscv::priv_lvl_t priv_lvl_i, // current privilege level
input ariane_pkg::irq_ctrl_t irq_ctrl_i,
Expand Down Expand Up @@ -88,11 +91,5 @@ module cva6_clic_controller #(
// Acknowledge kill if no irq is inflight and irq is not accepted this cycle
assign clic_kill_ack_o = clic_kill_req_i & ~irq_inflight_q & ~clic_irq_req_o;

always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
irq_inflight_q <= 1'b0;
end else begin
irq_inflight_q <= irq_inflight_d;
end
end
`FFARNC(mult_result_q, irq_inflight_d, clear_i, '0, clk_i, rst_ni)
endmodule
11 changes: 8 additions & 3 deletions core/frontend/instr_queue.sv
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Expand Up @@ -490,10 +490,15 @@ ariane_pkg::FETCH_FIFO_DEPTH
pc_q <= '0;
reset_address_q <= 1'b1;
end else begin
pc_q <= pc_d;
reset_address_q <= reset_address_d;
if (flush_i) begin
if (clear_i) begin
pc_q <= '0;
reset_address_q <= 1'b1;
end else begin
pc_q <= pc_d;
reset_address_q <= reset_address_d;
if (flush_i) begin
reset_address_q <= 1'b1;
end
end
end
end
Expand Down
167 changes: 100 additions & 67 deletions core/issue_read_operands.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,8 @@ module issue_read_operands
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
input logic rst_uarch_ni,
// Synchronous clear active high
input logic clear_i,
// Flush - CONTROLLER
input logic flush_i,
// Stall inserted by Acc dispatcher - ACC_DISPATCHER
Expand Down Expand Up @@ -333,56 +335,67 @@ module issue_read_operands
csr_valid_q <= 1'b0;
branch_valid_q <= 1'b0;
end else begin
alu_valid_q <= 1'b0;
lsu_valid_q <= 1'b0;
mult_valid_q <= 1'b0;
fpu_valid_q <= 1'b0;
fpu_fmt_q <= 2'b0;
fpu_rm_q <= 3'b0;
csr_valid_q <= 1'b0;
branch_valid_q <= 1'b0;
// Exception pass through:
// If an exception has occurred simply pass it through
// we do not want to issue this instruction
if (!issue_instr_i.ex.valid && issue_instr_valid_i && issue_ack_o) begin
case (issue_instr_i.fu)
ALU: begin
alu_valid_q <= 1'b1;
end
CTRL_FLOW: begin
branch_valid_q <= 1'b1;
end
MULT: begin
mult_valid_q <= 1'b1;
end
LOAD, STORE: begin
lsu_valid_q <= 1'b1;
end
CSR: begin
csr_valid_q <= 1'b1;
end
default: begin
if (issue_instr_i.fu == FPU && CVA6Cfg.FpPresent) begin
fpu_valid_q <= 1'b1;
fpu_fmt_q <= orig_instr.rftype.fmt; // fmt bits from instruction
fpu_rm_q <= orig_instr.rftype.rm; // rm bits from instruction
end else if (issue_instr_i.fu == FPU_VEC && CVA6Cfg.FpPresent) begin
fpu_valid_q <= 1'b1;
fpu_fmt_q <= orig_instr.rvftype.vfmt; // vfmt bits from instruction
fpu_rm_q <= {2'b0, orig_instr.rvftype.repl}; // repl bit from instruction
end
end
endcase
end
// if we got a flush request, de-assert the valid flag, otherwise we will start this
// functional unit with the wrong inputs
if (flush_i) begin
if (clear_i) begin
alu_valid_q <= '0;
lsu_valid_q <= '0;
mult_valid_q <= '0;
fpu_valid_q <= '0;
fpu_fmt_q <= '0;
fpu_rm_q <= '0;
csr_valid_q <= '0;
branch_valid_q <= '0;
end else begin
alu_valid_q <= 1'b0;
lsu_valid_q <= 1'b0;
mult_valid_q <= 1'b0;
fpu_valid_q <= 1'b0;
fpu_fmt_q <= 2'b0;
fpu_rm_q <= 3'b0;
csr_valid_q <= 1'b0;
branch_valid_q <= 1'b0;
// Exception pass through:
// If an exception has occurred simply pass it through
// we do not want to issue this instruction
if (!issue_instr_i.ex.valid && issue_instr_valid_i && issue_ack_o) begin
case (issue_instr_i.fu)
ALU: begin
alu_valid_q <= 1'b1;
end
CTRL_FLOW: begin
branch_valid_q <= 1'b1;
end
MULT: begin
mult_valid_q <= 1'b1;
end
LOAD, STORE: begin
lsu_valid_q <= 1'b1;
end
CSR: begin
csr_valid_q <= 1'b1;
end
default: begin
if (issue_instr_i.fu == FPU && CVA6Cfg.FpPresent) begin
fpu_valid_q <= 1'b1;
fpu_fmt_q <= orig_instr.rftype.fmt; // fmt bits from instruction
fpu_rm_q <= orig_instr.rftype.rm; // rm bits from instruction
end else if (issue_instr_i.fu == FPU_VEC && CVA6Cfg.FpPresent) begin
fpu_valid_q <= 1'b1;
fpu_fmt_q <= orig_instr.rvftype.vfmt; // vfmt bits from instruction
fpu_rm_q <= {2'b0, orig_instr.rvftype.repl}; // repl bit from instruction
end
end
endcase
end
// if we got a flush request, de-assert the valid flag, otherwise we will start this
// functional unit with the wrong inputs
if (flush_i) begin
alu_valid_q <= 1'b0;
lsu_valid_q <= 1'b0;
mult_valid_q <= 1'b0;
fpu_valid_q <= 1'b0;
csr_valid_q <= 1'b0;
branch_valid_q <= 1'b0;
end
end
end
end
Expand All @@ -393,20 +406,25 @@ module issue_read_operands
cvxif_valid_q <= 1'b0;
cvxif_off_instr_q <= 32'b0;
end else begin
cvxif_valid_q <= 1'b0;
cvxif_off_instr_q <= 32'b0;
if (!issue_instr_i.ex.valid && issue_instr_valid_i && issue_ack_o) begin
case (issue_instr_i.fu)
CVXIF: begin
cvxif_valid_q <= 1'b1;
cvxif_off_instr_q <= orig_instr;
end
default: ;
endcase
end
if (flush_i) begin
if (clear_i) begin
cvxif_valid_q <= 1'b0;
cvxif_off_instr_q <= 32'b0;
end else begin
cvxif_valid_q <= 1'b0;
cvxif_off_instr_q <= 32'b0;
if (!issue_instr_i.ex.valid && issue_instr_valid_i && issue_ack_o) begin
case (issue_instr_i.fu)
CVXIF: begin
cvxif_valid_q <= 1'b1;
cvxif_off_instr_q <= orig_instr;
end
default: ;
endcase
end
if (flush_i) begin
cvxif_valid_q <= 1'b0;
cvxif_off_instr_q <= 32'b0;
end
end
end
end
Expand Down Expand Up @@ -609,18 +627,33 @@ module issue_read_operands
is_compressed_instr_o <= 1'b0;
branch_predict_o <= {cf_t'(0), {riscv::VLEN{1'b0}}};
end else begin
operand_a_q <= operand_a_n;
operand_b_q <= operand_b_n;
imm_q <= imm_n;
fu_q <= fu_n;
operator_q <= operator_n;
trans_id_q <= trans_id_n;
if (CVA6Cfg.RVH) begin
tinst_q <= tinst_n;
if (clear_i) begin
operand_a_q <= '{default: 0};
operand_b_q <= '{default: 0};
imm_q <= '0;
fu_q <= NONE;
operator_q <= ADD;
trans_id_q <= '0;
if (CVA6Cfg.RVH) begin
tinst_q <= '0;
end
pc_o <= '0;
is_compressed_instr_o <= 1'b0;
branch_predict_o <= {cf_t'(0), {riscv::VLEN{1'b0}}};
end else begin
operand_a_q <= operand_a_n;
operand_b_q <= operand_b_n;
imm_q <= imm_n;
fu_q <= fu_n;
operator_q <= operator_n;
trans_id_q <= trans_id_n;
if (CVA6Cfg.RVH) begin
tinst_q <= tinst_n;
end
pc_o <= issue_instr_i.pc;
is_compressed_instr_o <= issue_instr_i.is_compressed;
branch_predict_o <= issue_instr_i.bp;
end
pc_o <= issue_instr_i.pc;
is_compressed_instr_o <= issue_instr_i.is_compressed;
branch_predict_o <= issue_instr_i.bp;
end
end

Expand Down
32 changes: 9 additions & 23 deletions core/load_unit.sv
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Expand Up @@ -112,7 +112,7 @@ module load_unit

logic [CVA6Cfg.NrLoadBufEntries-1:0] ldbuf_valid_q, ldbuf_valid_d;
logic [CVA6Cfg.NrLoadBufEntries-1:0] ldbuf_flushed_q, ldbuf_flushed_d;
ldbuf_t [CVA6Cfg.NrLoadBufEntries-1:0] ldbuf_q;
ldbuf_t [CVA6Cfg.NrLoadBufEntries-1:0] ldbuf_q, ldbuf_en;
logic ldbuf_empty, ldbuf_full;
ldbuf_id_t ldbuf_free_index;
logic ldbuf_w;
Expand Down Expand Up @@ -146,6 +146,9 @@ module load_unit

assign ldbuf_windex = (LDBUF_FALLTHROUGH && ldbuf_r) ? ldbuf_rindex : ldbuf_free_index;

for (genvar i = 0; i < CVA6Cfg.NrLoadBufEntries; i++)
assign ldbuf_en[i] = ((i == ldbuf_windex) & ldbuf_w) ? 1'b1 : 1'b0;

always_comb begin : ldbuf_comb
ldbuf_flushed_d = ldbuf_flushed_q;
ldbuf_valid_d = ldbuf_valid_q;
Expand All @@ -166,28 +169,11 @@ module load_unit
end
end

always_ff @(posedge clk_i or negedge rst_ni) begin : ldbuf_ff
if (!rst_ni) begin
ldbuf_flushed_q <= '0;
ldbuf_valid_q <= '0;
ldbuf_last_id_q <= '0;
ldbuf_q <= '0;
end else begin
if (clear_i) begin
ldbuf_flushed_q <= '0;
ldbuf_valid_q <= '0;
ldbuf_last_id_q <= '0;
ldbuf_q <= '0;
end else begin
ldbuf_flushed_q <= ldbuf_flushed_d;
ldbuf_valid_q <= ldbuf_valid_d;
if (ldbuf_w) begin
ldbuf_last_id_q <= ldbuf_windex;
ldbuf_q[ldbuf_windex] <= ldbuf_wdata;
end
end
end
end
`FFARNC(ldbuf_flushed_q, ldbuf_flushed_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(ldbuf_valid_q, ldbuf_valid_d, clear_i, '0, clk_i, rst_ni)
`FFLARNC(ldbuf_last_id_q, ldbuf_windex, ldbuf_w, clear_i, '0, clk_i, rst_ni)
for (genvar i = 0; i < CVA6Cfg.NrLoadBufEntries; i++)
`FFLARNC(ldbuf_q[i], ldbuf_wdata, ldbuf_en[i], clear_i, '0, clk_i, rst_ni)

// page offset is defined as the lower 12 bits, feed through for address checker
assign page_offset_o = lsu_ctrl_i.vaddr[11:0];
Expand Down
1 change: 1 addition & 0 deletions core/mult.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,7 @@ module mult
) i_multiplier (
.clk_i,
.rst_ni,
.clear_i,
.trans_id_i (fu_data_i.trans_id),
.operation_i (fu_data_i.operation),
.operand_a_i (fu_data_i.operand_a),
Expand Down
33 changes: 9 additions & 24 deletions core/multiplier.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@
// This unit relies on retiming features of the synthesizer
//

`include "common_cells/registers.svh"

module multiplier
import ariane_pkg::*;
Expand All @@ -24,6 +25,8 @@ module multiplier
input logic clk_i,
// Asynchronous reset active low - SUBSYSTEM
input logic rst_ni,
// Synchronous clear active high
input logic clear_i,
// Multiplier transaction ID - Mult
input logic [TRANS_ID_BITS-1:0] trans_id_i,
// Multiplier instruction is valid - Mult
Expand Down Expand Up @@ -138,32 +141,14 @@ module multiplier
endcase
end
if (CVA6Cfg.RVB) begin
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
clmul_q <= '0;
clmulr_q <= '0;
end else begin
clmul_q <= clmul_d;
clmulr_q <= clmulr_d;
end
end
`FFARNC(clmul_q, clmul_d, clear_i, '0, clk_i, rst_ni)
`FFARNC(clmulr_q, clmulr_d, clear_i, '0, clk_i, rst_ni)
end
// -----------------------
// Output pipeline register
// -----------------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
mult_valid_q <= '0;
trans_id_q <= '0;
operator_q <= MUL;
mult_result_q <= '0;
end else begin
// Input silencing
trans_id_q <= trans_id_i;
// Output Register
mult_valid_q <= mult_valid;
operator_q <= operator_d;
mult_result_q <= mult_result_d;
end
end
`FFARNC(mult_valid_q, mult_valid, clear_i, '0, clk_i, rst_ni)
`FFARNC(trans_id_q, trans_id_i, clear_i, '0, clk_i, rst_ni)
`FFARNC(operator_q, operator_d, clear_i, MUL, clk_i, rst_ni)
`FFARNC(mult_result_q, mult_result_d, clear_i, '0, clk_i, rst_ni)
endmodule

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