From adaa2278e6d259020772b71a2cf73413a03132ea Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Thu, 29 Feb 2024 17:12:34 +0100 Subject: [PATCH] csr_regfile.sv: add missing RVH-masks --- core/csr_regfile.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 047780d53d..e87a7b654b 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -978,7 +978,7 @@ module csr_regfile unique case (conv_csr_addr.address) // Floating-Point riscv::CSR_FFLAGS: begin - if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (v_q && vsstatus_q.fs == riscv::Off))) begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin dirty_fp_state_csr = 1'b1; fcsr_d.fflags = csr_wdata[4:0]; // this instruction has side-effects @@ -988,7 +988,7 @@ module csr_regfile end end riscv::CSR_FRM: begin - if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (v_q && vsstatus_q.fs == riscv::Off))) begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin dirty_fp_state_csr = 1'b1; fcsr_d.frm = csr_wdata[2:0]; // this instruction has side-effects @@ -998,7 +998,7 @@ module csr_regfile end end riscv::CSR_FCSR: begin - if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (v_q && vsstatus_q.fs == riscv::Off))) begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin dirty_fp_state_csr = 1'b1; fcsr_d[7:0] = csr_wdata[7:0]; // ignore writes to reserved space // this instruction has side-effects @@ -1008,7 +1008,7 @@ module csr_regfile end end riscv::CSR_FTRAN: begin - if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (v_q && vsstatus_q.fs == riscv::Off))) begin + if (CVA6Cfg.FpPresent && !(mstatus_q.fs == riscv::Off || (CVA6Cfg.RVH && v_q && vsstatus_q.fs == riscv::Off))) begin dirty_fp_state_csr = 1'b1; fcsr_d.fprec = csr_wdata[6:0]; // ignore writes to reserved space // this instruction has side-effects