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[WIP] - Cleaning up synchronous clear integration.
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Yvan Tortorella committed Mar 5, 2024
1 parent 571c615 commit b3c11e6
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Showing 23 changed files with 231 additions and 463 deletions.
2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -9,7 +9,7 @@ package:
dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 }
common_cells:
{ git: "https://github.com/pulp-platform/common_cells", version: 1.23.0 }
{ git: "https://github.com/pulp-platform/common_cells", rev: bd4bbe7 } # branch: yt/synch-clear
fpnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.1 }
tech_cells_generic:
{ git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
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32 changes: 10 additions & 22 deletions core/cache_subsystem/axi_adapter.sv
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Expand Up @@ -16,6 +16,8 @@
*/
//import std_cache_pkg::*;

`include "common_cells/registers.svh"

module axi_adapter #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned DATA_WIDTH = 256,
Expand Down Expand Up @@ -461,28 +463,14 @@ module axi_adapter #(
// ----------------
// Registers
// ----------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
// start in flushing state and initialize the memory
state_q <= IDLE;
cnt_q <= '0;
cache_line_q <= '0;
addr_offset_q <= '0;
id_q <= '0;
amo_q <= ariane_pkg::AMO_NONE;
size_q <= '0;
outstanding_aw_cnt_q <= '0;
end else begin
state_q <= state_d;
cnt_q <= cnt_d;
cache_line_q <= cache_line_d;
addr_offset_q <= addr_offset_d;
id_q <= id_d;
amo_q <= amo_d;
size_q <= size_d;
outstanding_aw_cnt_q <= outstanding_aw_cnt_d;
end
end
`FFARNC(state_q , state_d , 1'b0, IDLE , clk_i, rst_ni)
`FFARNC(cnt_q , cnt_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(cache_line_q , cache_line_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(addr_offset_q , addr_offset_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(id_q , id_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(amo_q , amo_d , 1'b0, ariane_pkg::AMO_NONE, clk_i, rst_ni)
`FFARNC(size_q , size_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(outstanding_aw_cnt_q , outstanding_aw_cnt_d, 1'b0, '0 , clk_i, rst_ni)

function automatic axi_pkg::atop_t atop_from_amo(ariane_pkg::amo_t amo);
axi_pkg::atop_t result = 6'b000000;
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15 changes: 4 additions & 11 deletions core/cache_subsystem/cache_ctrl.sv
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Expand Up @@ -17,6 +17,7 @@
//
// Description: Cache controller

`include "common_cells/registers.svh"

module cache_ctrl
import ariane_pkg::*;
Expand Down Expand Up @@ -442,17 +443,9 @@ module cache_ctrl
// --------------
// Registers
// --------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
state_q <= IDLE;
mem_req_q <= '0;
hit_way_q <= '0;
end else begin
state_q <= state_d;
mem_req_q <= mem_req_d;
hit_way_q <= hit_way_d;
end
end
`FFARNC(state_q , state_d , 1'b0, '0, clk_i, rst_ni)
`FFARNC(mem_req_q , mem_req_d, 1'b0, '0, clk_i, rst_ni)
`FFARNC(hit_way_q , hit_way_d, 1'b0, '0, clk_i, rst_ni)

//pragma translate_off
`ifndef VERILATOR
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17 changes: 8 additions & 9 deletions core/cache_subsystem/cva6_hpdcache_if_adapter.sv
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Expand Up @@ -9,6 +9,9 @@
// Authors: Cesar Fuguet
// Date: February, 2023
// Description: Interface adapter for the CVA6 core

`include "common_cells/registers.svh"

module cva6_hpdcache_if_adapter
import hpdcache_pkg::*;

Expand Down Expand Up @@ -108,7 +111,7 @@ module cva6_hpdcache_if_adapter
logic [ 7:0] amo_data_be;
hpdcache_req_op_t amo_op;
logic [31:0] amo_resp_word;
logic amo_pending_q;
logic amo_pending_q, amo_pending_n;

// AMO logic
// {{{
Expand Down Expand Up @@ -195,16 +198,12 @@ module cva6_hpdcache_if_adapter
: hpdcache_rsp_i.rdata[0];
// }}}

always_ff @(posedge clk_i or negedge rst_ni) begin : amo_pending_ff
if (!rst_ni) begin
amo_pending_q <= 1'b0;
end else begin
amo_pending_q <=
assign amo_pending_n =
( cva6_amo_req_i.req & hpdcache_req_ready_i & ~amo_pending_q) |
(~cva6_amo_resp_o.ack & amo_pending_q);
end
end
end

`FFARNC(amo_pending_q, amo_pending_n, 1'b0, 1'b0, clk_i, rst_ni)

// }}}
endgenerate
// }}}
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52 changes: 21 additions & 31 deletions core/cache_subsystem/cva6_icache.sv
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Expand Up @@ -24,6 +24,7 @@
// 3) NC accesses to I/O space are expected to return 32bit from memory.
//

`include "common_cells/registers.svh"

module cva6_icache
import ariane_pkg::*;
Expand Down Expand Up @@ -494,32 +495,16 @@ module cva6_icache
);
end


always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if (!rst_ni) begin
cl_tag_q <= '0;
flush_cnt_q <= '0;
vaddr_q <= '0;
cmp_en_q <= '0;
cache_en_q <= '0;
flush_q <= '0;
state_q <= FLUSH;
cl_offset_q <= '0;
repl_way_oh_q <= '0;
inv_q <= '0;
end else begin
cl_tag_q <= cl_tag_d;
flush_cnt_q <= flush_cnt_d;
vaddr_q <= vaddr_d;
cmp_en_q <= cmp_en_d;
cache_en_q <= cache_en_d;
flush_q <= flush_d;
state_q <= state_d;
cl_offset_q <= cl_offset_d;
repl_way_oh_q <= repl_way_oh_d;
inv_q <= inv_d;
end
end
`FFARNC(cl_tag_q , cl_tag_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(flush_cnt_q , flush_cnt_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(vaddr_q , vaddr_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(cmp_en_q , cmp_en_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(cache_en_q , cache_en_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(flush_q , flush_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(state_q , state_d , 1'b0, FLUSH, clk_i, rst_ni)
`FFARNC(cl_offset_q , cl_offset_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(repl_way_oh_q , repl_way_oh_d, 1'b0, '0 , clk_i, rst_ni)
`FFARNC(inv_q , inv_d , 1'b0, '0 , clk_i, rst_ni)

///////////////////////////////////////////////////////
// assertions
Expand Down Expand Up @@ -559,12 +544,17 @@ module cva6_icache
vld_mirror <= '{default: '0};
tag_mirror <= '{default: '0};
end else begin
for (int i = 0; i < ICACHE_SET_ASSOC; i++) begin
if (vld_req[i] & vld_we) begin
vld_mirror[vld_addr][i] <= vld_wdata[i];
tag_mirror[vld_addr][i] <= cl_tag_q;
// if (clear_i) begin
// vld_mirror <= '{default: '0};
// tag_mirror <= '{default: '0};
// end else begin
for (int i = 0; i < ICACHE_SET_ASSOC; i++) begin
if (vld_req[i] & vld_we) begin
vld_mirror[vld_addr][i] <= vld_wdata[i];
tag_mirror[vld_addr][i] <= cl_tag_q;
end
end
end
// end
end
end

Expand Down
19 changes: 6 additions & 13 deletions core/cache_subsystem/cva6_icache_axi_wrapper.sv
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Expand Up @@ -13,6 +13,8 @@
// Description: wrapper module to connect the L1I$ to a 64bit AXI bus.
//

`include "common_cells/registers.svh"

module cva6_icache_axi_wrapper
import ariane_pkg::*;
import wt_cache_pkg::*;
Expand Down Expand Up @@ -191,18 +193,9 @@ module cva6_icache_axi_wrapper
end

// Registers
always_ff @(posedge clk_i or negedge rst_ni) begin : p_rd_buf
if (!rst_ni) begin
req_valid_q <= 1'b0;
req_data_q <= '0;
first_q <= 1'b1;
rd_shift_q <= '0;
end else begin
req_valid_q <= req_valid_d;
req_data_q <= req_data_d;
first_q <= first_d;
rd_shift_q <= rd_shift_d;
end
end
`FFARNC(req_valid_q , req_valid_d, 1'b0, '0 , clk_i, rst_ni)
`FFARNC(req_data_q , req_data_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(first_q , first_d , 1'b0, 1'b0, clk_i, rst_ni)
`FFARNC(rd_shift_q , rd_shift_d , 1'b0, '0 , clk_i, rst_ni)

endmodule // cva6_icache_axi_wrapper
43 changes: 13 additions & 30 deletions core/cache_subsystem/miss_handler.sv
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Expand Up @@ -16,6 +16,8 @@
// MISS Handler
// --------------

`include "common_cells/registers.svh"

module miss_handler
import ariane_pkg::*;
import std_cache_pkg::*;
Expand Down Expand Up @@ -505,23 +507,12 @@ module miss_handler
// --------------------
// Sequential Process
// --------------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
mshr_q <= '0;
state_q <= INIT;
cnt_q <= '0;
evict_way_q <= '0;
evict_cl_q <= '0;
serve_amo_q <= 1'b0;
end else begin
mshr_q <= mshr_d;
state_q <= state_d;
cnt_q <= cnt_d;
evict_way_q <= evict_way_d;
evict_cl_q <= evict_cl_d;
serve_amo_q <= serve_amo_d;
end
end
`FFARNC(mshr_q , mshr_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(state_q , state_d , 1'b0, INIT, clk_i, rst_ni)
`FFARNC(cnt_q , cnt_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(evict_way_q , evict_way_d, 1'b0, '0 , clk_i, rst_ni)
`FFARNC(evict_cl_q , evict_cl_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(serve_amo_q , serve_amo_d, 1'b0, '0 , clk_i, rst_ni)

//pragma translate_off
`ifndef VERILATOR
Expand Down Expand Up @@ -798,19 +789,11 @@ module axi_adapter_arbiter #(
endcase
end

always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
state_q <= IDLE;
sel_q <= '0;
req_q <= '0;
outstanding_cnt_q <= '0;
end else begin
state_q <= state_d;
sel_q <= sel_d;
req_q <= req_d;
outstanding_cnt_q <= outstanding_cnt_d;
end
end
`FFARNC(state_q , state_d , 1'b0, IDLE, clk_i, rst_ni)
`FFARNC(sel_q , sel_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(req_q , req_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(outstanding_cnt_q , outstanding_cnt_d, 1'b0, '0 , clk_i, rst_ni)

// ------------
// Assertions
// ------------
Expand Down
11 changes: 4 additions & 7 deletions core/cache_subsystem/tag_cmp.sv
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Expand Up @@ -15,6 +15,9 @@
// Description: Arbitrates access to cache memories, simplified request grant protocol
// checks for hit or miss on cache
//

`include "common_cells/registers.svh"

module tag_cmp #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NR_PORTS = 3,
Expand Down Expand Up @@ -95,12 +98,6 @@ module tag_cmp #(
`endif
end

always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
id_q <= 0;
end else begin
id_q <= id_d;
end
end
`FFARNC(id_q, id_d, 1'b0, '0, clk_i, rst_ni)

endmodule
48 changes: 15 additions & 33 deletions core/cache_subsystem/wt_axi_adapter.sv
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Expand Up @@ -13,6 +13,7 @@
// Description: adapter module to connect the L1D$ and L1I$ to a 64bit AXI bus.
//

`include "common_cells/registers.svh"

module wt_axi_adapter
import ariane_pkg::*;
Expand Down Expand Up @@ -619,39 +620,20 @@ module wt_axi_adapter
// assign dcache_rtrn_o.inv.vld = '0;
// assign dcache_rtrn_o.inv.all = '0;

always_ff @(posedge clk_i or negedge rst_ni) begin : p_rd_buf
if (!rst_ni) begin
icache_first_q <= 1'b1;
dcache_first_q <= 1'b1;
icache_rd_shift_q <= '0;
icache_rd_shift_user_q <= '0;
dcache_rd_shift_q <= '0;
dcache_rd_shift_user_q <= '0;
icache_rtrn_vld_q <= '0;
dcache_rtrn_vld_q <= '0;
icache_rtrn_tid_q <= '0;
dcache_rtrn_tid_q <= '0;
dcache_rtrn_type_q <= wt_cache_pkg::DCACHE_LOAD_ACK;
dcache_rtrn_inv_q <= '0;
amo_off_q <= '0;
amo_gen_r_q <= 1'b0;
end else begin
icache_first_q <= icache_first_d;
dcache_first_q <= dcache_first_d;
icache_rd_shift_q <= icache_rd_shift_d;
icache_rd_shift_user_q <= icache_rd_shift_user_d;
dcache_rd_shift_q <= dcache_rd_shift_d;
dcache_rd_shift_user_q <= dcache_rd_shift_user_d;
icache_rtrn_vld_q <= icache_rtrn_vld_d;
dcache_rtrn_vld_q <= dcache_rtrn_vld_d;
icache_rtrn_tid_q <= icache_rtrn_tid_d;
dcache_rtrn_tid_q <= dcache_rtrn_tid_d;
dcache_rtrn_type_q <= dcache_rtrn_type_d;
dcache_rtrn_inv_q <= dcache_rtrn_inv_d;
amo_off_q <= amo_off_d;
amo_gen_r_q <= amo_gen_r_d;
end
end
`FFARNC(icache_first_q , icache_first_d , 1'b0, 1'b1 , clk_i, rst_ni)
`FFARNC(dcache_first_q , dcache_first_d , 1'b0, 1'b1 , clk_i, rst_ni)
`FFARNC(icache_rd_shift_q , icache_rd_shift_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(icache_rd_shift_user_q , icache_rd_shift_user_d, 1'b0, '0 , clk_i, rst_ni)
`FFARNC(dcache_rd_shift_q , dcache_rd_shift_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(dcache_rd_shift_user_q , dcache_rd_shift_user_d, 1'b0, '0 , clk_i, rst_ni)
`FFARNC(icache_rtrn_vld_q , icache_rtrn_vld_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(dcache_rtrn_vld_q , dcache_rtrn_vld_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(icache_rtrn_tid_q , icache_rtrn_tid_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(dcache_rtrn_tid_q , dcache_rtrn_tid_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(dcache_rtrn_type_q , dcache_rtrn_type_d , 1'b0, wt_cache_pkg::DCACHE_LOAD_ACK, clk_i, rst_ni)
`FFARNC(dcache_rtrn_inv_q , dcache_rtrn_inv_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(amo_off_q , amo_off_d , 1'b0, '0 , clk_i, rst_ni)
`FFARNC(amo_gen_r_q , amo_gen_r_d , 1'b0, '0 , clk_i, rst_ni)


///////////////////////////////////////////////////////
Expand Down
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