From ff4c978da7ddd18193c4a0ffea815b853fc49c8c Mon Sep 17 00:00:00 2001 From: Enrico Zelioli Date: Fri, 5 Jul 2024 15:56:29 +0200 Subject: [PATCH] vCLIC: Fix verilog formatting --- core/csr_regfile.sv | 23 ++++++++++++++--------- core/cva6_clic_controller.sv | 22 +++++++++++----------- core/include/ariane_pkg.sv | 4 ++-- 3 files changed, 27 insertions(+), 22 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index ac3b60de12..6208159ce0 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -403,10 +403,12 @@ module csr_regfile if (CVA6Cfg.RVH) csr_rdata = vsstatus_extended; else read_access_exception = 1'b1; riscv::CSR_VSIE: - if (CVA6Cfg.RVH) csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : ((mie_q & VS_DELEG_INTERRUPTS & hideleg_q) >> 1); + if (CVA6Cfg.RVH) + csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : ((mie_q & VS_DELEG_INTERRUPTS & hideleg_q) >> 1); else read_access_exception = 1'b1; riscv::CSR_VSIP: - if (CVA6Cfg.RVH) csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 :((mip_q & VS_DELEG_INTERRUPTS & hideleg_q) >> 1); + if (CVA6Cfg.RVH) + csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 :((mip_q & VS_DELEG_INTERRUPTS & hideleg_q) >> 1); else read_access_exception = 1'b1; riscv::CSR_VSTVEC: if (CVA6Cfg.RVH) csr_rdata = vstvec_q; @@ -541,13 +543,16 @@ module csr_regfile if (CVA6Cfg.RVH) csr_rdata = hideleg_q; else read_access_exception = 1'b1; riscv::CSR_HIE: - if (CVA6Cfg.RVH) csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? mie_q & riscv::MIP_SGEIP : mie_q & HS_DELEG_INTERRUPTS; + if (CVA6Cfg.RVH) + csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? mie_q & riscv::MIP_SGEIP : mie_q & HS_DELEG_INTERRUPTS; else read_access_exception = 1'b1; riscv::CSR_HIP: - if (CVA6Cfg.RVH) csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : mip_q & HS_DELEG_INTERRUPTS; + if (CVA6Cfg.RVH) + csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : mip_q & HS_DELEG_INTERRUPTS; else read_access_exception = 1'b1; riscv::CSR_HVIP: - if (CVA6Cfg.RVH) csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : mip_q & VS_DELEG_INTERRUPTS; + if (CVA6Cfg.RVH) + csr_rdata = (CVA6Cfg.RVVCLIC && clic_mode_o) ? '0 : mip_q & VS_DELEG_INTERRUPTS; else read_access_exception = 1'b1; riscv::CSR_HCOUNTEREN: if (CVA6Cfg.RVH) csr_rdata = hcounteren_q; @@ -1321,9 +1326,9 @@ module csr_regfile if (CVA6Cfg.RVH) begin // In CLIC mode only SGEIE bit is writable if (CVA6Cfg.RVVCLIC && clic_mode_o) begin - mask = riscv::MIP_SGEIP; + mask = riscv::MIP_SGEIP; end else begin - mask = HS_DELEG_INTERRUPTS; + mask = HS_DELEG_INTERRUPTS; end mie_d = (mie_q & ~mask) | (csr_wdata & mask); end else begin @@ -2566,7 +2571,7 @@ module csr_regfile vsepc_q <= {riscv::XLEN{1'b0}}; vscause_q <= {riscv::XLEN{1'b0}}; vstvec_q <= {riscv::XLEN{1'b0}}; - vstvt_q <= {(riscv::XLEN-9){1'b0}}; + vstvt_q <= {(riscv::XLEN - 9) {1'b0}}; vsscratch_q <= {riscv::XLEN{1'b0}}; vstval_q <= {riscv::XLEN{1'b0}}; vsatp_q <= {riscv::XLEN{1'b0}}; @@ -2633,7 +2638,7 @@ module csr_regfile scounteren_q <= scounteren_d; sscratch_q <= sscratch_d; if (CVA6Cfg.TvalEn) stval_q <= stval_d; - satp_q <= satp_d; + satp_q <= satp_d; stvt_q <= stvt_d; sintthresh_q <= sintthresh_d; end diff --git a/core/cva6_clic_controller.sv b/core/cva6_clic_controller.sv index 23544442ec..a4744300ee 100644 --- a/core/cva6_clic_controller.sv +++ b/core/cva6_clic_controller.sv @@ -67,26 +67,26 @@ module cva6_clic_controller #( clic_irq_req_o = clic_irq_valid_i; // Take S-mode interrupts with higher level end else if (clic_irq_priv_i == riscv::PRIV_LVL_S) begin - if (CVA6Cfg.RVH && v_i) begin // Hart currently in VS-mode - if (CVA6Cfg.RVVCLIC && clic_irq_v_i) begin // Virtual supervisor interrrupt + if (CVA6Cfg.RVH && v_i) begin // Hart currently in VS-mode + if (CVA6Cfg.RVVCLIC && clic_irq_v_i) begin // Virtual supervisor interrrupt if (clic_irq_vsid_i == irq_ctrl_i.vgein) begin // VS-mode interrupt is for currently running VS clic_irq_req_o = (clic_irq_level_i > max_vsthresh) && (clic_irq_valid_i) && irq_ctrl_i.sie; clic_irq_v = 1'b1; - end else begin // Received interrupt is delegated to a differet VS + end else begin // Received interrupt is delegated to a differet VS // Trap to HS-mode iff HIE.sgeie is set and HGEIE[vsid] is set clic_irq_req_o = (clic_irq_valid_i) && sgeie && irq_ctrl_i.hgeie[clic_irq_vsid_i]; end - end else begin // Hypervisor interrupt + end else begin // Hypervisor interrupt clic_irq_req_o = (clic_irq_level_i > max_sthresh) && (clic_irq_valid_i); // HS-mode sie is implicitly enabled in VS-mode end - end else begin // Hart currently in (H)S-mode - if (CVA6Cfg.RVVCLIC && clic_irq_v_i) begin // Virtual supervisor interrrupt + end else begin // Hart currently in (H)S-mode + if (CVA6Cfg.RVVCLIC && clic_irq_v_i) begin // Virtual supervisor interrrupt // The current custom vCLIC implementation does not provide a way to the hypervisor to set interrupt levels // to interrupts delegated to VS-mode. The incoming interrupt level is therefore ignored if the hart is running // in HS-mode and a VS-mode interrupt is taken iff both HIE.sgeie and HGEIE[vsid] bits are set (and interrupts // are globally enabled at supervisor level (i.e. MSTATUS.sie bit is set) clic_irq_req_o = (clic_irq_valid_i) && sgeie && irq_ctrl_i.hgeie[clic_irq_vsid_i] && irq_ctrl_i.sie; - end else begin // (Host) Supervisor interrupt + end else begin // (Host) Supervisor interrupt clic_irq_req_o = (clic_irq_level_i > max_sthresh) && (clic_irq_valid_i) && irq_ctrl_i.sie; end end @@ -102,17 +102,17 @@ module cva6_clic_controller #( if (clic_irq_vsid_i == irq_ctrl_i.vgein) begin // VS-mode interrupt is for currently running VS clic_irq_req_o = clic_irq_valid_i; clic_irq_v = 1'b1; - end else begin // Received interrupt is delegated to a differet VS + end else begin // Received interrupt is delegated to a differet VS // Trap to HS-mode iff HIE.sgeie is set and HGEIE[vsid] is set clic_irq_req_o = (clic_irq_valid_i) && sgeie && irq_ctrl_i.hgeie[clic_irq_vsid_i]; end - end else begin // Hypervisor interrupt + end else begin // Hypervisor interrupt clic_irq_req_o = clic_irq_valid_i; // MSTATUS.sie is implicitly enabled in VU-mode end end else begin // Hart currently in U-mode - if (CVA6Cfg.RVVCLIC && clic_irq_v_i) begin // Virtual supervisor interrrupt + if (CVA6Cfg.RVVCLIC && clic_irq_v_i) begin // Virtual supervisor interrrupt clic_irq_req_o = (clic_irq_valid_i) && sgeie && irq_ctrl_i.hgeie[clic_irq_vsid_i]; // MSTATUS.sie is implicitly enabled in U-mode - end else begin // (Host) Supervisor interrupt + end else begin // (Host) Supervisor interrupt clic_irq_req_o = clic_irq_valid_i; // HS-mode sie is implicitly enabled in U-mode end end diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 4a53377200..437056dd71 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -290,8 +290,8 @@ package ariane_pkg; riscv::xlen_t mip; riscv::xlen_t mideleg; riscv::xlen_t hideleg; - riscv::xlen_t hgeie; // Hypervisor Guest External Interrupt Enable (HGEIE) register - logic [5:0] vgein; // Virtual Guest external interrupt number (HSTATUS register) + riscv::xlen_t hgeie; // Hypervisor Guest External Interrupt Enable (HGEIE) register + logic [5:0] vgein; // Virtual Guest external interrupt number (HSTATUS register) logic sie; logic global_enable; } irq_ctrl_t;