[FIX] m/sret optimization #35
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Thanks @ezelioli! Did you observe a performance improvements for your use case? |
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Yes, that indeed avoids the deterministic icache misses I was experiencing when returning from interrupt service routines, which was increasing the pipeline recover time after an ISR from 6 to over 30 cycles. |
niwis
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Aug 11, 2023
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Great! LGTM. Would you mind opening the same PR upstream? https://github.com/openhwgroup/cva6
niwis
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Apr 25, 2024
* I-cache generats snoop read requests + fix in cache_ctrl to avoid deadlock * update ace lib * add WB w/ H config * revert read requests from the I-cache are forwarded to all D-caches * partial merge from origin/culsans_pulp * Bump ace --------- Co-authored-by: Massimiliano Giacometti <[email protected]>
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Treat m/sret operations as direct jumps to PC + 0 when computing the npc_d. This avoids polluting the cache with useless instructions, and generating spurious icache misses.