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fix add signal otherwise the chesire build will fail analyze #310: Commit 837754d pushed by Lura518
November 30, 2024 18:45 13s smmu-raroth
smmu-raroth
November 30, 2024 18:45 13s
fix typo analyze #309: Commit f6ae9be pushed by Lura518
November 30, 2024 18:30 12s smmu-raroth
smmu-raroth
November 30, 2024 18:30 12s
WIP adding dummy register to prevent that the core register update wr… analyze #308: Commit 365f500 pushed by Lura518
November 30, 2024 18:16 10s smmu-raroth
smmu-raroth
November 30, 2024 18:16 10s
add rw idma variant analyze #307: Commit 0110aca pushed by LuziLucia
November 28, 2024 15:12 12s luzil/interl
luzil/interl
November 28, 2024 15:12 12s
fix lowercase register names analyze #306: Commit 864e6af pushed by Lura518
November 28, 2024 10:45 10s smmu-raroth
smmu-raroth
November 28, 2024 10:45 10s
fix (reg-tpl) Signals not found - Use the .q subfield analyze #305: Commit 85c45ac pushed by Lura518
November 28, 2024 09:39 13s smmu-raroth
smmu-raroth
November 28, 2024 09:39 13s
smmu: typo while port declaration analyze #304: Commit 3fd1570 pushed by Lura518
November 27, 2024 10:12 10s smmu-raroth
smmu-raroth
November 27, 2024 10:12 10s
smmu: allows to access the sMMU Options register analyze #303: Commit 2a28a2b pushed by Lura518
November 27, 2024 10:08 13s smmu-raroth
smmu-raroth
November 27, 2024 10:08 13s
Added Register to support the stream MMU extension. analyze #302: Commit 3cd6e65 pushed by Lura518
November 27, 2024 09:04 14s smmu-raroth
smmu-raroth
November 27, 2024 09:04 14s
[fix] width arrays, mismatch ports correction analyze #301: Commit d99955a pushed by DanielKellerM
November 26, 2024 10:46 10s dkeller/chimera
dkeller/chimera
November 26, 2024 10:46 10s
Patch for VCS analyze #300: Commit bde568e pushed by Scheremo
November 19, 2024 10:55 14s scheremo/32b
scheremo/32b
November 19, 2024 10:55 14s
Patch for 32 Bit systems analyze #299: Commit 975016f pushed by Scheremo
November 18, 2024 10:35 13s scheremo/32b
scheremo/32b
November 18, 2024 10:35 13s
Remove non-required configs analyze #298: Commit d15cf7e pushed by thommythomaso
November 11, 2024 13:50 10s neopxdma-tbenz
neopxdma-tbenz
November 11, 2024 13:50 10s
Add small IO DMA configs analyze #297: Commit bf3174d pushed by thommythomaso
November 6, 2024 15:57 14s iodma-tbenz
iodma-tbenz
November 6, 2024 15:57 14s
src: Add multicast capabilities to Snitch DMA analyze #296: Pull request #60 opened by colluca
September 26, 2024 14:53 18s mcast
mcast
September 26, 2024 14:53 18s
src: Add multicast capabilities to Snitch DMA analyze #295: Commit 8fe5b03 pushed by colluca
September 26, 2024 14:42 13s mcast
mcast
September 26, 2024 14:42 13s
Restore tracing in Snitch DMA analyze #294: Pull request #52 synchronize by fischeti
August 28, 2024 07:25 2m 44s snitch-tracing
snitch-tracing
August 28, 2024 07:25 2m 44s
src: Guard tracing logic during synthesis (#58) analyze #293: Commit 9cbcd30 pushed by fischeti
August 28, 2024 07:25 2m 34s snitch-tracing
snitch-tracing
August 28, 2024 07:25 2m 34s
src: Guard tracing logic during synthesis analyze #292: Pull request #58 opened by fischeti
August 28, 2024 07:24 27s fix-snitch-tracing
fix-snitch-tracing
August 28, 2024 07:24 27s
src: Guard tracing logic during synthesis analyze #291: Commit 5273ab7 pushed by fischeti
August 28, 2024 07:22 2m 37s fix-snitch-tracing
fix-snitch-tracing
August 28, 2024 07:22 2m 37s
Add inst64 32 bit bypasses analyze #290: Commit 9edf489 pushed by Scheremo
August 12, 2024 15:44 2m 39s scheremo/32b_fixes
scheremo/32b_fixes
August 12, 2024 15:44 2m 39s
INIT read: Only assign buffer_in_valid_o if datapath req valid analyze #289: Pull request #57 opened by micprog
August 6, 2024 14:33 9m 34s michaero/init_read_buffer
michaero/init_read_buffer
August 6, 2024 14:33 9m 34s
Support multiple protocols with reg frontend analyze #288: Pull request #56 synchronize by micprog
August 6, 2024 14:33 5m 0s michaero/reg_multistream
michaero/reg_multistream
August 6, 2024 14:33 5m 0s
Multistream register frontend: Fix number of protocol bits and location analyze #287: Commit 0e45b5a pushed by micprog
August 6, 2024 14:33 3m 15s michaero/reg_multistream
michaero/reg_multistream
August 6, 2024 14:33 3m 15s
INIT read: Only assign buffer_in_valid_o if datapath req valid analyze #286: Commit 81e0ca7 pushed by micprog
August 6, 2024 14:32 3m 28s michaero/init_read_buffer
michaero/init_read_buffer
August 6, 2024 14:32 3m 28s