diff --git a/jobs/jobs.json b/jobs/jobs.json index e09ccdbf..3554dfc3 100644 --- a/jobs/jobs.json +++ b/jobs/jobs.json @@ -199,6 +199,20 @@ "simple" : "backend_rw_axi/simple.txt" }, "params" : { + "DataWidth" : 32, + "AddrWidth" : 32, + "UserWidth" : 1, + "AxiIdWidth" : 12, + "NumAxInFlight" : 3, + "BufferDepth" : 3, + "TFLenWidth" : 32, + "MemSysDepth" : 0, + "CombinedShifter" : 0, + "MaskInvalidData" : 1, + "RAWCouplingAvail" : 0, + "HardwareLegalizer" : 1, + "RejectZeroTransfers" : 1, + "ErrorHandling" : 0 }, "proc_id" : "rw_axi_rw_axis", "testbench" : "tb_idma_backend_rw_axi_rw_axis", diff --git a/src/backend/idma_axis_read.sv b/src/backend/idma_axis_read.sv index 11eb3b61..36002be7 100644 --- a/src/backend/idma_axis_read.sv +++ b/src/backend/idma_axis_read.sv @@ -50,9 +50,9 @@ module idma_axis_read #( output logic read_meta_ready_o, /// AXI Stream read manager port request - output read_req_t read_req_o, + input read_req_t read_req_i, /// AXI Stream read manager port response - input read_rsp_t read_rsp_i, + output read_rsp_t read_rsp_o, /// Response channel valid and ready output logic r_chan_ready_o, @@ -105,7 +105,7 @@ module idma_axis_read #( // a barrel shifter is a concatenation of the same array with twice and a normal // shift. Optimized for Synopsys DesignWare. - assign buffer_in_o = read_rsp_i.t.data; + assign buffer_in_o = read_req_i.t.data; assign mask_in = {read_aligned_in_mask, read_aligned_in_mask} >> r_dp_req_i.shift; @@ -115,17 +115,17 @@ module idma_axis_read #( // the buffer can be pushed to if all the masked FIFO buffers (mask_in) are ready. assign in_ready = &(buffer_in_ready_i | ~mask_in); // the read can accept data if the buffer is ready and the response channel is ready - assign read_req_o.tready = in_ready & r_dp_rsp_ready_i & r_dp_req_valid_i; + assign read_rsp_o.tready = in_ready & r_dp_rsp_ready_i & r_dp_req_valid_i; // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.tvalid & in_ready & r_dp_rsp_ready_i; + assign in_valid = read_req_i.tvalid & in_ready & r_dp_rsp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read - assign r_dp_req_ready_o = r_dp_req_valid_i & r_dp_rsp_ready_i & read_rsp_i.tvalid & in_ready; - assign r_chan_ready_o = read_req_o.tready; - assign r_chan_valid_o = read_rsp_i.tvalid; + assign r_dp_req_ready_o = r_dp_req_valid_i & r_dp_rsp_ready_i & read_req_i.tvalid & in_ready; + assign r_chan_ready_o = read_rsp_o.tready; + assign r_chan_valid_o = read_req_i.tvalid; // connect r_dp response payload assign r_dp_rsp_o.resp = '0; @@ -133,6 +133,6 @@ module idma_axis_read #( assign r_dp_rsp_o.first = 1'b1; // r_dp_valid_o is triggered once the last element is here or an error occurs - assign r_dp_rsp_valid_o = read_rsp_i.tvalid & in_ready; + assign r_dp_rsp_valid_o = read_req_i.tvalid & in_ready; endmodule diff --git a/src/backend/idma_axis_write.sv b/src/backend/idma_axis_write.sv index d5982f7a..d4e9f7bc 100644 --- a/src/backend/idma_axis_write.sv +++ b/src/backend/idma_axis_write.sv @@ -124,7 +124,7 @@ module idma_axis_write #( // always_comb process implements masking of invalid data always_comb begin : proc_mask // defaults - write_req_o.t = aw_req_i.axi_stream.t_chan; + write_req_o.t = aw_req_i.axis.t_chan; buffer_data_masked = '0; // control the write to the bus apply data to the bus only if data should be written if (ready_to_write == 1'b1 & !dp_poison_i) begin @@ -143,7 +143,7 @@ module idma_axis_write #( // not used signal assign buffer_data_masked = '0; // simpler: direct connection - assign write_req_o.t = aw_req_i.axi_stream.t_chan; + assign write_req_o.t = aw_req_i.axis.t_chan; assign write_req_o.t.data = buffer_out_i; assign write_req_o.t.keep = dp_poison_i ? '0 : mask_out; end diff --git a/src/backend/tpl/idma_backend.sv.tpl b/src/backend/tpl/idma_backend.sv.tpl index f74caad3..9279a91c 100644 --- a/src/backend/tpl/idma_backend.sv.tpl +++ b/src/backend/tpl/idma_backend.sv.tpl @@ -122,17 +122,33 @@ module idma_backend_${name_uniqueifier} #( % for protocol in used_read_protocols: /// ${database[protocol]['full_name']} read request +% if database[protocol]['passive_req'] == 'true': + input ${protocol}\ +% if database[protocol]['read_slave'] == 'true': +_read\ +% endif +_req_t ${protocol}_read_req_i, +% else: output ${protocol}\ % if database[protocol]['read_slave'] == 'true': _read\ % endif _req_t ${protocol}_read_req_o, +% endif /// ${database[protocol]['full_name']} read response +% if database[protocol]['passive_req'] == 'true': + output ${protocol}\ +% if database[protocol]['read_slave'] == 'true': +_read\ +% endif +_rsp_t ${protocol}_read_rsp_o, +% else: input ${protocol}\ % if database[protocol]['read_slave'] == 'true': _read\ % endif _rsp_t ${protocol}_read_rsp_i, +% endif % endfor % for protocol in used_write_protocols: @@ -713,8 +729,13 @@ _rsp_t ${protocol}_write_rsp_i, .testmode_i ( testmode_i )\ % for protocol in used_read_protocols: , +% if database[protocol]['passive_req'] == 'true': + .${protocol}_read_req_i ( ${protocol}_read_req_i ), + .${protocol}_read_rsp_o ( ${protocol}_read_rsp_o )\ +% else: .${protocol}_read_req_o ( ${protocol}_read_req_o ), .${protocol}_read_rsp_i ( ${protocol}_read_rsp_i )\ +% endif % endfor % for protocol in used_write_protocols: , diff --git a/src/backend/tpl/idma_backend_synth.sv.tpl b/src/backend/tpl/idma_backend_synth.sv.tpl index a2fd3b0d..df99fdf7 100644 --- a/src/backend/tpl/idma_backend_synth.sv.tpl +++ b/src/backend/tpl/idma_backend_synth.sv.tpl @@ -338,8 +338,13 @@ ${p}_${database[p]['write_meta_channel']}_width\ .eh_req_ready_o ( eh_req_ready_o )\ % for protocol in used_read_protocols: , +% if database[protocol]['passive_req'] == 'true': + .${protocol}_read_req_i ( ${protocol}_read_req ), + .${protocol}_read_rsp_o ( ${protocol}_read_rsp )\ +% else: .${protocol}_read_req_o ( ${protocol}_read_req ), .${protocol}_read_rsp_i ( ${protocol}_read_rsp )\ +% endif % endfor % for protocol in used_write_protocols: , diff --git a/src/backend/tpl/idma_transport_layer.sv.tpl b/src/backend/tpl/idma_transport_layer.sv.tpl index a9e1d59b..28b4a0f4 100644 --- a/src/backend/tpl/idma_transport_layer.sv.tpl +++ b/src/backend/tpl/idma_transport_layer.sv.tpl @@ -75,17 +75,33 @@ module idma_transport_layer_${name_uniqueifier} #( % for protocol in used_read_protocols: /// ${database[protocol]['full_name']} read request +% if database[protocol]['passive_req'] == 'true': + input ${protocol}\ +% if database[protocol]['read_slave'] == 'true': +_read\ +% endif +_req_t ${protocol}_read_req_i, +% else: output ${protocol}\ % if database[protocol]['read_slave'] == 'true': _read\ % endif _req_t ${protocol}_read_req_o, +% endif /// ${database[protocol]['full_name']} read response +% if database[protocol]['passive_req'] == 'true': + output ${protocol}\ +% if database[protocol]['read_slave'] == 'true': +_read\ +% endif +_rsp_t ${protocol}_read_rsp_o, +% else: input ${protocol}\ % if database[protocol]['read_slave'] == 'true': _read\ % endif _rsp_t ${protocol}_read_rsp_i, +% endif % endfor % for protocol in used_write_protocols: diff --git a/src/db/idma_axi.yml b/src/db/idma_axi.yml index 5e4c5f22..c80096e1 100644 --- a/src/db/idma_axi.yml +++ b/src/db/idma_axi.yml @@ -17,6 +17,7 @@ read_meta_channel: "ar_chan" write_meta_channel: "aw_chan" combined_aw_and_w: "false" read_slave: "false" +passive_req: "false" read_meta_channel_width: "localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth);" write_meta_channel_width: "localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth);" typedefs: | diff --git a/src/db/idma_axi_lite.yml b/src/db/idma_axi_lite.yml index 16623d2d..be959e1f 100644 --- a/src/db/idma_axi_lite.yml +++ b/src/db/idma_axi_lite.yml @@ -15,6 +15,7 @@ read_meta_channel: "ar_chan" write_meta_channel: "aw_chan" combined_aw_and_w: "false" read_slave: "false" +passive_req: "false" read_meta_channel_width: | "localparam int unsigned axi_lite_ar_chan_width = $bits(axi_lite_ar_chan_t);" write_meta_channel_width: | diff --git a/src/db/idma_axi_stream.yml b/src/db/idma_axi_stream.yml index ec4b5af3..7b91c69b 100644 --- a/src/db/idma_axi_stream.yml +++ b/src/db/idma_axi_stream.yml @@ -14,7 +14,8 @@ legalizer_force_decouple: "false" write_meta_channel: "t_chan" read_meta_channel: "t_chan" combined_aw_and_w: "true" -read_slave: "true" +read_slave: "false" +passive_req: "true" meta_channel_width: "localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t);" typedefs: | `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t) @@ -23,17 +24,18 @@ typedefs: | `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axis_rsp_t) read_bridge_template: | // AXI Stream to OBI Read Bridge - obi_req_t axi_stream_obi_read_req; - obi_rsp_t axi_stream_obi_read_rsp; + obi_req_t axis_obi_read_req; + obi_rsp_t axis_obi_read_rsp; - assign axi_stream_obi_read_req.a.we = 1'b0; - assign axi_stream_obi_read_req.a.wdata = '0; - assign axi_stream_obi_read_req.a.be = '1; + assign axis_obi_read_req.a.we = 1'b0; + assign axis_obi_read_req.a.wdata = '0; + assign axis_obi_read_req.a.be = '1; - assign axi_stream_obi_read_req.r_ready = axis_read_req.tvalid; - assign axis_read_rsp.tready = axi_stream_obi_read_rsp.r_valid; + assign axis_obi_read_req.r_ready = axis_read_rsp.tready; + assign axis_read_req.tvalid = axis_obi_read_rsp.r_valid; always_comb begin - axis_read_req.t.data = axi_stream_obi_read_rsp.r.rdata; + axis_read_req.t = '0; + axis_read_req.t.data = axis_obi_read_rsp.r.rdata; end int unsigned launched_axis_jobs; @@ -82,21 +84,21 @@ read_bridge_template: | while(axis_jobs.size() > 0) begin current_job = axis_jobs.pop_front(); address = { current_job.src_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }; - axi_stream_obi_read_req.a_req = 1'b0; - axi_stream_obi_read_req.a.aid = current_job.id; + axis_obi_read_req.a_req = 1'b0; + axis_obi_read_req.a.aid = current_job.id; // Wait for launch of job wait(launched_axis_jobs > 0); launched_axis_jobs--; while(address < (current_job.src_addr + current_job.length)) begin - axi_stream_obi_read_req.a.addr = address; - axi_stream_obi_read_req.a_req = 1'b1; + axis_obi_read_req.a.addr = address; + axis_obi_read_req.a_req = 1'b1; @(posedge clk); - if(axi_stream_obi_read_rsp.a_gnt && axi_stream_obi_read_req.a_req) begin + if(axis_obi_read_rsp.a_gnt && axis_obi_read_req.a_req) begin address += StrbWidth; end end - axi_stream_obi_read_req.a_req = 1'b0; + axis_obi_read_req.a_req = 1'b0; end end @@ -110,27 +112,27 @@ read_bridge_template: | .obi_rsp_t ( obi_rsp_t ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) - ) i_axi_stream_obi2axi_bridge_read ( + ) i_axis_obi2axi_bridge_read ( .clk_i ( clk ), .rst_ni ( rst_n ), - .obi_req_i ( axi_stream_obi_read_req ), - .obi_rsp_o ( axi_stream_obi_read_rsp ), - .axi_req_o ( axi_stream_axi_read_req ), - .axi_rsp_i ( axi_stream_axi_read_rsp ) + .obi_req_i ( axis_obi_read_req ), + .obi_rsp_o ( axis_obi_read_rsp ), + .axi_req_o ( axis_axi_read_req ), + .axi_rsp_i ( axis_axi_read_rsp ) ); write_bridge_template: | // AXI Stream to OBI Write Bridge - obi_req_t axi_stream_obi_write_req; - obi_rsp_t axi_stream_obi_write_rsp; + obi_req_t axis_obi_write_req; + obi_rsp_t axis_obi_write_rsp; - assign axi_stream_obi_write_req.a_req = axis_write_req.tvalid; - assign axi_stream_obi_write_req.a.we = 1'b1; - assign axi_stream_obi_write_req.a.wdata = axis_write_req.t.data; - assign axi_stream_obi_write_req.a.be = axis_write_req.t.keep; - assign axi_stream_obi_write_req.a.aid = axis_write_req.t.id; - assign axi_stream_obi_write_req.r_ready = 1'b1; + assign axis_obi_write_req.a_req = axis_write_req.tvalid; + assign axis_obi_write_req.a.we = 1'b1; + assign axis_obi_write_req.a.wdata = axis_write_req.t.data; + assign axis_obi_write_req.a.be = axis_write_req.t.keep; + assign axis_obi_write_req.a.aid = axis_write_req.t.id; + assign axis_obi_write_req.r_ready = 1'b1; - assign axis_write_rsp.tready = axi_stream_obi_write_rsp.a_gnt; + assign axis_write_rsp.tready = axis_obi_write_rsp.a_gnt; initial begin string job_file; @@ -168,7 +170,7 @@ write_bridge_template: | while(axis_jobs.size() > 0) begin current_job = axis_jobs.pop_front(); address = { current_job.dst_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }; - axi_stream_obi_write_req.a.addr = address; + axis_obi_write_req.a.addr = address; // Wait for first write wait(axis_write_req.tvalid); @@ -180,7 +182,7 @@ write_bridge_template: | // Increment address address += StrbWidth; - axi_stream_obi_write_req.a.addr = address; + axis_obi_write_req.a.addr = address; end end end @@ -196,25 +198,25 @@ write_bridge_template: | .obi_rsp_t ( obi_rsp_t ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) - ) i_axi_stream_obi2axi_bridge_write ( + ) i_axis_obi2axi_bridge_write ( .clk_i ( clk ), .rst_ni ( rst_n ), - .obi_req_i ( axi_stream_obi_write_req ), - .obi_rsp_o ( axi_stream_obi_write_rsp ), - .axi_req_o ( axi_stream_axi_write_req ), - .axi_rsp_i ( axi_stream_axi_write_rsp ) + .obi_req_i ( axis_obi_write_req ), + .obi_rsp_o ( axis_obi_write_rsp ), + .axi_req_o ( axis_axi_write_req ), + .axi_rsp_i ( axis_axi_write_rsp ) ); legalizer_read_meta_channel: | r_req_o.ar_req = '0; legalizer_write_meta_channel: | - w_req_o.aw_req.axi_stream.t_chan = '{ + w_req_o.aw_req.axis.t_chan = '{ data: '0, strb: '1, keep: '0, last: w_tf_q.length == w_num_bytes, id: opt_tf_q.axi_id, - dest: w_tf_q.base_addr[$bits(w_req_o.aw_req.axi_stream.t_chan.dest)-1:0], - user: w_tf_q.base_addr[$bits(w_req_o.aw_req.axi_stream.t_chan.user)-1+:$bits(w_req_o.aw_req.axi_stream.t_chan.dest)] + dest: w_tf_q.base_addr[$bits(w_req_o.aw_req.axis.t_chan.dest)-1:0], + user: w_tf_q.base_addr[$bits(w_req_o.aw_req.axis.t_chan.user)-1+:$bits(w_req_o.aw_req.axis.t_chan.dest)] }; read_template: | idma_axis_read #( @@ -236,8 +238,8 @@ read_template: | .read_meta_req_i ( ${read_meta_request} ), .read_meta_valid_i ( ${read_meta_valid} ), .read_meta_ready_o ( ${read_meta_ready} ), - .read_req_o ( ${read_request} ), - .read_rsp_i ( ${read_response} ), + .read_req_i ( ${read_request} ), + .read_rsp_o ( ${read_response} ), .r_chan_valid_o ( ${r_chan_valid} ), .r_chan_ready_o ( ${r_chan_ready} ), .buffer_in_o ( ${buffer_in} ), @@ -276,57 +278,57 @@ write_template: | .buffer_out_ready_o ( ${buffer_out_ready} ) ); synth_wrapper_ports_read: | - input data_t axi_stream_read_data_i, - input strb_t axi_stream_read_strb_i, - input strb_t axi_stream_read_keep_i, - input logic axi_stream_read_last_i, - input id_t axi_stream_read_id_i, - input id_t axi_stream_read_dest_i, - input user_t axi_stream_read_user_i, - input logic axi_stream_read_tvalid_i, + input data_t axis_read_data_i, + input strb_t axis_read_strb_i, + input strb_t axis_read_keep_i, + input logic axis_read_last_i, + input id_t axis_read_id_i, + input id_t axis_read_dest_i, + input user_t axis_read_user_i, + input logic axis_read_tvalid_i, - output logic axi_stream_read_tready_o, + output logic axis_read_tready_o, synth_wrapper_ports_write: | - output data_t axi_stream_write_data_o, - output strb_t axi_stream_write_strb_o, - output strb_t axi_stream_write_keep_o, - output logic axi_stream_write_last_o, - output id_t axi_stream_write_id_o, - output id_t axi_stream_write_dest_o, - output user_t axi_stream_write_user_o, - output logic axi_stream_write_tvalid_o, + output data_t axis_write_data_o, + output strb_t axis_write_strb_o, + output strb_t axis_write_keep_o, + output logic axis_write_last_o, + output id_t axis_write_id_o, + output id_t axis_write_dest_o, + output user_t axis_write_user_o, + output logic axis_write_tvalid_o, - input logic axi_stream_write_tready_i, + input logic axis_write_tready_i, synth_wrapper_assign_read: | - assign axi_stream_read_rsp.t.data = axi_stream_read_data_i; - assign axi_stream_read_rsp.t.strb = axi_stream_read_strb_i; - assign axi_stream_read_rsp.t.keep = axi_stream_read_keep_i; - assign axi_stream_read_rsp.t.last = axi_stream_read_last_i; - assign axi_stream_read_rsp.t.id = axi_stream_read_id_i; - assign axi_stream_read_rsp.t.dest = axi_stream_read_dest_i; - assign axi_stream_read_rsp.t.user = axi_stream_read_user_i; - assign axi_stream_read_rsp.tvalid = axi_stream_read_tvalid_i; + assign axis_read_req.t.data = axis_read_data_i; + assign axis_read_req.t.strb = axis_read_strb_i; + assign axis_read_req.t.keep = axis_read_keep_i; + assign axis_read_req.t.last = axis_read_last_i; + assign axis_read_req.t.id = axis_read_id_i; + assign axis_read_req.t.dest = axis_read_dest_i; + assign axis_read_req.t.user = axis_read_user_i; + assign axis_read_req.tvalid = axis_read_tvalid_i; - assign axi_stream_read_tready_o = axi_stream_read_req.tready; + assign axis_read_tready_o = axis_read_rsp.tready; synth_wrapper_assign_write: | - assign axi_stream_write_data_o = axi_stream_write_req.t.data; - assign axi_stream_write_strb_o = axi_stream_write_req.t.strb; - assign axi_stream_write_keep_o = axi_stream_write_req.t.keep; - assign axi_stream_write_last_o = axi_stream_write_req.t.last; - assign axi_stream_write_id_o = axi_stream_write_req.t.id; - assign axi_stream_write_dest_o = axi_stream_write_req.t.dest; - assign axi_stream_write_user_o = axi_stream_write_req.t.user; - assign axi_stream_write_tvalid_o = axi_stream_write_req.tvalid; + assign axis_write_data_o = axis_write_req.t.data; + assign axis_write_strb_o = axis_write_req.t.strb; + assign axis_write_keep_o = axis_write_req.t.keep; + assign axis_write_last_o = axis_write_req.t.last; + assign axis_write_id_o = axis_write_req.t.id; + assign axis_write_dest_o = axis_write_req.t.dest; + assign axis_write_user_o = axis_write_req.t.user; + assign axis_write_tvalid_o = axis_write_req.tvalid; - assign axi_stream_write_rsp.tready = axi_stream_write_tready_i; + assign axis_write_rsp.tready = axis_write_tready_i; trace_signals: read: rsp: - valid: axi_stream_read_rsp_i.tvalid - ready: axi_stream_read_req_o.tready - strobe: axi_stream_read_rsp_i.t.strb + valid: axis_read_req_i.tvalid + ready: axis_read_rsp_o.tready + strobe: axis_read_req_i.t.strb write: req: - valid: axi_stream_write_req_o.tvalid - ready: axi_stream_write_rsp_i.tready - strobe: axi_stream_write_req_o.t.strb + valid: axis_write_req_o.tvalid + ready: axis_write_rsp_i.tready + strobe: axis_write_req_o.t.strb diff --git a/src/db/idma_init.yml b/src/db/idma_init.yml index 09efc745..35e40911 100644 --- a/src/db/idma_init.yml +++ b/src/db/idma_init.yml @@ -16,6 +16,7 @@ write_meta_channel: "req_chan" meta_channel_width: "localparam int unsigned init_req_chan_width = $bits(init_req_chan_t);" combined_aw_and_w: "false" read_slave: "false" +passive_req: "false" typedefs: | /// init read request typedef struct packed { diff --git a/src/db/idma_obi.yml b/src/db/idma_obi.yml index e26e6508..c2b44b19 100644 --- a/src/db/idma_obi.yml +++ b/src/db/idma_obi.yml @@ -15,6 +15,7 @@ read_meta_channel: "a_chan" write_meta_channel: "a_chan" combined_aw_and_w: "true" read_slave: "false" +passive_req: "false" meta_channel_width: "localparam int unsigned obi_a_chan_width = $bits(obi_a_chan_t);" typedefs: | `IDMA_OBI_TYPEDEF_A_CHAN_T(obi_a_chan_t, addr_t, data_t, strb_t, id_t) diff --git a/src/db/idma_tilelink.yml b/src/db/idma_tilelink.yml index 7838be18..82c263bf 100644 --- a/src/db/idma_tilelink.yml +++ b/src/db/idma_tilelink.yml @@ -18,6 +18,7 @@ write_meta_channel: "a_chan" meta_channel_width: "localparam int unsigned tilelink_a_chan_width = $bits(tilelink_a_chan_t);" combined_aw_and_w: "true" read_slave: "false" +passive_req: "false" # logic[3:0] is the size field, is 4 bit as we're limited by the TLToAXI4 Bridge typedefs: | `IDMA_TILELINK_TYPEDEF_A_CHAN_T(tilelink_a_chan_t, addr_t, data_t, strb_t, logic[3:0], logic[4:0]) diff --git a/test/include/tb_tasks.svh b/test/include/tb_tasks.svh index cf54d728..e8f223a3 100644 --- a/test/include/tb_tasks.svh +++ b/test/include/tb_tasks.svh @@ -159,7 +159,7 @@ `ifdef PROT_AXI4_STREAM // write a byte to the AXI Stream AXI-attached memory - task write_byte_axi_stream_axi_mem ( + task write_byte_axis_axi_mem ( input byte_t byte_i, input addr_t addr_i ); @@ -167,7 +167,7 @@ endtask // read a byte from the AXI Stream AXI-attached memory - task read_byte_axi_stream_axi_mem ( + task read_byte_axis_axi_mem ( output byte_t byte_o, input addr_t addr_i ); @@ -178,7 +178,7 @@ endtask `else // write a byte to the AXI Stream AXI-attached memory - task write_byte_axi_stream_axi_mem ( + task write_byte_axis_axi_mem ( input byte_t byte_i, input addr_t addr_i ); @@ -186,7 +186,7 @@ endtask // read a byte from the AXI Stream AXI-attached memory - task read_byte_axi_stream_axi_mem ( + task read_byte_axis_axi_mem ( output byte_t byte_o, input addr_t addr_i ); @@ -238,7 +238,7 @@ idma_pkg::AXI_LITE: read_byte_axi_lite_axi_mem (data, addr_i + now); idma_pkg::OBI: read_byte_obi_axi_mem (data, addr_i + now); idma_pkg::TILELINK: read_byte_tilelink_axi_mem (data, addr_i + now); - idma_pkg::AXI_STREAM: read_byte_axi_stream_axi_mem(data, addr_i + now); + idma_pkg::AXI_STREAM: read_byte_axis_axi_mem(data, addr_i + now); idma_pkg::INIT: begin now++; continue; // Omit checks against INIT terminate events @@ -334,7 +334,7 @@ end idma_pkg::AXI_STREAM: begin model.write_byte ( ~{to_write[3:0], to_write[7:4]}, now_r.src_addr + now, idma_pkg::AXI_STREAM ); - write_byte_axi_stream_axi_mem ( ~{to_write[3:0], to_write[7:4]}, now_r.src_addr + now ); + write_byte_axis_axi_mem ( ~{to_write[3:0], to_write[7:4]}, now_r.src_addr + now ); end default: $fatal(1, "init_mem not implemented for used protocol!"); endcase diff --git a/test/tpl/tb_idma_backend.sv.tpl b/test/tpl/tb_idma_backend.sv.tpl index bbc5bc24..74b1b290 100644 --- a/test/tpl/tb_idma_backend.sv.tpl +++ b/test/tpl/tb_idma_backend.sv.tpl @@ -213,7 +213,7 @@ ${p}_${database[p]['write_meta_channel']}_width\ idma_rsp_t idma_rsp; logic rsp_valid; logic rsp_ready; -% if 'axi_stream' in used_write_protocols and False: +% if 'axis' in used_write_protocols and False: idma_rsp_t idma_rsp_w, idma_rsp_w2; logic rsp_valid_w, rsp_ready_w, rsp_valid_w2, rsp_ready_w2; % endif @@ -581,8 +581,13 @@ ${p}_${database[p]['write_meta_channel']}_width\ .eh_req_ready_o ( eh_req_ready )\ % for protocol in used_read_protocols: , +% if database[protocol]['passive_req'] == 'true': + .${protocol}_read_req_i ( ${protocol}_read_req ), + .${protocol}_read_rsp_o ( ${protocol}_read_rsp )\ +% else: .${protocol}_read_req_o ( ${protocol}_read_req ), .${protocol}_read_rsp_i ( ${protocol}_read_rsp )\ +% endif % endfor % for protocol in used_write_protocols: , @@ -612,7 +617,7 @@ ${p}_${database[p]['write_meta_channel']}_width\ //-------------------------------------- // TB connections //-------------------------------------- -% if 'axi_stream' in used_write_protocols and False: +% if 'axis' in used_write_protocols and False: // Delay iDMA response 2 cycles such that all axi stream writes are finished spill_register #( diff --git a/util/mario/transport_layer.py b/util/mario/transport_layer.py index d3ab3b5f..17a23a36 100644 --- a/util/mario/transport_layer.py +++ b/util/mario/transport_layer.py @@ -33,6 +33,13 @@ def render_read_mgr_inst(prot_id: str, prot_ids: dict, db: dict) -> dict: read_req_str = f'{rp}_req_t' read_rsp_str = f'{rp}_rsp_t' + if db[rp]['passive_req'] == 'true': + read_port_dir_req_str = 'i' + read_port_dir_rsp_str = 'o' + else: + read_port_dir_req_str = 'o' + read_port_dir_rsp_str = 'i' + if srp: read_dp_valid_in = 'r_dp_valid_i' read_dp_ready_out = 'r_dp_ready_o' @@ -78,8 +85,8 @@ def render_read_mgr_inst(prot_id: str, prot_ids: dict, db: dict) -> dict: 'read_meta_request': read_meta_request, 'read_meta_valid': read_meta_valid, 'read_meta_ready': read_meta_ready, - 'read_request': f'{rp}_read_req_o', - 'read_response': f'{rp}_read_rsp_i', + 'read_request': f'{rp}_read_req_{read_port_dir_req_str}', + 'read_response': f'{rp}_read_rsp_{read_port_dir_rsp_str}', 'r_chan_valid': r_chan_valid, 'r_chan_ready': r_chan_ready, 'buffer_in': buffer_in,