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[parameter] Correct DMA backend numbers for MemPool and TeraPool
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yichao-zh committed Nov 1, 2023
1 parent 643b22f commit b2866e6
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Showing 2 changed files with 5 additions and 2 deletions.
2 changes: 1 addition & 1 deletion config/config.mk
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ axi_data_width ?= 512
ro_line_width ?= 512

# Number of DMA backends in each group
dmas_per_group ?= 8
dmas_per_group ?= 4

#############################
## Xqueues configuration ##
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5 changes: 4 additions & 1 deletion config/terapool.mk
Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,13 @@ banking_factor ?= 4
remote_group_latency_cycles ?= 7

# Radix for hierarchical AXI interconnect
axi_hier_radix ?= 9
axi_hier_radix ?= 10

# Number of AXI masters per group
axi_masters_per_group ?= 4

# Number of DMA backends in each group
dmas_per_group ?= 8

# L2 Banks/Channels
l2_banks = 16

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