From b2866e643fe328a542c3209b83bb40c165f673d2 Mon Sep 17 00:00:00 2001
From: Yichao Zhang <yiczhang@iis.ee.ethz.ch>
Date: Wed, 1 Nov 2023 14:10:04 +0100
Subject: [PATCH] [parameter] Correct DMA backend numbers for MemPool and
 TeraPool

---
 config/config.mk   | 2 +-
 config/terapool.mk | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/config/config.mk b/config/config.mk
index a3b134fc2..0b424a1be 100644
--- a/config/config.mk
+++ b/config/config.mk
@@ -50,7 +50,7 @@ axi_data_width ?= 512
 ro_line_width ?= 512
 
 # Number of DMA backends in each group
-dmas_per_group ?= 8
+dmas_per_group ?= 4
 
 #############################
 ##  Xqueues configuration  ##
diff --git a/config/terapool.mk b/config/terapool.mk
index 4a28e6fb0..631fb6d83 100644
--- a/config/terapool.mk
+++ b/config/terapool.mk
@@ -31,10 +31,13 @@ banking_factor ?= 4
 remote_group_latency_cycles ?= 7
 
 # Radix for hierarchical AXI interconnect
-axi_hier_radix ?= 9
+axi_hier_radix ?= 10
 
 # Number of AXI masters per group
 axi_masters_per_group ?= 4
 
+# Number of DMA backends in each group
+dmas_per_group ?= 8
+
 # L2 Banks/Channels
 l2_banks = 16