Add pulp_cluster target

configs/pulp_cluster.sh

@@ -0,0 +1,16 @@
+#!/bin/bash -e
+
+export PULPRT_TARGET=pulp_cluster
+export PULPRUN_TARGET=pulp_cluster
+export CONFIG_NO_FC=1
+
+if [  -n "${ZSH_VERSION:-}" ]; then
+        DIR="$(readlink -f -- "${(%):-%x}")"
+        scriptDir="$(dirname $DIR)"
+else
+
+    scriptDir="$(dirname "$(readlink -f "${BASH_SOURCE[0]}")")"
+
+fi
+
+source $scriptDir/common.sh

include/archi/chips/pulp_cluster/apb_soc.h

@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARCHI_PULP_APB_SOC_H__
+#define __ARCHI_PULP_APB_SOC_H__
+
+#define APB_SOC_BOOT_OTHER    0
+#define APB_SOC_BOOT_JTAG     1
+#define APB_SOC_BOOT_SPI      2
+#define APB_SOC_BOOT_ROM      3
+#define APB_SOC_BOOT_PRELOAD  4
+#define APB_SOC_BOOT_HYPER    5
+#define APB_SOC_BOOT_SPIM     6
+#define APB_SOC_BOOT_SPIM_QPI 7
+
+#define APB_SOC_PLT_OTHER   0
+#define APB_SOC_PLT_FPGA    1
+#define APB_SOC_PLT_RTL     2
+#define APB_SOC_PLT_VP      3
+#define APB_SOC_PLT_CHIP    4
+
+//PADs configuration is made of 8bits out of which only the first 6 are used
+//bit0    enable pull UP
+//bit1    enable pull DOWN
+//bit2    enable ST
+//bit3    enable SlewRate Limit
+//bit4..5 Driving Strength
+//bit6..7 not used
+
+#define APB_SOC_BOOTADDR_OFFSET   0x04
+#define APB_SOC_INFO_OFFSET       0x00 //contains number of cores [31:16] and clusters [15:0]
+#define APB_SOC_INFOEXTD_OFFSET   0x04 //not used at the moment
+#define APB_SOC_NOTUSED0_OFFSET   0x08 //not used at the moment
+#define APB_SOC_CLUSTER_ISOLATE_OFFSET   0x0C //not used at the moment
+
+#define	APB_SOC_PADFUN0_OFFSET	  0x10
+#define	APB_SOC_PADCFG0_OFFSET	  0x20
+
+#define APB_SOC_PADFUN_OFFSET(g)   (APB_SOC_PADFUN0_OFFSET+(g)*4) //sets the mux for pins  g*16+0 (bits [1:0]) to g*16+15 (bits [31:30])
+#define APB_SOC_PADFUN_NO(pad)     ((pad) >> 4)
+#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16)
+#define APB_SOC_PADFUN_SIZE        2
+#define ARCHI_APB_SOC_PADFUN_NB          4
+#define APB_SOC_PADFUN_BIT(pad)    (((pad) & 0xF) << 1)
+
+#define APB_SOC_PADCFG_OFFSET(g)   (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin  g*4+0(bits [7:0]) to pin  g*4+3(bits [31:24])
+#define APB_SOC_PADCFG_NO(pad)     ((pad) >> 2)
+#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4)
+#define APB_SOC_PADCFG_SIZE        8
+#define APB_SOC_PADCFG_BIT(pad)    (((pad) & 0x3) << 3)
+
+#define APB_SOC_PWRCMD_OFFSET     0x60 //change power mode(not funtional yet)
+#define APB_SOC_PWRCFG_OFFSET     0x64 //configures power modes(not funtional yet)
+#define APB_SOC_PWRREG_OFFSET     0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot
+#define APB_SOC_BUSY_OFFSET       0x6C //not used at the moment
+#define APB_SOC_MMARGIN_OFFSET    0x70 //memory margin pins(not used at the moment)
+#define APB_SOC_JTAG_REG          0x74 // R/W register for interaction with the the chip environment
+#define APB_SOC_L2_SLEEP_OFFSET   0x78 //memory margin pins(not used at the moment)
+#define APB_SOC_NOTUSED3_OFFSET   0x7C //not used at the moment
+#define APB_SOC_CLKDIV0_OFFSET    0x80 //soc clock divider(to be removed)
+#define APB_SOC_CLKDIV1_OFFSET    0x84 //cluster clock divider(to be removed)
+#define APB_SOC_CLKDIV2_OFFSET    0x88 //not used at the moment
+#define APB_SOC_CLKDIV3_OFFSET    0x8C //not used at the moment
+#define APB_SOC_CLKDIV4_OFFSET    0x90 //not used at the moment
+#define APB_SOC_NOTUSED4_OFFSET   0x94 //not used at the moment
+#define APB_SOC_NOTUSED5_OFFSET   0x98 //not used at the moment
+#define APB_SOC_NOTUSED6_OFFSET   0x9C //not used at the moment
+#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
+#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
+#define APB_SOC_PADS_CONFIG       0xC4
+
+#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0
+
+#define APB_SOC_JTAG_REG_EXT_BIT   8
+#define APB_SOC_JTAG_REG_EXT_WIDTH 4
+
+#define APB_SOC_JTAG_REG_LOC_BIT   0
+#define APB_SOC_JTAG_REG_LOC_WIDTH 4
+
+#define APB_SOC_INFO_CORES_OFFSET    (APB_SOC_INFO_OFFSET + 2)
+#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET)
+
+#define APB_SOC_STATUS_EOC_BIT  31
+#define APB_SOC_NB_CORE_BIT     16
+
+
+#define APB_SOC_BYPASS_OFFSET   0x70
+
+#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10
+#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3
+#define APB_SOC_BYPASS_USER0_BIT       14
+#define APB_SOC_BYPASS_USER1_BIT       15
+
+
+#define APB_SOC_FLL_CTRL_OFFSET         0xD0
+#define APB_SOC_CLKDIV_SOC_OFFSET       0xD4
+#define APB_SOC_CLKDIV_CLUSTER_OFFSET   0xD8
+#define APB_SOC_CLKDIV_PERIPH_OFFSET    0xDC
+
+
+#define APB_SOC_FLL_CTRL_SOC_BIT        0
+#define APB_SOC_FLL_CTRL_CLUSTER_BIT    1
+#define APB_SOC_FLL_CTRL_PERIPH_BIT     2
+
+
+#define APB_SOC_RTC_OFFSET     0x1D0
+
+#endif

include/archi/chips/pulp_cluster/apb_soc_ctrl.h

@@ -0,0 +1,115 @@
+
+/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT.
+ */
+
+/*
+ * Copyright (C) 2018 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INCLUDE_ARCHI_CHIPS_PULP_APB_SOC_CTRL_H__
+#define __INCLUDE_ARCHI_CHIPS_PULP_APB_SOC_CTRL_H__
+
+#ifndef LANGUAGE_ASSEMBLY
+
+#include <stdint.h>
+#include "archi/utils.h"
+
+#endif
+
+
+
+
+//
+// REGISTERS
+//
+
+// Value of pad bootsel
+#define APB_SOC_BOOTSEL_OFFSET                   0xc4
+
+
+
+//
+// REGISTERS FIELDS
+//
+
+
+
+//
+// REGISTERS STRUCTS
+//
+
+#ifndef LANGUAGE_ASSEMBLY
+
+typedef union {
+  struct {
+  };
+  unsigned int raw;
+} __attribute__((packed)) apb_soc_bootsel_t;
+
+#endif
+
+
+
+//
+// REGISTERS STRUCTS
+//
+
+#ifdef __GVSOC__
+
+class vp_apb_soc_bootsel : public vp::reg_32
+{
+public:
+};
+
+#endif
+
+
+
+//
+// REGISTERS GLOBAL STRUCT
+//
+
+#ifndef LANGUAGE_ASSEMBLY
+
+typedef struct {
+  unsigned int bootsel         ; // Value of pad bootsel
+} __attribute__((packed)) apb_soc_apb_soc_t;
+
+#endif
+
+
+
+//
+// REGISTERS ACCESS FUNCTIONS
+//
+
+#ifndef LANGUAGE_ASSEMBLY
+
+static inline uint32_t apb_soc_bootsel_get(uint32_t base) { return ARCHI_READ(base, APB_SOC_BOOTSEL_OFFSET); }
+static inline void apb_soc_bootsel_set(uint32_t base, uint32_t value) { ARCHI_WRITE(base, APB_SOC_BOOTSEL_OFFSET, value); }
+
+#endif
+
+
+
+//
+// REGISTERS FIELDS MACROS
+//
+
+#ifndef LANGUAGE_ASSEMBLY
+
+#endif
+
+#endif

include/archi/chips/pulp_cluster/memory_map.h

@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2018 ETH Zurich, University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __ARCHI_CHIPS_PULP_MEMORY_MAP_H__
+#define __ARCHI_CHIPS_PULP_MEMORY_MAP_H__
+
+
+/*
+ * MEMORIES
+ */
+
+#define ARCHI_L2_PRIV0_ADDR  0x1c000000
+#define ARCHI_L2_PRIV0_SIZE  0x00008000
+
+#define ARCHI_L2_PRIV1_ADDR  0x1c008000
+#define ARCHI_L2_PRIV1_SIZE  0x00008000
+
+#define ARCHI_L2_SHARED_ADDR  0x1c010000
+#define ARCHI_L2_SHARED_SIZE  0x00070000
+
+
+/*
+ * SOC PERIPHERALS
+ */
+
+#define ARCHI_SOC_PERIPHERALS_ADDR    0x1A100000
+
+#define ARCHI_FC_TIMER_SIZE                 0x00000800
+
+
+#define ARCHI_FLL_OFFSET              0x00000000
+#define ARCHI_GPIO_OFFSET             0x00001000
+#define ARCHI_UDMA_OFFSET             0x00002000
+#define ARCHI_APB_SOC_CTRL_OFFSET     0x00004000
+#define ARCHI_SOC_EU_OFFSET           0x00006000
+#define ARCHI_FC_ITC_OFFSET           0x00009800
+#define ARCHI_FC_TIMER_OFFSET         0x0000B000
+#define ARCHI_STDOUT_OFFSET           0x0000F000
+
+
+
+#define ARCHI_GPIO_ADDR              ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET )
+#define ARCHI_UDMA_ADDR              ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET )
+#define ARCHI_APB_SOC_CTRL_ADDR      ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET )
+#define ARCHI_SOC_EU_ADDR            ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET )
+#define ARCHI_FC_ITC_ADDR            ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET )
+#define ARCHI_FC_TIMER_ADDR          ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET )
+#define ARCHI_STDOUT_ADDR            0x40000000
+
+#define ARCHI_FLL_AREA_SIZE          0x00000010
+
+
+
+
+/*
+ * FC
+ */
+
+#define ARCHI_FC_ADDR                   0x00000000
+#define ARCHI_FC_GLOBAL_ADDR            0x1B000000
+
+
+/*
+ * CLUSTER
+ */
+
+#define ARCHI_CLUSTER_ADDR              0x00000000
+#define ARCHI_CLUSTER_SIZE              0x00400000
+#define ARCHI_CLUSTER_GLOBAL_ADDR(cid)  (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE)
+
+
+
+/*
+ * CLUSTER PERIPHERALS
+ */
+
+#define ARCHI_CLUSTER_PERIPHERALS_OFFSET 0x00200000
+
+#define ARCHI_TIMER_SIZE                 0x00000800
+
+#define ARCHI_CLUSTER_CTRL_OFFSET        0x00000000
+#define ARCHI_TIMER_OFFSET               0x00000400
+#define ARCHI_EU_OFFSET                  0x00000800
+#define ARCHI_HWCE_OFFSET                0x00001000
+#define ARCHI_ICACHE_CTRL_OFFSET         0x00001400
+#define ARCHI_MCHAN_EXT_OFFSET           0x00001800
+
+#define ARCHI_CLUSTER_PERIPHERALS_ADDR             ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
+#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
+
+#define ARCHI_CLUSTER_CTRL_ADDR                    ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_CLUSTER_CTRL_OFFSET )
+#define ARCHI_ICACHE_CTRL_ADDR                     ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_ICACHE_CTRL_OFFSET )
+#define ARCHI_EU_ADDR                              ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_EU_OFFSET )
+#define ARCHI_HWCE_ADDR                            ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWCE_OFFSET )
+#define ARCHI_MCHAN_EXT_ADDR                       ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET )
+
+
+
+/*
+ * CLUSTER DEMUX PERIPHERALS
+ */
+
+#define ARCHI_DEMUX_PERIPHERALS_OFFSET        0x204000
+
+#define ARCHI_EU_DEMUX_OFFSET                 ( 0x00000 )
+#define ARCHI_MCHAN_DEMUX_OFFSET              ( 0x00400 )
+
+
+#define ARCHI_DEMUX_PERIPHERALS_ADDR          ( ARCHI_CLUSTER_ADDR + ARCHI_DEMUX_PERIPHERALS_OFFSET )
+
+#define ARCHI_EU_DEMUX_ADDR                   ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET )
+#define ARCHI_MCHAN_DEMUX_ADDR                ( ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET )
+
+#endif