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focusrite.s
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.equ GLOBCTL, 0xffb1
.equ OEPINT, 0xffb4
.equ IEPINT, 0xffb3
.equ VECINT, 0xffb2
.equ IEPCNF0, 0xff68
.equ IEPBBAX0, 0xff69
.equ IEPBSIZ0, 0xff6a
.equ IEPDCNTX0, 0xff6b
.equ IEPCNF2, 0xff58
.equ IEPBBAX2, 0xff59
.equ IEPBSIZ2, 0xff5a
.equ IEPDCNTX2, 0xff5b
.equ IEPBBAY2, 0xff5d
.equ IEPDCNTY2, 0xff5f
.equ OEPCNF0, 0xffa8
.equ OEPBBAX0, 0xffa9
.equ OEPBSIZ0, 0xffaa
.equ OEPDCNTX0, 0xffab
.equ OEPCNF1, 0xffa0
.equ OEPBBAX1, 0xffa1
.equ OEPBSIZ1, 0xffa2
.equ OEPDCNTX1, 0xffa3
.equ OEPBBAY1, 0xffa5
.equ SETUP_PKT, 0xff28
.equ MEMCFG, 0xffb0
.equ I2CCTL, 0xffc0
.equ I2CDATO, 0xffc1
.equ I2CDATI, 0xffc2
.equ USBFADR, 0xffff
.equ USBSTA, 0xfffe
.equ USBIMSK, 0xfffd
.equ USBCTL, 0xfffc
; C-port
.equ CPTVSLH, 0xFFD7
.equ CPTVSLL, 0xFFD8
.equ CPTDATH, 0xFFD9
.equ CPTDATL, 0xFFDA
.equ CPTADR, 0xFFDB
.equ CPTSTA, 0xFFDC
.equ CPTCTL, 0xFFDC
.equ CPTCNF4, 0xFFDD
.equ CPTCNF3, 0xFFDE
.equ CPTCNF2, 0xFFDF
.equ CPTCNF1, 0xFFE0
; Adaptive Clock Generator
.equ ACGCTL, 0xFFE1
.equ ACGDCTL, 0xFFE2
.equ ACGCAPH, 0xFFE3
.equ ACGCAPL, 0xFFE4
.equ ACGFRQ2, 0xFFE5
.equ ACGFRQ1, 0xFFE6
.equ ACGFRQ0, 0xFFE7
; DMA
.equ DMACTL0, 0xFFE8
.equ DMATSH0, 0xFFE9
.equ DMATSL0, 0xFFEA
.equ DMACTL1, 0xFFEE
.equ DMATSH1, 0xFFEF
.equ DMATSL1, 0xFFF0
.equ DMACTL2, 0xFFF4
.equ DMATSH2, 0xFFF5
.equ DMATSL2, 0xFFF6
.equ DMACTL3, 0xFFF7
.equ DMATSH3, 0xFFF8
.equ DMATSL3, 0xFFF9
.equ EP0_BYTES, 8
.equ EP0_IN_SIZ, ((EP0_BYTES + 7) / 8)
.equ EP0_IN, (SETUP_PKT - (8 * EP0_IN_SIZ))
.equ EP0_IN_BBAX, ((EP0_IN / 8) & 0xff)
.equ EP0_OUT_SIZ, ((EP0_BYTES + 7) / 8)
.equ EP0_OUT, (EP0_IN - (8 * EP0_OUT_SIZ))
.equ EP0_OUT_BBAX, ((EP0_OUT / 8) & 0xff)
.equ EP1_BYTES, (288 * 2)
.equ EP1_OUT_SIZ, ((EP1_BYTES + 7) / 8)
.equ EP1_OUTX, (EP0_OUT - (8 * EP1_OUT_SIZ))
.equ EP1_OUT_BBAX, ((EP1_OUTX / 8) & 0xff)
.equ EP1_OUTY, (EP1_OUTX - (8 * EP1_OUT_SIZ))
.equ EP1_OUT_BBAY, ((EP1_OUTY / 8) & 0xff)
.equ EP2_BYTES, 288
.equ EP2_IN_SIZ, ((EP2_BYTES + 7) / 8)
.equ EP2_INX, (EP1_OUTY - (8 * EP2_IN_SIZ))
.equ EP2_IN_BBAX, ((EP2_INX / 8) & 0xff)
.equ EP2_INY, (EP2_INX - (8 * EP2_IN_SIZ))
.equ EP2_IN_BBAY, ((EP2_INY / 8) & 0xff)
.iflt EP0_IN - 0xff00
.error 1; EP0 buffer start out of range
.endif
.iflt EP0_OUT - 0xff00
.error 1; EP0 buffer start out of range
.endif
; recursive macro example
; usage: sum 0 5
.macro sum from,to
.byte from
.ifgt to - from
sum (from+1) to
.endif
.endm
.macro usb_string name value
.nchr len, value
.ifgt len - 126
.error 1
.endif
name: .byte 2 * (len + 1)
.ascii value
.endm
.macro dispatch_address handler
.iflt handler - . - 1
.error 1 ; handler adress out of range
.endif
.ifgt handler - . - 1 - 255
.error 1 ; handler adress out of range
.endif
.byte handler - . - 1
.endm
.macro dispatch_entry value handler
.byte value
dispatch_address handler
.endm
.macro setup_entry type request handler
.byte type
.byte request
.word handler
.endm
.area RSEG (ABS,DATA)
.org 0x0000
AR0: .ds 1
AR1: .ds 1
AR2: .ds 1
AR3: .ds 1
AR4: .ds 1
AR5: .ds 1
AR6: .ds 1
AR7: .ds 1
BR0: .ds 1
BR1: .ds 1
BR2: .ds 1
BR3: .ds 1
BR4: .ds 1
BR5: .ds 1
BR6: .ds 1
BR7: .ds 1
.area BSEG (ABS,DATA)
.org 0x0020
usbState: .ds 1
.equ usbStateSetupInvalid, 0
.equ usbStateSetAddress, 1
.equ usbStateIn0Done, 2
.equ usbStateZeroPad, 3
.equ usbStateStringCnt, 4
.equ usbStateHTDData, 5
.equ usbStateCopyIRAM, 6
.equ usbStateCopyXRAM, 7
usbState2: .ds 1
.equ usbStateAddressValid, 8
miscState: .ds 1
.equ uartEmpty, 16
.equ swapOutput, 17 ; In 2ch mode, output on terminals 3+4 instead of 1+2
audioState: .ds 1
.equ audioIf1On, 24
.equ audioIf2On, 25
.equ audio24bit, 26
.org 0x0080
.equ UartBufSize, 0x40
.equ StackSize, 0x40
stack: .ds StackSize
uartbuf: .ds UartBufSize
.area DSEG (DATA)
bmRequestType: .ds 1
bRequest: .ds 1
wValueLo: .ds 1
wValueHi: .ds 1
wIndexLo: .ds 1
wIndexHi: .ds 1
wLengthLo: .ds 1
wLengthHi: .ds 1
txPtr: .dw 1
. = . - 2
txPtrLo: .ds 1
txPtrHi: .ds 1
txSizeLo: .ds 1
txSizeHi: .ds 1
sofCtr: .ds 1
freqLockCtr: .ds 1
uartReadPtr: .ds 1
uartWritePtr: .ds 1
pACGCapL: .ds 1
pACGCapH: .ds 1
acgDeltaL: .ds 1
acgDeltaH: .ds 1
acgFrqLo: .ds 1
getBuf: .ds 4
codecCache: .ds 8 ; CS4272 has 8 registers
envMaxL: .ds 1
envMaxR: .ds 1
.area CSEG (CODE,ABS)
_reset: ljmp _start
.org 3
ljmp vec_int0
.org 6
.word infobytes
.org 0x20
ajmp bad_vec
.org 0x23
push PSW
setb PSW.3
mov R7, A
ajmp uart_vec
vec_int0:
bad_vec:
clr TI
mov SBUF, #'!'
bad_vec_wait:
jnb TI, bad_vec_wait
sjmp bad_vec
_start:
clr A
mov PSW, A
mov R0, A
clear_iram:
mov @R0, A
djnz R0, clear_iram
mov SP, #0x6f
; Port defaults
mov P1, #0xdf ; Turn on LED1 (LD1)
mov P2, #0xff ; Select 0xff00 as base for MOVX with R0/R1
orl P3, #0x3b
anl P3, #0xef ; Turn on front panel USB LED
mov R0, #GLOBCTL
mov A, #0xC4 ; Enable 24MHz CPU clock, enable USB block
movx @R0, A
mov RCAP2H, #0xff
mov RCAP2L, #0xf3 ; 57600 baud (~57692; 0.16% error)
mov T2CON, #0x34
mov SCON, #0x50
mov TH2, #0xff
mov TL2, #0xff
clr IT0 ; Trigger extint on falling edge
mov uartReadPtr, #uartbuf
mov uartWritePtr, #uartbuf
setb uartEmpty
mov IE, #0x90 ; Enable interrupts (uart only)
mov DPTR, #message_hello
acall serial_puts
wait_uart_finished:
jnb uartEmpty, wait_uart_finished
acall usb_init
loop:
mov R0, #VECINT
movx A, @R0
xrl A, #0x24 ; 0x24 => no interrupt pending
jz loop
cjne A, #(0x12 ^ 0x24), vec_early_check_not_setup
sjmp vec_setup_skip_early_ack
vec_early_check_not_setup:
; ACK interrupt
movx @R0, A
vec_setup_skip_early_ack:
acall vec_dispatch
sjmp loop
fetchx_postinc:
movx A, @DPTR
inc DPTR
ret
fetchc_postinc:
clr A
movc A, @A+DPTR
inc DPTR
ret
fetchi_postinc:
push AR0
mov R0, DPL
mov A, @R0
inc DPTR
pop AR0
ret
vec_dispatch:
acall dispatch
dispatch_entry (0x08^0x24) vec_in_ep0
dispatch_entry (0x00^0x24) vec_out_ep0
dispatch_entry (0x17^0x24) vec_reset
dispatch_entry (0x12^0x24) vec_setup
dispatch_entry (0x13^0x24) vec_psof
dispatch_entry (0x14^0x24) vec_sof
dispatch_entry 0 vec_default
vec_default:
mov A, #'V'
acall serial_write
mov R0, #USBIMSK
movx A, @R0
acall serial_hex ; Dump mask
mov R0, #VECINT
movx A, @R0
acall serial_hex ; Dump vec num
ret
vec_reset:
; Turn off power
setb P1.6
mov DPTR, #message_rst
acall serial_puts
acall usb_init
ret
vec_psof:
vec_sof:
ajmp vec_sof_softpll
vec_in_ep0:
mov A, #'i'
acall serial_write
acall write_to_ep0
jbc usbStateSetAddress, vec_in_ep0_set_addr
ret
vec_in_ep0_set_addr:
mov A, wValueLo
mov R7, A
mov R0, #USBFADR
movx @R0, A
setb usbStateAddressValid
mov A, #'A'
acall serial_write
mov A, R7
acall serial_hex
;mov R0, #IEPCNF0
;movx A, @R0
;orl A, #0x08 ; Stall endpoint
;movx @R0, A
ret
vec_out_ep0:
mov A, #'o'
acall serial_write
mov R0, #OEPDCNTX0
movx A, @R0
clr ACC.7
jz vec_out_ep0_no_data
; TODO: Copy data to iram
; Only one place using it so far, so not bothering here
vec_out_ep0_no_data:
; Clear NAK
mov R0, #OEPDCNTX0
clr A
movx @R0, A
; TODO: Support multiple packets, not used here.
jb usbStateHTDData, setup_htd_got_data
ret
vec_setup:
mov A, #' '
acall serial_write
mov A, #'S'
acall serial_write
; Unstall endpoints
mov A, #0xa4 ; Unstall in/out EP0
mov R0, #IEPCNF0
movx @R0, A
mov R0, #OEPCNF0
movx @R0, A
mov A, #0x80 ; NACK IN/OUT
mov R0, #IEPDCNTX0
movx @R0, A
mov R0, #OEPDCNTX0
movx @R0, A
mov usbState, #0
mov txSizeLo, #0
mov txSizeHi, #0
mov R1, #SETUP_PKT
mov R0, #bmRequestType
mov R2, #8
copy_setup_pkt:
movx A, @R1
mov @R0, A
inc R1
inc R0
djnz R2, copy_setup_pkt
mov A, bmRequestType
jb ACC.7, setup_dth
; host is writing to device, check if there will OUT with data.
mov A, wLengthLo
orl A, wLengthHi
jz setup_htd_no_data
; Unnak OUT EP0 and wait for data
movx @R0, A
mov R0, #OEPDCNTX0
movx @R0, A
setb usbStateHTDData
sjmp setup_exit
setup_htd_got_data:
setup_htd_no_data:
sjmp setup_dispatch
setup_dth:
; Assume that we read the requested size
mov txSizeLo, wLengthLo
mov txSizeHi, wLengthHi
setup_dispatch:
mov DPTR, #(setup_dispatch_table - 2)
setup_dispatch_check_next:
inc DPTR
inc DPTR
acall fetchc_postinc
mov R2, A
acall fetchc_postinc
mov R3, A
orl A, R2
inc A
jnz setup_not_default
ajmp setup_default
setup_not_default:
mov A, R2
xrl A, bmRequestType
jnz setup_dispatch_check_next
mov A, R3
xrl A, bRequest
jnz setup_dispatch_check_next
acall fetchc_postinc
mov R2, A
acall fetchc_postinc
mov DPL, A
mov DPH, R2
acall setup_dispatch_do_call
jnb usbStateSetupInvalid, setup_done_valid
mov A, #0xac ; Stall IN/OUT EPs
mov R0, #IEPCNF0
movx @R0, A
mov R0, #OEPCNF0
movx @R0, A
clr A
mov R0, #IEPDCNTX0
movx @R0, A
mov R0, #OEPDCNTX0
movx @R0, A
sjmp setup_exit
setup_done_valid:
mov A, bmRequestType
jb ACC.7, setup_exit
; Unnak IN for final ACK
clr A
mov R0, #IEPDCNTX0
movx @R0, A
setup_exit:
; Late ACK for SETUP interrupt
mov R0, #VECINT
movx @R0, A
ret
setup_dispatch_do_call:
clr A
jmp @A+DPTR
setup_dispatch_table:
setup_entry 0x80 0 setup_dth_dev_get_status
setup_entry 0x80 6 setup_dth_dev_get_descriptor
setup_entry 0xc0 0x90 setup_dth_vend_read_xram
setup_entry 0x40 0x91 setup_dth_vend_write_xram
setup_entry 0xc0 0x94 setup_dth_vend_read_code
setup_entry 0xc0 0x96 setup_dth_vend_read_iram
setup_entry 0x40 0x97 setup_dth_vend_write_iram
setup_entry 0xc0 0x9a setup_dth_vend_read_codec
setup_entry 0x40 0x9b setup_dth_vend_write_codec
setup_entry 0xc0 0xa0 setup_dth_vend_read_envelope
setup_entry 0xa1 0x81 setup_dth_class_if_get_cur
setup_entry 0xa1 0x82 setup_dth_class_if_get_min
setup_entry 0xa1 0x83 setup_dth_class_if_get_max
setup_entry 0xa1 0x84 setup_dth_class_if_get_res
setup_entry 0x21 0x01 setup_htd_class_if_set_cur
setup_entry 0x21 0x02 setup_htd_class_if_set_min
setup_entry 0x21 0x03 setup_htd_class_if_set_max
setup_entry 0x21 0x04 setup_htd_class_if_set_res
setup_entry 0x00 5 setup_htd_dev_set_address
setup_entry 0x00 9 setup_htd_dev_set_configuration
setup_entry 0x01 0x0b setup_htd_dev_set_interface
.byte 0xff, 0xff
setup_dth_vend_read_iram:
mov txPtrLo, wIndexLo
ajmp writei_to_ep0
setup_dth_vend_read_codec:
; CS4272 regs are at addr 1 to 8
mov A, wIndexLo
dec A
anl A, #7
add A, #codecCache
mov txPtrLo, A ; read cache value
ajmp writei_to_ep0
setup_dth_vend_read_xram:
mov txPtrLo, wIndexLo
mov txPtrHi, wIndexHi
ajmp writex_to_ep0
setup_dth_vend_read_code:
mov txPtrLo, wIndexLo
mov txPtrHi, wIndexHi
ajmp write_to_ep0
setup_dth_vend_read_envelope:
clr A
xch A, envMaxL
mov getBuf, A
clr A
xch A, envMaxR
mov getBuf+1, A
mov txPtrLo, #getBuf
ajmp writei_to_ep0
setup_dth_vend_write_iram:
mov R0, wIndexLo
mov A, wValueLo
mov @R0, A
ajmp write_to_ep0 ; 0-byte write
setup_dth_vend_write_codec:
mov R2, wIndexLo
mov R3, wValueLo
acall codec_spi_write
ajmp write_to_ep0 ; 0-byte write
setup_dth_vend_write_xram:
mov DPL, wIndexLo
mov DPH, wIndexHi
mov A, wValueLo
movx @DPTR, A
ajmp write_to_ep0 ; 0-byte write
setup_htd_class_if_set_min:
setup_htd_class_if_set_max:
setup_htd_class_if_set_res:
; not supported
setb usbStateSetupInvalid
ret
setup_htd_class_if_set_cur:
mov A, #'V'
acall serial_write
mov R0, #(EP0_OUT + 1)
movx A, @R0
; Negate value (register is attenuation in dB)
cpl A
inc A
anl A, #0x7f
push ACC
acall serial_hex
pop ACC
; Not bothering exposing the channels seperately here
mov R2, #CS4272_DAC_A_MUTE_VOL
mov R3, A
acall codec_spi_write
mov R2, #CS4272_DAC_B_MUTE_VOL
acall codec_spi_write
ret
setup_dth_class_if_get_write:
mov txPtrHi, DPH
mov txPtrLo, DPL
mov txSizeLo, #0x2
ajmp write_to_ep0
setup_dth_class_if_get_min:
mov DPTR, #uac_volume_min
sjmp setup_dth_class_if_get_write
setup_dth_class_if_get_max:
mov DPTR, #uac_volume_max
sjmp setup_dth_class_if_get_write
setup_dth_class_if_get_res:
mov DPTR, #uac_volume_res
sjmp setup_dth_class_if_get_write
setup_dth_class_if_get_cur:
mov A, #'u'
acall serial_write
mov A, wIndexHi
acall serial_hex
; Check requested control is in supported range
mov A, wValueHi
jz setup_dth_class_if_get_stall
add A, #-3
jc setup_dth_class_if_get_stall
mov A, wIndexLo
acall serial_hex
mov A, bRequest
acall serial_hex
mov A, wValueHi
acall serial_hex
mov A, wValueLo
acall serial_hex
mov A, wLengthLo
acall serial_hex
clr A
mov getBuf, A
mov getBuf+1, A
mov txSizeLo, #0x2
mov txPtrLo, #getBuf
acall writei_to_ep0
; not checking wIndex since there only is one feature unit
ret
setup_dth_class_if_get_stall:
ajmp write_stall_ep0
setup_dth_dev_get_status:
mov DPTR, #usb_status_ok
mov txSizeLo, #2
mov txPtrHi, DPH
mov txPtrLo, DPL
acall write_to_ep0
ret
setup_dth_dev_get_descriptor:
mov A, wValueHi
acall dispatch
dispatch_entry 3 setup_dth_get_desc_string
dispatch_entry 2 setup_dth_get_desc_configuration
dispatch_entry 1 setup_dth_get_desc_device
dispatch_entry 0 setup_dth_get_desc_bad
clamp_size:
mov A, wLengthLo
clr C
subb A, txSizeLo
mov A, wLengthHi
subb A, txSizeHi
jnc clamp_size_exit
mov txSizeHi, wLengthHi
mov txSizeLo, wLengthLo
clamp_size_exit:
ret
setup_dth_get_desc_device:
mov DPTR, #usb_dev_desc
mov txSizeLo, #0x12
setup_dth_get_desc:
mov txPtrHi, DPH
mov txPtrLo, DPL
acall clamp_size
acall write_to_ep0
ret
setup_dth_get_desc_configuration:
mov DPTR, #usb_cnf_desc
mov txSizeHi, #(usb_cnf_len >> 8)
mov txSizeLo, #usb_cnf_len
sjmp setup_dth_get_desc
setup_dth_get_desc_string:
mov A, wValueLo
cjne A, #0, not_string_0
mov DPTR, #usb_string_lang
mov txSizeLo, #4
sjmp string_write
not_string_0:
setb usbStateZeroPad
setb usbStateStringCnt
mov DPTR, #usb_s_mfg
; first byte is precalulated length byte
clr A
movc A, @A+DPTR
mov txSizeLo, A
string_write:
mov txPtrHi, DPH
mov txPtrLo, DPL
acall write_to_ep0
ret
setup_dth_get_desc_bad:
mov A, #'d'
acall serial_write
mov A, wValueHi
acall serial_hex
mov A, wValueLo
acall serial_hex
; Cause IN to STALL
setb usbStateIn0Done
acall write_to_ep0
ret
setup_htd_dev_set_address:
setb usbStateSetAddress
mov R0, #IEPDCNTX0
clr A
movx @R0, A
mov A, #'a'
acall serial_write
ret
setup_htd_dev_set_configuration:
mov A, #'c'
acall serial_write
; Basic codec setup (sets up clock)
acall codec_init
; Enable c-port
mov R0, #GLOBCTL
movx A, @R0
setb ACC.0
movx @R0, A
; Enable PSOF/SOF interrupt
mov sofCtr, #0x00
mov freqLockCtr, #10
mov R0, #USBIMSK
movx A, @R0
orl A, #0x18
movx @R0, A
mov R0, #ACGCTL
mov A, #0x50 ; Enable MCLKO, capture source MCLKO, input is MCLKI2, divider disabled
movx @R0, A
mov R0, #ACGDCTL
mov A, #0x17 ; divm is 2 (MCLKO), divi is 8 (MCLKI2)
movx @R0, A
; Enable divider:
; A.5.3.7: "The MCU should program the MCLK input select bit, the MCLK capture source bit and the MCLK output enable bit before setting this bit to a 1"
mov R0, #ACGCTL
mov A, #0x54 ; Enable MCLKO, capture source MCLKO, input is MCLKI2, divider enabled
movx @R0, A
; ACGDCTL (in particular divi counter) has trouble loading
; properly sometimes (some strange timing issue with the latch?)
; Load it repeatedly just to be sure.
mov R0, #ACGDCTL
mov A, #0x17
mov R1, #0
acgdctl_safety_loop:
movx @R0, A
djnz R1, acgdctl_safety_loop
; Should be safe to turn on power now (this also ungates the step-up
; SYNC signal if phantom power is selected)
clr P1.6 ; Turn on power to main analog sections
; Abuse codec_spi_init as a delay function
acall codec_spi_init
; Release reset
clr P1.7
; External clock, no delay should be needed between releasing
; reset and starting the cs4272 control port write.
acall codec_spi_init
ret
setup_htd_dev_set_interface:
mov A, #'i'
acall serial_write
mov A, wIndexLo ; interface index
acall serial_hex
mov A, #'a'
acall serial_write
mov A, wValueLo ; altsetting index
acall serial_hex
mov A, wIndexLo
cjne A, #1, set_interface_not_if1
; Interface 1 (playback)
mov A, wValueLo ; altsetting index
xrl A, #0x80
acall dispatch
dispatch_entry (0x80^0x00) set_interface_if1_as0_off
dispatch_entry (0x80^0x01) set_interface_if1_as1_16bit_2ch
dispatch_entry (0x80^0x02) set_interface_if1_as2_16bit_4ch
dispatch_entry (0x80^0x03) set_interface_if1_as3_24bit_2ch
dispatch_entry (0x80^0x04) set_interface_if1_as4_24bit_4ch
dispatch_entry 0 set_interface_error
set_interface_not_if1:
cjne A, #2, set_interface_not_if2
; Interface 2 (record)
mov A, wValueLo ; altsetting index
xrl A, #0x80
acall dispatch
dispatch_entry (0x80^0x00) set_interface_if2_as0_off
dispatch_entry (0x80^0x01) set_interface_if2_as1_16bit_2ch
dispatch_entry (0x80^0x02) set_interface_if2_as2_24bit_2ch
dispatch_entry 0 set_interface_error
set_interface_not_if2:
set_interface_error:
setb usbStateSetupInvalid
ret
set_interface_if1_as0_off:
clr audioIf1On
ret
set_interface_if1_as1_16bit_2ch:
jnb audioIf2On, set_interface_if1_as1_16bit_2ch_do
jb audio24bit, set_interface_error
set_interface_if1_as1_16bit_2ch_do:
mov DPTR, #codec_out_2ch_16bit
jnb swapOutput, set_interface_if1_as1_16bit_2ch_do_unswapped
mov DPTR, #codec_out_2ch_16bit_alt
set_interface_if1_as1_16bit_2ch_do_unswapped:
acall usb_init_loop
sjmp set_interface_if1_exit_on_16bit
set_interface_if1_as2_16bit_4ch:
jnb audioIf2On, set_interface_if1_as2_16bit_4ch_do
jb audio24bit, set_interface_error
set_interface_if1_as2_16bit_4ch_do:
mov DPTR, #codec_out_4ch_16bit
acall usb_init_loop
sjmp set_interface_if1_exit_on_16bit
set_interface_if1_as3_24bit_2ch:
jnb audioIf2On, set_interface_if1_as3_24bit_2ch_do
jnb audio24bit, set_interface_error
set_interface_if1_as3_24bit_2ch_do:
mov DPTR, #codec_out_2ch_24bit
jnb swapOutput, set_interface_if1_as3_24bit_2ch_do_unswapped
mov DPTR, #codec_out_2ch_24bit_alt
set_interface_if1_as3_24bit_2ch_do_unswapped:
acall usb_init_loop
sjmp set_interface_if1_exit_on_24bit
set_interface_if1_as4_24bit_4ch:
jnb audioIf2On, set_interface_if1_as4_24bit_4ch_do
jnb audio24bit, set_interface_error
set_interface_if1_as4_24bit_4ch_do:
mov DPTR, #codec_out_4ch_24bit
acall usb_init_loop
sjmp set_interface_if1_exit_on_24bit
set_interface_if1_exit_on_16bit:
acall codec_set_16bit
setb audioIf1On
ret
set_interface_if1_exit_on_24bit:
acall codec_set_24bit
setb audioIf1On
ret
set_interface_if2_as0_off:
clr audioIf2On
ret
set_interface_if2_as1_16bit_2ch:
jnb audioIf1On, set_interface_if2_as1_16bit_2ch_do
jb audio24bit, set_interface_error
set_interface_if2_as1_16bit_2ch_do:
mov DPTR, #codec_in_2ch_16bit
acall usb_init_loop
acall codec_set_16bit
sjmp set_interface_if2_exit_on
set_interface_if2_as2_24bit_2ch:
jnb audioIf1On, set_interface_if2_as2_24bit_2ch_do
jnb audio24bit, set_interface_error
set_interface_if2_as2_24bit_2ch_do:
mov DPTR, #codec_in_2ch_24bit
acall usb_init_loop
acall codec_set_24bit
sjmp set_interface_if2_exit_on
set_interface_if2_exit_on:
setb audioIf2On
ret
setup_default:
setb usbStateSetupInvalid
mov A, #'?'
acall serial_write
mov A, bmRequestType
acall serial_hex
mov A, bRequest
acall serial_hex
ret
vec_sof_waitlock:
djnz sofCtr, vec_sof_waitlock_nodec
dec A
mov freqLockCtr, A
vec_sof_waitlock_nodec:
ret
vec_sof_softpll:
mov A, freqLockCtr
jnz vec_sof_waitlock
; Update delta from capture and previous capture
mov R0, #ACGCAPL
movx A, @R0
clr C
subb A, pACGCapL
mov acgDeltaL, A
mov R2, A
movx A, @R0
mov pACGCapL, A ; Update previous value
mov R0, #ACGCAPH
movx A, @R0
subb A, pACGCapH
add A, #-0x30 ; Subtract expected delta (0x3000 for 48kHz)
mov acgDeltaH, A
movx A, @R0
mov pACGCapH, A ; Update previous value
; Load R3 with sign-extend value
mov A, acgDeltaH
mov R3, #0
jnb ACC.7, vec_sof_softpll_delta_pos
dec R3
vec_sof_softpll_delta_pos:
; Accumulate error
; At 48kHz, 1 sample offset is equivalent to 256 running sum
xch A, R2
add A, acgFrqLo